smp.c 22 KB

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  1. /*
  2. * SMP initialisation and IPI support
  3. * Based on arch/arm/kernel/smp.c
  4. *
  5. * Copyright (C) 2012 ARM Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/acpi.h>
  20. #include <linux/delay.h>
  21. #include <linux/init.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/sched.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/cache.h>
  26. #include <linux/profile.h>
  27. #include <linux/errno.h>
  28. #include <linux/mm.h>
  29. #include <linux/err.h>
  30. #include <linux/cpu.h>
  31. #include <linux/smp.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/irq.h>
  34. #include <linux/percpu.h>
  35. #include <linux/clockchips.h>
  36. #include <linux/completion.h>
  37. #include <linux/of.h>
  38. #include <linux/irq_work.h>
  39. #include <asm/alternative.h>
  40. #include <asm/atomic.h>
  41. #include <asm/cacheflush.h>
  42. #include <asm/cpu.h>
  43. #include <asm/cputype.h>
  44. #include <asm/cpu_ops.h>
  45. #include <asm/mmu_context.h>
  46. #include <asm/numa.h>
  47. #include <asm/pgtable.h>
  48. #include <asm/pgalloc.h>
  49. #include <asm/processor.h>
  50. #include <asm/smp_plat.h>
  51. #include <asm/sections.h>
  52. #include <asm/tlbflush.h>
  53. #include <asm/ptrace.h>
  54. #include <asm/virt.h>
  55. #define CREATE_TRACE_POINTS
  56. #include <trace/events/ipi.h>
  57. DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
  58. EXPORT_PER_CPU_SYMBOL(cpu_number);
  59. /*
  60. * as from 2.5, kernels no longer have an init_tasks structure
  61. * so we need some other way of telling a new secondary core
  62. * where to place its SVC stack
  63. */
  64. struct secondary_data secondary_data;
  65. /* Number of CPUs which aren't online, but looping in kernel text. */
  66. int cpus_stuck_in_kernel;
  67. enum ipi_msg_type {
  68. IPI_RESCHEDULE,
  69. IPI_CALL_FUNC,
  70. IPI_CPU_STOP,
  71. IPI_TIMER,
  72. IPI_IRQ_WORK,
  73. IPI_WAKEUP
  74. };
  75. #ifdef CONFIG_ARM64_VHE
  76. /* Whether the boot CPU is running in HYP mode or not*/
  77. static bool boot_cpu_hyp_mode;
  78. static inline void save_boot_cpu_run_el(void)
  79. {
  80. boot_cpu_hyp_mode = is_kernel_in_hyp_mode();
  81. }
  82. static inline bool is_boot_cpu_in_hyp_mode(void)
  83. {
  84. return boot_cpu_hyp_mode;
  85. }
  86. /*
  87. * Verify that a secondary CPU is running the kernel at the same
  88. * EL as that of the boot CPU.
  89. */
  90. void verify_cpu_run_el(void)
  91. {
  92. bool in_el2 = is_kernel_in_hyp_mode();
  93. bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode();
  94. if (in_el2 ^ boot_cpu_el2) {
  95. pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n",
  96. smp_processor_id(),
  97. in_el2 ? 2 : 1,
  98. boot_cpu_el2 ? 2 : 1);
  99. cpu_panic_kernel();
  100. }
  101. }
  102. #else
  103. static inline void save_boot_cpu_run_el(void) {}
  104. #endif
  105. #ifdef CONFIG_HOTPLUG_CPU
  106. static int op_cpu_kill(unsigned int cpu);
  107. #else
  108. static inline int op_cpu_kill(unsigned int cpu)
  109. {
  110. return -ENOSYS;
  111. }
  112. #endif
  113. /*
  114. * Boot a secondary CPU, and assign it the specified idle task.
  115. * This also gives us the initial stack to use for this CPU.
  116. */
  117. static int boot_secondary(unsigned int cpu, struct task_struct *idle)
  118. {
  119. if (cpu_ops[cpu]->cpu_boot)
  120. return cpu_ops[cpu]->cpu_boot(cpu);
  121. return -EOPNOTSUPP;
  122. }
  123. static DECLARE_COMPLETION(cpu_running);
  124. int __cpu_up(unsigned int cpu, struct task_struct *idle)
  125. {
  126. int ret;
  127. long status;
  128. /*
  129. * We need to tell the secondary core where to find its stack and the
  130. * page tables.
  131. */
  132. secondary_data.task = idle;
  133. secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
  134. update_cpu_boot_status(CPU_MMU_OFF);
  135. __flush_dcache_area(&secondary_data, sizeof(secondary_data));
  136. /*
  137. * Now bring the CPU into our world.
  138. */
  139. ret = boot_secondary(cpu, idle);
  140. if (ret == 0) {
  141. /*
  142. * CPU was successfully started, wait for it to come online or
  143. * time out.
  144. */
  145. wait_for_completion_timeout(&cpu_running,
  146. msecs_to_jiffies(1000));
  147. if (!cpu_online(cpu)) {
  148. pr_crit("CPU%u: failed to come online\n", cpu);
  149. ret = -EIO;
  150. }
  151. } else {
  152. pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
  153. }
  154. secondary_data.task = NULL;
  155. secondary_data.stack = NULL;
  156. status = READ_ONCE(secondary_data.status);
  157. if (ret && status) {
  158. if (status == CPU_MMU_OFF)
  159. status = READ_ONCE(__early_cpu_boot_status);
  160. switch (status) {
  161. default:
  162. pr_err("CPU%u: failed in unknown state : 0x%lx\n",
  163. cpu, status);
  164. break;
  165. case CPU_KILL_ME:
  166. if (!op_cpu_kill(cpu)) {
  167. pr_crit("CPU%u: died during early boot\n", cpu);
  168. break;
  169. }
  170. /* Fall through */
  171. pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
  172. case CPU_STUCK_IN_KERNEL:
  173. pr_crit("CPU%u: is stuck in kernel\n", cpu);
  174. cpus_stuck_in_kernel++;
  175. break;
  176. case CPU_PANIC_KERNEL:
  177. panic("CPU%u detected unsupported configuration\n", cpu);
  178. }
  179. }
  180. return ret;
  181. }
  182. /*
  183. * This is the secondary CPU boot entry. We're using this CPUs
  184. * idle thread stack, but a set of temporary page tables.
  185. */
  186. asmlinkage void secondary_start_kernel(void)
  187. {
  188. struct mm_struct *mm = &init_mm;
  189. unsigned int cpu;
  190. cpu = task_cpu(current);
  191. set_my_cpu_offset(per_cpu_offset(cpu));
  192. /*
  193. * All kernel threads share the same mm context; grab a
  194. * reference and switch to it.
  195. */
  196. atomic_inc(&mm->mm_count);
  197. current->active_mm = mm;
  198. /*
  199. * TTBR0 is only used for the identity mapping at this stage. Make it
  200. * point to zero page to avoid speculatively fetching new entries.
  201. */
  202. cpu_uninstall_idmap();
  203. preempt_disable();
  204. trace_hardirqs_off();
  205. /*
  206. * If the system has established the capabilities, make sure
  207. * this CPU ticks all of those. If it doesn't, the CPU will
  208. * fail to come online.
  209. */
  210. check_local_cpu_capabilities();
  211. if (cpu_ops[cpu]->cpu_postboot)
  212. cpu_ops[cpu]->cpu_postboot();
  213. /*
  214. * Log the CPU info before it is marked online and might get read.
  215. */
  216. cpuinfo_store_cpu();
  217. /*
  218. * Enable GIC and timers.
  219. */
  220. notify_cpu_starting(cpu);
  221. store_cpu_topology(cpu);
  222. /*
  223. * OK, now it's safe to let the boot CPU continue. Wait for
  224. * the CPU migration code to notice that the CPU is online
  225. * before we continue.
  226. */
  227. pr_info("CPU%u: Booted secondary processor [%08x]\n",
  228. cpu, read_cpuid_id());
  229. update_cpu_boot_status(CPU_BOOT_SUCCESS);
  230. set_cpu_online(cpu, true);
  231. complete(&cpu_running);
  232. local_irq_enable();
  233. local_async_enable();
  234. /*
  235. * OK, it's off to the idle thread for us
  236. */
  237. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  238. }
  239. #ifdef CONFIG_HOTPLUG_CPU
  240. static int op_cpu_disable(unsigned int cpu)
  241. {
  242. /*
  243. * If we don't have a cpu_die method, abort before we reach the point
  244. * of no return. CPU0 may not have an cpu_ops, so test for it.
  245. */
  246. if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
  247. return -EOPNOTSUPP;
  248. /*
  249. * We may need to abort a hot unplug for some other mechanism-specific
  250. * reason.
  251. */
  252. if (cpu_ops[cpu]->cpu_disable)
  253. return cpu_ops[cpu]->cpu_disable(cpu);
  254. return 0;
  255. }
  256. /*
  257. * __cpu_disable runs on the processor to be shutdown.
  258. */
  259. int __cpu_disable(void)
  260. {
  261. unsigned int cpu = smp_processor_id();
  262. int ret;
  263. ret = op_cpu_disable(cpu);
  264. if (ret)
  265. return ret;
  266. /*
  267. * Take this CPU offline. Once we clear this, we can't return,
  268. * and we must not schedule until we're ready to give up the cpu.
  269. */
  270. set_cpu_online(cpu, false);
  271. /*
  272. * OK - migrate IRQs away from this CPU
  273. */
  274. irq_migrate_all_off_this_cpu();
  275. return 0;
  276. }
  277. static int op_cpu_kill(unsigned int cpu)
  278. {
  279. /*
  280. * If we have no means of synchronising with the dying CPU, then assume
  281. * that it is really dead. We can only wait for an arbitrary length of
  282. * time and hope that it's dead, so let's skip the wait and just hope.
  283. */
  284. if (!cpu_ops[cpu]->cpu_kill)
  285. return 0;
  286. return cpu_ops[cpu]->cpu_kill(cpu);
  287. }
  288. /*
  289. * called on the thread which is asking for a CPU to be shutdown -
  290. * waits until shutdown has completed, or it is timed out.
  291. */
  292. void __cpu_die(unsigned int cpu)
  293. {
  294. int err;
  295. if (!cpu_wait_death(cpu, 5)) {
  296. pr_crit("CPU%u: cpu didn't die\n", cpu);
  297. return;
  298. }
  299. pr_notice("CPU%u: shutdown\n", cpu);
  300. /*
  301. * Now that the dying CPU is beyond the point of no return w.r.t.
  302. * in-kernel synchronisation, try to get the firwmare to help us to
  303. * verify that it has really left the kernel before we consider
  304. * clobbering anything it might still be using.
  305. */
  306. err = op_cpu_kill(cpu);
  307. if (err)
  308. pr_warn("CPU%d may not have shut down cleanly: %d\n",
  309. cpu, err);
  310. }
  311. /*
  312. * Called from the idle thread for the CPU which has been shutdown.
  313. *
  314. * Note that we disable IRQs here, but do not re-enable them
  315. * before returning to the caller. This is also the behaviour
  316. * of the other hotplug-cpu capable cores, so presumably coming
  317. * out of idle fixes this.
  318. */
  319. void cpu_die(void)
  320. {
  321. unsigned int cpu = smp_processor_id();
  322. idle_task_exit();
  323. local_irq_disable();
  324. /* Tell __cpu_die() that this CPU is now safe to dispose of */
  325. (void)cpu_report_death();
  326. /*
  327. * Actually shutdown the CPU. This must never fail. The specific hotplug
  328. * mechanism must perform all required cache maintenance to ensure that
  329. * no dirty lines are lost in the process of shutting down the CPU.
  330. */
  331. cpu_ops[cpu]->cpu_die(cpu);
  332. BUG();
  333. }
  334. #endif
  335. /*
  336. * Kill the calling secondary CPU, early in bringup before it is turned
  337. * online.
  338. */
  339. void cpu_die_early(void)
  340. {
  341. int cpu = smp_processor_id();
  342. pr_crit("CPU%d: will not boot\n", cpu);
  343. /* Mark this CPU absent */
  344. set_cpu_present(cpu, 0);
  345. #ifdef CONFIG_HOTPLUG_CPU
  346. update_cpu_boot_status(CPU_KILL_ME);
  347. /* Check if we can park ourselves */
  348. if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die)
  349. cpu_ops[cpu]->cpu_die(cpu);
  350. #endif
  351. update_cpu_boot_status(CPU_STUCK_IN_KERNEL);
  352. cpu_park_loop();
  353. }
  354. static void __init hyp_mode_check(void)
  355. {
  356. if (is_hyp_mode_available())
  357. pr_info("CPU: All CPU(s) started at EL2\n");
  358. else if (is_hyp_mode_mismatched())
  359. WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC,
  360. "CPU: CPUs started in inconsistent modes");
  361. else
  362. pr_info("CPU: All CPU(s) started at EL1\n");
  363. }
  364. void __init smp_cpus_done(unsigned int max_cpus)
  365. {
  366. pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
  367. setup_cpu_features();
  368. hyp_mode_check();
  369. apply_alternatives_all();
  370. }
  371. void __init smp_prepare_boot_cpu(void)
  372. {
  373. set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
  374. /*
  375. * Initialise the static keys early as they may be enabled by the
  376. * cpufeature code.
  377. */
  378. jump_label_init();
  379. cpuinfo_store_boot_cpu();
  380. save_boot_cpu_run_el();
  381. /*
  382. * Run the errata work around checks on the boot CPU, once we have
  383. * initialised the cpu feature infrastructure from
  384. * cpuinfo_store_boot_cpu() above.
  385. */
  386. update_cpu_errata_workarounds();
  387. }
  388. static u64 __init of_get_cpu_mpidr(struct device_node *dn)
  389. {
  390. const __be32 *cell;
  391. u64 hwid;
  392. /*
  393. * A cpu node with missing "reg" property is
  394. * considered invalid to build a cpu_logical_map
  395. * entry.
  396. */
  397. cell = of_get_property(dn, "reg", NULL);
  398. if (!cell) {
  399. pr_err("%s: missing reg property\n", dn->full_name);
  400. return INVALID_HWID;
  401. }
  402. hwid = of_read_number(cell, of_n_addr_cells(dn));
  403. /*
  404. * Non affinity bits must be set to 0 in the DT
  405. */
  406. if (hwid & ~MPIDR_HWID_BITMASK) {
  407. pr_err("%s: invalid reg property\n", dn->full_name);
  408. return INVALID_HWID;
  409. }
  410. return hwid;
  411. }
  412. /*
  413. * Duplicate MPIDRs are a recipe for disaster. Scan all initialized
  414. * entries and check for duplicates. If any is found just ignore the
  415. * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid
  416. * matching valid MPIDR values.
  417. */
  418. static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid)
  419. {
  420. unsigned int i;
  421. for (i = 1; (i < cpu) && (i < NR_CPUS); i++)
  422. if (cpu_logical_map(i) == hwid)
  423. return true;
  424. return false;
  425. }
  426. /*
  427. * Initialize cpu operations for a logical cpu and
  428. * set it in the possible mask on success
  429. */
  430. static int __init smp_cpu_setup(int cpu)
  431. {
  432. if (cpu_read_ops(cpu))
  433. return -ENODEV;
  434. if (cpu_ops[cpu]->cpu_init(cpu))
  435. return -ENODEV;
  436. set_cpu_possible(cpu, true);
  437. return 0;
  438. }
  439. static bool bootcpu_valid __initdata;
  440. static unsigned int cpu_count = 1;
  441. #ifdef CONFIG_ACPI
  442. /*
  443. * acpi_map_gic_cpu_interface - parse processor MADT entry
  444. *
  445. * Carry out sanity checks on MADT processor entry and initialize
  446. * cpu_logical_map on success
  447. */
  448. static void __init
  449. acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
  450. {
  451. u64 hwid = processor->arm_mpidr;
  452. if (!(processor->flags & ACPI_MADT_ENABLED)) {
  453. pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
  454. return;
  455. }
  456. if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) {
  457. pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid);
  458. return;
  459. }
  460. if (is_mpidr_duplicate(cpu_count, hwid)) {
  461. pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid);
  462. return;
  463. }
  464. /* Check if GICC structure of boot CPU is available in the MADT */
  465. if (cpu_logical_map(0) == hwid) {
  466. if (bootcpu_valid) {
  467. pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n",
  468. hwid);
  469. return;
  470. }
  471. bootcpu_valid = true;
  472. early_map_cpu_to_node(0, acpi_numa_get_nid(0, hwid));
  473. return;
  474. }
  475. if (cpu_count >= NR_CPUS)
  476. return;
  477. /* map the logical cpu id to cpu MPIDR */
  478. cpu_logical_map(cpu_count) = hwid;
  479. /*
  480. * Set-up the ACPI parking protocol cpu entries
  481. * while initializing the cpu_logical_map to
  482. * avoid parsing MADT entries multiple times for
  483. * nothing (ie a valid cpu_logical_map entry should
  484. * contain a valid parking protocol data set to
  485. * initialize the cpu if the parking protocol is
  486. * the only available enable method).
  487. */
  488. acpi_set_mailbox_entry(cpu_count, processor);
  489. early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid));
  490. cpu_count++;
  491. }
  492. static int __init
  493. acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
  494. const unsigned long end)
  495. {
  496. struct acpi_madt_generic_interrupt *processor;
  497. processor = (struct acpi_madt_generic_interrupt *)header;
  498. if (BAD_MADT_GICC_ENTRY(processor, end))
  499. return -EINVAL;
  500. acpi_table_print_madt_entry(header);
  501. acpi_map_gic_cpu_interface(processor);
  502. return 0;
  503. }
  504. #else
  505. #define acpi_table_parse_madt(...) do { } while (0)
  506. #endif
  507. /*
  508. * Enumerate the possible CPU set from the device tree and build the
  509. * cpu logical map array containing MPIDR values related to logical
  510. * cpus. Assumes that cpu_logical_map(0) has already been initialized.
  511. */
  512. static void __init of_parse_and_init_cpus(void)
  513. {
  514. struct device_node *dn = NULL;
  515. while ((dn = of_find_node_by_type(dn, "cpu"))) {
  516. u64 hwid = of_get_cpu_mpidr(dn);
  517. if (hwid == INVALID_HWID)
  518. goto next;
  519. if (is_mpidr_duplicate(cpu_count, hwid)) {
  520. pr_err("%s: duplicate cpu reg properties in the DT\n",
  521. dn->full_name);
  522. goto next;
  523. }
  524. /*
  525. * The numbering scheme requires that the boot CPU
  526. * must be assigned logical id 0. Record it so that
  527. * the logical map built from DT is validated and can
  528. * be used.
  529. */
  530. if (hwid == cpu_logical_map(0)) {
  531. if (bootcpu_valid) {
  532. pr_err("%s: duplicate boot cpu reg property in DT\n",
  533. dn->full_name);
  534. goto next;
  535. }
  536. bootcpu_valid = true;
  537. early_map_cpu_to_node(0, of_node_to_nid(dn));
  538. /*
  539. * cpu_logical_map has already been
  540. * initialized and the boot cpu doesn't need
  541. * the enable-method so continue without
  542. * incrementing cpu.
  543. */
  544. continue;
  545. }
  546. if (cpu_count >= NR_CPUS)
  547. goto next;
  548. pr_debug("cpu logical map 0x%llx\n", hwid);
  549. cpu_logical_map(cpu_count) = hwid;
  550. early_map_cpu_to_node(cpu_count, of_node_to_nid(dn));
  551. next:
  552. cpu_count++;
  553. }
  554. }
  555. /*
  556. * Enumerate the possible CPU set from the device tree or ACPI and build the
  557. * cpu logical map array containing MPIDR values related to logical
  558. * cpus. Assumes that cpu_logical_map(0) has already been initialized.
  559. */
  560. void __init smp_init_cpus(void)
  561. {
  562. int i;
  563. if (acpi_disabled)
  564. of_parse_and_init_cpus();
  565. else
  566. /*
  567. * do a walk of MADT to determine how many CPUs
  568. * we have including disabled CPUs, and get information
  569. * we need for SMP init
  570. */
  571. acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
  572. acpi_parse_gic_cpu_interface, 0);
  573. if (cpu_count > nr_cpu_ids)
  574. pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n",
  575. cpu_count, nr_cpu_ids);
  576. if (!bootcpu_valid) {
  577. pr_err("missing boot CPU MPIDR, not enabling secondaries\n");
  578. return;
  579. }
  580. /*
  581. * We need to set the cpu_logical_map entries before enabling
  582. * the cpus so that cpu processor description entries (DT cpu nodes
  583. * and ACPI MADT entries) can be retrieved by matching the cpu hwid
  584. * with entries in cpu_logical_map while initializing the cpus.
  585. * If the cpu set-up fails, invalidate the cpu_logical_map entry.
  586. */
  587. for (i = 1; i < nr_cpu_ids; i++) {
  588. if (cpu_logical_map(i) != INVALID_HWID) {
  589. if (smp_cpu_setup(i))
  590. cpu_logical_map(i) = INVALID_HWID;
  591. }
  592. }
  593. }
  594. void __init smp_prepare_cpus(unsigned int max_cpus)
  595. {
  596. int err;
  597. unsigned int cpu;
  598. unsigned int this_cpu;
  599. init_cpu_topology();
  600. this_cpu = smp_processor_id();
  601. store_cpu_topology(this_cpu);
  602. numa_store_cpu_info(this_cpu);
  603. /*
  604. * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
  605. * secondary CPUs present.
  606. */
  607. if (max_cpus == 0)
  608. return;
  609. /*
  610. * Initialise the present map (which describes the set of CPUs
  611. * actually populated at the present time) and release the
  612. * secondaries from the bootloader.
  613. */
  614. for_each_possible_cpu(cpu) {
  615. per_cpu(cpu_number, cpu) = cpu;
  616. if (cpu == smp_processor_id())
  617. continue;
  618. if (!cpu_ops[cpu])
  619. continue;
  620. err = cpu_ops[cpu]->cpu_prepare(cpu);
  621. if (err)
  622. continue;
  623. set_cpu_present(cpu, true);
  624. numa_store_cpu_info(cpu);
  625. }
  626. }
  627. void (*__smp_cross_call)(const struct cpumask *, unsigned int);
  628. void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
  629. {
  630. __smp_cross_call = fn;
  631. }
  632. static const char *ipi_types[NR_IPI] __tracepoint_string = {
  633. #define S(x,s) [x] = s
  634. S(IPI_RESCHEDULE, "Rescheduling interrupts"),
  635. S(IPI_CALL_FUNC, "Function call interrupts"),
  636. S(IPI_CPU_STOP, "CPU stop interrupts"),
  637. S(IPI_TIMER, "Timer broadcast interrupts"),
  638. S(IPI_IRQ_WORK, "IRQ work interrupts"),
  639. S(IPI_WAKEUP, "CPU wake-up interrupts"),
  640. };
  641. static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
  642. {
  643. trace_ipi_raise(target, ipi_types[ipinr]);
  644. __smp_cross_call(target, ipinr);
  645. }
  646. void show_ipi_list(struct seq_file *p, int prec)
  647. {
  648. unsigned int cpu, i;
  649. for (i = 0; i < NR_IPI; i++) {
  650. seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
  651. prec >= 4 ? " " : "");
  652. for_each_online_cpu(cpu)
  653. seq_printf(p, "%10u ",
  654. __get_irq_stat(cpu, ipi_irqs[i]));
  655. seq_printf(p, " %s\n", ipi_types[i]);
  656. }
  657. }
  658. u64 smp_irq_stat_cpu(unsigned int cpu)
  659. {
  660. u64 sum = 0;
  661. int i;
  662. for (i = 0; i < NR_IPI; i++)
  663. sum += __get_irq_stat(cpu, ipi_irqs[i]);
  664. return sum;
  665. }
  666. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  667. {
  668. smp_cross_call(mask, IPI_CALL_FUNC);
  669. }
  670. void arch_send_call_function_single_ipi(int cpu)
  671. {
  672. smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
  673. }
  674. #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
  675. void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
  676. {
  677. smp_cross_call(mask, IPI_WAKEUP);
  678. }
  679. #endif
  680. #ifdef CONFIG_IRQ_WORK
  681. void arch_irq_work_raise(void)
  682. {
  683. if (__smp_cross_call)
  684. smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
  685. }
  686. #endif
  687. /*
  688. * ipi_cpu_stop - handle IPI from smp_send_stop()
  689. */
  690. static void ipi_cpu_stop(unsigned int cpu)
  691. {
  692. set_cpu_online(cpu, false);
  693. local_irq_disable();
  694. while (1)
  695. cpu_relax();
  696. }
  697. /*
  698. * Main handler for inter-processor interrupts
  699. */
  700. void handle_IPI(int ipinr, struct pt_regs *regs)
  701. {
  702. unsigned int cpu = smp_processor_id();
  703. struct pt_regs *old_regs = set_irq_regs(regs);
  704. if ((unsigned)ipinr < NR_IPI) {
  705. trace_ipi_entry_rcuidle(ipi_types[ipinr]);
  706. __inc_irq_stat(cpu, ipi_irqs[ipinr]);
  707. }
  708. switch (ipinr) {
  709. case IPI_RESCHEDULE:
  710. scheduler_ipi();
  711. break;
  712. case IPI_CALL_FUNC:
  713. irq_enter();
  714. generic_smp_call_function_interrupt();
  715. irq_exit();
  716. break;
  717. case IPI_CPU_STOP:
  718. irq_enter();
  719. ipi_cpu_stop(cpu);
  720. irq_exit();
  721. break;
  722. #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
  723. case IPI_TIMER:
  724. irq_enter();
  725. tick_receive_broadcast();
  726. irq_exit();
  727. break;
  728. #endif
  729. #ifdef CONFIG_IRQ_WORK
  730. case IPI_IRQ_WORK:
  731. irq_enter();
  732. irq_work_run();
  733. irq_exit();
  734. break;
  735. #endif
  736. #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL
  737. case IPI_WAKEUP:
  738. WARN_ONCE(!acpi_parking_protocol_valid(cpu),
  739. "CPU%u: Wake-up IPI outside the ACPI parking protocol\n",
  740. cpu);
  741. break;
  742. #endif
  743. default:
  744. pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
  745. break;
  746. }
  747. if ((unsigned)ipinr < NR_IPI)
  748. trace_ipi_exit_rcuidle(ipi_types[ipinr]);
  749. set_irq_regs(old_regs);
  750. }
  751. void smp_send_reschedule(int cpu)
  752. {
  753. smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
  754. }
  755. #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
  756. void tick_broadcast(const struct cpumask *mask)
  757. {
  758. smp_cross_call(mask, IPI_TIMER);
  759. }
  760. #endif
  761. void smp_send_stop(void)
  762. {
  763. unsigned long timeout;
  764. if (num_online_cpus() > 1) {
  765. cpumask_t mask;
  766. cpumask_copy(&mask, cpu_online_mask);
  767. cpumask_clear_cpu(smp_processor_id(), &mask);
  768. if (system_state == SYSTEM_BOOTING ||
  769. system_state == SYSTEM_RUNNING)
  770. pr_crit("SMP: stopping secondary CPUs\n");
  771. smp_cross_call(&mask, IPI_CPU_STOP);
  772. }
  773. /* Wait up to one second for other CPUs to stop */
  774. timeout = USEC_PER_SEC;
  775. while (num_online_cpus() > 1 && timeout--)
  776. udelay(1);
  777. if (num_online_cpus() > 1)
  778. pr_warning("SMP: failed to stop secondary CPUs %*pbl\n",
  779. cpumask_pr_args(cpu_online_mask));
  780. }
  781. /*
  782. * not supported here
  783. */
  784. int setup_profiling_timer(unsigned int multiplier)
  785. {
  786. return -EINVAL;
  787. }
  788. static bool have_cpu_die(void)
  789. {
  790. #ifdef CONFIG_HOTPLUG_CPU
  791. int any_cpu = raw_smp_processor_id();
  792. if (cpu_ops[any_cpu]->cpu_die)
  793. return true;
  794. #endif
  795. return false;
  796. }
  797. bool cpus_are_stuck_in_kernel(void)
  798. {
  799. bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die());
  800. return !!cpus_stuck_in_kernel || smp_spin_tables;
  801. }