tegra210-smaug.dts 55 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/mfd/max77620.h>
  4. #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  5. #include "tegra210.dtsi"
  6. / {
  7. model = "Google Pixel C";
  8. compatible = "google,smaug-rev8", "google,smaug-rev7",
  9. "google,smaug-rev6", "google,smaug-rev5",
  10. "google,smaug-rev4", "google,smaug-rev3",
  11. "google,smaug-rev2", "google,smaug-rev1",
  12. "google,smaug", "nvidia,tegra210";
  13. aliases {
  14. serial0 = &uarta;
  15. };
  16. chosen {
  17. bootargs = "earlycon";
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory {
  21. device_type = "memory";
  22. reg = <0x0 0x80000000 0x0 0xc0000000>;
  23. };
  24. host1x@50000000 {
  25. dpaux: dpaux@545c0000 {
  26. status = "okay";
  27. };
  28. };
  29. pinmux: pinmux@700008d4 {
  30. pinctrl-names = "boot";
  31. pinctrl-0 = <&state_boot>;
  32. state_boot: pinmux {
  33. pex_l0_rst_n_pa0 {
  34. nvidia,pins = "pex_l0_rst_n_pa0";
  35. nvidia,function = "rsvd1";
  36. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  37. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  38. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  39. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  40. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  41. };
  42. pex_l0_clkreq_n_pa1 {
  43. nvidia,pins = "pex_l0_clkreq_n_pa1";
  44. nvidia,function = "rsvd1";
  45. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  46. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  47. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  48. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  49. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  50. };
  51. pex_wake_n_pa2 {
  52. nvidia,pins = "pex_wake_n_pa2";
  53. nvidia,function = "rsvd1";
  54. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  55. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  56. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  57. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  58. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  59. };
  60. pex_l1_rst_n_pa3 {
  61. nvidia,pins = "pex_l1_rst_n_pa3";
  62. nvidia,function = "rsvd1";
  63. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  64. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  65. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  66. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  67. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  68. };
  69. pex_l1_clkreq_n_pa4 {
  70. nvidia,pins = "pex_l1_clkreq_n_pa4";
  71. nvidia,function = "rsvd1";
  72. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  73. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  74. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  75. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  76. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  77. };
  78. sata_led_active_pa5 {
  79. nvidia,pins = "sata_led_active_pa5";
  80. nvidia,function = "rsvd1";
  81. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  82. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  83. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  84. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  85. };
  86. pa6 {
  87. nvidia,pins = "pa6";
  88. nvidia,function = "rsvd1";
  89. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  92. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  93. };
  94. dap1_fs_pb0 {
  95. nvidia,pins = "dap1_fs_pb0";
  96. nvidia,function = "i2s1";
  97. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  98. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  99. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  100. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  101. };
  102. dap1_din_pb1 {
  103. nvidia,pins = "dap1_din_pb1";
  104. nvidia,function = "i2s1";
  105. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  107. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  108. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  109. };
  110. dap1_dout_pb2 {
  111. nvidia,pins = "dap1_dout_pb2";
  112. nvidia,function = "i2s1";
  113. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  114. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  116. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  117. };
  118. dap1_sclk_pb3 {
  119. nvidia,pins = "dap1_sclk_pb3";
  120. nvidia,function = "i2s1";
  121. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  122. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  124. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  125. };
  126. spi2_mosi_pb4 {
  127. nvidia,pins = "spi2_mosi_pb4";
  128. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  130. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  131. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  132. };
  133. spi2_miso_pb5 {
  134. nvidia,pins = "spi2_miso_pb5";
  135. nvidia,function = "rsvd2";
  136. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  137. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  138. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  139. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  140. };
  141. spi2_sck_pb6 {
  142. nvidia,pins = "spi2_sck_pb6";
  143. nvidia,function = "rsvd2";
  144. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  145. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  146. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  147. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  148. };
  149. spi2_cs0_pb7 {
  150. nvidia,pins = "spi2_cs0_pb7";
  151. nvidia,function = "rsvd2";
  152. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  153. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  154. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  155. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  156. };
  157. spi1_mosi_pc0 {
  158. nvidia,pins = "spi1_mosi_pc0";
  159. nvidia,function = "spi1";
  160. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  161. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  162. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  163. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  164. };
  165. spi1_miso_pc1 {
  166. nvidia,pins = "spi1_miso_pc1";
  167. nvidia,function = "spi1";
  168. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  169. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  170. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  171. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  172. };
  173. spi1_sck_pc2 {
  174. nvidia,pins = "spi1_sck_pc2";
  175. nvidia,function = "spi1";
  176. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  177. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  178. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  179. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  180. };
  181. spi1_cs0_pc3 {
  182. nvidia,pins = "spi1_cs0_pc3";
  183. nvidia,function = "spi1";
  184. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  185. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  186. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  187. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  188. };
  189. spi1_cs1_pc4 {
  190. nvidia,pins = "spi1_cs1_pc4";
  191. nvidia,function = "rsvd1";
  192. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  193. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  194. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  195. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  196. };
  197. spi4_sck_pc5 {
  198. nvidia,pins = "spi4_sck_pc5";
  199. nvidia,function = "rsvd1";
  200. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  201. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  202. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  203. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  204. };
  205. spi4_cs0_pc6 {
  206. nvidia,pins = "spi4_cs0_pc6";
  207. nvidia,function = "rsvd1";
  208. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  209. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  210. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  211. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  212. };
  213. spi4_mosi_pc7 {
  214. nvidia,pins = "spi4_mosi_pc7";
  215. nvidia,function = "rsvd1";
  216. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  217. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  218. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  219. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  220. };
  221. spi4_miso_pd0 {
  222. nvidia,pins = "spi4_miso_pd0";
  223. nvidia,function = "rsvd1";
  224. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  225. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  226. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  227. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  228. };
  229. uart3_tx_pd1 {
  230. nvidia,pins = "uart3_tx_pd1";
  231. nvidia,function = "uartc";
  232. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  233. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  234. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  235. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  236. };
  237. uart3_rx_pd2 {
  238. nvidia,pins = "uart3_rx_pd2";
  239. nvidia,function = "uartc";
  240. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  241. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  242. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  243. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  244. };
  245. uart3_rts_pd3 {
  246. nvidia,pins = "uart3_rts_pd3";
  247. nvidia,function = "uartc";
  248. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  249. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  250. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  251. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  252. };
  253. uart3_cts_pd4 {
  254. nvidia,pins = "uart3_cts_pd4";
  255. nvidia,function = "uartc";
  256. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  257. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  258. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  259. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  260. };
  261. dmic1_clk_pe0 {
  262. nvidia,pins = "dmic1_clk_pe0";
  263. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  264. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  265. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  266. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  267. };
  268. dmic1_dat_pe1 {
  269. nvidia,pins = "dmic1_dat_pe1";
  270. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  271. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  272. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  273. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  274. };
  275. dmic2_clk_pe2 {
  276. nvidia,pins = "dmic2_clk_pe2";
  277. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  278. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  279. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  280. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  281. };
  282. dmic2_dat_pe3 {
  283. nvidia,pins = "dmic2_dat_pe3";
  284. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  285. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  286. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  287. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  288. };
  289. dmic3_clk_pe4 {
  290. nvidia,pins = "dmic3_clk_pe4";
  291. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  292. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  293. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  294. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  295. };
  296. dmic3_dat_pe5 {
  297. nvidia,pins = "dmic3_dat_pe5";
  298. nvidia,function = "rsvd2";
  299. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  300. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  301. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  302. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  303. };
  304. pe6 {
  305. nvidia,pins = "pe6";
  306. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  307. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  308. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  309. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  310. };
  311. pe7 {
  312. nvidia,pins = "pe7";
  313. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  314. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  315. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  316. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  317. };
  318. gen3_i2c_scl_pf0 {
  319. nvidia,pins = "gen3_i2c_scl_pf0";
  320. nvidia,function = "i2c3";
  321. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  322. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  323. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  324. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  325. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  326. };
  327. gen3_i2c_sda_pf1 {
  328. nvidia,pins = "gen3_i2c_sda_pf1";
  329. nvidia,function = "i2c3";
  330. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  331. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  332. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  333. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  334. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  335. };
  336. uart2_tx_pg0 {
  337. nvidia,pins = "uart2_tx_pg0";
  338. nvidia,function = "uartb";
  339. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  340. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  341. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  342. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  343. };
  344. uart2_rx_pg1 {
  345. nvidia,pins = "uart2_rx_pg1";
  346. nvidia,function = "uartb";
  347. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  348. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  349. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  350. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  351. };
  352. uart2_rts_pg2 {
  353. nvidia,pins = "uart2_rts_pg2";
  354. nvidia,function = "rsvd2";
  355. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  356. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  357. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  358. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  359. };
  360. uart2_cts_pg3 {
  361. nvidia,pins = "uart2_cts_pg3";
  362. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  363. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  364. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  365. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  366. };
  367. wifi_en_ph0 {
  368. nvidia,pins = "wifi_en_ph0";
  369. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  370. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  371. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  372. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  373. };
  374. wifi_rst_ph1 {
  375. nvidia,pins = "wifi_rst_ph1";
  376. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  377. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  378. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  379. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  380. };
  381. wifi_wake_ap_ph2 {
  382. nvidia,pins = "wifi_wake_ap_ph2";
  383. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  384. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  385. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  386. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  387. };
  388. ap_wake_bt_ph3 {
  389. nvidia,pins = "ap_wake_bt_ph3";
  390. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  391. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  392. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  393. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  394. };
  395. bt_rst_ph4 {
  396. nvidia,pins = "bt_rst_ph4";
  397. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  398. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  399. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  400. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  401. };
  402. bt_wake_ap_ph5 {
  403. nvidia,pins = "bt_wake_ap_ph5";
  404. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  405. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  406. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  407. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  408. };
  409. ph6 {
  410. nvidia,pins = "ph6";
  411. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  412. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  413. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  414. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  415. };
  416. ap_wake_nfc_ph7 {
  417. nvidia,pins = "ap_wake_nfc_ph7";
  418. nvidia,function = "rsvd0";
  419. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  420. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  421. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  422. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  423. };
  424. nfc_en_pi0 {
  425. nvidia,pins = "nfc_en_pi0";
  426. nvidia,function = "rsvd0";
  427. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  428. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  429. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  430. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  431. };
  432. nfc_int_pi1 {
  433. nvidia,pins = "nfc_int_pi1";
  434. nvidia,function = "rsvd0";
  435. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  436. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  437. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  438. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  439. };
  440. gps_en_pi2 {
  441. nvidia,pins = "gps_en_pi2";
  442. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  443. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  444. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  445. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  446. };
  447. gps_rst_pi3 {
  448. nvidia,pins = "gps_rst_pi3";
  449. nvidia,function = "rsvd0";
  450. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  451. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  452. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  453. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  454. };
  455. uart4_tx_pi4 {
  456. nvidia,pins = "uart4_tx_pi4";
  457. nvidia,function = "uartd";
  458. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  459. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  460. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  461. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  462. };
  463. uart4_rx_pi5 {
  464. nvidia,pins = "uart4_rx_pi5";
  465. nvidia,function = "uartd";
  466. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  467. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  468. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  469. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  470. };
  471. uart4_rts_pi6 {
  472. nvidia,pins = "uart4_rts_pi6";
  473. nvidia,function = "uartd";
  474. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  475. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  476. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  477. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  478. };
  479. uart4_cts_pi7 {
  480. nvidia,pins = "uart4_cts_pi7";
  481. nvidia,function = "uartd";
  482. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  483. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  484. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  485. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  486. };
  487. gen1_i2c_sda_pj0 {
  488. nvidia,pins = "gen1_i2c_sda_pj0";
  489. nvidia,function = "i2c1";
  490. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  491. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  492. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  493. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  494. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  495. };
  496. gen1_i2c_scl_pj1 {
  497. nvidia,pins = "gen1_i2c_scl_pj1";
  498. nvidia,function = "i2c1";
  499. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  500. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  501. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  502. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  503. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  504. };
  505. gen2_i2c_scl_pj2 {
  506. nvidia,pins = "gen2_i2c_scl_pj2";
  507. nvidia,function = "i2c2";
  508. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  509. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  510. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  511. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  512. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  513. };
  514. gen2_i2c_sda_pj3 {
  515. nvidia,pins = "gen2_i2c_sda_pj3";
  516. nvidia,function = "i2c2";
  517. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  518. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  519. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  520. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  521. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  522. };
  523. dap4_fs_pj4 {
  524. nvidia,pins = "dap4_fs_pj4";
  525. nvidia,function = "rsvd1";
  526. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  527. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  528. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  529. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  530. };
  531. dap4_din_pj5 {
  532. nvidia,pins = "dap4_din_pj5";
  533. nvidia,function = "rsvd1";
  534. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  535. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  536. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  537. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  538. };
  539. dap4_dout_pj6 {
  540. nvidia,pins = "dap4_dout_pj6";
  541. nvidia,function = "rsvd1";
  542. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  543. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  544. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  545. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  546. };
  547. dap4_sclk_pj7 {
  548. nvidia,pins = "dap4_sclk_pj7";
  549. nvidia,function = "rsvd1";
  550. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  551. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  552. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  553. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  554. };
  555. pk0 {
  556. nvidia,pins = "pk0";
  557. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  558. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  559. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  560. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  561. };
  562. pk1 {
  563. nvidia,pins = "pk1";
  564. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  565. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  566. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  567. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  568. };
  569. pk2 {
  570. nvidia,pins = "pk2";
  571. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  572. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  573. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  574. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  575. };
  576. pk3 {
  577. nvidia,pins = "pk3";
  578. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  579. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  580. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  581. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  582. };
  583. pk4 {
  584. nvidia,pins = "pk4";
  585. nvidia,function = "rsvd1";
  586. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  587. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  588. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  589. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  590. };
  591. pk5 {
  592. nvidia,pins = "pk5";
  593. nvidia,function = "rsvd1";
  594. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  595. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  596. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  597. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  598. };
  599. pk6 {
  600. nvidia,pins = "pk6";
  601. nvidia,function = "rsvd1";
  602. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  603. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  604. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  605. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  606. };
  607. pk7 {
  608. nvidia,pins = "pk7";
  609. nvidia,function = "rsvd1";
  610. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  611. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  612. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  613. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  614. };
  615. pl0 {
  616. nvidia,pins = "pl0";
  617. nvidia,function = "rsvd0";
  618. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  619. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  620. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  621. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  622. };
  623. pl1 {
  624. nvidia,pins = "pl1";
  625. nvidia,function = "rsvd1";
  626. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  627. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  628. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  629. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  630. };
  631. sdmmc1_clk_pm0 {
  632. nvidia,pins = "sdmmc1_clk_pm0";
  633. nvidia,function = "rsvd1";
  634. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  635. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  636. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  637. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  638. };
  639. sdmmc1_cmd_pm1 {
  640. nvidia,pins = "sdmmc1_cmd_pm1";
  641. nvidia,function = "rsvd2";
  642. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  643. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  644. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  645. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  646. };
  647. sdmmc1_dat3_pm2 {
  648. nvidia,pins = "sdmmc1_dat3_pm2";
  649. nvidia,function = "rsvd2";
  650. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  651. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  652. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  653. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  654. };
  655. sdmmc1_dat2_pm3 {
  656. nvidia,pins = "sdmmc1_dat2_pm3";
  657. nvidia,function = "rsvd2";
  658. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  659. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  660. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  661. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  662. };
  663. sdmmc1_dat1_pm4 {
  664. nvidia,pins = "sdmmc1_dat1_pm4";
  665. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  666. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  667. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  668. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  669. };
  670. sdmmc1_dat0_pm5 {
  671. nvidia,pins = "sdmmc1_dat0_pm5";
  672. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  673. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  674. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  675. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  676. };
  677. sdmmc3_clk_pp0 {
  678. nvidia,pins = "sdmmc3_clk_pp0";
  679. nvidia,function = "rsvd1";
  680. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  681. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  682. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  683. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  684. };
  685. sdmmc3_cmd_pp1 {
  686. nvidia,pins = "sdmmc3_cmd_pp1";
  687. nvidia,function = "rsvd1";
  688. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  689. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  690. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  691. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  692. };
  693. sdmmc3_dat3_pp2 {
  694. nvidia,pins = "sdmmc3_dat3_pp2";
  695. nvidia,function = "rsvd1";
  696. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  697. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  698. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  699. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  700. };
  701. sdmmc3_dat2_pp3 {
  702. nvidia,pins = "sdmmc3_dat2_pp3";
  703. nvidia,function = "rsvd1";
  704. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  705. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  706. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  707. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  708. };
  709. sdmmc3_dat1_pp4 {
  710. nvidia,pins = "sdmmc3_dat1_pp4";
  711. nvidia,function = "rsvd1";
  712. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  713. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  714. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  715. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  716. };
  717. sdmmc3_dat0_pp5 {
  718. nvidia,pins = "sdmmc3_dat0_pp5";
  719. nvidia,function = "rsvd1";
  720. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  721. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  722. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  723. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  724. };
  725. cam1_mclk_ps0 {
  726. nvidia,pins = "cam1_mclk_ps0";
  727. nvidia,function = "extperiph3";
  728. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  729. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  730. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  731. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  732. };
  733. cam2_mclk_ps1 {
  734. nvidia,pins = "cam2_mclk_ps1";
  735. nvidia,function = "extperiph3";
  736. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  737. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  738. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  739. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  740. };
  741. cam_i2c_scl_ps2 {
  742. nvidia,pins = "cam_i2c_scl_ps2";
  743. nvidia,function = "i2cvi";
  744. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  745. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  746. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  747. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  748. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  749. };
  750. cam_i2c_sda_ps3 {
  751. nvidia,pins = "cam_i2c_sda_ps3";
  752. nvidia,function = "i2cvi";
  753. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  754. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  755. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  756. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  757. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  758. };
  759. cam_rst_ps4 {
  760. nvidia,pins = "cam_rst_ps4";
  761. nvidia,function = "rsvd1";
  762. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  763. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  764. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  765. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  766. };
  767. cam_af_en_ps5 {
  768. nvidia,pins = "cam_af_en_ps5";
  769. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  770. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  771. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  772. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  773. };
  774. cam_flash_en_ps6 {
  775. nvidia,pins = "cam_flash_en_ps6";
  776. nvidia,function = "rsvd2";
  777. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  778. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  779. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  780. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  781. };
  782. cam1_pwdn_ps7 {
  783. nvidia,pins = "cam1_pwdn_ps7";
  784. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  785. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  786. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  787. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  788. };
  789. cam2_pwdn_pt0 {
  790. nvidia,pins = "cam2_pwdn_pt0";
  791. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  792. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  793. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  794. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  795. };
  796. cam1_strobe_pt1 {
  797. nvidia,pins = "cam1_strobe_pt1";
  798. nvidia,function = "rsvd1";
  799. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  800. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  801. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  802. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  803. };
  804. uart1_tx_pu0 {
  805. nvidia,pins = "uart1_tx_pu0";
  806. nvidia,function = "uarta";
  807. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  808. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  809. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  810. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  811. };
  812. uart1_rx_pu1 {
  813. nvidia,pins = "uart1_rx_pu1";
  814. nvidia,function = "uarta";
  815. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  816. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  817. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  818. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  819. };
  820. uart1_rts_pu2 {
  821. nvidia,pins = "uart1_rts_pu2";
  822. nvidia,function = "rsvd1";
  823. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  824. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  825. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  826. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  827. };
  828. uart1_cts_pu3 {
  829. nvidia,pins = "uart1_cts_pu3";
  830. nvidia,function = "rsvd1";
  831. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  832. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  833. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  834. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  835. };
  836. lcd_bl_pwm_pv0 {
  837. nvidia,pins = "lcd_bl_pwm_pv0";
  838. nvidia,function = "rsvd3";
  839. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  840. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  841. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  842. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  843. };
  844. lcd_bl_en_pv1 {
  845. nvidia,pins = "lcd_bl_en_pv1";
  846. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  847. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  848. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  849. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  850. };
  851. lcd_rst_pv2 {
  852. nvidia,pins = "lcd_rst_pv2";
  853. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  854. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  855. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  856. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  857. };
  858. lcd_gpio1_pv3 {
  859. nvidia,pins = "lcd_gpio1_pv3";
  860. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  861. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  862. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  863. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  864. };
  865. lcd_gpio2_pv4 {
  866. nvidia,pins = "lcd_gpio2_pv4";
  867. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  868. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  869. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  870. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  871. };
  872. ap_ready_pv5 {
  873. nvidia,pins = "ap_ready_pv5";
  874. nvidia,function = "rsvd0";
  875. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  876. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  877. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  878. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  879. };
  880. touch_rst_pv6 {
  881. nvidia,pins = "touch_rst_pv6";
  882. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  883. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  884. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  885. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  886. };
  887. touch_clk_pv7 {
  888. nvidia,pins = "touch_clk_pv7";
  889. nvidia,function = "touch";
  890. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  891. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  892. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  893. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  894. };
  895. modem_wake_ap_px0 {
  896. nvidia,pins = "modem_wake_ap_px0";
  897. nvidia,function = "rsvd0";
  898. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  899. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  900. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  901. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  902. };
  903. touch_int_px1 {
  904. nvidia,pins = "touch_int_px1";
  905. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  906. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  907. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  908. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  909. };
  910. motion_int_px2 {
  911. nvidia,pins = "motion_int_px2";
  912. nvidia,function = "rsvd0";
  913. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  914. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  915. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  916. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  917. };
  918. als_prox_int_px3 {
  919. nvidia,pins = "als_prox_int_px3";
  920. nvidia,function = "rsvd0";
  921. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  922. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  923. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  924. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  925. };
  926. temp_alert_px4 {
  927. nvidia,pins = "temp_alert_px4";
  928. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  929. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  930. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  931. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  932. };
  933. button_power_on_px5 {
  934. nvidia,pins = "button_power_on_px5";
  935. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  936. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  937. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  938. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  939. };
  940. button_vol_up_px6 {
  941. nvidia,pins = "button_vol_up_px6";
  942. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  943. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  944. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  945. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  946. };
  947. button_vol_down_px7 {
  948. nvidia,pins = "button_vol_down_px7";
  949. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  950. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  951. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  952. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  953. };
  954. button_slide_sw_py0 {
  955. nvidia,pins = "button_slide_sw_py0";
  956. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  957. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  958. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  959. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  960. };
  961. button_home_py1 {
  962. nvidia,pins = "button_home_py1";
  963. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  964. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  965. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  966. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  967. };
  968. lcd_te_py2 {
  969. nvidia,pins = "lcd_te_py2";
  970. nvidia,function = "displaya";
  971. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  972. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  973. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  974. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  975. };
  976. pwr_i2c_scl_py3 {
  977. nvidia,pins = "pwr_i2c_scl_py3";
  978. nvidia,function = "i2cpmu";
  979. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  980. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  981. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  982. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  983. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  984. };
  985. pwr_i2c_sda_py4 {
  986. nvidia,pins = "pwr_i2c_sda_py4";
  987. nvidia,function = "i2cpmu";
  988. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  989. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  990. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  991. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  992. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  993. };
  994. clk_32k_out_py5 {
  995. nvidia,pins = "clk_32k_out_py5";
  996. nvidia,function = "soc";
  997. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  998. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  999. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1000. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1001. };
  1002. pz0 {
  1003. nvidia,pins = "pz0";
  1004. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1005. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1006. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1007. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1008. };
  1009. pz1 {
  1010. nvidia,pins = "pz1";
  1011. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1012. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1013. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1014. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1015. };
  1016. pz2 {
  1017. nvidia,pins = "pz2";
  1018. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1019. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1020. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1021. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1022. };
  1023. pz3 {
  1024. nvidia,pins = "pz3";
  1025. nvidia,function = "rsvd1";
  1026. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1027. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1028. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1029. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1030. };
  1031. pz4 {
  1032. nvidia,pins = "pz4";
  1033. nvidia,function = "rsvd1";
  1034. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1035. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1036. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1037. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1038. };
  1039. pz5 {
  1040. nvidia,pins = "pz5";
  1041. nvidia,function = "soc";
  1042. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1043. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1044. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1045. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1046. };
  1047. dap2_fs_paa0 {
  1048. nvidia,pins = "dap2_fs_paa0";
  1049. nvidia,function = "i2s2";
  1050. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1051. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1052. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1053. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1054. };
  1055. dap2_sclk_paa1 {
  1056. nvidia,pins = "dap2_sclk_paa1";
  1057. nvidia,function = "i2s2";
  1058. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1059. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1060. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1061. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1062. };
  1063. dap2_din_paa2 {
  1064. nvidia,pins = "dap2_din_paa2";
  1065. nvidia,function = "i2s2";
  1066. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1067. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1068. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1069. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1070. };
  1071. dap2_dout_paa3 {
  1072. nvidia,pins = "dap2_dout_paa3";
  1073. nvidia,function = "i2s2";
  1074. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1075. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1076. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1077. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1078. };
  1079. aud_mclk_pbb0 {
  1080. nvidia,pins = "aud_mclk_pbb0";
  1081. nvidia,function = "aud";
  1082. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1083. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1084. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1085. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1086. };
  1087. dvfs_pwm_pbb1 {
  1088. nvidia,pins = "dvfs_pwm_pbb1";
  1089. nvidia,function = "rsvd0";
  1090. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1091. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1092. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1093. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1094. };
  1095. dvfs_clk_pbb2 {
  1096. nvidia,pins = "dvfs_clk_pbb2";
  1097. nvidia,function = "rsvd0";
  1098. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1099. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1100. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1101. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1102. };
  1103. gpio_x1_aud_pbb3 {
  1104. nvidia,pins = "gpio_x1_aud_pbb3";
  1105. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1106. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1107. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1108. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1109. };
  1110. gpio_x3_aud_pbb4 {
  1111. nvidia,pins = "gpio_x3_aud_pbb4";
  1112. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1113. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1114. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1115. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1116. };
  1117. hdmi_cec_pcc0 {
  1118. nvidia,pins = "hdmi_cec_pcc0";
  1119. nvidia,function = "rsvd1";
  1120. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1121. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1122. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1123. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1124. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1125. };
  1126. hdmi_int_dp_hpd_pcc1 {
  1127. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1128. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1130. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1131. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1132. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1133. };
  1134. spdif_out_pcc2 {
  1135. nvidia,pins = "spdif_out_pcc2";
  1136. nvidia,function = "rsvd1";
  1137. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1138. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1139. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1141. };
  1142. spdif_in_pcc3 {
  1143. nvidia,pins = "spdif_in_pcc3";
  1144. nvidia,function = "rsvd1";
  1145. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1146. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1147. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1148. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1149. };
  1150. usb_vbus_en0_pcc4 {
  1151. nvidia,pins = "usb_vbus_en0_pcc4";
  1152. nvidia,function = "rsvd1";
  1153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1154. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1155. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1156. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1157. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1158. };
  1159. usb_vbus_en1_pcc5 {
  1160. nvidia,pins = "usb_vbus_en1_pcc5";
  1161. nvidia,function = "rsvd1";
  1162. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1163. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1164. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1165. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1166. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1167. };
  1168. dp_hpd0_pcc6 {
  1169. nvidia,pins = "dp_hpd0_pcc6";
  1170. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1171. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1172. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1173. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1174. };
  1175. pcc7 {
  1176. nvidia,pins = "pcc7";
  1177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1179. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1180. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1181. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1182. };
  1183. spi2_cs1_pdd0 {
  1184. nvidia,pins = "spi2_cs1_pdd0";
  1185. nvidia,function = "rsvd1";
  1186. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1187. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1188. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1189. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1190. };
  1191. qspi_sck_pee0 {
  1192. nvidia,pins = "qspi_sck_pee0";
  1193. nvidia,function = "qspi";
  1194. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1195. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1196. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1197. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1198. };
  1199. qspi_cs_n_pee1 {
  1200. nvidia,pins = "qspi_cs_n_pee1";
  1201. nvidia,function = "qspi";
  1202. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1203. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1204. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1205. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1206. };
  1207. qspi_io0_pee2 {
  1208. nvidia,pins = "qspi_io0_pee2";
  1209. nvidia,function = "qspi";
  1210. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1211. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1212. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1213. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1214. };
  1215. qspi_io1_pee3 {
  1216. nvidia,pins = "qspi_io1_pee3";
  1217. nvidia,function = "qspi";
  1218. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1219. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1220. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1221. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1222. };
  1223. qspi_io2_pee4 {
  1224. nvidia,pins = "qspi_io2_pee4";
  1225. nvidia,function = "rsvd1";
  1226. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1227. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1228. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1229. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1230. };
  1231. qspi_io3_pee5 {
  1232. nvidia,pins = "qspi_io3_pee5";
  1233. nvidia,function = "rsvd1";
  1234. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1235. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1236. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1237. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1238. };
  1239. core_pwr_req {
  1240. nvidia,pins = "core_pwr_req";
  1241. nvidia,function = "core";
  1242. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1243. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1244. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1245. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1246. };
  1247. cpu_pwr_req {
  1248. nvidia,pins = "cpu_pwr_req";
  1249. nvidia,function = "cpu";
  1250. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1252. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1253. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1254. };
  1255. pwr_int_n {
  1256. nvidia,pins = "pwr_int_n";
  1257. nvidia,function = "pmi";
  1258. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1259. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1260. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1261. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1262. };
  1263. clk_32k_in {
  1264. nvidia,pins = "clk_32k_in";
  1265. nvidia,function = "clk";
  1266. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1267. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1268. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1269. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1270. };
  1271. jtag_rtck {
  1272. nvidia,pins = "jtag_rtck";
  1273. nvidia,function = "jtag";
  1274. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1275. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1276. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1277. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1278. };
  1279. clk_req {
  1280. nvidia,pins = "clk_req";
  1281. nvidia,function = "rsvd1";
  1282. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1283. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1284. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1285. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1286. };
  1287. shutdown {
  1288. nvidia,pins = "shutdown";
  1289. nvidia,function = "shutdown";
  1290. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1291. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1292. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1293. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1294. };
  1295. };
  1296. };
  1297. serial@70006000 {
  1298. status = "okay";
  1299. };
  1300. i2c@7000c400 {
  1301. status = "okay";
  1302. clock-frequency = <1000000>;
  1303. ec@1e {
  1304. compatible = "google,cros-ec-i2c";
  1305. reg = <0x1e>;
  1306. interrupt-parent = <&gpio>;
  1307. interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
  1308. wakeup-source;
  1309. ec_i2c_0: i2c-tunnel {
  1310. compatible = "google,cros-ec-i2c-tunnel";
  1311. #address-cells = <1>;
  1312. #size-cells = <0>;
  1313. google,remote-bus = <0>;
  1314. battery: bq27742@55 {
  1315. compatible = "ti,bq27742";
  1316. reg = <0x55>;
  1317. battery-name = "battery";
  1318. };
  1319. };
  1320. };
  1321. };
  1322. i2c@7000d000 {
  1323. status = "okay";
  1324. clock-frequency = <1000000>;
  1325. max77620: max77620@3c {
  1326. compatible = "maxim,max77620";
  1327. reg = <0x3c>;
  1328. interrupts = <0 86 IRQ_TYPE_NONE>;
  1329. #interrupt-cells = <2>;
  1330. interrupt-controller;
  1331. gpio-controller;
  1332. #gpio-cells = <2>;
  1333. pinctrl-names = "default";
  1334. pinctrl-0 = <&max77620_default>;
  1335. max77620_default: pinmux@0 {
  1336. pin_gpio {
  1337. pins = "gpio0", "gpio1", "gpio2", "gpio7";
  1338. function = "gpio";
  1339. };
  1340. /*
  1341. * GPIO3 is used to en_pp3300, and it is part of power
  1342. * sequence, So it must be sequenced up (automatically
  1343. * set by OTP) and down properly.
  1344. */
  1345. pin_gpio3 {
  1346. pins = "gpio3";
  1347. function = "fps-out";
  1348. drive-open-drain = <1>;
  1349. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1350. maxim,active-fps-power-up-slot = <4>;
  1351. maxim,active-fps-power-down-slot = <2>;
  1352. };
  1353. pin_gpio5_6 {
  1354. pins = "gpio5", "gpio6";
  1355. function = "gpio";
  1356. drive-push-pull = <1>;
  1357. };
  1358. pin_32k {
  1359. pins = "gpio4";
  1360. function = "32k-out1";
  1361. };
  1362. };
  1363. fps {
  1364. fps0 {
  1365. maxim,shutdown-fps-time-period-us = <5120>;
  1366. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1367. };
  1368. fps1 {
  1369. maxim,shutdown-fps-time-period-us = <5120>;
  1370. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
  1371. maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
  1372. };
  1373. fps2 {
  1374. maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
  1375. };
  1376. };
  1377. regulators {
  1378. in-ldo0-1-supply = <&pp1350>;
  1379. in-ldo2-supply = <&pp3300>;
  1380. in-ldo3-5-supply = <&pp3300>;
  1381. in-ldo7-8-supply = <&pp1350>;
  1382. ppvar_soc: sd0 {
  1383. regulator-name = "PPVAR_SOC";
  1384. regulator-min-microvolt = <825000>;
  1385. regulator-max-microvolt = <1125000>;
  1386. regulator-always-on;
  1387. regulator-boot-on;
  1388. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1389. maxim,active-fps-power-up-slot = <1>;
  1390. maxim,active-fps-power-down-slot = <7>;
  1391. };
  1392. pp1100_sd1: sd1 {
  1393. regulator-name = "PP1100";
  1394. regulator-min-microvolt = <1125000>;
  1395. regulator-max-microvolt = <1125000>;
  1396. regulator-always-on;
  1397. regulator-boot-on;
  1398. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1399. maxim,active-fps-power-up-slot = <5>;
  1400. maxim,active-fps-power-down-slot = <1>;
  1401. };
  1402. pp1350: sd2 {
  1403. regulator-name = "PP1350";
  1404. regulator-min-microvolt = <1350000>;
  1405. regulator-max-microvolt = <1350000>;
  1406. regulator-always-on;
  1407. regulator-boot-on;
  1408. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1409. maxim,active-fps-power-up-slot = <2>;
  1410. maxim,active-fps-power-down-slot = <5>;
  1411. };
  1412. pp1800: sd3 {
  1413. regulator-name = "PP1800";
  1414. regulator-min-microvolt = <1800000>;
  1415. regulator-max-microvolt = <1800000>;
  1416. regulator-always-on;
  1417. regulator-boot-on;
  1418. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1419. maxim,active-fps-power-up-slot = <3>;
  1420. maxim,active-fps-power-down-slot = <3>;
  1421. };
  1422. pp1200_avdd: ldo0 {
  1423. regulator-name = "PP1200_AVDD";
  1424. regulator-min-microvolt = <1200000>;
  1425. regulator-max-microvolt = <1200000>;
  1426. regulator-enable-ramp-delay = <26>;
  1427. regulator-ramp-delay = <100000>;
  1428. regulator-boot-on;
  1429. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1430. maxim,active-fps-power-up-slot = <0>;
  1431. maxim,active-fps-power-down-slot = <7>;
  1432. };
  1433. pp1200_rcam: ldo1 {
  1434. regulator-name = "PP1200_RCAM";
  1435. regulator-min-microvolt = <1200000>;
  1436. regulator-max-microvolt = <1200000>;
  1437. regulator-enable-ramp-delay = <22>;
  1438. regulator-ramp-delay = <100000>;
  1439. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1440. maxim,active-fps-power-up-slot = <0>;
  1441. maxim,active-fps-power-down-slot = <7>;
  1442. };
  1443. pp_ldo2: ldo2 {
  1444. regulator-name = "PP_LDO2";
  1445. regulator-min-microvolt = <1800000>;
  1446. regulator-max-microvolt = <1800000>;
  1447. regulator-enable-ramp-delay = <62>;
  1448. regulator-ramp-delay = <11000>;
  1449. regulator-always-on;
  1450. regulator-boot-on;
  1451. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1452. maxim,active-fps-power-up-slot = <0>;
  1453. maxim,active-fps-power-down-slot = <7>;
  1454. };
  1455. pp2800l_rcam: ldo3 {
  1456. regulator-name = "PP2800L_RCAM";
  1457. regulator-min-microvolt = <2800000>;
  1458. regulator-max-microvolt = <2800000>;
  1459. regulator-enable-ramp-delay = <50>;
  1460. regulator-ramp-delay = <100000>;
  1461. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1462. maxim,active-fps-power-up-slot = <0>;
  1463. maxim,active-fps-power-down-slot = <7>;
  1464. };
  1465. pp100_soc_rtc: ldo4 {
  1466. regulator-name = "PP1100_SOC_RTC";
  1467. regulator-min-microvolt = <850000>;
  1468. regulator-max-microvolt = <850000>;
  1469. regulator-enable-ramp-delay = <22>;
  1470. regulator-ramp-delay = <100000>;
  1471. regulator-always-on; /* Check this */
  1472. regulator-boot-on;
  1473. maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
  1474. maxim,active-fps-power-up-slot = <1>;
  1475. maxim,active-fps-power-down-slot = <7>;
  1476. };
  1477. pp2800l_fcam: ldo5 {
  1478. regulator-name = "PP2800L_FCAM";
  1479. regulator-min-microvolt = <2800000>;
  1480. regulator-max-microvolt = <2800000>;
  1481. regulator-enable-ramp-delay = <62>;
  1482. regulator-ramp-delay = <100000>;
  1483. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1484. maxim,active-fps-power-up-slot = <0>;
  1485. maxim,active-fps-power-down-slot = <7>;
  1486. };
  1487. ldo6 {
  1488. /* Unused. */
  1489. regulator-name = "PP_LDO6";
  1490. regulator-min-microvolt = <1800000>;
  1491. regulator-max-microvolt = <1800000>;
  1492. regulator-enable-ramp-delay = <36>;
  1493. regulator-ramp-delay = <100000>;
  1494. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1495. maxim,active-fps-power-up-slot = <0>;
  1496. maxim,active-fps-power-down-slot = <7>;
  1497. };
  1498. pp1050_avdd: ldo7 {
  1499. regulator-name = "PP1050_AVDD";
  1500. regulator-min-microvolt = <1050000>;
  1501. regulator-max-microvolt = <1050000>;
  1502. regulator-enable-ramp-delay = <24>;
  1503. regulator-ramp-delay = <100000>;
  1504. regulator-always-on;
  1505. regulator-boot-on;
  1506. maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
  1507. maxim,active-fps-power-up-slot = <3>;
  1508. maxim,active-fps-power-down-slot = <4>;
  1509. };
  1510. avddio_1v05: ldo8 {
  1511. regulator-name = "AVDDIO_1V05";
  1512. regulator-min-microvolt = <1050000>;
  1513. regulator-max-microvolt = <1050000>;
  1514. regulator-enable-ramp-delay = <22>;
  1515. regulator-ramp-delay = <100000>;
  1516. regulator-boot-on;
  1517. maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
  1518. maxim,active-fps-power-up-slot = <0>;
  1519. maxim,active-fps-power-down-slot = <7>;
  1520. };
  1521. };
  1522. };
  1523. };
  1524. i2c@7000d100 {
  1525. status = "okay";
  1526. clock-frequency = <400000>;
  1527. nau8825@1a {
  1528. compatible = "nuvoton,nau8825";
  1529. reg = <0x1a>;
  1530. interrupt-parent = <&gpio>;
  1531. interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
  1532. clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
  1533. clock-names = "mclk";
  1534. nuvoton,jkdet-enable;
  1535. nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
  1536. nuvoton,vref-impedance = <2>;
  1537. nuvoton,micbias-voltage = <6>;
  1538. nuvoton,sar-threshold-num = <4>;
  1539. nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
  1540. nuvoton,sar-hysteresis = <1>;
  1541. nuvoton,sar-voltage = <0>;
  1542. nuvoton,sar-compare-time = <0>;
  1543. nuvoton,sar-sampling-time = <0>;
  1544. nuvoton,short-key-debounce = <2>;
  1545. nuvoton,jack-insert-debounce = <7>;
  1546. nuvoton,jack-eject-debounce = <7>;
  1547. status = "okay";
  1548. };
  1549. audio-codec@2d {
  1550. compatible = "realtek,rt5677";
  1551. reg = <0x2d>;
  1552. interrupt-parent = <&gpio>;
  1553. interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>;
  1554. realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
  1555. gpio-controller;
  1556. #gpio-cells = <2>;
  1557. status = "okay";
  1558. };
  1559. };
  1560. pmc@7000e400 {
  1561. nvidia,invert-interrupt;
  1562. nvidia,suspend-mode = <0>;
  1563. nvidia,cpu-pwr-good-time = <0>;
  1564. nvidia,cpu-pwr-off-time = <0>;
  1565. nvidia,core-pwr-good-time = <12000 6000>;
  1566. nvidia,core-pwr-off-time = <39053>;
  1567. nvidia,core-power-req-active-high;
  1568. nvidia,sys-clock-req-active-high;
  1569. status = "okay";
  1570. };
  1571. usb@70090000 {
  1572. phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
  1573. <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
  1574. phy-names = "usb2-0", "usb3-0";
  1575. dvddio-pex-supply = <&avddio_1v05>;
  1576. hvddio-pex-supply = <&pp1800>;
  1577. avdd-usb-supply = <&pp3300>;
  1578. avdd-pll-utmip-supply = <&pp1800>;
  1579. avdd-pll-uerefe-supply = <&pp1050_avdd>;
  1580. dvdd-pex-pll-supply = <&avddio_1v05>;
  1581. hvdd-pex-pll-e-supply = <&pp1800>;
  1582. status = "okay";
  1583. };
  1584. padctl@7009f000 {
  1585. status = "okay";
  1586. pads {
  1587. usb2 {
  1588. status = "okay";
  1589. lanes {
  1590. usb2-0 {
  1591. nvidia,function = "xusb";
  1592. status = "okay";
  1593. };
  1594. };
  1595. };
  1596. pcie {
  1597. status = "okay";
  1598. lanes {
  1599. pcie-6 {
  1600. nvidia,function = "usb3-ss";
  1601. status = "okay";
  1602. };
  1603. };
  1604. };
  1605. };
  1606. ports {
  1607. usb2-0 {
  1608. status = "okay";
  1609. vbus-supply = <&usbc_vbus>;
  1610. mode = "otg";
  1611. };
  1612. usb3-0 {
  1613. nvidia,usb2-companion = <0>;
  1614. status = "okay";
  1615. };
  1616. };
  1617. };
  1618. sdhci@700b0600 {
  1619. bus-width = <8>;
  1620. non-removable;
  1621. status = "okay";
  1622. };
  1623. aconnect@702c0000 {
  1624. status = "okay";
  1625. dma@702e2000 {
  1626. status = "okay";
  1627. };
  1628. agic@702f9000 {
  1629. status = "okay";
  1630. };
  1631. };
  1632. clocks {
  1633. compatible = "simple-bus";
  1634. #address-cells = <1>;
  1635. #size-cells = <0>;
  1636. clk32k_in: clock@0 {
  1637. compatible = "fixed-clock";
  1638. reg = <0>;
  1639. #clock-cells = <0>;
  1640. clock-frequency = <32768>;
  1641. };
  1642. };
  1643. cpus {
  1644. cpu@0 {
  1645. enable-method = "psci";
  1646. };
  1647. cpu@1 {
  1648. enable-method = "psci";
  1649. };
  1650. cpu@2 {
  1651. enable-method = "psci";
  1652. };
  1653. cpu@3 {
  1654. enable-method = "psci";
  1655. };
  1656. };
  1657. gpio-keys {
  1658. compatible = "gpio-keys";
  1659. gpio-keys,name = "gpio-keys";
  1660. power {
  1661. label = "Power";
  1662. gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
  1663. linux,code = <KEY_POWER>;
  1664. debounce-interval = <30>;
  1665. wakeup-source;
  1666. };
  1667. lid {
  1668. label = "Lid";
  1669. gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>;
  1670. linux,input-type = <EV_SW>;
  1671. linux,code = <SW_LID>;
  1672. wakeup-source;
  1673. };
  1674. tablet_mode {
  1675. label = "Tablet Mode";
  1676. gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
  1677. linux,input-type = <EV_SW>;
  1678. linux,code = <SW_TABLET_MODE>;
  1679. wakeup-source;
  1680. };
  1681. volume_down {
  1682. label = "Volume Down";
  1683. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  1684. linux,code = <KEY_VOLUMEDOWN>;
  1685. };
  1686. volume_up {
  1687. label = "Volume Up";
  1688. gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>;
  1689. linux,code = <KEY_VOLUMEUP>;
  1690. };
  1691. };
  1692. max98357a {
  1693. compatible = "maxim,max98357a";
  1694. status = "okay";
  1695. };
  1696. psci {
  1697. compatible = "arm,psci-1.0";
  1698. method = "smc";
  1699. };
  1700. regulators {
  1701. compatible = "simple-bus";
  1702. device_type = "fixed-regulators";
  1703. #address-cells = <1>;
  1704. #size-cells = <0>;
  1705. ppvar_sys: regulator@0 {
  1706. compatible = "regulator-fixed";
  1707. reg = <0>;
  1708. regulator-name = "PPVAR_SYS";
  1709. regulator-min-microvolt = <4400000>;
  1710. regulator-max-microvolt = <4400000>;
  1711. regulator-always-on;
  1712. };
  1713. pplcd_vdd: regulator@1 {
  1714. compatible = "regulator-fixed";
  1715. reg = <1>;
  1716. regulator-name = "PPLCD_VDD";
  1717. regulator-min-microvolt = <4400000>;
  1718. regulator-max-microvolt = <4400000>;
  1719. gpio = <&gpio TEGRA_GPIO(V, 4) 0>;
  1720. enable-active-high;
  1721. regulator-boot-on;
  1722. };
  1723. pp3000_always: regulator@2 {
  1724. compatible = "regulator-fixed";
  1725. reg = <2>;
  1726. regulator-name = "PP3000_ALWAYS";
  1727. regulator-min-microvolt = <3000000>;
  1728. regulator-max-microvolt = <3000000>;
  1729. regulator-always-on;
  1730. };
  1731. pp3300: regulator@3 {
  1732. compatible = "regulator-fixed";
  1733. reg = <3>;
  1734. regulator-name = "PP3300";
  1735. regulator-min-microvolt = <3300000>;
  1736. regulator-max-microvolt = <3300000>;
  1737. regulator-boot-on;
  1738. regulator-always-on;
  1739. enable-active-high;
  1740. };
  1741. pp5000: regulator@4 {
  1742. compatible = "regulator-fixed";
  1743. reg = <4>;
  1744. regulator-name = "PP5000";
  1745. regulator-min-microvolt = <5000000>;
  1746. regulator-max-microvolt = <5000000>;
  1747. regulator-always-on;
  1748. };
  1749. pp1800_lcdio: regulator@5 {
  1750. compatible = "regulator-fixed";
  1751. reg = <5>;
  1752. regulator-name = "PP1800_LCDIO";
  1753. regulator-min-microvolt = <1800000>;
  1754. regulator-max-microvolt = <1800000>;
  1755. gpio = <&gpio TEGRA_GPIO(V, 3) 0>;
  1756. enable-active-high;
  1757. regulator-boot-on;
  1758. };
  1759. pp1800_cam: regulator@6 {
  1760. compatible = "regulator-fixed";
  1761. reg= <6>;
  1762. regulator-name = "PP1800_CAM";
  1763. regulator-min-microvolt = <1800000>;
  1764. regulator-max-microvolt = <1800000>;
  1765. gpio = <&gpio TEGRA_GPIO(K, 3) 0>;
  1766. enable-active-high;
  1767. };
  1768. usbc_vbus: regulator@7 {
  1769. compatible = "regulator-fixed";
  1770. reg = <7>;
  1771. regulator-name = "USBC_VBUS";
  1772. regulator-min-microvolt = <5000000>;
  1773. regulator-max-microvolt = <5000000>;
  1774. };
  1775. };
  1776. };