juno-r1.dts 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. /*
  2. * ARM Ltd. Juno Platform
  3. *
  4. * Copyright (c) 2015 ARM Ltd.
  5. *
  6. * This file is licensed under a dual GPLv2 or BSD license.
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. / {
  11. model = "ARM Juno development board (r1)";
  12. compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
  13. interrupt-parent = <&gic>;
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. aliases {
  17. serial0 = &soc_uart0;
  18. };
  19. chosen {
  20. stdout-path = "serial0:115200n8";
  21. };
  22. psci {
  23. compatible = "arm,psci-0.2";
  24. method = "smc";
  25. };
  26. cpus {
  27. #address-cells = <2>;
  28. #size-cells = <0>;
  29. cpu-map {
  30. cluster0 {
  31. core0 {
  32. cpu = <&A57_0>;
  33. };
  34. core1 {
  35. cpu = <&A57_1>;
  36. };
  37. };
  38. cluster1 {
  39. core0 {
  40. cpu = <&A53_0>;
  41. };
  42. core1 {
  43. cpu = <&A53_1>;
  44. };
  45. core2 {
  46. cpu = <&A53_2>;
  47. };
  48. core3 {
  49. cpu = <&A53_3>;
  50. };
  51. };
  52. };
  53. idle-states {
  54. entry-method = "arm,psci";
  55. CPU_SLEEP_0: cpu-sleep-0 {
  56. compatible = "arm,idle-state";
  57. arm,psci-suspend-param = <0x0010000>;
  58. local-timer-stop;
  59. entry-latency-us = <300>;
  60. exit-latency-us = <1200>;
  61. min-residency-us = <2000>;
  62. };
  63. CLUSTER_SLEEP_0: cluster-sleep-0 {
  64. compatible = "arm,idle-state";
  65. arm,psci-suspend-param = <0x1010000>;
  66. local-timer-stop;
  67. entry-latency-us = <400>;
  68. exit-latency-us = <1200>;
  69. min-residency-us = <2500>;
  70. };
  71. };
  72. A57_0: cpu@0 {
  73. compatible = "arm,cortex-a57","arm,armv8";
  74. reg = <0x0 0x0>;
  75. device_type = "cpu";
  76. enable-method = "psci";
  77. next-level-cache = <&A57_L2>;
  78. clocks = <&scpi_dvfs 0>;
  79. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  80. capacity-dmips-mhz = <1024>;
  81. };
  82. A57_1: cpu@1 {
  83. compatible = "arm,cortex-a57","arm,armv8";
  84. reg = <0x0 0x1>;
  85. device_type = "cpu";
  86. enable-method = "psci";
  87. next-level-cache = <&A57_L2>;
  88. clocks = <&scpi_dvfs 0>;
  89. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  90. capacity-dmips-mhz = <1024>;
  91. };
  92. A53_0: cpu@100 {
  93. compatible = "arm,cortex-a53","arm,armv8";
  94. reg = <0x0 0x100>;
  95. device_type = "cpu";
  96. enable-method = "psci";
  97. next-level-cache = <&A53_L2>;
  98. clocks = <&scpi_dvfs 1>;
  99. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  100. capacity-dmips-mhz = <578>;
  101. };
  102. A53_1: cpu@101 {
  103. compatible = "arm,cortex-a53","arm,armv8";
  104. reg = <0x0 0x101>;
  105. device_type = "cpu";
  106. enable-method = "psci";
  107. next-level-cache = <&A53_L2>;
  108. clocks = <&scpi_dvfs 1>;
  109. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  110. capacity-dmips-mhz = <578>;
  111. };
  112. A53_2: cpu@102 {
  113. compatible = "arm,cortex-a53","arm,armv8";
  114. reg = <0x0 0x102>;
  115. device_type = "cpu";
  116. enable-method = "psci";
  117. next-level-cache = <&A53_L2>;
  118. clocks = <&scpi_dvfs 1>;
  119. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  120. capacity-dmips-mhz = <578>;
  121. };
  122. A53_3: cpu@103 {
  123. compatible = "arm,cortex-a53","arm,armv8";
  124. reg = <0x0 0x103>;
  125. device_type = "cpu";
  126. enable-method = "psci";
  127. next-level-cache = <&A53_L2>;
  128. clocks = <&scpi_dvfs 1>;
  129. cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  130. capacity-dmips-mhz = <578>;
  131. };
  132. A57_L2: l2-cache0 {
  133. compatible = "cache";
  134. };
  135. A53_L2: l2-cache1 {
  136. compatible = "cache";
  137. };
  138. };
  139. pmu_a57 {
  140. compatible = "arm,cortex-a57-pmu";
  141. interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
  142. <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
  143. interrupt-affinity = <&A57_0>,
  144. <&A57_1>;
  145. };
  146. pmu_a53 {
  147. compatible = "arm,cortex-a53-pmu";
  148. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  149. <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  150. <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
  151. <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  152. interrupt-affinity = <&A53_0>,
  153. <&A53_1>,
  154. <&A53_2>,
  155. <&A53_3>;
  156. };
  157. #include "juno-base.dtsi"
  158. };
  159. &memtimer {
  160. status = "okay";
  161. };
  162. &pcie_ctlr {
  163. status = "okay";
  164. };
  165. &etm0 {
  166. cpu = <&A57_0>;
  167. };
  168. &etm1 {
  169. cpu = <&A57_1>;
  170. };
  171. &etm2 {
  172. cpu = <&A53_0>;
  173. };
  174. &etm3 {
  175. cpu = <&A53_1>;
  176. };
  177. &etm4 {
  178. cpu = <&A53_2>;
  179. };
  180. &etm5 {
  181. cpu = <&A53_3>;
  182. };
  183. &big_cluster_thermal_zone {
  184. status = "okay";
  185. };
  186. &little_cluster_thermal_zone {
  187. status = "okay";
  188. };
  189. &gpu0_thermal_zone {
  190. status = "okay";
  191. };
  192. &gpu1_thermal_zone {
  193. status = "okay";
  194. };