meson-gxbb.dtsi 10 KB

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  1. /*
  2. * Copyright (c) 2016 Andreas Färber
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include "meson-gx.dtsi"
  43. #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  44. #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  45. #include <dt-bindings/clock/gxbb-clkc.h>
  46. #include <dt-bindings/clock/gxbb-aoclkc.h>
  47. #include <dt-bindings/reset/gxbb-aoclkc.h>
  48. / {
  49. compatible = "amlogic,meson-gxbb";
  50. scpi {
  51. compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
  52. mboxes = <&mailbox 1 &mailbox 2>;
  53. shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
  54. scpi_clocks: clocks {
  55. compatible = "arm,scpi-clocks";
  56. scpi_dvfs: scpi_clocks@0 {
  57. compatible = "arm,scpi-dvfs-clocks";
  58. #clock-cells = <1>;
  59. clock-indices = <0>;
  60. clock-output-names = "vcpu";
  61. };
  62. };
  63. scpi_sensors: sensors {
  64. compatible = "arm,scpi-sensors";
  65. #thermal-sensor-cells = <1>;
  66. };
  67. };
  68. soc {
  69. usb0_phy: phy@c0000000 {
  70. compatible = "amlogic,meson-gxbb-usb2-phy";
  71. #phy-cells = <0>;
  72. reg = <0x0 0xc0000000 0x0 0x20>;
  73. resets = <&reset RESET_USB_OTG>;
  74. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
  75. clock-names = "usb_general", "usb";
  76. status = "disabled";
  77. };
  78. usb1_phy: phy@c0000020 {
  79. compatible = "amlogic,meson-gxbb-usb2-phy";
  80. #phy-cells = <0>;
  81. reg = <0x0 0xc0000020 0x0 0x20>;
  82. resets = <&reset RESET_USB_OTG>;
  83. clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
  84. clock-names = "usb_general", "usb";
  85. status = "disabled";
  86. };
  87. sram: sram@c8000000 {
  88. compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
  89. reg = <0x0 0xc8000000 0x0 0x14000>;
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. ranges = <0 0x0 0xc8000000 0x14000>;
  93. cpu_scp_lpri: scp-shmem@0 {
  94. compatible = "amlogic,meson-gxbb-scp-shmem";
  95. reg = <0x13000 0x400>;
  96. };
  97. cpu_scp_hpri: scp-shmem@200 {
  98. compatible = "amlogic,meson-gxbb-scp-shmem";
  99. reg = <0x13400 0x400>;
  100. };
  101. };
  102. usb0: usb@c9000000 {
  103. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  104. reg = <0x0 0xc9000000 0x0 0x40000>;
  105. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  106. clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
  107. clock-names = "otg";
  108. phys = <&usb0_phy>;
  109. phy-names = "usb2-phy";
  110. dr_mode = "host";
  111. status = "disabled";
  112. };
  113. usb1: usb@c9100000 {
  114. compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  115. reg = <0x0 0xc9100000 0x0 0x40000>;
  116. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  117. clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  118. clock-names = "otg";
  119. phys = <&usb1_phy>;
  120. phy-names = "usb2-phy";
  121. dr_mode = "host";
  122. status = "disabled";
  123. };
  124. };
  125. };
  126. &cpu0 {
  127. clocks = <&scpi_dvfs 0>;
  128. };
  129. &cpu1 {
  130. clocks = <&scpi_dvfs 0>;
  131. };
  132. &cpu2 {
  133. clocks = <&scpi_dvfs 0>;
  134. };
  135. &cpu3 {
  136. clocks = <&scpi_dvfs 0>;
  137. };
  138. &cbus {
  139. spifc: spi@8c80 {
  140. compatible = "amlogic,meson-gxbb-spifc";
  141. reg = <0x0 0x08c80 0x0 0x80>;
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. clocks = <&clkc CLKID_SPI>;
  145. status = "disabled";
  146. };
  147. };
  148. &ethmac {
  149. clocks = <&clkc CLKID_ETH>,
  150. <&clkc CLKID_FCLK_DIV2>,
  151. <&clkc CLKID_MPLL2>;
  152. clock-names = "stmmaceth", "clkin0", "clkin1";
  153. };
  154. &aobus {
  155. pinctrl_aobus: pinctrl@14 {
  156. compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  157. #address-cells = <2>;
  158. #size-cells = <2>;
  159. ranges;
  160. gpio_ao: bank@14 {
  161. reg = <0x0 0x00014 0x0 0x8>,
  162. <0x0 0x0002c 0x0 0x4>,
  163. <0x0 0x00024 0x0 0x8>;
  164. reg-names = "mux", "pull", "gpio";
  165. gpio-controller;
  166. #gpio-cells = <2>;
  167. };
  168. uart_ao_a_pins: uart_ao_a {
  169. mux {
  170. groups = "uart_tx_ao_a", "uart_rx_ao_a";
  171. function = "uart_ao";
  172. };
  173. };
  174. remote_input_ao_pins: remote_input_ao {
  175. mux {
  176. groups = "remote_input_ao";
  177. function = "remote_input_ao";
  178. };
  179. };
  180. i2c_ao_pins: i2c_ao {
  181. mux {
  182. groups = "i2c_sck_ao",
  183. "i2c_sda_ao";
  184. function = "i2c_ao";
  185. };
  186. };
  187. pwm_ao_a_3_pins: pwm_ao_a_3 {
  188. mux {
  189. groups = "pwm_ao_a_3";
  190. function = "pwm_ao_a_3";
  191. };
  192. };
  193. pwm_ao_a_6_pins: pwm_ao_a_6 {
  194. mux {
  195. groups = "pwm_ao_a_6";
  196. function = "pwm_ao_a_6";
  197. };
  198. };
  199. pwm_ao_a_12_pins: pwm_ao_a_12 {
  200. mux {
  201. groups = "pwm_ao_a_12";
  202. function = "pwm_ao_a_12";
  203. };
  204. };
  205. pwm_ao_b_pins: pwm_ao_b {
  206. mux {
  207. groups = "pwm_ao_b";
  208. function = "pwm_ao_b";
  209. };
  210. };
  211. };
  212. clkc_AO: clock-controller@040 {
  213. compatible = "amlogic,gxbb-aoclkc";
  214. reg = <0x0 0x00040 0x0 0x4>;
  215. #clock-cells = <1>;
  216. #reset-cells = <1>;
  217. };
  218. pwm_ab_AO: pwm@550 {
  219. compatible = "amlogic,meson-gxbb-pwm";
  220. reg = <0x0 0x0550 0x0 0x10>;
  221. #pwm-cells = <3>;
  222. status = "disabled";
  223. };
  224. i2c_AO: i2c@500 {
  225. compatible = "amlogic,meson-gxbb-i2c";
  226. reg = <0x0 0x500 0x0 0x20>;
  227. interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
  228. clocks = <&clkc CLKID_AO_I2C>;
  229. #address-cells = <1>;
  230. #size-cells = <0>;
  231. status = "disabled";
  232. };
  233. };
  234. &periphs {
  235. pinctrl_periphs: pinctrl@4b0 {
  236. compatible = "amlogic,meson-gxbb-periphs-pinctrl";
  237. #address-cells = <2>;
  238. #size-cells = <2>;
  239. ranges;
  240. gpio: bank@4b0 {
  241. reg = <0x0 0x004b0 0x0 0x28>,
  242. <0x0 0x004e8 0x0 0x14>,
  243. <0x0 0x00120 0x0 0x14>,
  244. <0x0 0x00430 0x0 0x40>;
  245. reg-names = "mux", "pull", "pull-enable", "gpio";
  246. gpio-controller;
  247. #gpio-cells = <2>;
  248. };
  249. emmc_pins: emmc {
  250. mux {
  251. groups = "emmc_nand_d07",
  252. "emmc_cmd",
  253. "emmc_clk",
  254. "emmc_ds";
  255. function = "emmc";
  256. };
  257. };
  258. nor_pins: nor {
  259. mux {
  260. groups = "nor_d",
  261. "nor_q",
  262. "nor_c",
  263. "nor_cs";
  264. function = "nor";
  265. };
  266. };
  267. sdcard_pins: sdcard {
  268. mux {
  269. groups = "sdcard_d0",
  270. "sdcard_d1",
  271. "sdcard_d2",
  272. "sdcard_d3",
  273. "sdcard_cmd",
  274. "sdcard_clk";
  275. function = "sdcard";
  276. };
  277. };
  278. sdio_pins: sdio {
  279. mux {
  280. groups = "sdio_d0",
  281. "sdio_d1",
  282. "sdio_d2",
  283. "sdio_d3",
  284. "sdio_cmd",
  285. "sdio_clk";
  286. function = "sdio";
  287. };
  288. };
  289. sdio_irq_pins: sdio_irq {
  290. mux {
  291. groups = "sdio_irq";
  292. function = "sdio";
  293. };
  294. };
  295. uart_a_pins: uart_a {
  296. mux {
  297. groups = "uart_tx_a",
  298. "uart_rx_a";
  299. function = "uart_a";
  300. };
  301. };
  302. uart_b_pins: uart_b {
  303. mux {
  304. groups = "uart_tx_b",
  305. "uart_rx_b";
  306. function = "uart_b";
  307. };
  308. };
  309. uart_c_pins: uart_c {
  310. mux {
  311. groups = "uart_tx_c",
  312. "uart_rx_c";
  313. function = "uart_c";
  314. };
  315. };
  316. i2c_a_pins: i2c_a {
  317. mux {
  318. groups = "i2c_sck_a",
  319. "i2c_sda_a";
  320. function = "i2c_a";
  321. };
  322. };
  323. i2c_b_pins: i2c_b {
  324. mux {
  325. groups = "i2c_sck_b",
  326. "i2c_sda_b";
  327. function = "i2c_b";
  328. };
  329. };
  330. i2c_c_pins: i2c_c {
  331. mux {
  332. groups = "i2c_sck_c",
  333. "i2c_sda_c";
  334. function = "i2c_c";
  335. };
  336. };
  337. eth_rgmii_pins: eth-rgmii {
  338. mux {
  339. groups = "eth_mdio",
  340. "eth_mdc",
  341. "eth_clk_rx_clk",
  342. "eth_rx_dv",
  343. "eth_rxd0",
  344. "eth_rxd1",
  345. "eth_rxd2",
  346. "eth_rxd3",
  347. "eth_rgmii_tx_clk",
  348. "eth_tx_en",
  349. "eth_txd0",
  350. "eth_txd1",
  351. "eth_txd2",
  352. "eth_txd3";
  353. function = "eth";
  354. };
  355. };
  356. eth_rmii_pins: eth-rmii {
  357. mux {
  358. groups = "eth_mdio",
  359. "eth_mdc",
  360. "eth_clk_rx_clk",
  361. "eth_rx_dv",
  362. "eth_rxd0",
  363. "eth_rxd1",
  364. "eth_tx_en",
  365. "eth_txd0",
  366. "eth_txd1";
  367. function = "eth";
  368. };
  369. };
  370. pwm_a_x_pins: pwm_a_x {
  371. mux {
  372. groups = "pwm_a_x";
  373. function = "pwm_a_x";
  374. };
  375. };
  376. pwm_a_y_pins: pwm_a_y {
  377. mux {
  378. groups = "pwm_a_y";
  379. function = "pwm_a_y";
  380. };
  381. };
  382. pwm_b_pins: pwm_b {
  383. mux {
  384. groups = "pwm_b";
  385. function = "pwm_b";
  386. };
  387. };
  388. pwm_d_pins: pwm_d {
  389. mux {
  390. groups = "pwm_d";
  391. function = "pwm_d";
  392. };
  393. };
  394. pwm_e_pins: pwm_e {
  395. mux {
  396. groups = "pwm_e";
  397. function = "pwm_e";
  398. };
  399. };
  400. pwm_f_x_pins: pwm_f_x {
  401. mux {
  402. groups = "pwm_f_x";
  403. function = "pwm_f_x";
  404. };
  405. };
  406. pwm_f_y_pins: pwm_f_y {
  407. mux {
  408. groups = "pwm_f_y";
  409. function = "pwm_f_y";
  410. };
  411. };
  412. };
  413. };
  414. &hiubus {
  415. clkc: clock-controller@0 {
  416. compatible = "amlogic,gxbb-clkc";
  417. #clock-cells = <1>;
  418. reg = <0x0 0x0 0x0 0x3db>;
  419. };
  420. };
  421. &i2c_A {
  422. clocks = <&clkc CLKID_I2C>;
  423. };
  424. &i2c_B {
  425. clocks = <&clkc CLKID_I2C>;
  426. };
  427. &i2c_C {
  428. clocks = <&clkc CLKID_I2C>;
  429. };
  430. &sd_emmc_a {
  431. clocks = <&clkc CLKID_SD_EMMC_A>,
  432. <&xtal>,
  433. <&clkc CLKID_FCLK_DIV2>;
  434. clock-names = "core", "clkin0", "clkin1";
  435. };
  436. &sd_emmc_b {
  437. clocks = <&clkc CLKID_SD_EMMC_B>,
  438. <&xtal>,
  439. <&clkc CLKID_FCLK_DIV2>;
  440. clock-names = "core", "clkin0", "clkin1";
  441. };
  442. &sd_emmc_c {
  443. clocks = <&clkc CLKID_SD_EMMC_C>,
  444. <&xtal>,
  445. <&clkc CLKID_FCLK_DIV2>;
  446. clock-names = "core", "clkin0", "clkin1";
  447. };
  448. &vpu {
  449. compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
  450. };