core.c 27 KB

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  1. /*
  2. * arch/arm/mach-ep93xx/core.c
  3. * Core routines for Cirrus EP93xx chips.
  4. *
  5. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  6. * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  7. *
  8. * Thanks go to Michael Burian and Ray Lehtiniemi for their key
  9. * role in the ep93xx linux community.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or (at
  14. * your option) any later version.
  15. */
  16. #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/sys_soc.h>
  23. #include <linux/irq.h>
  24. #include <linux/io.h>
  25. #include <linux/gpio.h>
  26. #include <linux/leds.h>
  27. #include <linux/termios.h>
  28. #include <linux/amba/bus.h>
  29. #include <linux/amba/serial.h>
  30. #include <linux/mtd/physmap.h>
  31. #include <linux/i2c.h>
  32. #include <linux/i2c-gpio.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/export.h>
  35. #include <linux/irqchip/arm-vic.h>
  36. #include <linux/reboot.h>
  37. #include <linux/usb/ohci_pdriver.h>
  38. #include <linux/random.h>
  39. #include <mach/hardware.h>
  40. #include <linux/platform_data/video-ep93xx.h>
  41. #include <linux/platform_data/keypad-ep93xx.h>
  42. #include <linux/platform_data/spi-ep93xx.h>
  43. #include <mach/gpio-ep93xx.h>
  44. #include <asm/mach/arch.h>
  45. #include <asm/mach/map.h>
  46. #include "soc.h"
  47. /*************************************************************************
  48. * Static I/O mappings that are needed for all EP93xx platforms
  49. *************************************************************************/
  50. static struct map_desc ep93xx_io_desc[] __initdata = {
  51. {
  52. .virtual = EP93XX_AHB_VIRT_BASE,
  53. .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  54. .length = EP93XX_AHB_SIZE,
  55. .type = MT_DEVICE,
  56. }, {
  57. .virtual = EP93XX_APB_VIRT_BASE,
  58. .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  59. .length = EP93XX_APB_SIZE,
  60. .type = MT_DEVICE,
  61. },
  62. };
  63. void __init ep93xx_map_io(void)
  64. {
  65. iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  66. }
  67. /*************************************************************************
  68. * EP93xx IRQ handling
  69. *************************************************************************/
  70. void __init ep93xx_init_irq(void)
  71. {
  72. vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
  73. vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
  74. }
  75. /*************************************************************************
  76. * EP93xx System Controller Software Locked register handling
  77. *************************************************************************/
  78. /*
  79. * syscon_swlock prevents anything else from writing to the syscon
  80. * block while a software locked register is being written.
  81. */
  82. static DEFINE_SPINLOCK(syscon_swlock);
  83. void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
  84. {
  85. unsigned long flags;
  86. spin_lock_irqsave(&syscon_swlock, flags);
  87. __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
  88. __raw_writel(val, reg);
  89. spin_unlock_irqrestore(&syscon_swlock, flags);
  90. }
  91. void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
  92. {
  93. unsigned long flags;
  94. unsigned int val;
  95. spin_lock_irqsave(&syscon_swlock, flags);
  96. val = __raw_readl(EP93XX_SYSCON_DEVCFG);
  97. val &= ~clear_bits;
  98. val |= set_bits;
  99. __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
  100. __raw_writel(val, EP93XX_SYSCON_DEVCFG);
  101. spin_unlock_irqrestore(&syscon_swlock, flags);
  102. }
  103. /**
  104. * ep93xx_chip_revision() - returns the EP93xx chip revision
  105. *
  106. * See <mach/platform.h> for more information.
  107. */
  108. unsigned int ep93xx_chip_revision(void)
  109. {
  110. unsigned int v;
  111. v = __raw_readl(EP93XX_SYSCON_SYSCFG);
  112. v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
  113. v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
  114. return v;
  115. }
  116. EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
  117. /*************************************************************************
  118. * EP93xx GPIO
  119. *************************************************************************/
  120. static struct resource ep93xx_gpio_resource[] = {
  121. DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
  122. };
  123. static struct platform_device ep93xx_gpio_device = {
  124. .name = "gpio-ep93xx",
  125. .id = -1,
  126. .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
  127. .resource = ep93xx_gpio_resource,
  128. };
  129. /*************************************************************************
  130. * EP93xx peripheral handling
  131. *************************************************************************/
  132. #define EP93XX_UART_MCR_OFFSET (0x0100)
  133. static void ep93xx_uart_set_mctrl(struct amba_device *dev,
  134. void __iomem *base, unsigned int mctrl)
  135. {
  136. unsigned int mcr;
  137. mcr = 0;
  138. if (mctrl & TIOCM_RTS)
  139. mcr |= 2;
  140. if (mctrl & TIOCM_DTR)
  141. mcr |= 1;
  142. __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
  143. }
  144. static struct amba_pl010_data ep93xx_uart_data = {
  145. .set_mctrl = ep93xx_uart_set_mctrl,
  146. };
  147. static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
  148. { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
  149. static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
  150. { IRQ_EP93XX_UART2 }, NULL);
  151. static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
  152. { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
  153. static struct resource ep93xx_rtc_resource[] = {
  154. DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
  155. };
  156. static struct platform_device ep93xx_rtc_device = {
  157. .name = "ep93xx-rtc",
  158. .id = -1,
  159. .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
  160. .resource = ep93xx_rtc_resource,
  161. };
  162. /*************************************************************************
  163. * EP93xx OHCI USB Host
  164. *************************************************************************/
  165. static struct clk *ep93xx_ohci_host_clock;
  166. static int ep93xx_ohci_power_on(struct platform_device *pdev)
  167. {
  168. if (!ep93xx_ohci_host_clock) {
  169. ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL);
  170. if (IS_ERR(ep93xx_ohci_host_clock))
  171. return PTR_ERR(ep93xx_ohci_host_clock);
  172. }
  173. return clk_enable(ep93xx_ohci_host_clock);
  174. }
  175. static void ep93xx_ohci_power_off(struct platform_device *pdev)
  176. {
  177. clk_disable(ep93xx_ohci_host_clock);
  178. }
  179. static struct usb_ohci_pdata ep93xx_ohci_pdata = {
  180. .power_on = ep93xx_ohci_power_on,
  181. .power_off = ep93xx_ohci_power_off,
  182. .power_suspend = ep93xx_ohci_power_off,
  183. };
  184. static struct resource ep93xx_ohci_resources[] = {
  185. DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
  186. DEFINE_RES_IRQ(IRQ_EP93XX_USB),
  187. };
  188. static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32);
  189. static struct platform_device ep93xx_ohci_device = {
  190. .name = "ohci-platform",
  191. .id = -1,
  192. .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
  193. .resource = ep93xx_ohci_resources,
  194. .dev = {
  195. .dma_mask = &ep93xx_ohci_dma_mask,
  196. .coherent_dma_mask = DMA_BIT_MASK(32),
  197. .platform_data = &ep93xx_ohci_pdata,
  198. },
  199. };
  200. /*************************************************************************
  201. * EP93xx physmap'ed flash
  202. *************************************************************************/
  203. static struct physmap_flash_data ep93xx_flash_data;
  204. static struct resource ep93xx_flash_resource = {
  205. .flags = IORESOURCE_MEM,
  206. };
  207. static struct platform_device ep93xx_flash = {
  208. .name = "physmap-flash",
  209. .id = 0,
  210. .dev = {
  211. .platform_data = &ep93xx_flash_data,
  212. },
  213. .num_resources = 1,
  214. .resource = &ep93xx_flash_resource,
  215. };
  216. /**
  217. * ep93xx_register_flash() - Register the external flash device.
  218. * @width: bank width in octets
  219. * @start: resource start address
  220. * @size: resource size
  221. */
  222. void __init ep93xx_register_flash(unsigned int width,
  223. resource_size_t start, resource_size_t size)
  224. {
  225. ep93xx_flash_data.width = width;
  226. ep93xx_flash_resource.start = start;
  227. ep93xx_flash_resource.end = start + size - 1;
  228. platform_device_register(&ep93xx_flash);
  229. }
  230. /*************************************************************************
  231. * EP93xx ethernet peripheral handling
  232. *************************************************************************/
  233. static struct ep93xx_eth_data ep93xx_eth_data;
  234. static struct resource ep93xx_eth_resource[] = {
  235. DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
  236. DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
  237. };
  238. static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
  239. static struct platform_device ep93xx_eth_device = {
  240. .name = "ep93xx-eth",
  241. .id = -1,
  242. .dev = {
  243. .platform_data = &ep93xx_eth_data,
  244. .coherent_dma_mask = DMA_BIT_MASK(32),
  245. .dma_mask = &ep93xx_eth_dma_mask,
  246. },
  247. .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
  248. .resource = ep93xx_eth_resource,
  249. };
  250. /**
  251. * ep93xx_register_eth - Register the built-in ethernet platform device.
  252. * @data: platform specific ethernet configuration (__initdata)
  253. * @copy_addr: flag indicating that the MAC address should be copied
  254. * from the IndAd registers (as programmed by the bootloader)
  255. */
  256. void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
  257. {
  258. if (copy_addr)
  259. memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
  260. ep93xx_eth_data = *data;
  261. platform_device_register(&ep93xx_eth_device);
  262. }
  263. /*************************************************************************
  264. * EP93xx i2c peripheral handling
  265. *************************************************************************/
  266. static struct i2c_gpio_platform_data ep93xx_i2c_data;
  267. static struct platform_device ep93xx_i2c_device = {
  268. .name = "i2c-gpio",
  269. .id = 0,
  270. .dev = {
  271. .platform_data = &ep93xx_i2c_data,
  272. },
  273. };
  274. /**
  275. * ep93xx_register_i2c - Register the i2c platform device.
  276. * @data: platform specific i2c-gpio configuration (__initdata)
  277. * @devices: platform specific i2c bus device information (__initdata)
  278. * @num: the number of devices on the i2c bus
  279. */
  280. void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
  281. struct i2c_board_info *devices, int num)
  282. {
  283. /*
  284. * Set the EEPROM interface pin drive type control.
  285. * Defines the driver type for the EECLK and EEDAT pins as either
  286. * open drain, which will require an external pull-up, or a normal
  287. * CMOS driver.
  288. */
  289. if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
  290. pr_warning("sda != EEDAT, open drain has no effect\n");
  291. if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
  292. pr_warning("scl != EECLK, open drain has no effect\n");
  293. __raw_writel((data->sda_is_open_drain << 1) |
  294. (data->scl_is_open_drain << 0),
  295. EP93XX_GPIO_EEDRIVE);
  296. ep93xx_i2c_data = *data;
  297. i2c_register_board_info(0, devices, num);
  298. platform_device_register(&ep93xx_i2c_device);
  299. }
  300. /*************************************************************************
  301. * EP93xx SPI peripheral handling
  302. *************************************************************************/
  303. static struct ep93xx_spi_info ep93xx_spi_master_data;
  304. static struct resource ep93xx_spi_resources[] = {
  305. DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
  306. DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
  307. };
  308. static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
  309. static struct platform_device ep93xx_spi_device = {
  310. .name = "ep93xx-spi",
  311. .id = 0,
  312. .dev = {
  313. .platform_data = &ep93xx_spi_master_data,
  314. .coherent_dma_mask = DMA_BIT_MASK(32),
  315. .dma_mask = &ep93xx_spi_dma_mask,
  316. },
  317. .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
  318. .resource = ep93xx_spi_resources,
  319. };
  320. /**
  321. * ep93xx_register_spi() - registers spi platform device
  322. * @info: ep93xx board specific spi master info (__initdata)
  323. * @devices: SPI devices to register (__initdata)
  324. * @num: number of SPI devices to register
  325. *
  326. * This function registers platform device for the EP93xx SPI controller and
  327. * also makes sure that SPI pins are muxed so that I2S is not using those pins.
  328. */
  329. void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
  330. struct spi_board_info *devices, int num)
  331. {
  332. /*
  333. * When SPI is used, we need to make sure that I2S is muxed off from
  334. * SPI pins.
  335. */
  336. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
  337. ep93xx_spi_master_data = *info;
  338. spi_register_board_info(devices, num);
  339. platform_device_register(&ep93xx_spi_device);
  340. }
  341. /*************************************************************************
  342. * EP93xx LEDs
  343. *************************************************************************/
  344. static const struct gpio_led ep93xx_led_pins[] __initconst = {
  345. {
  346. .name = "platform:grled",
  347. .gpio = EP93XX_GPIO_LINE_GRLED,
  348. }, {
  349. .name = "platform:rdled",
  350. .gpio = EP93XX_GPIO_LINE_RDLED,
  351. },
  352. };
  353. static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
  354. .num_leds = ARRAY_SIZE(ep93xx_led_pins),
  355. .leds = ep93xx_led_pins,
  356. };
  357. /*************************************************************************
  358. * EP93xx pwm peripheral handling
  359. *************************************************************************/
  360. static struct resource ep93xx_pwm0_resource[] = {
  361. DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
  362. };
  363. static struct platform_device ep93xx_pwm0_device = {
  364. .name = "ep93xx-pwm",
  365. .id = 0,
  366. .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
  367. .resource = ep93xx_pwm0_resource,
  368. };
  369. static struct resource ep93xx_pwm1_resource[] = {
  370. DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
  371. };
  372. static struct platform_device ep93xx_pwm1_device = {
  373. .name = "ep93xx-pwm",
  374. .id = 1,
  375. .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
  376. .resource = ep93xx_pwm1_resource,
  377. };
  378. void __init ep93xx_register_pwm(int pwm0, int pwm1)
  379. {
  380. if (pwm0)
  381. platform_device_register(&ep93xx_pwm0_device);
  382. /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
  383. if (pwm1)
  384. platform_device_register(&ep93xx_pwm1_device);
  385. }
  386. int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
  387. {
  388. int err;
  389. if (pdev->id == 0) {
  390. err = 0;
  391. } else if (pdev->id == 1) {
  392. err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
  393. dev_name(&pdev->dev));
  394. if (err)
  395. return err;
  396. err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
  397. if (err)
  398. goto fail;
  399. /* PWM 1 output on EGPIO[14] */
  400. ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
  401. } else {
  402. err = -ENODEV;
  403. }
  404. return err;
  405. fail:
  406. gpio_free(EP93XX_GPIO_LINE_EGPIO14);
  407. return err;
  408. }
  409. EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
  410. void ep93xx_pwm_release_gpio(struct platform_device *pdev)
  411. {
  412. if (pdev->id == 1) {
  413. gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
  414. gpio_free(EP93XX_GPIO_LINE_EGPIO14);
  415. /* EGPIO[14] used for GPIO */
  416. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
  417. }
  418. }
  419. EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
  420. /*************************************************************************
  421. * EP93xx video peripheral handling
  422. *************************************************************************/
  423. static struct ep93xxfb_mach_info ep93xxfb_data;
  424. static struct resource ep93xx_fb_resource[] = {
  425. DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
  426. };
  427. static struct platform_device ep93xx_fb_device = {
  428. .name = "ep93xx-fb",
  429. .id = -1,
  430. .dev = {
  431. .platform_data = &ep93xxfb_data,
  432. .coherent_dma_mask = DMA_BIT_MASK(32),
  433. .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
  434. },
  435. .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
  436. .resource = ep93xx_fb_resource,
  437. };
  438. /* The backlight use a single register in the framebuffer's register space */
  439. #define EP93XX_RASTER_REG_BRIGHTNESS 0x20
  440. static struct resource ep93xx_bl_resources[] = {
  441. DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
  442. EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
  443. };
  444. static struct platform_device ep93xx_bl_device = {
  445. .name = "ep93xx-bl",
  446. .id = -1,
  447. .num_resources = ARRAY_SIZE(ep93xx_bl_resources),
  448. .resource = ep93xx_bl_resources,
  449. };
  450. /**
  451. * ep93xx_register_fb - Register the framebuffer platform device.
  452. * @data: platform specific framebuffer configuration (__initdata)
  453. */
  454. void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
  455. {
  456. ep93xxfb_data = *data;
  457. platform_device_register(&ep93xx_fb_device);
  458. platform_device_register(&ep93xx_bl_device);
  459. }
  460. /*************************************************************************
  461. * EP93xx matrix keypad peripheral handling
  462. *************************************************************************/
  463. static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
  464. static struct resource ep93xx_keypad_resource[] = {
  465. DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
  466. DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
  467. };
  468. static struct platform_device ep93xx_keypad_device = {
  469. .name = "ep93xx-keypad",
  470. .id = -1,
  471. .dev = {
  472. .platform_data = &ep93xx_keypad_data,
  473. },
  474. .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
  475. .resource = ep93xx_keypad_resource,
  476. };
  477. /**
  478. * ep93xx_register_keypad - Register the keypad platform device.
  479. * @data: platform specific keypad configuration (__initdata)
  480. */
  481. void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
  482. {
  483. ep93xx_keypad_data = *data;
  484. platform_device_register(&ep93xx_keypad_device);
  485. }
  486. int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
  487. {
  488. int err;
  489. int i;
  490. for (i = 0; i < 8; i++) {
  491. err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
  492. if (err)
  493. goto fail_gpio_c;
  494. err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
  495. if (err)
  496. goto fail_gpio_d;
  497. }
  498. /* Enable the keypad controller; GPIO ports C and D used for keypad */
  499. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
  500. EP93XX_SYSCON_DEVCFG_GONK);
  501. return 0;
  502. fail_gpio_d:
  503. gpio_free(EP93XX_GPIO_LINE_C(i));
  504. fail_gpio_c:
  505. for (--i; i >= 0; --i) {
  506. gpio_free(EP93XX_GPIO_LINE_C(i));
  507. gpio_free(EP93XX_GPIO_LINE_D(i));
  508. }
  509. return err;
  510. }
  511. EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
  512. void ep93xx_keypad_release_gpio(struct platform_device *pdev)
  513. {
  514. int i;
  515. for (i = 0; i < 8; i++) {
  516. gpio_free(EP93XX_GPIO_LINE_C(i));
  517. gpio_free(EP93XX_GPIO_LINE_D(i));
  518. }
  519. /* Disable the keypad controller; GPIO ports C and D used for GPIO */
  520. ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
  521. EP93XX_SYSCON_DEVCFG_GONK);
  522. }
  523. EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
  524. /*************************************************************************
  525. * EP93xx I2S audio peripheral handling
  526. *************************************************************************/
  527. static struct resource ep93xx_i2s_resource[] = {
  528. DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
  529. };
  530. static struct platform_device ep93xx_i2s_device = {
  531. .name = "ep93xx-i2s",
  532. .id = -1,
  533. .num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
  534. .resource = ep93xx_i2s_resource,
  535. };
  536. static struct platform_device ep93xx_pcm_device = {
  537. .name = "ep93xx-pcm-audio",
  538. .id = -1,
  539. };
  540. void __init ep93xx_register_i2s(void)
  541. {
  542. platform_device_register(&ep93xx_i2s_device);
  543. platform_device_register(&ep93xx_pcm_device);
  544. }
  545. #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
  546. EP93XX_SYSCON_DEVCFG_I2SONAC97)
  547. #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
  548. EP93XX_SYSCON_I2SCLKDIV_SPOL)
  549. int ep93xx_i2s_acquire(void)
  550. {
  551. unsigned val;
  552. ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
  553. EP93XX_SYSCON_DEVCFG_I2S_MASK);
  554. /*
  555. * This is potentially racy with the clock api for i2s_mclk, sclk and
  556. * lrclk. Since the i2s driver is the only user of those clocks we
  557. * rely on it to prevent parallel use of this function and the
  558. * clock api for the i2s clocks.
  559. */
  560. val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
  561. val &= ~EP93XX_I2SCLKDIV_MASK;
  562. val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
  563. ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
  564. return 0;
  565. }
  566. EXPORT_SYMBOL(ep93xx_i2s_acquire);
  567. void ep93xx_i2s_release(void)
  568. {
  569. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
  570. }
  571. EXPORT_SYMBOL(ep93xx_i2s_release);
  572. /*************************************************************************
  573. * EP93xx AC97 audio peripheral handling
  574. *************************************************************************/
  575. static struct resource ep93xx_ac97_resources[] = {
  576. DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
  577. DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
  578. };
  579. static struct platform_device ep93xx_ac97_device = {
  580. .name = "ep93xx-ac97",
  581. .id = -1,
  582. .num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
  583. .resource = ep93xx_ac97_resources,
  584. };
  585. void __init ep93xx_register_ac97(void)
  586. {
  587. /*
  588. * Make sure that the AC97 pins are not used by I2S.
  589. */
  590. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
  591. platform_device_register(&ep93xx_ac97_device);
  592. platform_device_register(&ep93xx_pcm_device);
  593. }
  594. /*************************************************************************
  595. * EP93xx Watchdog
  596. *************************************************************************/
  597. static struct resource ep93xx_wdt_resources[] = {
  598. DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
  599. };
  600. static struct platform_device ep93xx_wdt_device = {
  601. .name = "ep93xx-wdt",
  602. .id = -1,
  603. .num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
  604. .resource = ep93xx_wdt_resources,
  605. };
  606. /*************************************************************************
  607. * EP93xx IDE
  608. *************************************************************************/
  609. static struct resource ep93xx_ide_resources[] = {
  610. DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
  611. DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
  612. };
  613. static struct platform_device ep93xx_ide_device = {
  614. .name = "ep93xx-ide",
  615. .id = -1,
  616. .dev = {
  617. .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
  618. .coherent_dma_mask = DMA_BIT_MASK(32),
  619. },
  620. .num_resources = ARRAY_SIZE(ep93xx_ide_resources),
  621. .resource = ep93xx_ide_resources,
  622. };
  623. void __init ep93xx_register_ide(void)
  624. {
  625. platform_device_register(&ep93xx_ide_device);
  626. }
  627. int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
  628. {
  629. int err;
  630. int i;
  631. err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
  632. if (err)
  633. return err;
  634. err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
  635. if (err)
  636. goto fail_egpio15;
  637. for (i = 2; i < 8; i++) {
  638. err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
  639. if (err)
  640. goto fail_gpio_e;
  641. }
  642. for (i = 4; i < 8; i++) {
  643. err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
  644. if (err)
  645. goto fail_gpio_g;
  646. }
  647. for (i = 0; i < 8; i++) {
  648. err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
  649. if (err)
  650. goto fail_gpio_h;
  651. }
  652. /* GPIO ports E[7:2], G[7:4] and H used by IDE */
  653. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
  654. EP93XX_SYSCON_DEVCFG_GONIDE |
  655. EP93XX_SYSCON_DEVCFG_HONIDE);
  656. return 0;
  657. fail_gpio_h:
  658. for (--i; i >= 0; --i)
  659. gpio_free(EP93XX_GPIO_LINE_H(i));
  660. i = 8;
  661. fail_gpio_g:
  662. for (--i; i >= 4; --i)
  663. gpio_free(EP93XX_GPIO_LINE_G(i));
  664. i = 8;
  665. fail_gpio_e:
  666. for (--i; i >= 2; --i)
  667. gpio_free(EP93XX_GPIO_LINE_E(i));
  668. gpio_free(EP93XX_GPIO_LINE_EGPIO15);
  669. fail_egpio15:
  670. gpio_free(EP93XX_GPIO_LINE_EGPIO2);
  671. return err;
  672. }
  673. EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
  674. void ep93xx_ide_release_gpio(struct platform_device *pdev)
  675. {
  676. int i;
  677. for (i = 2; i < 8; i++)
  678. gpio_free(EP93XX_GPIO_LINE_E(i));
  679. for (i = 4; i < 8; i++)
  680. gpio_free(EP93XX_GPIO_LINE_G(i));
  681. for (i = 0; i < 8; i++)
  682. gpio_free(EP93XX_GPIO_LINE_H(i));
  683. gpio_free(EP93XX_GPIO_LINE_EGPIO15);
  684. gpio_free(EP93XX_GPIO_LINE_EGPIO2);
  685. /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
  686. ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
  687. EP93XX_SYSCON_DEVCFG_GONIDE |
  688. EP93XX_SYSCON_DEVCFG_HONIDE);
  689. }
  690. EXPORT_SYMBOL(ep93xx_ide_release_gpio);
  691. /*************************************************************************
  692. * EP93xx Security peripheral
  693. *************************************************************************/
  694. /*
  695. * The Maverick Key is 256 bits of micro fuses blown at the factory during
  696. * manufacturing to uniquely identify a part.
  697. *
  698. * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
  699. */
  700. #define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
  701. #define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
  702. #define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
  703. #define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
  704. #define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
  705. #define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
  706. #define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
  707. #define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
  708. #define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
  709. #define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
  710. #define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
  711. #define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
  712. #define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
  713. #define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
  714. static char ep93xx_soc_id[33];
  715. static const char __init *ep93xx_get_soc_id(void)
  716. {
  717. unsigned int id, id2, id3, id4, id5;
  718. if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
  719. return "bad Hamming code";
  720. id = __raw_readl(EP93XX_SECURITY_UNIQID);
  721. id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
  722. id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
  723. id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
  724. id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
  725. if (id != id2)
  726. return "invalid";
  727. /* Toss the unique ID into the entropy pool */
  728. add_device_randomness(&id2, 4);
  729. add_device_randomness(&id3, 4);
  730. add_device_randomness(&id4, 4);
  731. add_device_randomness(&id5, 4);
  732. snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
  733. "%08x%08x%08x%08x", id2, id3, id4, id5);
  734. return ep93xx_soc_id;
  735. }
  736. static const char __init *ep93xx_get_soc_rev(void)
  737. {
  738. int rev = ep93xx_chip_revision();
  739. switch (rev) {
  740. case EP93XX_CHIP_REV_D0:
  741. return "D0";
  742. case EP93XX_CHIP_REV_D1:
  743. return "D1";
  744. case EP93XX_CHIP_REV_E0:
  745. return "E0";
  746. case EP93XX_CHIP_REV_E1:
  747. return "E1";
  748. case EP93XX_CHIP_REV_E2:
  749. return "E2";
  750. default:
  751. return "unknown";
  752. }
  753. }
  754. static const char __init *ep93xx_get_machine_name(void)
  755. {
  756. return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
  757. }
  758. static struct device __init *ep93xx_init_soc(void)
  759. {
  760. struct soc_device_attribute *soc_dev_attr;
  761. struct soc_device *soc_dev;
  762. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  763. if (!soc_dev_attr)
  764. return NULL;
  765. soc_dev_attr->machine = ep93xx_get_machine_name();
  766. soc_dev_attr->family = "Cirrus Logic EP93xx";
  767. soc_dev_attr->revision = ep93xx_get_soc_rev();
  768. soc_dev_attr->soc_id = ep93xx_get_soc_id();
  769. soc_dev = soc_device_register(soc_dev_attr);
  770. if (IS_ERR(soc_dev)) {
  771. kfree(soc_dev_attr->machine);
  772. kfree(soc_dev_attr);
  773. return NULL;
  774. }
  775. return soc_device_to_device(soc_dev);
  776. }
  777. struct device __init *ep93xx_init_devices(void)
  778. {
  779. struct device *parent;
  780. /* Disallow access to MaverickCrunch initially */
  781. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
  782. /* Default all ports to GPIO */
  783. ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
  784. EP93XX_SYSCON_DEVCFG_GONK |
  785. EP93XX_SYSCON_DEVCFG_EONIDE |
  786. EP93XX_SYSCON_DEVCFG_GONIDE |
  787. EP93XX_SYSCON_DEVCFG_HONIDE);
  788. parent = ep93xx_init_soc();
  789. /* Get the GPIO working early, other devices need it */
  790. platform_device_register(&ep93xx_gpio_device);
  791. amba_device_register(&uart1_device, &iomem_resource);
  792. amba_device_register(&uart2_device, &iomem_resource);
  793. amba_device_register(&uart3_device, &iomem_resource);
  794. platform_device_register(&ep93xx_rtc_device);
  795. platform_device_register(&ep93xx_ohci_device);
  796. platform_device_register(&ep93xx_wdt_device);
  797. gpio_led_register_device(-1, &ep93xx_led_data);
  798. return parent;
  799. }
  800. void ep93xx_restart(enum reboot_mode mode, const char *cmd)
  801. {
  802. /*
  803. * Set then clear the SWRST bit to initiate a software reset
  804. */
  805. ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
  806. ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
  807. while (1)
  808. ;
  809. }
  810. void __init ep93xx_init_late(void)
  811. {
  812. crunch_init();
  813. }