rtc-sh.c 19 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/kernel.h>
  20. #include <linux/bcd.h>
  21. #include <linux/rtc.h>
  22. #include <linux/init.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/seq_file.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/io.h>
  28. #include <linux/log2.h>
  29. #include <linux/clk.h>
  30. #include <linux/slab.h>
  31. #ifdef CONFIG_SUPERH
  32. #include <asm/rtc.h>
  33. #else
  34. /* Default values for RZ/A RTC */
  35. #define rtc_reg_size sizeof(u16)
  36. #define RTC_BIT_INVERTED 0 /* no chip bugs */
  37. #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
  38. #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
  39. #endif
  40. #define DRV_NAME "sh-rtc"
  41. #define RTC_REG(r) ((r) * rtc_reg_size)
  42. #define R64CNT RTC_REG(0)
  43. #define RSECCNT RTC_REG(1) /* RTC sec */
  44. #define RMINCNT RTC_REG(2) /* RTC min */
  45. #define RHRCNT RTC_REG(3) /* RTC hour */
  46. #define RWKCNT RTC_REG(4) /* RTC week */
  47. #define RDAYCNT RTC_REG(5) /* RTC day */
  48. #define RMONCNT RTC_REG(6) /* RTC month */
  49. #define RYRCNT RTC_REG(7) /* RTC year */
  50. #define RSECAR RTC_REG(8) /* ALARM sec */
  51. #define RMINAR RTC_REG(9) /* ALARM min */
  52. #define RHRAR RTC_REG(10) /* ALARM hour */
  53. #define RWKAR RTC_REG(11) /* ALARM week */
  54. #define RDAYAR RTC_REG(12) /* ALARM day */
  55. #define RMONAR RTC_REG(13) /* ALARM month */
  56. #define RCR1 RTC_REG(14) /* Control */
  57. #define RCR2 RTC_REG(15) /* Control */
  58. /*
  59. * Note on RYRAR and RCR3: Up until this point most of the register
  60. * definitions are consistent across all of the available parts. However,
  61. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  62. * register used to control RYRCNT/RYRAR compare) varies considerably
  63. * across various parts, occasionally being mapped in to a completely
  64. * unrelated address space. For proper RYRAR support a separate resource
  65. * would have to be handed off, but as this is purely optional in
  66. * practice, we simply opt not to support it, thereby keeping the code
  67. * quite a bit more simplified.
  68. */
  69. /* ALARM Bits - or with BCD encoded value */
  70. #define AR_ENB 0x80 /* Enable for alarm cmp */
  71. /* Period Bits */
  72. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  73. #define PF_COUNT 0x200 /* Half periodic counter */
  74. #define PF_OXS 0x400 /* Periodic One x Second */
  75. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  76. #define PF_MASK 0xf00
  77. /* RCR1 Bits */
  78. #define RCR1_CF 0x80 /* Carry Flag */
  79. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  80. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  81. #define RCR1_AF 0x01 /* Alarm Flag */
  82. /* RCR2 Bits */
  83. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  84. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  85. #define RCR2_RTCEN 0x08 /* ENable RTC */
  86. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  87. #define RCR2_RESET 0x02 /* Reset bit */
  88. #define RCR2_START 0x01 /* Start bit */
  89. struct sh_rtc {
  90. void __iomem *regbase;
  91. unsigned long regsize;
  92. struct resource *res;
  93. int alarm_irq;
  94. int periodic_irq;
  95. int carry_irq;
  96. struct clk *clk;
  97. struct rtc_device *rtc_dev;
  98. spinlock_t lock;
  99. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  100. unsigned short periodic_freq;
  101. };
  102. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  103. {
  104. unsigned int tmp, pending;
  105. tmp = readb(rtc->regbase + RCR1);
  106. pending = tmp & RCR1_CF;
  107. tmp &= ~RCR1_CF;
  108. writeb(tmp, rtc->regbase + RCR1);
  109. /* Users have requested One x Second IRQ */
  110. if (pending && rtc->periodic_freq & PF_OXS)
  111. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  112. return pending;
  113. }
  114. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  115. {
  116. unsigned int tmp, pending;
  117. tmp = readb(rtc->regbase + RCR1);
  118. pending = tmp & RCR1_AF;
  119. tmp &= ~(RCR1_AF | RCR1_AIE);
  120. writeb(tmp, rtc->regbase + RCR1);
  121. if (pending)
  122. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  123. return pending;
  124. }
  125. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  126. {
  127. struct rtc_device *rtc_dev = rtc->rtc_dev;
  128. struct rtc_task *irq_task;
  129. unsigned int tmp, pending;
  130. tmp = readb(rtc->regbase + RCR2);
  131. pending = tmp & RCR2_PEF;
  132. tmp &= ~RCR2_PEF;
  133. writeb(tmp, rtc->regbase + RCR2);
  134. if (!pending)
  135. return 0;
  136. /* Half period enabled than one skipped and the next notified */
  137. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  138. rtc->periodic_freq &= ~PF_COUNT;
  139. else {
  140. if (rtc->periodic_freq & PF_HP)
  141. rtc->periodic_freq |= PF_COUNT;
  142. if (rtc->periodic_freq & PF_KOU) {
  143. spin_lock(&rtc_dev->irq_task_lock);
  144. irq_task = rtc_dev->irq_task;
  145. if (irq_task)
  146. irq_task->func(irq_task->private_data);
  147. spin_unlock(&rtc_dev->irq_task_lock);
  148. } else
  149. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  150. }
  151. return pending;
  152. }
  153. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  154. {
  155. struct sh_rtc *rtc = dev_id;
  156. int ret;
  157. spin_lock(&rtc->lock);
  158. ret = __sh_rtc_interrupt(rtc);
  159. spin_unlock(&rtc->lock);
  160. return IRQ_RETVAL(ret);
  161. }
  162. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  163. {
  164. struct sh_rtc *rtc = dev_id;
  165. int ret;
  166. spin_lock(&rtc->lock);
  167. ret = __sh_rtc_alarm(rtc);
  168. spin_unlock(&rtc->lock);
  169. return IRQ_RETVAL(ret);
  170. }
  171. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  172. {
  173. struct sh_rtc *rtc = dev_id;
  174. int ret;
  175. spin_lock(&rtc->lock);
  176. ret = __sh_rtc_periodic(rtc);
  177. spin_unlock(&rtc->lock);
  178. return IRQ_RETVAL(ret);
  179. }
  180. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  181. {
  182. struct sh_rtc *rtc = dev_id;
  183. int ret;
  184. spin_lock(&rtc->lock);
  185. ret = __sh_rtc_interrupt(rtc);
  186. ret |= __sh_rtc_alarm(rtc);
  187. ret |= __sh_rtc_periodic(rtc);
  188. spin_unlock(&rtc->lock);
  189. return IRQ_RETVAL(ret);
  190. }
  191. static int sh_rtc_irq_set_state(struct device *dev, int enable)
  192. {
  193. struct sh_rtc *rtc = dev_get_drvdata(dev);
  194. unsigned int tmp;
  195. spin_lock_irq(&rtc->lock);
  196. tmp = readb(rtc->regbase + RCR2);
  197. if (enable) {
  198. rtc->periodic_freq |= PF_KOU;
  199. tmp &= ~RCR2_PEF; /* Clear PES bit */
  200. tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
  201. } else {
  202. rtc->periodic_freq &= ~PF_KOU;
  203. tmp &= ~(RCR2_PESMASK | RCR2_PEF);
  204. }
  205. writeb(tmp, rtc->regbase + RCR2);
  206. spin_unlock_irq(&rtc->lock);
  207. return 0;
  208. }
  209. static int sh_rtc_irq_set_freq(struct device *dev, int freq)
  210. {
  211. struct sh_rtc *rtc = dev_get_drvdata(dev);
  212. int tmp, ret = 0;
  213. spin_lock_irq(&rtc->lock);
  214. tmp = rtc->periodic_freq & PF_MASK;
  215. switch (freq) {
  216. case 0:
  217. rtc->periodic_freq = 0x00;
  218. break;
  219. case 1:
  220. rtc->periodic_freq = 0x60;
  221. break;
  222. case 2:
  223. rtc->periodic_freq = 0x50;
  224. break;
  225. case 4:
  226. rtc->periodic_freq = 0x40;
  227. break;
  228. case 8:
  229. rtc->periodic_freq = 0x30 | PF_HP;
  230. break;
  231. case 16:
  232. rtc->periodic_freq = 0x30;
  233. break;
  234. case 32:
  235. rtc->periodic_freq = 0x20 | PF_HP;
  236. break;
  237. case 64:
  238. rtc->periodic_freq = 0x20;
  239. break;
  240. case 128:
  241. rtc->periodic_freq = 0x10 | PF_HP;
  242. break;
  243. case 256:
  244. rtc->periodic_freq = 0x10;
  245. break;
  246. default:
  247. ret = -ENOTSUPP;
  248. }
  249. if (ret == 0)
  250. rtc->periodic_freq |= tmp;
  251. spin_unlock_irq(&rtc->lock);
  252. return ret;
  253. }
  254. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  255. {
  256. struct sh_rtc *rtc = dev_get_drvdata(dev);
  257. unsigned int tmp;
  258. spin_lock_irq(&rtc->lock);
  259. tmp = readb(rtc->regbase + RCR1);
  260. if (enable)
  261. tmp |= RCR1_AIE;
  262. else
  263. tmp &= ~RCR1_AIE;
  264. writeb(tmp, rtc->regbase + RCR1);
  265. spin_unlock_irq(&rtc->lock);
  266. }
  267. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  268. {
  269. struct sh_rtc *rtc = dev_get_drvdata(dev);
  270. unsigned int tmp;
  271. tmp = readb(rtc->regbase + RCR1);
  272. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  273. tmp = readb(rtc->regbase + RCR2);
  274. seq_printf(seq, "periodic_IRQ\t: %s\n",
  275. (tmp & RCR2_PESMASK) ? "yes" : "no");
  276. return 0;
  277. }
  278. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  279. {
  280. struct sh_rtc *rtc = dev_get_drvdata(dev);
  281. unsigned int tmp;
  282. spin_lock_irq(&rtc->lock);
  283. tmp = readb(rtc->regbase + RCR1);
  284. if (!enable)
  285. tmp &= ~RCR1_CIE;
  286. else
  287. tmp |= RCR1_CIE;
  288. writeb(tmp, rtc->regbase + RCR1);
  289. spin_unlock_irq(&rtc->lock);
  290. }
  291. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  292. {
  293. sh_rtc_setaie(dev, enabled);
  294. return 0;
  295. }
  296. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  297. {
  298. struct sh_rtc *rtc = dev_get_drvdata(dev);
  299. unsigned int sec128, sec2, yr, yr100, cf_bit;
  300. do {
  301. unsigned int tmp;
  302. spin_lock_irq(&rtc->lock);
  303. tmp = readb(rtc->regbase + RCR1);
  304. tmp &= ~RCR1_CF; /* Clear CF-bit */
  305. tmp |= RCR1_CIE;
  306. writeb(tmp, rtc->regbase + RCR1);
  307. sec128 = readb(rtc->regbase + R64CNT);
  308. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  309. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  310. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  311. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  312. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  313. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  314. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  315. yr = readw(rtc->regbase + RYRCNT);
  316. yr100 = bcd2bin(yr >> 8);
  317. yr &= 0xff;
  318. } else {
  319. yr = readb(rtc->regbase + RYRCNT);
  320. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  321. }
  322. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  323. sec2 = readb(rtc->regbase + R64CNT);
  324. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  325. spin_unlock_irq(&rtc->lock);
  326. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  327. #if RTC_BIT_INVERTED != 0
  328. if ((sec128 & RTC_BIT_INVERTED))
  329. tm->tm_sec--;
  330. #endif
  331. /* only keep the carry interrupt enabled if UIE is on */
  332. if (!(rtc->periodic_freq & PF_OXS))
  333. sh_rtc_setcie(dev, 0);
  334. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  335. "mday=%d, mon=%d, year=%d, wday=%d\n",
  336. __func__,
  337. tm->tm_sec, tm->tm_min, tm->tm_hour,
  338. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  339. return 0;
  340. }
  341. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  342. {
  343. struct sh_rtc *rtc = dev_get_drvdata(dev);
  344. unsigned int tmp;
  345. int year;
  346. spin_lock_irq(&rtc->lock);
  347. /* Reset pre-scaler & stop RTC */
  348. tmp = readb(rtc->regbase + RCR2);
  349. tmp |= RCR2_RESET;
  350. tmp &= ~RCR2_START;
  351. writeb(tmp, rtc->regbase + RCR2);
  352. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  353. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  354. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  355. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  356. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  357. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  358. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  359. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  360. bin2bcd(tm->tm_year % 100);
  361. writew(year, rtc->regbase + RYRCNT);
  362. } else {
  363. year = tm->tm_year % 100;
  364. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  365. }
  366. /* Start RTC */
  367. tmp = readb(rtc->regbase + RCR2);
  368. tmp &= ~RCR2_RESET;
  369. tmp |= RCR2_RTCEN | RCR2_START;
  370. writeb(tmp, rtc->regbase + RCR2);
  371. spin_unlock_irq(&rtc->lock);
  372. return 0;
  373. }
  374. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  375. {
  376. unsigned int byte;
  377. int value = 0xff; /* return 0xff for ignored values */
  378. byte = readb(rtc->regbase + reg_off);
  379. if (byte & AR_ENB) {
  380. byte &= ~AR_ENB; /* strip the enable bit */
  381. value = bcd2bin(byte);
  382. }
  383. return value;
  384. }
  385. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  386. {
  387. struct sh_rtc *rtc = dev_get_drvdata(dev);
  388. struct rtc_time *tm = &wkalrm->time;
  389. spin_lock_irq(&rtc->lock);
  390. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  391. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  392. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  393. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  394. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  395. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  396. if (tm->tm_mon > 0)
  397. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  398. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  399. spin_unlock_irq(&rtc->lock);
  400. return 0;
  401. }
  402. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  403. int value, int reg_off)
  404. {
  405. /* < 0 for a value that is ignored */
  406. if (value < 0)
  407. writeb(0, rtc->regbase + reg_off);
  408. else
  409. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  410. }
  411. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  412. {
  413. struct sh_rtc *rtc = dev_get_drvdata(dev);
  414. unsigned int rcr1;
  415. struct rtc_time *tm = &wkalrm->time;
  416. int mon;
  417. spin_lock_irq(&rtc->lock);
  418. /* disable alarm interrupt and clear the alarm flag */
  419. rcr1 = readb(rtc->regbase + RCR1);
  420. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  421. writeb(rcr1, rtc->regbase + RCR1);
  422. /* set alarm time */
  423. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  424. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  425. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  426. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  427. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  428. mon = tm->tm_mon;
  429. if (mon >= 0)
  430. mon += 1;
  431. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  432. if (wkalrm->enabled) {
  433. rcr1 |= RCR1_AIE;
  434. writeb(rcr1, rtc->regbase + RCR1);
  435. }
  436. spin_unlock_irq(&rtc->lock);
  437. return 0;
  438. }
  439. static const struct rtc_class_ops sh_rtc_ops = {
  440. .read_time = sh_rtc_read_time,
  441. .set_time = sh_rtc_set_time,
  442. .read_alarm = sh_rtc_read_alarm,
  443. .set_alarm = sh_rtc_set_alarm,
  444. .proc = sh_rtc_proc,
  445. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  446. };
  447. static int __init sh_rtc_probe(struct platform_device *pdev)
  448. {
  449. struct sh_rtc *rtc;
  450. struct resource *res;
  451. struct rtc_time r;
  452. char clk_name[6];
  453. int clk_id, ret;
  454. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  455. if (unlikely(!rtc))
  456. return -ENOMEM;
  457. spin_lock_init(&rtc->lock);
  458. /* get periodic/carry/alarm irqs */
  459. ret = platform_get_irq(pdev, 0);
  460. if (unlikely(ret <= 0)) {
  461. dev_err(&pdev->dev, "No IRQ resource\n");
  462. return -ENOENT;
  463. }
  464. rtc->periodic_irq = ret;
  465. rtc->carry_irq = platform_get_irq(pdev, 1);
  466. rtc->alarm_irq = platform_get_irq(pdev, 2);
  467. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  468. if (!res)
  469. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  470. if (unlikely(res == NULL)) {
  471. dev_err(&pdev->dev, "No IO resource\n");
  472. return -ENOENT;
  473. }
  474. rtc->regsize = resource_size(res);
  475. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  476. rtc->regsize, pdev->name);
  477. if (unlikely(!rtc->res))
  478. return -EBUSY;
  479. rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
  480. rtc->regsize);
  481. if (unlikely(!rtc->regbase))
  482. return -EINVAL;
  483. if (!pdev->dev.of_node) {
  484. clk_id = pdev->id;
  485. /* With a single device, the clock id is still "rtc0" */
  486. if (clk_id < 0)
  487. clk_id = 0;
  488. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  489. } else
  490. snprintf(clk_name, sizeof(clk_name), "fck");
  491. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  492. if (IS_ERR(rtc->clk)) {
  493. /*
  494. * No error handling for rtc->clk intentionally, not all
  495. * platforms will have a unique clock for the RTC, and
  496. * the clk API can handle the struct clk pointer being
  497. * NULL.
  498. */
  499. rtc->clk = NULL;
  500. }
  501. clk_enable(rtc->clk);
  502. rtc->capabilities = RTC_DEF_CAPABILITIES;
  503. #ifdef CONFIG_SUPERH
  504. if (dev_get_platdata(&pdev->dev)) {
  505. struct sh_rtc_platform_info *pinfo =
  506. dev_get_platdata(&pdev->dev);
  507. /*
  508. * Some CPUs have special capabilities in addition to the
  509. * default set. Add those in here.
  510. */
  511. rtc->capabilities |= pinfo->capabilities;
  512. }
  513. #endif
  514. if (rtc->carry_irq <= 0) {
  515. /* register shared periodic/carry/alarm irq */
  516. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  517. sh_rtc_shared, 0, "sh-rtc", rtc);
  518. if (unlikely(ret)) {
  519. dev_err(&pdev->dev,
  520. "request IRQ failed with %d, IRQ %d\n", ret,
  521. rtc->periodic_irq);
  522. goto err_unmap;
  523. }
  524. } else {
  525. /* register periodic/carry/alarm irqs */
  526. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  527. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  528. if (unlikely(ret)) {
  529. dev_err(&pdev->dev,
  530. "request period IRQ failed with %d, IRQ %d\n",
  531. ret, rtc->periodic_irq);
  532. goto err_unmap;
  533. }
  534. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  535. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  536. if (unlikely(ret)) {
  537. dev_err(&pdev->dev,
  538. "request carry IRQ failed with %d, IRQ %d\n",
  539. ret, rtc->carry_irq);
  540. goto err_unmap;
  541. }
  542. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  543. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  544. if (unlikely(ret)) {
  545. dev_err(&pdev->dev,
  546. "request alarm IRQ failed with %d, IRQ %d\n",
  547. ret, rtc->alarm_irq);
  548. goto err_unmap;
  549. }
  550. }
  551. platform_set_drvdata(pdev, rtc);
  552. /* everything disabled by default */
  553. sh_rtc_irq_set_freq(&pdev->dev, 0);
  554. sh_rtc_irq_set_state(&pdev->dev, 0);
  555. sh_rtc_setaie(&pdev->dev, 0);
  556. sh_rtc_setcie(&pdev->dev, 0);
  557. rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
  558. &sh_rtc_ops, THIS_MODULE);
  559. if (IS_ERR(rtc->rtc_dev)) {
  560. ret = PTR_ERR(rtc->rtc_dev);
  561. goto err_unmap;
  562. }
  563. rtc->rtc_dev->max_user_freq = 256;
  564. /* reset rtc to epoch 0 if time is invalid */
  565. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  566. rtc_time_to_tm(0, &r);
  567. rtc_set_time(rtc->rtc_dev, &r);
  568. }
  569. device_init_wakeup(&pdev->dev, 1);
  570. return 0;
  571. err_unmap:
  572. clk_disable(rtc->clk);
  573. return ret;
  574. }
  575. static int __exit sh_rtc_remove(struct platform_device *pdev)
  576. {
  577. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  578. sh_rtc_irq_set_state(&pdev->dev, 0);
  579. sh_rtc_setaie(&pdev->dev, 0);
  580. sh_rtc_setcie(&pdev->dev, 0);
  581. clk_disable(rtc->clk);
  582. return 0;
  583. }
  584. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  585. {
  586. struct sh_rtc *rtc = dev_get_drvdata(dev);
  587. irq_set_irq_wake(rtc->periodic_irq, enabled);
  588. if (rtc->carry_irq > 0) {
  589. irq_set_irq_wake(rtc->carry_irq, enabled);
  590. irq_set_irq_wake(rtc->alarm_irq, enabled);
  591. }
  592. }
  593. static int __maybe_unused sh_rtc_suspend(struct device *dev)
  594. {
  595. if (device_may_wakeup(dev))
  596. sh_rtc_set_irq_wake(dev, 1);
  597. return 0;
  598. }
  599. static int __maybe_unused sh_rtc_resume(struct device *dev)
  600. {
  601. if (device_may_wakeup(dev))
  602. sh_rtc_set_irq_wake(dev, 0);
  603. return 0;
  604. }
  605. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  606. static const struct of_device_id sh_rtc_of_match[] = {
  607. { .compatible = "renesas,sh-rtc", },
  608. { /* sentinel */ }
  609. };
  610. MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
  611. static struct platform_driver sh_rtc_platform_driver = {
  612. .driver = {
  613. .name = DRV_NAME,
  614. .pm = &sh_rtc_pm_ops,
  615. .of_match_table = sh_rtc_of_match,
  616. },
  617. .remove = __exit_p(sh_rtc_remove),
  618. };
  619. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  620. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  621. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  622. "Jamie Lenehan <lenehan@twibble.org>, "
  623. "Angelo Castello <angelo.castello@st.com>");
  624. MODULE_LICENSE("GPL");
  625. MODULE_ALIAS("platform:" DRV_NAME);