core.c 6.2 KB

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  1. /*
  2. * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/types.h>
  20. #include <crypto/algapi.h>
  21. #include <crypto/internal/hash.h>
  22. #include <crypto/sha.h>
  23. #include "core.h"
  24. #include "cipher.h"
  25. #include "sha.h"
  26. #define QCE_MAJOR_VERSION5 0x05
  27. #define QCE_QUEUE_LENGTH 1
  28. static const struct qce_algo_ops *qce_ops[] = {
  29. &ablkcipher_ops,
  30. &ahash_ops,
  31. };
  32. static void qce_unregister_algs(struct qce_device *qce)
  33. {
  34. const struct qce_algo_ops *ops;
  35. int i;
  36. for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
  37. ops = qce_ops[i];
  38. ops->unregister_algs(qce);
  39. }
  40. }
  41. static int qce_register_algs(struct qce_device *qce)
  42. {
  43. const struct qce_algo_ops *ops;
  44. int i, ret = -ENODEV;
  45. for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
  46. ops = qce_ops[i];
  47. ret = ops->register_algs(qce);
  48. if (ret)
  49. break;
  50. }
  51. return ret;
  52. }
  53. static int qce_handle_request(struct crypto_async_request *async_req)
  54. {
  55. int ret = -EINVAL, i;
  56. const struct qce_algo_ops *ops;
  57. u32 type = crypto_tfm_alg_type(async_req->tfm);
  58. for (i = 0; i < ARRAY_SIZE(qce_ops); i++) {
  59. ops = qce_ops[i];
  60. if (type != ops->type)
  61. continue;
  62. ret = ops->async_req_handle(async_req);
  63. break;
  64. }
  65. return ret;
  66. }
  67. static int qce_handle_queue(struct qce_device *qce,
  68. struct crypto_async_request *req)
  69. {
  70. struct crypto_async_request *async_req, *backlog;
  71. unsigned long flags;
  72. int ret = 0, err;
  73. spin_lock_irqsave(&qce->lock, flags);
  74. if (req)
  75. ret = crypto_enqueue_request(&qce->queue, req);
  76. /* busy, do not dequeue request */
  77. if (qce->req) {
  78. spin_unlock_irqrestore(&qce->lock, flags);
  79. return ret;
  80. }
  81. backlog = crypto_get_backlog(&qce->queue);
  82. async_req = crypto_dequeue_request(&qce->queue);
  83. if (async_req)
  84. qce->req = async_req;
  85. spin_unlock_irqrestore(&qce->lock, flags);
  86. if (!async_req)
  87. return ret;
  88. if (backlog) {
  89. spin_lock_bh(&qce->lock);
  90. backlog->complete(backlog, -EINPROGRESS);
  91. spin_unlock_bh(&qce->lock);
  92. }
  93. err = qce_handle_request(async_req);
  94. if (err) {
  95. qce->result = err;
  96. tasklet_schedule(&qce->done_tasklet);
  97. }
  98. return ret;
  99. }
  100. static void qce_tasklet_req_done(unsigned long data)
  101. {
  102. struct qce_device *qce = (struct qce_device *)data;
  103. struct crypto_async_request *req;
  104. unsigned long flags;
  105. spin_lock_irqsave(&qce->lock, flags);
  106. req = qce->req;
  107. qce->req = NULL;
  108. spin_unlock_irqrestore(&qce->lock, flags);
  109. if (req)
  110. req->complete(req, qce->result);
  111. qce_handle_queue(qce, NULL);
  112. }
  113. static int qce_async_request_enqueue(struct qce_device *qce,
  114. struct crypto_async_request *req)
  115. {
  116. return qce_handle_queue(qce, req);
  117. }
  118. static void qce_async_request_done(struct qce_device *qce, int ret)
  119. {
  120. qce->result = ret;
  121. tasklet_schedule(&qce->done_tasklet);
  122. }
  123. static int qce_check_version(struct qce_device *qce)
  124. {
  125. u32 major, minor, step;
  126. qce_get_version(qce, &major, &minor, &step);
  127. /*
  128. * the driver does not support v5 with minor 0 because it has special
  129. * alignment requirements.
  130. */
  131. if (major != QCE_MAJOR_VERSION5 || minor == 0)
  132. return -ENODEV;
  133. qce->burst_size = QCE_BAM_BURST_SIZE;
  134. qce->pipe_pair_id = 1;
  135. dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
  136. major, minor, step);
  137. return 0;
  138. }
  139. static int qce_crypto_probe(struct platform_device *pdev)
  140. {
  141. struct device *dev = &pdev->dev;
  142. struct qce_device *qce;
  143. struct resource *res;
  144. int ret;
  145. qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
  146. if (!qce)
  147. return -ENOMEM;
  148. qce->dev = dev;
  149. platform_set_drvdata(pdev, qce);
  150. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  151. qce->base = devm_ioremap_resource(&pdev->dev, res);
  152. if (IS_ERR(qce->base))
  153. return PTR_ERR(qce->base);
  154. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  155. if (ret < 0)
  156. return ret;
  157. qce->core = devm_clk_get(qce->dev, "core");
  158. if (IS_ERR(qce->core))
  159. return PTR_ERR(qce->core);
  160. qce->iface = devm_clk_get(qce->dev, "iface");
  161. if (IS_ERR(qce->iface))
  162. return PTR_ERR(qce->iface);
  163. qce->bus = devm_clk_get(qce->dev, "bus");
  164. if (IS_ERR(qce->bus))
  165. return PTR_ERR(qce->bus);
  166. ret = clk_prepare_enable(qce->core);
  167. if (ret)
  168. return ret;
  169. ret = clk_prepare_enable(qce->iface);
  170. if (ret)
  171. goto err_clks_core;
  172. ret = clk_prepare_enable(qce->bus);
  173. if (ret)
  174. goto err_clks_iface;
  175. ret = qce_dma_request(qce->dev, &qce->dma);
  176. if (ret)
  177. goto err_clks;
  178. ret = qce_check_version(qce);
  179. if (ret)
  180. goto err_clks;
  181. spin_lock_init(&qce->lock);
  182. tasklet_init(&qce->done_tasklet, qce_tasklet_req_done,
  183. (unsigned long)qce);
  184. crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);
  185. qce->async_req_enqueue = qce_async_request_enqueue;
  186. qce->async_req_done = qce_async_request_done;
  187. ret = qce_register_algs(qce);
  188. if (ret)
  189. goto err_dma;
  190. return 0;
  191. err_dma:
  192. qce_dma_release(&qce->dma);
  193. err_clks:
  194. clk_disable_unprepare(qce->bus);
  195. err_clks_iface:
  196. clk_disable_unprepare(qce->iface);
  197. err_clks_core:
  198. clk_disable_unprepare(qce->core);
  199. return ret;
  200. }
  201. static int qce_crypto_remove(struct platform_device *pdev)
  202. {
  203. struct qce_device *qce = platform_get_drvdata(pdev);
  204. tasklet_kill(&qce->done_tasklet);
  205. qce_unregister_algs(qce);
  206. qce_dma_release(&qce->dma);
  207. clk_disable_unprepare(qce->bus);
  208. clk_disable_unprepare(qce->iface);
  209. clk_disable_unprepare(qce->core);
  210. return 0;
  211. }
  212. static const struct of_device_id qce_crypto_of_match[] = {
  213. { .compatible = "qcom,crypto-v5.1", },
  214. {}
  215. };
  216. MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
  217. static struct platform_driver qce_crypto_driver = {
  218. .probe = qce_crypto_probe,
  219. .remove = qce_crypto_remove,
  220. .driver = {
  221. .name = KBUILD_MODNAME,
  222. .of_match_table = qce_crypto_of_match,
  223. },
  224. };
  225. module_platform_driver(qce_crypto_driver);
  226. MODULE_LICENSE("GPL v2");
  227. MODULE_DESCRIPTION("Qualcomm crypto engine driver");
  228. MODULE_ALIAS("platform:" KBUILD_MODNAME);
  229. MODULE_AUTHOR("The Linux Foundation");