core_intr.c 16 KB

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  1. /*
  2. * core_intr.c - DesignWare HS OTG Controller common interrupt handling
  3. *
  4. * Copyright (C) 2004-2013 Synopsys, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. /*
  37. * This file contains the common interrupt handlers
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/io.h>
  46. #include <linux/slab.h>
  47. #include <linux/usb.h>
  48. #include <linux/usb/hcd.h>
  49. #include <linux/usb/ch11.h>
  50. #include "core.h"
  51. #include "hcd.h"
  52. static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  53. {
  54. switch (hsotg->op_state) {
  55. case OTG_STATE_A_HOST:
  56. return "a_host";
  57. case OTG_STATE_A_SUSPEND:
  58. return "a_suspend";
  59. case OTG_STATE_A_PERIPHERAL:
  60. return "a_peripheral";
  61. case OTG_STATE_B_PERIPHERAL:
  62. return "b_peripheral";
  63. case OTG_STATE_B_HOST:
  64. return "b_host";
  65. default:
  66. return "unknown";
  67. }
  68. }
  69. /**
  70. * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  71. * When the PRTINT interrupt fires, there are certain status bits in the Host
  72. * Port that needs to get cleared.
  73. *
  74. * @hsotg: Programming view of DWC_otg controller
  75. */
  76. static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  77. {
  78. u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
  79. if (hprt0 & HPRT0_ENACHG) {
  80. hprt0 &= ~HPRT0_ENA;
  81. dwc2_writel(hprt0, hsotg->regs + HPRT0);
  82. }
  83. }
  84. /**
  85. * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  86. *
  87. * @hsotg: Programming view of DWC_otg controller
  88. */
  89. static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  90. {
  91. /* Clear interrupt */
  92. dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
  93. dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
  94. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  95. }
  96. /**
  97. * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
  98. * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
  99. *
  100. * @hsotg: Programming view of DWC_otg controller
  101. */
  102. static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
  103. {
  104. u32 gotgint;
  105. u32 gotgctl;
  106. u32 gintmsk;
  107. gotgint = dwc2_readl(hsotg->regs + GOTGINT);
  108. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  109. dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
  110. dwc2_op_state_str(hsotg));
  111. if (gotgint & GOTGINT_SES_END_DET) {
  112. dev_dbg(hsotg->dev,
  113. " ++OTG Interrupt: Session End Detected++ (%s)\n",
  114. dwc2_op_state_str(hsotg));
  115. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  116. if (dwc2_is_device_mode(hsotg))
  117. dwc2_hsotg_disconnect(hsotg);
  118. if (hsotg->op_state == OTG_STATE_B_HOST) {
  119. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  120. } else {
  121. /*
  122. * If not B_HOST and Device HNP still set, HNP did
  123. * not succeed!
  124. */
  125. if (gotgctl & GOTGCTL_DEVHNPEN) {
  126. dev_dbg(hsotg->dev, "Session End Detected\n");
  127. dev_err(hsotg->dev,
  128. "Device Not Connected/Responding!\n");
  129. }
  130. /*
  131. * If Session End Detected the B-Cable has been
  132. * disconnected
  133. */
  134. /* Reset to a clean state */
  135. hsotg->lx_state = DWC2_L0;
  136. }
  137. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  138. gotgctl &= ~GOTGCTL_DEVHNPEN;
  139. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  140. }
  141. if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
  142. dev_dbg(hsotg->dev,
  143. " ++OTG Interrupt: Session Request Success Status Change++\n");
  144. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  145. if (gotgctl & GOTGCTL_SESREQSCS) {
  146. if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
  147. hsotg->params.i2c_enable > 0) {
  148. hsotg->srp_success = 1;
  149. } else {
  150. /* Clear Session Request */
  151. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  152. gotgctl &= ~GOTGCTL_SESREQ;
  153. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  154. }
  155. }
  156. }
  157. if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
  158. /*
  159. * Print statements during the HNP interrupt handling
  160. * can cause it to fail
  161. */
  162. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  163. /*
  164. * WA for 3.00a- HW is not setting cur_mode, even sometimes
  165. * this does not help
  166. */
  167. if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
  168. udelay(100);
  169. if (gotgctl & GOTGCTL_HSTNEGSCS) {
  170. if (dwc2_is_host_mode(hsotg)) {
  171. hsotg->op_state = OTG_STATE_B_HOST;
  172. /*
  173. * Need to disable SOF interrupt immediately.
  174. * When switching from device to host, the PCD
  175. * interrupt handler won't handle the interrupt
  176. * if host mode is already set. The HCD
  177. * interrupt handler won't get called if the
  178. * HCD state is HALT. This means that the
  179. * interrupt does not get handled and Linux
  180. * complains loudly.
  181. */
  182. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  183. gintmsk &= ~GINTSTS_SOF;
  184. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  185. /*
  186. * Call callback function with spin lock
  187. * released
  188. */
  189. spin_unlock(&hsotg->lock);
  190. /* Initialize the Core for Host mode */
  191. dwc2_hcd_start(hsotg);
  192. spin_lock(&hsotg->lock);
  193. hsotg->op_state = OTG_STATE_B_HOST;
  194. }
  195. } else {
  196. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  197. gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
  198. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  199. dev_dbg(hsotg->dev, "HNP Failed\n");
  200. dev_err(hsotg->dev,
  201. "Device Not Connected/Responding\n");
  202. }
  203. }
  204. if (gotgint & GOTGINT_HST_NEG_DET) {
  205. /*
  206. * The disconnect interrupt is set at the same time as
  207. * Host Negotiation Detected. During the mode switch all
  208. * interrupts are cleared so the disconnect interrupt
  209. * handler will not get executed.
  210. */
  211. dev_dbg(hsotg->dev,
  212. " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
  213. (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
  214. if (dwc2_is_device_mode(hsotg)) {
  215. dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
  216. hsotg->op_state);
  217. spin_unlock(&hsotg->lock);
  218. dwc2_hcd_disconnect(hsotg, false);
  219. spin_lock(&hsotg->lock);
  220. hsotg->op_state = OTG_STATE_A_PERIPHERAL;
  221. } else {
  222. /* Need to disable SOF interrupt immediately */
  223. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  224. gintmsk &= ~GINTSTS_SOF;
  225. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  226. spin_unlock(&hsotg->lock);
  227. dwc2_hcd_start(hsotg);
  228. spin_lock(&hsotg->lock);
  229. hsotg->op_state = OTG_STATE_A_HOST;
  230. }
  231. }
  232. if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
  233. dev_dbg(hsotg->dev,
  234. " ++OTG Interrupt: A-Device Timeout Change++\n");
  235. if (gotgint & GOTGINT_DBNCE_DONE)
  236. dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
  237. /* Clear GOTGINT */
  238. dwc2_writel(gotgint, hsotg->regs + GOTGINT);
  239. }
  240. /**
  241. * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
  242. * Change Interrupt
  243. *
  244. * @hsotg: Programming view of DWC_otg controller
  245. *
  246. * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
  247. * Device to Host Mode transition or a Host to Device Mode transition. This only
  248. * occurs when the cable is connected/removed from the PHY connector.
  249. */
  250. static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
  251. {
  252. u32 gintmsk;
  253. /* Clear interrupt */
  254. dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
  255. /* Need to disable SOF interrupt immediately */
  256. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  257. gintmsk &= ~GINTSTS_SOF;
  258. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  259. dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
  260. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  261. /*
  262. * Need to schedule a work, as there are possible DELAY function calls.
  263. * Release lock before scheduling workq as it holds spinlock during
  264. * scheduling.
  265. */
  266. if (hsotg->wq_otg) {
  267. spin_unlock(&hsotg->lock);
  268. queue_work(hsotg->wq_otg, &hsotg->wf_otg);
  269. spin_lock(&hsotg->lock);
  270. }
  271. }
  272. /**
  273. * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
  274. * initiating the Session Request Protocol to request the host to turn on bus
  275. * power so a new session can begin
  276. *
  277. * @hsotg: Programming view of DWC_otg controller
  278. *
  279. * This handler responds by turning on bus power. If the DWC_otg controller is
  280. * in low power mode, this handler brings the controller out of low power mode
  281. * before turning on bus power.
  282. */
  283. static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
  284. {
  285. int ret;
  286. /* Clear interrupt */
  287. dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
  288. dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
  289. hsotg->lx_state);
  290. if (dwc2_is_device_mode(hsotg)) {
  291. if (hsotg->lx_state == DWC2_L2) {
  292. ret = dwc2_exit_hibernation(hsotg, true);
  293. if (ret && (ret != -ENOTSUPP))
  294. dev_err(hsotg->dev,
  295. "exit hibernation failed\n");
  296. }
  297. /*
  298. * Report disconnect if there is any previous session
  299. * established
  300. */
  301. dwc2_hsotg_disconnect(hsotg);
  302. }
  303. }
  304. /*
  305. * This interrupt indicates that the DWC_otg controller has detected a
  306. * resume or remote wakeup sequence. If the DWC_otg controller is in
  307. * low power mode, the handler must brings the controller out of low
  308. * power mode. The controller automatically begins resume signaling.
  309. * The handler schedules a time to stop resume signaling.
  310. */
  311. static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
  312. {
  313. int ret;
  314. /* Clear interrupt */
  315. dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
  316. dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
  317. dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
  318. if (dwc2_is_device_mode(hsotg)) {
  319. dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
  320. dwc2_readl(hsotg->regs + DSTS));
  321. if (hsotg->lx_state == DWC2_L2) {
  322. u32 dctl = dwc2_readl(hsotg->regs + DCTL);
  323. /* Clear Remote Wakeup Signaling */
  324. dctl &= ~DCTL_RMTWKUPSIG;
  325. dwc2_writel(dctl, hsotg->regs + DCTL);
  326. ret = dwc2_exit_hibernation(hsotg, true);
  327. if (ret && (ret != -ENOTSUPP))
  328. dev_err(hsotg->dev, "exit hibernation failed\n");
  329. call_gadget(hsotg, resume);
  330. }
  331. /* Change to L0 state */
  332. hsotg->lx_state = DWC2_L0;
  333. } else {
  334. if (hsotg->params.hibernation)
  335. return;
  336. if (hsotg->lx_state != DWC2_L1) {
  337. u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
  338. /* Restart the Phy Clock */
  339. pcgcctl &= ~PCGCTL_STOPPCLK;
  340. dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
  341. mod_timer(&hsotg->wkp_timer,
  342. jiffies + msecs_to_jiffies(71));
  343. } else {
  344. /* Change to L0 state */
  345. hsotg->lx_state = DWC2_L0;
  346. }
  347. }
  348. }
  349. /*
  350. * This interrupt indicates that a device has been disconnected from the
  351. * root port
  352. */
  353. static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
  354. {
  355. dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
  356. dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
  357. dwc2_is_host_mode(hsotg) ? "Host" : "Device",
  358. dwc2_op_state_str(hsotg));
  359. if (hsotg->op_state == OTG_STATE_A_HOST)
  360. dwc2_hcd_disconnect(hsotg, false);
  361. }
  362. /*
  363. * This interrupt indicates that SUSPEND state has been detected on the USB.
  364. *
  365. * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
  366. * to "a_host".
  367. *
  368. * When power management is enabled the core will be put in low power mode.
  369. */
  370. static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
  371. {
  372. u32 dsts;
  373. int ret;
  374. /* Clear interrupt */
  375. dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
  376. dev_dbg(hsotg->dev, "USB SUSPEND\n");
  377. if (dwc2_is_device_mode(hsotg)) {
  378. /*
  379. * Check the Device status register to determine if the Suspend
  380. * state is active
  381. */
  382. dsts = dwc2_readl(hsotg->regs + DSTS);
  383. dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
  384. dev_dbg(hsotg->dev,
  385. "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
  386. !!(dsts & DSTS_SUSPSTS),
  387. hsotg->hw_params.power_optimized);
  388. if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
  389. /* Ignore suspend request before enumeration */
  390. if (!dwc2_is_device_connected(hsotg)) {
  391. dev_dbg(hsotg->dev,
  392. "ignore suspend request before enumeration\n");
  393. return;
  394. }
  395. ret = dwc2_enter_hibernation(hsotg);
  396. if (ret) {
  397. if (ret != -ENOTSUPP)
  398. dev_err(hsotg->dev,
  399. "enter hibernation failed\n");
  400. goto skip_power_saving;
  401. }
  402. udelay(100);
  403. /* Ask phy to be suspended */
  404. if (!IS_ERR_OR_NULL(hsotg->uphy))
  405. usb_phy_set_suspend(hsotg->uphy, true);
  406. skip_power_saving:
  407. /*
  408. * Change to L2 (suspend) state before releasing
  409. * spinlock
  410. */
  411. hsotg->lx_state = DWC2_L2;
  412. /* Call gadget suspend callback */
  413. call_gadget(hsotg, suspend);
  414. }
  415. } else {
  416. if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
  417. dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
  418. /* Change to L2 (suspend) state */
  419. hsotg->lx_state = DWC2_L2;
  420. /* Clear the a_peripheral flag, back to a_host */
  421. spin_unlock(&hsotg->lock);
  422. dwc2_hcd_start(hsotg);
  423. spin_lock(&hsotg->lock);
  424. hsotg->op_state = OTG_STATE_A_HOST;
  425. }
  426. }
  427. }
  428. #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
  429. GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
  430. GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
  431. GINTSTS_USBSUSP | GINTSTS_PRTINT)
  432. /*
  433. * This function returns the Core Interrupt register
  434. */
  435. static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
  436. {
  437. u32 gintsts;
  438. u32 gintmsk;
  439. u32 gahbcfg;
  440. u32 gintmsk_common = GINTMSK_COMMON;
  441. gintsts = dwc2_readl(hsotg->regs + GINTSTS);
  442. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  443. gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  444. /* If any common interrupts set */
  445. if (gintsts & gintmsk_common)
  446. dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
  447. gintsts, gintmsk);
  448. if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
  449. return gintsts & gintmsk & gintmsk_common;
  450. else
  451. return 0;
  452. }
  453. /*
  454. * Common interrupt handler
  455. *
  456. * The common interrupts are those that occur in both Host and Device mode.
  457. * This handler handles the following interrupts:
  458. * - Mode Mismatch Interrupt
  459. * - OTG Interrupt
  460. * - Connector ID Status Change Interrupt
  461. * - Disconnect Interrupt
  462. * - Session Request Interrupt
  463. * - Resume / Remote Wakeup Detected Interrupt
  464. * - Suspend Interrupt
  465. */
  466. irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
  467. {
  468. struct dwc2_hsotg *hsotg = dev;
  469. u32 gintsts;
  470. irqreturn_t retval = IRQ_NONE;
  471. spin_lock(&hsotg->lock);
  472. if (!dwc2_is_controller_alive(hsotg)) {
  473. dev_warn(hsotg->dev, "Controller is dead\n");
  474. goto out;
  475. }
  476. gintsts = dwc2_read_common_intr(hsotg);
  477. if (gintsts & ~GINTSTS_PRTINT)
  478. retval = IRQ_HANDLED;
  479. if (gintsts & GINTSTS_MODEMIS)
  480. dwc2_handle_mode_mismatch_intr(hsotg);
  481. if (gintsts & GINTSTS_OTGINT)
  482. dwc2_handle_otg_intr(hsotg);
  483. if (gintsts & GINTSTS_CONIDSTSCHNG)
  484. dwc2_handle_conn_id_status_change_intr(hsotg);
  485. if (gintsts & GINTSTS_DISCONNINT)
  486. dwc2_handle_disconnect_intr(hsotg);
  487. if (gintsts & GINTSTS_SESSREQINT)
  488. dwc2_handle_session_req_intr(hsotg);
  489. if (gintsts & GINTSTS_WKUPINT)
  490. dwc2_handle_wakeup_detected_intr(hsotg);
  491. if (gintsts & GINTSTS_USBSUSP)
  492. dwc2_handle_usb_suspend_intr(hsotg);
  493. if (gintsts & GINTSTS_PRTINT) {
  494. /*
  495. * The port interrupt occurs while in device mode with HPRT0
  496. * Port Enable/Disable
  497. */
  498. if (dwc2_is_device_mode(hsotg)) {
  499. dev_dbg(hsotg->dev,
  500. " --Port interrupt received in Device mode--\n");
  501. dwc2_handle_usb_port_intr(hsotg);
  502. retval = IRQ_HANDLED;
  503. }
  504. }
  505. out:
  506. spin_unlock(&hsotg->lock);
  507. return retval;
  508. }