pcbios.c 10 KB

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  1. /*
  2. * BIOS32 and PCI BIOS handling.
  3. */
  4. #include <linux/pci.h>
  5. #include <linux/init.h>
  6. #include <linux/slab.h>
  7. #include <linux/module.h>
  8. #include <linux/uaccess.h>
  9. #include <asm/pci_x86.h>
  10. #include <asm/pci-functions.h>
  11. #include <asm/cacheflush.h>
  12. /* BIOS32 signature: "_32_" */
  13. #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
  14. /* PCI signature: "PCI " */
  15. #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
  16. /* PCI service signature: "$PCI" */
  17. #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
  18. /* PCI BIOS hardware mechanism flags */
  19. #define PCIBIOS_HW_TYPE1 0x01
  20. #define PCIBIOS_HW_TYPE2 0x02
  21. #define PCIBIOS_HW_TYPE1_SPEC 0x10
  22. #define PCIBIOS_HW_TYPE2_SPEC 0x20
  23. int pcibios_enabled;
  24. /* According to the BIOS specification at:
  25. * http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
  26. * restrict the x zone to some pages and make it ro. But this may be
  27. * broken on some bios, complex to handle with static_protections.
  28. * We could make the 0xe0000-0x100000 range rox, but this can break
  29. * some ISA mapping.
  30. *
  31. * So we let's an rw and x hole when pcibios is used. This shouldn't
  32. * happen for modern system with mmconfig, and if you don't want it
  33. * you could disable pcibios...
  34. */
  35. static inline void set_bios_x(void)
  36. {
  37. pcibios_enabled = 1;
  38. set_memory_x(PAGE_OFFSET + BIOS_BEGIN, (BIOS_END - BIOS_BEGIN) >> PAGE_SHIFT);
  39. if (__supported_pte_mask & _PAGE_NX)
  40. printk(KERN_INFO "PCI : PCI BIOS area is rw and x. Use pci=nobios if you want it NX.\n");
  41. }
  42. /*
  43. * This is the standard structure used to identify the entry point
  44. * to the BIOS32 Service Directory, as documented in
  45. * Standard BIOS 32-bit Service Directory Proposal
  46. * Revision 0.4 May 24, 1993
  47. * Phoenix Technologies Ltd.
  48. * Norwood, MA
  49. * and the PCI BIOS specification.
  50. */
  51. union bios32 {
  52. struct {
  53. unsigned long signature; /* _32_ */
  54. unsigned long entry; /* 32 bit physical address */
  55. unsigned char revision; /* Revision level, 0 */
  56. unsigned char length; /* Length in paragraphs should be 01 */
  57. unsigned char checksum; /* All bytes must add up to zero */
  58. unsigned char reserved[5]; /* Must be zero */
  59. } fields;
  60. char chars[16];
  61. };
  62. /*
  63. * Physical address of the service directory. I don't know if we're
  64. * allowed to have more than one of these or not, so just in case
  65. * we'll make pcibios_present() take a memory start parameter and store
  66. * the array there.
  67. */
  68. static struct {
  69. unsigned long address;
  70. unsigned short segment;
  71. } bios32_indirect __initdata = { 0, __KERNEL_CS };
  72. /*
  73. * Returns the entry point for the given service, NULL on error
  74. */
  75. static unsigned long __init bios32_service(unsigned long service)
  76. {
  77. unsigned char return_code; /* %al */
  78. unsigned long address; /* %ebx */
  79. unsigned long length; /* %ecx */
  80. unsigned long entry; /* %edx */
  81. unsigned long flags;
  82. local_irq_save(flags);
  83. __asm__("lcall *(%%edi); cld"
  84. : "=a" (return_code),
  85. "=b" (address),
  86. "=c" (length),
  87. "=d" (entry)
  88. : "0" (service),
  89. "1" (0),
  90. "D" (&bios32_indirect));
  91. local_irq_restore(flags);
  92. switch (return_code) {
  93. case 0:
  94. return address + entry;
  95. case 0x80: /* Not present */
  96. printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
  97. return 0;
  98. default: /* Shouldn't happen */
  99. printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
  100. service, return_code);
  101. return 0;
  102. }
  103. }
  104. static struct {
  105. unsigned long address;
  106. unsigned short segment;
  107. } pci_indirect = { 0, __KERNEL_CS };
  108. static int pci_bios_present;
  109. static int __init check_pcibios(void)
  110. {
  111. u32 signature, eax, ebx, ecx;
  112. u8 status, major_ver, minor_ver, hw_mech;
  113. unsigned long flags, pcibios_entry;
  114. if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
  115. pci_indirect.address = pcibios_entry + PAGE_OFFSET;
  116. local_irq_save(flags);
  117. __asm__(
  118. "lcall *(%%edi); cld\n\t"
  119. "jc 1f\n\t"
  120. "xor %%ah, %%ah\n"
  121. "1:"
  122. : "=d" (signature),
  123. "=a" (eax),
  124. "=b" (ebx),
  125. "=c" (ecx)
  126. : "1" (PCIBIOS_PCI_BIOS_PRESENT),
  127. "D" (&pci_indirect)
  128. : "memory");
  129. local_irq_restore(flags);
  130. status = (eax >> 8) & 0xff;
  131. hw_mech = eax & 0xff;
  132. major_ver = (ebx >> 8) & 0xff;
  133. minor_ver = ebx & 0xff;
  134. if (pcibios_last_bus < 0)
  135. pcibios_last_bus = ecx & 0xff;
  136. DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
  137. status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
  138. if (status || signature != PCI_SIGNATURE) {
  139. printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
  140. status, signature);
  141. return 0;
  142. }
  143. printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
  144. major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
  145. #ifdef CONFIG_PCI_DIRECT
  146. if (!(hw_mech & PCIBIOS_HW_TYPE1))
  147. pci_probe &= ~PCI_PROBE_CONF1;
  148. if (!(hw_mech & PCIBIOS_HW_TYPE2))
  149. pci_probe &= ~PCI_PROBE_CONF2;
  150. #endif
  151. return 1;
  152. }
  153. return 0;
  154. }
  155. static int pci_bios_read(unsigned int seg, unsigned int bus,
  156. unsigned int devfn, int reg, int len, u32 *value)
  157. {
  158. unsigned long result = 0;
  159. unsigned long flags;
  160. unsigned long bx = (bus << 8) | devfn;
  161. u16 number = 0, mask = 0;
  162. WARN_ON(seg);
  163. if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
  164. return -EINVAL;
  165. raw_spin_lock_irqsave(&pci_config_lock, flags);
  166. switch (len) {
  167. case 1:
  168. number = PCIBIOS_READ_CONFIG_BYTE;
  169. mask = 0xff;
  170. break;
  171. case 2:
  172. number = PCIBIOS_READ_CONFIG_WORD;
  173. mask = 0xffff;
  174. break;
  175. case 4:
  176. number = PCIBIOS_READ_CONFIG_DWORD;
  177. break;
  178. }
  179. __asm__("lcall *(%%esi); cld\n\t"
  180. "jc 1f\n\t"
  181. "xor %%ah, %%ah\n"
  182. "1:"
  183. : "=c" (*value),
  184. "=a" (result)
  185. : "1" (number),
  186. "b" (bx),
  187. "D" ((long)reg),
  188. "S" (&pci_indirect));
  189. /*
  190. * Zero-extend the result beyond 8 or 16 bits, do not trust the
  191. * BIOS having done it:
  192. */
  193. if (mask)
  194. *value &= mask;
  195. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  196. return (int)((result & 0xff00) >> 8);
  197. }
  198. static int pci_bios_write(unsigned int seg, unsigned int bus,
  199. unsigned int devfn, int reg, int len, u32 value)
  200. {
  201. unsigned long result = 0;
  202. unsigned long flags;
  203. unsigned long bx = (bus << 8) | devfn;
  204. u16 number = 0;
  205. WARN_ON(seg);
  206. if ((bus > 255) || (devfn > 255) || (reg > 255))
  207. return -EINVAL;
  208. raw_spin_lock_irqsave(&pci_config_lock, flags);
  209. switch (len) {
  210. case 1:
  211. number = PCIBIOS_WRITE_CONFIG_BYTE;
  212. break;
  213. case 2:
  214. number = PCIBIOS_WRITE_CONFIG_WORD;
  215. break;
  216. case 4:
  217. number = PCIBIOS_WRITE_CONFIG_DWORD;
  218. break;
  219. }
  220. __asm__("lcall *(%%esi); cld\n\t"
  221. "jc 1f\n\t"
  222. "xor %%ah, %%ah\n"
  223. "1:"
  224. : "=a" (result)
  225. : "0" (number),
  226. "c" (value),
  227. "b" (bx),
  228. "D" ((long)reg),
  229. "S" (&pci_indirect));
  230. raw_spin_unlock_irqrestore(&pci_config_lock, flags);
  231. return (int)((result & 0xff00) >> 8);
  232. }
  233. /*
  234. * Function table for BIOS32 access
  235. */
  236. static const struct pci_raw_ops pci_bios_access = {
  237. .read = pci_bios_read,
  238. .write = pci_bios_write
  239. };
  240. /*
  241. * Try to find PCI BIOS.
  242. */
  243. static const struct pci_raw_ops *__init pci_find_bios(void)
  244. {
  245. union bios32 *check;
  246. unsigned char sum;
  247. int i, length;
  248. /*
  249. * Follow the standard procedure for locating the BIOS32 Service
  250. * directory by scanning the permissible address range from
  251. * 0xe0000 through 0xfffff for a valid BIOS32 structure.
  252. */
  253. for (check = (union bios32 *) __va(0xe0000);
  254. check <= (union bios32 *) __va(0xffff0);
  255. ++check) {
  256. long sig;
  257. if (probe_kernel_address(&check->fields.signature, sig))
  258. continue;
  259. if (check->fields.signature != BIOS32_SIGNATURE)
  260. continue;
  261. length = check->fields.length * 16;
  262. if (!length)
  263. continue;
  264. sum = 0;
  265. for (i = 0; i < length ; ++i)
  266. sum += check->chars[i];
  267. if (sum != 0)
  268. continue;
  269. if (check->fields.revision != 0) {
  270. printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
  271. check->fields.revision, check);
  272. continue;
  273. }
  274. DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
  275. if (check->fields.entry >= 0x100000) {
  276. printk("PCI: BIOS32 entry (0x%p) in high memory, "
  277. "cannot use.\n", check);
  278. return NULL;
  279. } else {
  280. unsigned long bios32_entry = check->fields.entry;
  281. DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n",
  282. bios32_entry);
  283. bios32_indirect.address = bios32_entry + PAGE_OFFSET;
  284. set_bios_x();
  285. if (check_pcibios())
  286. return &pci_bios_access;
  287. }
  288. break; /* Hopefully more than one BIOS32 cannot happen... */
  289. }
  290. return NULL;
  291. }
  292. /*
  293. * BIOS Functions for IRQ Routing
  294. */
  295. struct irq_routing_options {
  296. u16 size;
  297. struct irq_info *table;
  298. u16 segment;
  299. } __attribute__((packed));
  300. struct irq_routing_table * pcibios_get_irq_routing_table(void)
  301. {
  302. struct irq_routing_options opt;
  303. struct irq_routing_table *rt = NULL;
  304. int ret, map;
  305. unsigned long page;
  306. if (!pci_bios_present)
  307. return NULL;
  308. page = __get_free_page(GFP_KERNEL);
  309. if (!page)
  310. return NULL;
  311. opt.table = (struct irq_info *) page;
  312. opt.size = PAGE_SIZE;
  313. opt.segment = __KERNEL_DS;
  314. DBG("PCI: Fetching IRQ routing table... ");
  315. __asm__("push %%es\n\t"
  316. "push %%ds\n\t"
  317. "pop %%es\n\t"
  318. "lcall *(%%esi); cld\n\t"
  319. "pop %%es\n\t"
  320. "jc 1f\n\t"
  321. "xor %%ah, %%ah\n"
  322. "1:"
  323. : "=a" (ret),
  324. "=b" (map),
  325. "=m" (opt)
  326. : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
  327. "1" (0),
  328. "D" ((long) &opt),
  329. "S" (&pci_indirect),
  330. "m" (opt)
  331. : "memory");
  332. DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
  333. if (ret & 0xff00)
  334. printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
  335. else if (opt.size) {
  336. rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
  337. if (rt) {
  338. memset(rt, 0, sizeof(struct irq_routing_table));
  339. rt->size = opt.size + sizeof(struct irq_routing_table);
  340. rt->exclusive_irqs = map;
  341. memcpy(rt->slots, (void *) page, opt.size);
  342. printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
  343. }
  344. }
  345. free_page(page);
  346. return rt;
  347. }
  348. EXPORT_SYMBOL(pcibios_get_irq_routing_table);
  349. int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
  350. {
  351. int ret;
  352. __asm__("lcall *(%%esi); cld\n\t"
  353. "jc 1f\n\t"
  354. "xor %%ah, %%ah\n"
  355. "1:"
  356. : "=a" (ret)
  357. : "0" (PCIBIOS_SET_PCI_HW_INT),
  358. "b" ((dev->bus->number << 8) | dev->devfn),
  359. "c" ((irq << 8) | (pin + 10)),
  360. "S" (&pci_indirect));
  361. return !(ret & 0xff00);
  362. }
  363. EXPORT_SYMBOL(pcibios_set_irq_routing);
  364. void __init pci_pcbios_init(void)
  365. {
  366. if ((pci_probe & PCI_PROBE_BIOS)
  367. && ((raw_pci_ops = pci_find_bios()))) {
  368. pci_bios_present = 1;
  369. }
  370. }