setup.c 22 KB

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  1. /*
  2. * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  3. * and RBTX49xx patch from CELF patch archive.
  4. *
  5. * 2003-2005 (c) MontaVista Software, Inc.
  6. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/string.h>
  17. #include <linux/module.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/gpio.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/serial_core.h>
  23. #include <linux/mtd/physmap.h>
  24. #include <linux/leds.h>
  25. #include <linux/device.h>
  26. #include <linux/slab.h>
  27. #include <linux/irq.h>
  28. #include <asm/bootinfo.h>
  29. #include <asm/idle.h>
  30. #include <asm/time.h>
  31. #include <asm/reboot.h>
  32. #include <asm/r4kcache.h>
  33. #include <asm/sections.h>
  34. #include <asm/txx9/generic.h>
  35. #include <asm/txx9/pci.h>
  36. #include <asm/txx9tmr.h>
  37. #include <asm/txx9/ndfmc.h>
  38. #include <asm/txx9/dmac.h>
  39. #ifdef CONFIG_CPU_TX49XX
  40. #include <asm/txx9/tx4938.h>
  41. #endif
  42. /* EBUSC settings of TX4927, etc. */
  43. struct resource txx9_ce_res[8];
  44. static char txx9_ce_res_name[8][4]; /* "CEn" */
  45. /* pcode, internal register */
  46. unsigned int txx9_pcode;
  47. char txx9_pcode_str[8];
  48. static struct resource txx9_reg_res = {
  49. .name = txx9_pcode_str,
  50. .flags = IORESOURCE_MEM,
  51. };
  52. void __init
  53. txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
  54. {
  55. int i;
  56. for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
  57. sprintf(txx9_ce_res_name[i], "CE%d", i);
  58. txx9_ce_res[i].flags = IORESOURCE_MEM;
  59. txx9_ce_res[i].name = txx9_ce_res_name[i];
  60. }
  61. txx9_pcode = pcode;
  62. sprintf(txx9_pcode_str, "TX%x", pcode);
  63. if (base) {
  64. txx9_reg_res.start = base & 0xfffffffffULL;
  65. txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
  66. request_resource(&iomem_resource, &txx9_reg_res);
  67. }
  68. }
  69. /* clocks */
  70. unsigned int txx9_master_clock;
  71. unsigned int txx9_cpu_clock;
  72. unsigned int txx9_gbus_clock;
  73. #ifdef CONFIG_CPU_TX39XX
  74. /* don't enable by default - see errata */
  75. int txx9_ccfg_toeon __initdata;
  76. #else
  77. int txx9_ccfg_toeon __initdata = 1;
  78. #endif
  79. /* Minimum CLK support */
  80. struct clk *clk_get(struct device *dev, const char *id)
  81. {
  82. if (!strcmp(id, "spi-baseclk"))
  83. return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
  84. if (!strcmp(id, "imbus_clk"))
  85. return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
  86. return ERR_PTR(-ENOENT);
  87. }
  88. EXPORT_SYMBOL(clk_get);
  89. int clk_enable(struct clk *clk)
  90. {
  91. return 0;
  92. }
  93. EXPORT_SYMBOL(clk_enable);
  94. void clk_disable(struct clk *clk)
  95. {
  96. }
  97. EXPORT_SYMBOL(clk_disable);
  98. unsigned long clk_get_rate(struct clk *clk)
  99. {
  100. return (unsigned long)clk;
  101. }
  102. EXPORT_SYMBOL(clk_get_rate);
  103. void clk_put(struct clk *clk)
  104. {
  105. }
  106. EXPORT_SYMBOL(clk_put);
  107. #define BOARD_VEC(board) extern struct txx9_board_vec board;
  108. #include <asm/txx9/boards.h>
  109. #undef BOARD_VEC
  110. struct txx9_board_vec *txx9_board_vec __initdata;
  111. static char txx9_system_type[32];
  112. static struct txx9_board_vec *board_vecs[] __initdata = {
  113. #define BOARD_VEC(board) &board,
  114. #include <asm/txx9/boards.h>
  115. #undef BOARD_VEC
  116. };
  117. static struct txx9_board_vec *__init find_board_byname(const char *name)
  118. {
  119. int i;
  120. /* search board_vecs table */
  121. for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
  122. if (strstr(board_vecs[i]->system, name))
  123. return board_vecs[i];
  124. }
  125. return NULL;
  126. }
  127. static void __init prom_init_cmdline(void)
  128. {
  129. int argc;
  130. int *argv32;
  131. int i; /* Always ignore the "-c" at argv[0] */
  132. if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
  133. /*
  134. * argc is not a valid number, or argv32 is not a valid
  135. * pointer
  136. */
  137. argc = 0;
  138. argv32 = NULL;
  139. } else {
  140. argc = (int)fw_arg0;
  141. argv32 = (int *)fw_arg1;
  142. }
  143. arcs_cmdline[0] = '\0';
  144. for (i = 1; i < argc; i++) {
  145. char *str = (char *)(long)argv32[i];
  146. if (i != 1)
  147. strcat(arcs_cmdline, " ");
  148. if (strchr(str, ' ')) {
  149. strcat(arcs_cmdline, "\"");
  150. strcat(arcs_cmdline, str);
  151. strcat(arcs_cmdline, "\"");
  152. } else
  153. strcat(arcs_cmdline, str);
  154. }
  155. }
  156. static int txx9_ic_disable __initdata;
  157. static int txx9_dc_disable __initdata;
  158. #if defined(CONFIG_CPU_TX49XX)
  159. /* flush all cache on very early stage (before 4k_cache_init) */
  160. static void __init early_flush_dcache(void)
  161. {
  162. unsigned int conf = read_c0_config();
  163. unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
  164. unsigned int linesz = 32;
  165. unsigned long addr, end;
  166. end = INDEX_BASE + dc_size / 4;
  167. /* 4way, waybit=0 */
  168. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  169. cache_op(Index_Writeback_Inv_D, addr | 0);
  170. cache_op(Index_Writeback_Inv_D, addr | 1);
  171. cache_op(Index_Writeback_Inv_D, addr | 2);
  172. cache_op(Index_Writeback_Inv_D, addr | 3);
  173. }
  174. }
  175. static void __init txx9_cache_fixup(void)
  176. {
  177. unsigned int conf;
  178. conf = read_c0_config();
  179. /* flush and disable */
  180. if (txx9_ic_disable) {
  181. conf |= TX49_CONF_IC;
  182. write_c0_config(conf);
  183. }
  184. if (txx9_dc_disable) {
  185. early_flush_dcache();
  186. conf |= TX49_CONF_DC;
  187. write_c0_config(conf);
  188. }
  189. /* enable cache */
  190. conf = read_c0_config();
  191. if (!txx9_ic_disable)
  192. conf &= ~TX49_CONF_IC;
  193. if (!txx9_dc_disable)
  194. conf &= ~TX49_CONF_DC;
  195. write_c0_config(conf);
  196. if (conf & TX49_CONF_IC)
  197. pr_info("TX49XX I-Cache disabled.\n");
  198. if (conf & TX49_CONF_DC)
  199. pr_info("TX49XX D-Cache disabled.\n");
  200. }
  201. #elif defined(CONFIG_CPU_TX39XX)
  202. /* flush all cache on very early stage (before tx39_cache_init) */
  203. static void __init early_flush_dcache(void)
  204. {
  205. unsigned int conf = read_c0_config();
  206. unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
  207. TX39_CONF_DCS_SHIFT));
  208. unsigned int linesz = 16;
  209. unsigned long addr, end;
  210. end = INDEX_BASE + dc_size / 2;
  211. /* 2way, waybit=0 */
  212. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  213. cache_op(Index_Writeback_Inv_D, addr | 0);
  214. cache_op(Index_Writeback_Inv_D, addr | 1);
  215. }
  216. }
  217. static void __init txx9_cache_fixup(void)
  218. {
  219. unsigned int conf;
  220. conf = read_c0_config();
  221. /* flush and disable */
  222. if (txx9_ic_disable) {
  223. conf &= ~TX39_CONF_ICE;
  224. write_c0_config(conf);
  225. }
  226. if (txx9_dc_disable) {
  227. early_flush_dcache();
  228. conf &= ~TX39_CONF_DCE;
  229. write_c0_config(conf);
  230. }
  231. /* enable cache */
  232. conf = read_c0_config();
  233. if (!txx9_ic_disable)
  234. conf |= TX39_CONF_ICE;
  235. if (!txx9_dc_disable)
  236. conf |= TX39_CONF_DCE;
  237. write_c0_config(conf);
  238. if (!(conf & TX39_CONF_ICE))
  239. pr_info("TX39XX I-Cache disabled.\n");
  240. if (!(conf & TX39_CONF_DCE))
  241. pr_info("TX39XX D-Cache disabled.\n");
  242. }
  243. #else
  244. static inline void txx9_cache_fixup(void)
  245. {
  246. }
  247. #endif
  248. static void __init preprocess_cmdline(void)
  249. {
  250. static char cmdline[COMMAND_LINE_SIZE] __initdata;
  251. char *s;
  252. strcpy(cmdline, arcs_cmdline);
  253. s = cmdline;
  254. arcs_cmdline[0] = '\0';
  255. while (s && *s) {
  256. char *str = strsep(&s, " ");
  257. if (strncmp(str, "board=", 6) == 0) {
  258. txx9_board_vec = find_board_byname(str + 6);
  259. continue;
  260. } else if (strncmp(str, "masterclk=", 10) == 0) {
  261. unsigned int val;
  262. if (kstrtouint(str + 10, 10, &val) == 0)
  263. txx9_master_clock = val;
  264. continue;
  265. } else if (strcmp(str, "icdisable") == 0) {
  266. txx9_ic_disable = 1;
  267. continue;
  268. } else if (strcmp(str, "dcdisable") == 0) {
  269. txx9_dc_disable = 1;
  270. continue;
  271. } else if (strcmp(str, "toeoff") == 0) {
  272. txx9_ccfg_toeon = 0;
  273. continue;
  274. } else if (strcmp(str, "toeon") == 0) {
  275. txx9_ccfg_toeon = 1;
  276. continue;
  277. }
  278. if (arcs_cmdline[0])
  279. strcat(arcs_cmdline, " ");
  280. strcat(arcs_cmdline, str);
  281. }
  282. txx9_cache_fixup();
  283. }
  284. static void __init select_board(void)
  285. {
  286. const char *envstr;
  287. /* first, determine by "board=" argument in preprocess_cmdline() */
  288. if (txx9_board_vec)
  289. return;
  290. /* next, determine by "board" envvar */
  291. envstr = prom_getenv("board");
  292. if (envstr) {
  293. txx9_board_vec = find_board_byname(envstr);
  294. if (txx9_board_vec)
  295. return;
  296. }
  297. /* select "default" board */
  298. #ifdef CONFIG_TOSHIBA_JMR3927
  299. txx9_board_vec = &jmr3927_vec;
  300. #endif
  301. #ifdef CONFIG_CPU_TX49XX
  302. switch (TX4938_REV_PCODE()) {
  303. #ifdef CONFIG_TOSHIBA_RBTX4927
  304. case 0x4927:
  305. txx9_board_vec = &rbtx4927_vec;
  306. break;
  307. case 0x4937:
  308. txx9_board_vec = &rbtx4937_vec;
  309. break;
  310. #endif
  311. #ifdef CONFIG_TOSHIBA_RBTX4938
  312. case 0x4938:
  313. txx9_board_vec = &rbtx4938_vec;
  314. break;
  315. #endif
  316. #ifdef CONFIG_TOSHIBA_RBTX4939
  317. case 0x4939:
  318. txx9_board_vec = &rbtx4939_vec;
  319. break;
  320. #endif
  321. }
  322. #endif
  323. }
  324. void __init prom_init(void)
  325. {
  326. prom_init_cmdline();
  327. preprocess_cmdline();
  328. select_board();
  329. strcpy(txx9_system_type, txx9_board_vec->system);
  330. txx9_board_vec->prom_init();
  331. }
  332. void __init prom_free_prom_memory(void)
  333. {
  334. unsigned long saddr = PAGE_SIZE;
  335. unsigned long eaddr = __pa_symbol(&_text);
  336. if (saddr < eaddr)
  337. free_init_pages("prom memory", saddr, eaddr);
  338. }
  339. const char *get_system_type(void)
  340. {
  341. return txx9_system_type;
  342. }
  343. const char *__init prom_getenv(const char *name)
  344. {
  345. const s32 *str;
  346. if (fw_arg2 < CKSEG0)
  347. return NULL;
  348. str = (const s32 *)fw_arg2;
  349. /* YAMON style ("name", "value" pairs) */
  350. while (str[0] && str[1]) {
  351. if (!strcmp((const char *)(unsigned long)str[0], name))
  352. return (const char *)(unsigned long)str[1];
  353. str += 2;
  354. }
  355. return NULL;
  356. }
  357. static void __noreturn txx9_machine_halt(void)
  358. {
  359. local_irq_disable();
  360. clear_c0_status(ST0_IM);
  361. while (1) {
  362. if (cpu_wait) {
  363. (*cpu_wait)();
  364. if (cpu_has_counter) {
  365. /*
  366. * Clear counter interrupt while it
  367. * breaks WAIT instruction even if
  368. * masked.
  369. */
  370. write_c0_compare(0);
  371. }
  372. }
  373. }
  374. }
  375. /* Watchdog support */
  376. void __init txx9_wdt_init(unsigned long base)
  377. {
  378. struct resource res = {
  379. .start = base,
  380. .end = base + 0x100 - 1,
  381. .flags = IORESOURCE_MEM,
  382. };
  383. platform_device_register_simple("txx9wdt", -1, &res, 1);
  384. }
  385. void txx9_wdt_now(unsigned long base)
  386. {
  387. struct txx9_tmr_reg __iomem *tmrptr =
  388. ioremap(base, sizeof(struct txx9_tmr_reg));
  389. /* disable watch dog timer */
  390. __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
  391. __raw_writel(0, &tmrptr->tcr);
  392. /* kick watchdog */
  393. __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
  394. __raw_writel(1, &tmrptr->cpra); /* immediate */
  395. __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
  396. &tmrptr->tcr);
  397. }
  398. /* SPI support */
  399. void __init txx9_spi_init(int busid, unsigned long base, int irq)
  400. {
  401. struct resource res[] = {
  402. {
  403. .start = base,
  404. .end = base + 0x20 - 1,
  405. .flags = IORESOURCE_MEM,
  406. }, {
  407. .start = irq,
  408. .flags = IORESOURCE_IRQ,
  409. },
  410. };
  411. platform_device_register_simple("spi_txx9", busid,
  412. res, ARRAY_SIZE(res));
  413. }
  414. void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
  415. {
  416. struct platform_device *pdev =
  417. platform_device_alloc("tc35815-mac", id);
  418. if (!pdev ||
  419. platform_device_add_data(pdev, ethaddr, 6) ||
  420. platform_device_add(pdev))
  421. platform_device_put(pdev);
  422. }
  423. void __init txx9_sio_init(unsigned long baseaddr, int irq,
  424. unsigned int line, unsigned int sclk, int nocts)
  425. {
  426. #ifdef CONFIG_SERIAL_TXX9
  427. struct uart_port req;
  428. memset(&req, 0, sizeof(req));
  429. req.line = line;
  430. req.iotype = UPIO_MEM;
  431. req.membase = ioremap(baseaddr, 0x24);
  432. req.mapbase = baseaddr;
  433. req.irq = irq;
  434. if (!nocts)
  435. req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
  436. if (sclk) {
  437. req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
  438. req.uartclk = sclk;
  439. } else
  440. req.uartclk = TXX9_IMCLK;
  441. early_serial_txx9_setup(&req);
  442. #endif /* CONFIG_SERIAL_TXX9 */
  443. }
  444. #ifdef CONFIG_EARLY_PRINTK
  445. static void null_prom_putchar(char c)
  446. {
  447. }
  448. void (*txx9_prom_putchar)(char c) = null_prom_putchar;
  449. void prom_putchar(char c)
  450. {
  451. txx9_prom_putchar(c);
  452. }
  453. static void __iomem *early_txx9_sio_port;
  454. static void early_txx9_sio_putchar(char c)
  455. {
  456. #define TXX9_SICISR 0x0c
  457. #define TXX9_SITFIFO 0x1c
  458. #define TXX9_SICISR_TXALS 0x00000002
  459. while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
  460. TXX9_SICISR_TXALS))
  461. ;
  462. __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
  463. }
  464. void __init txx9_sio_putchar_init(unsigned long baseaddr)
  465. {
  466. early_txx9_sio_port = ioremap(baseaddr, 0x24);
  467. txx9_prom_putchar = early_txx9_sio_putchar;
  468. }
  469. #endif /* CONFIG_EARLY_PRINTK */
  470. /* wrappers */
  471. void __init plat_mem_setup(void)
  472. {
  473. ioport_resource.start = 0;
  474. ioport_resource.end = ~0UL; /* no limit */
  475. iomem_resource.start = 0;
  476. iomem_resource.end = ~0UL; /* no limit */
  477. /* fallback restart/halt routines */
  478. _machine_restart = (void (*)(char *))txx9_machine_halt;
  479. _machine_halt = txx9_machine_halt;
  480. pm_power_off = txx9_machine_halt;
  481. #ifdef CONFIG_PCI
  482. pcibios_plat_setup = txx9_pcibios_setup;
  483. #endif
  484. txx9_board_vec->mem_setup();
  485. }
  486. void __init arch_init_irq(void)
  487. {
  488. txx9_board_vec->irq_setup();
  489. }
  490. void __init plat_time_init(void)
  491. {
  492. #ifdef CONFIG_CPU_TX49XX
  493. mips_hpt_frequency = txx9_cpu_clock / 2;
  494. #endif
  495. txx9_board_vec->time_init();
  496. }
  497. static int __init _txx9_arch_init(void)
  498. {
  499. if (txx9_board_vec->arch_init)
  500. txx9_board_vec->arch_init();
  501. return 0;
  502. }
  503. arch_initcall(_txx9_arch_init);
  504. static int __init _txx9_device_init(void)
  505. {
  506. if (txx9_board_vec->device_init)
  507. txx9_board_vec->device_init();
  508. return 0;
  509. }
  510. device_initcall(_txx9_device_init);
  511. int (*txx9_irq_dispatch)(int pending);
  512. asmlinkage void plat_irq_dispatch(void)
  513. {
  514. int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  515. int irq = txx9_irq_dispatch(pending);
  516. if (likely(irq >= 0))
  517. do_IRQ(irq);
  518. else
  519. spurious_interrupt();
  520. }
  521. /* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
  522. #ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
  523. static unsigned long __swizzle_addr_none(unsigned long port)
  524. {
  525. return port;
  526. }
  527. unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
  528. EXPORT_SYMBOL(__swizzle_addr_b);
  529. #endif
  530. #ifdef NEEDS_TXX9_IOSWABW
  531. static u16 ioswabw_default(volatile u16 *a, u16 x)
  532. {
  533. return le16_to_cpu(x);
  534. }
  535. static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
  536. {
  537. return x;
  538. }
  539. u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
  540. EXPORT_SYMBOL(ioswabw);
  541. u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
  542. EXPORT_SYMBOL(__mem_ioswabw);
  543. #endif
  544. void __init txx9_physmap_flash_init(int no, unsigned long addr,
  545. unsigned long size,
  546. const struct physmap_flash_data *pdata)
  547. {
  548. #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
  549. struct resource res = {
  550. .start = addr,
  551. .end = addr + size - 1,
  552. .flags = IORESOURCE_MEM,
  553. };
  554. struct platform_device *pdev;
  555. static struct mtd_partition parts[2];
  556. struct physmap_flash_data pdata_part;
  557. /* If this area contained boot area, make separate partition */
  558. if (pdata->nr_parts == 0 && !pdata->parts &&
  559. addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
  560. !parts[0].name) {
  561. parts[0].name = "boot";
  562. parts[0].offset = 0x1fc00000 - addr;
  563. parts[0].size = addr + size - 0x1fc00000;
  564. parts[1].name = "user";
  565. parts[1].offset = 0;
  566. parts[1].size = 0x1fc00000 - addr;
  567. pdata_part = *pdata;
  568. pdata_part.nr_parts = ARRAY_SIZE(parts);
  569. pdata_part.parts = parts;
  570. pdata = &pdata_part;
  571. }
  572. pdev = platform_device_alloc("physmap-flash", no);
  573. if (!pdev ||
  574. platform_device_add_resources(pdev, &res, 1) ||
  575. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  576. platform_device_add(pdev))
  577. platform_device_put(pdev);
  578. #endif
  579. }
  580. void __init txx9_ndfmc_init(unsigned long baseaddr,
  581. const struct txx9ndfmc_platform_data *pdata)
  582. {
  583. #if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
  584. struct resource res = {
  585. .start = baseaddr,
  586. .end = baseaddr + 0x1000 - 1,
  587. .flags = IORESOURCE_MEM,
  588. };
  589. struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
  590. if (!pdev ||
  591. platform_device_add_resources(pdev, &res, 1) ||
  592. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  593. platform_device_add(pdev))
  594. platform_device_put(pdev);
  595. #endif
  596. }
  597. #if IS_ENABLED(CONFIG_LEDS_GPIO)
  598. static DEFINE_SPINLOCK(txx9_iocled_lock);
  599. #define TXX9_IOCLED_MAXLEDS 8
  600. struct txx9_iocled_data {
  601. struct gpio_chip chip;
  602. u8 cur_val;
  603. void __iomem *mmioaddr;
  604. struct gpio_led_platform_data pdata;
  605. struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
  606. char names[TXX9_IOCLED_MAXLEDS][32];
  607. };
  608. static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
  609. {
  610. struct txx9_iocled_data *data =
  611. container_of(chip, struct txx9_iocled_data, chip);
  612. return !!(data->cur_val & (1 << offset));
  613. }
  614. static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
  615. int value)
  616. {
  617. struct txx9_iocled_data *data =
  618. container_of(chip, struct txx9_iocled_data, chip);
  619. unsigned long flags;
  620. spin_lock_irqsave(&txx9_iocled_lock, flags);
  621. if (value)
  622. data->cur_val |= 1 << offset;
  623. else
  624. data->cur_val &= ~(1 << offset);
  625. writeb(data->cur_val, data->mmioaddr);
  626. mmiowb();
  627. spin_unlock_irqrestore(&txx9_iocled_lock, flags);
  628. }
  629. static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
  630. {
  631. return 0;
  632. }
  633. static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
  634. int value)
  635. {
  636. txx9_iocled_set(chip, offset, value);
  637. return 0;
  638. }
  639. void __init txx9_iocled_init(unsigned long baseaddr,
  640. int basenum, unsigned int num, int lowactive,
  641. const char *color, char **deftriggers)
  642. {
  643. struct txx9_iocled_data *iocled;
  644. struct platform_device *pdev;
  645. int i;
  646. static char *default_triggers[] __initdata = {
  647. "heartbeat",
  648. "ide-disk",
  649. "nand-disk",
  650. NULL,
  651. };
  652. if (!deftriggers)
  653. deftriggers = default_triggers;
  654. iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
  655. if (!iocled)
  656. return;
  657. iocled->mmioaddr = ioremap(baseaddr, 1);
  658. if (!iocled->mmioaddr)
  659. goto out_free;
  660. iocled->chip.get = txx9_iocled_get;
  661. iocled->chip.set = txx9_iocled_set;
  662. iocled->chip.direction_input = txx9_iocled_dir_in;
  663. iocled->chip.direction_output = txx9_iocled_dir_out;
  664. iocled->chip.label = "iocled";
  665. iocled->chip.base = basenum;
  666. iocled->chip.ngpio = num;
  667. if (gpiochip_add(&iocled->chip))
  668. goto out_unmap;
  669. if (basenum < 0)
  670. basenum = iocled->chip.base;
  671. pdev = platform_device_alloc("leds-gpio", basenum);
  672. if (!pdev)
  673. goto out_gpio;
  674. iocled->pdata.num_leds = num;
  675. iocled->pdata.leds = iocled->leds;
  676. for (i = 0; i < num; i++) {
  677. struct gpio_led *led = &iocled->leds[i];
  678. snprintf(iocled->names[i], sizeof(iocled->names[i]),
  679. "iocled:%s:%u", color, i);
  680. led->name = iocled->names[i];
  681. led->gpio = basenum + i;
  682. led->active_low = lowactive;
  683. if (deftriggers && *deftriggers)
  684. led->default_trigger = *deftriggers++;
  685. }
  686. pdev->dev.platform_data = &iocled->pdata;
  687. if (platform_device_add(pdev))
  688. goto out_pdev;
  689. return;
  690. out_pdev:
  691. platform_device_put(pdev);
  692. out_gpio:
  693. gpiochip_remove(&iocled->chip);
  694. out_unmap:
  695. iounmap(iocled->mmioaddr);
  696. out_free:
  697. kfree(iocled);
  698. }
  699. #else /* CONFIG_LEDS_GPIO */
  700. void __init txx9_iocled_init(unsigned long baseaddr,
  701. int basenum, unsigned int num, int lowactive,
  702. const char *color, char **deftriggers)
  703. {
  704. }
  705. #endif /* CONFIG_LEDS_GPIO */
  706. void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
  707. const struct txx9dmac_platform_data *pdata)
  708. {
  709. #if IS_ENABLED(CONFIG_TXX9_DMAC)
  710. struct resource res[] = {
  711. {
  712. .start = baseaddr,
  713. .end = baseaddr + 0x800 - 1,
  714. .flags = IORESOURCE_MEM,
  715. #ifndef CONFIG_MACH_TX49XX
  716. }, {
  717. .start = irq,
  718. .flags = IORESOURCE_IRQ,
  719. #endif
  720. }
  721. };
  722. #ifdef CONFIG_MACH_TX49XX
  723. struct resource chan_res[] = {
  724. {
  725. .flags = IORESOURCE_IRQ,
  726. }
  727. };
  728. #endif
  729. struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
  730. struct txx9dmac_chan_platform_data cpdata;
  731. int i;
  732. if (!pdev ||
  733. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  734. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  735. platform_device_add(pdev)) {
  736. platform_device_put(pdev);
  737. return;
  738. }
  739. memset(&cpdata, 0, sizeof(cpdata));
  740. cpdata.dmac_dev = pdev;
  741. for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
  742. #ifdef CONFIG_MACH_TX49XX
  743. chan_res[0].start = irq + i;
  744. #endif
  745. pdev = platform_device_alloc("txx9dmac-chan",
  746. id * TXX9_DMA_MAX_NR_CHANNELS + i);
  747. if (!pdev ||
  748. #ifdef CONFIG_MACH_TX49XX
  749. platform_device_add_resources(pdev, chan_res,
  750. ARRAY_SIZE(chan_res)) ||
  751. #endif
  752. platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
  753. platform_device_add(pdev))
  754. platform_device_put(pdev);
  755. }
  756. #endif
  757. }
  758. void __init txx9_aclc_init(unsigned long baseaddr, int irq,
  759. unsigned int dmac_id,
  760. unsigned int dma_chan_out,
  761. unsigned int dma_chan_in)
  762. {
  763. #if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
  764. unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
  765. struct resource res[] = {
  766. {
  767. .start = baseaddr,
  768. .end = baseaddr + 0x100 - 1,
  769. .flags = IORESOURCE_MEM,
  770. }, {
  771. .start = irq,
  772. .flags = IORESOURCE_IRQ,
  773. }, {
  774. .name = "txx9dmac-chan",
  775. .start = dma_base + dma_chan_out,
  776. .flags = IORESOURCE_DMA,
  777. }, {
  778. .name = "txx9dmac-chan",
  779. .start = dma_base + dma_chan_in,
  780. .flags = IORESOURCE_DMA,
  781. }
  782. };
  783. struct platform_device *pdev =
  784. platform_device_alloc("txx9aclc-ac97", -1);
  785. if (!pdev ||
  786. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  787. platform_device_add(pdev))
  788. platform_device_put(pdev);
  789. #endif
  790. }
  791. static struct bus_type txx9_sramc_subsys = {
  792. .name = "txx9_sram",
  793. .dev_name = "txx9_sram",
  794. };
  795. struct txx9_sramc_dev {
  796. struct device dev;
  797. struct bin_attribute bindata_attr;
  798. void __iomem *base;
  799. };
  800. static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj,
  801. struct bin_attribute *bin_attr,
  802. char *buf, loff_t pos, size_t size)
  803. {
  804. struct txx9_sramc_dev *dev = bin_attr->private;
  805. size_t ramsize = bin_attr->size;
  806. if (pos >= ramsize)
  807. return 0;
  808. if (pos + size > ramsize)
  809. size = ramsize - pos;
  810. memcpy_fromio(buf, dev->base + pos, size);
  811. return size;
  812. }
  813. static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj,
  814. struct bin_attribute *bin_attr,
  815. char *buf, loff_t pos, size_t size)
  816. {
  817. struct txx9_sramc_dev *dev = bin_attr->private;
  818. size_t ramsize = bin_attr->size;
  819. if (pos >= ramsize)
  820. return 0;
  821. if (pos + size > ramsize)
  822. size = ramsize - pos;
  823. memcpy_toio(dev->base + pos, buf, size);
  824. return size;
  825. }
  826. static void txx9_device_release(struct device *dev)
  827. {
  828. struct txx9_sramc_dev *tdev;
  829. tdev = container_of(dev, struct txx9_sramc_dev, dev);
  830. kfree(tdev);
  831. }
  832. void __init txx9_sramc_init(struct resource *r)
  833. {
  834. struct txx9_sramc_dev *dev;
  835. size_t size;
  836. int err;
  837. err = subsys_system_register(&txx9_sramc_subsys, NULL);
  838. if (err)
  839. return;
  840. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  841. if (!dev)
  842. return;
  843. size = resource_size(r);
  844. dev->base = ioremap(r->start, size);
  845. if (!dev->base) {
  846. kfree(dev);
  847. return;
  848. }
  849. dev->dev.release = &txx9_device_release;
  850. dev->dev.bus = &txx9_sramc_subsys;
  851. sysfs_bin_attr_init(&dev->bindata_attr);
  852. dev->bindata_attr.attr.name = "bindata";
  853. dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
  854. dev->bindata_attr.read = txx9_sram_read;
  855. dev->bindata_attr.write = txx9_sram_write;
  856. dev->bindata_attr.size = size;
  857. dev->bindata_attr.private = dev;
  858. err = device_register(&dev->dev);
  859. if (err)
  860. goto exit_put;
  861. err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
  862. if (err) {
  863. device_unregister(&dev->dev);
  864. iounmap(dev->base);
  865. kfree(dev);
  866. }
  867. return;
  868. exit_put:
  869. put_device(&dev->dev);
  870. return;
  871. }