intel_display.c 457 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749475047514752475347544755475647574758475947604761476247634764476547664767476847694770477147724773477447754776477747784779478047814782478347844785478647874788478947904791479247934794479547964797479847994800480148024803480448054806480748084809481048114812481348144815481648174818481948204821482248234824482548264827482848294830483148324833483448354836483748384839484048414842484348444845484648474848484948504851485248534854485548564857485848594860486148624863486448654866486748684869487048714872487348744875487648774878487948804881488248834884488548864887488848894890489148924893489448954896489748984899490049014902490349044905490649074908490949104911491249134914491549164917491849194920492149224923492449254926492749284929493049314932493349344935493649374938493949404941494249434944494549464947494849494950495149524953495449554956495749584959496049614962496349644965496649674968496949704971497249734974497549764977497849794980498149824983498449854986498749884989499049914992499349944995499649974998499950005001500250035004500550065007500850095010501150125013501450155016501750185019502050215022502350245025502650275028502950305031503250335034503550365037503850395040504150425043504450455046504750485049505050515052505350545055505650575058505950605061506250635064506550665067506850695070507150725073507450755076507750785079508050815082508350845085508650875088508950905091509250935094509550965097509850995100510151025103510451055106510751085109511051115112511351145115511651175118511951205121512251235124512551265127512851295130513151325133513451355136513751385139514051415142514351445145514651475148514951505151515251535154515551565157515851595160516151625163516451655166516751685169517051715172517351745175517651775178517951805181518251835184518551865187518851895190519151925193519451955196519751985199520052015202520352045205520652075208520952105211521252135214521552165217521852195220522152225223522452255226522752285229523052315232523352345235523652375238523952405241524252435244524552465247524852495250525152525253525452555256525752585259526052615262526352645265526652675268526952705271527252735274527552765277527852795280528152825283528452855286528752885289529052915292529352945295529652975298529953005301530253035304530553065307530853095310531153125313531453155316531753185319532053215322532353245325532653275328532953305331533253335334533553365337533853395340534153425343534453455346534753485349535053515352535353545355535653575358535953605361536253635364536553665367536853695370537153725373537453755376537753785379538053815382538353845385538653875388538953905391539253935394539553965397539853995400540154025403540454055406540754085409541054115412541354145415541654175418541954205421542254235424542554265427542854295430543154325433543454355436543754385439544054415442544354445445544654475448544954505451545254535454545554565457545854595460546154625463546454655466546754685469547054715472547354745475547654775478547954805481548254835484548554865487548854895490549154925493549454955496549754985499550055015502550355045505550655075508550955105511551255135514551555165517551855195520552155225523552455255526552755285529553055315532553355345535553655375538553955405541554255435544554555465547554855495550555155525553555455555556555755585559556055615562556355645565556655675568556955705571557255735574557555765577557855795580558155825583558455855586558755885589559055915592559355945595559655975598559956005601560256035604560556065607560856095610561156125613561456155616561756185619562056215622562356245625562656275628562956305631563256335634563556365637563856395640564156425643564456455646564756485649565056515652565356545655565656575658565956605661566256635664566556665667566856695670567156725673567456755676567756785679568056815682568356845685568656875688568956905691569256935694569556965697569856995700570157025703570457055706570757085709571057115712571357145715571657175718571957205721572257235724572557265727572857295730573157325733573457355736573757385739574057415742574357445745574657475748574957505751575257535754575557565757575857595760576157625763576457655766576757685769577057715772577357745775577657775778577957805781578257835784578557865787578857895790579157925793579457955796579757985799580058015802580358045805580658075808580958105811581258135814581558165817581858195820582158225823582458255826582758285829583058315832583358345835583658375838583958405841584258435844584558465847584858495850585158525853585458555856585758585859586058615862586358645865586658675868586958705871587258735874587558765877587858795880588158825883588458855886588758885889589058915892589358945895589658975898589959005901590259035904590559065907590859095910591159125913591459155916591759185919592059215922592359245925592659275928592959305931593259335934593559365937593859395940594159425943594459455946594759485949595059515952595359545955595659575958595959605961596259635964596559665967596859695970597159725973597459755976597759785979598059815982598359845985598659875988598959905991599259935994599559965997599859996000600160026003600460056006600760086009601060116012601360146015601660176018601960206021602260236024602560266027602860296030603160326033603460356036603760386039604060416042604360446045604660476048604960506051605260536054605560566057605860596060606160626063606460656066606760686069607060716072607360746075607660776078607960806081608260836084608560866087608860896090609160926093609460956096609760986099610061016102610361046105610661076108610961106111611261136114611561166117611861196120612161226123612461256126612761286129613061316132613361346135613661376138613961406141614261436144614561466147614861496150615161526153615461556156615761586159616061616162616361646165616661676168616961706171617261736174617561766177617861796180618161826183618461856186618761886189619061916192619361946195619661976198619962006201620262036204620562066207620862096210621162126213621462156216621762186219622062216222622362246225622662276228622962306231623262336234623562366237623862396240624162426243624462456246624762486249625062516252625362546255625662576258625962606261626262636264626562666267626862696270627162726273627462756276627762786279628062816282628362846285628662876288628962906291629262936294629562966297629862996300630163026303630463056306630763086309631063116312631363146315631663176318631963206321632263236324632563266327632863296330633163326333633463356336633763386339634063416342634363446345634663476348634963506351635263536354635563566357635863596360636163626363636463656366636763686369637063716372637363746375637663776378637963806381638263836384638563866387638863896390639163926393639463956396639763986399640064016402640364046405640664076408640964106411641264136414641564166417641864196420642164226423642464256426642764286429643064316432643364346435643664376438643964406441644264436444644564466447644864496450645164526453645464556456645764586459646064616462646364646465646664676468646964706471647264736474647564766477647864796480648164826483648464856486648764886489649064916492649364946495649664976498649965006501650265036504650565066507650865096510651165126513651465156516651765186519652065216522652365246525652665276528652965306531653265336534653565366537653865396540654165426543654465456546654765486549655065516552655365546555655665576558655965606561656265636564656565666567656865696570657165726573657465756576657765786579658065816582658365846585658665876588658965906591659265936594659565966597659865996600660166026603660466056606660766086609661066116612661366146615661666176618661966206621662266236624662566266627662866296630663166326633663466356636663766386639664066416642664366446645664666476648664966506651665266536654665566566657665866596660666166626663666466656666666766686669667066716672667366746675667666776678667966806681668266836684668566866687668866896690669166926693669466956696669766986699670067016702670367046705670667076708670967106711671267136714671567166717671867196720672167226723672467256726672767286729673067316732673367346735673667376738673967406741674267436744674567466747674867496750675167526753675467556756675767586759676067616762676367646765676667676768676967706771677267736774677567766777677867796780678167826783678467856786678767886789679067916792679367946795679667976798679968006801680268036804680568066807680868096810681168126813681468156816681768186819682068216822682368246825682668276828682968306831683268336834683568366837683868396840684168426843684468456846684768486849685068516852685368546855685668576858685968606861686268636864686568666867686868696870687168726873687468756876687768786879688068816882688368846885688668876888688968906891689268936894689568966897689868996900690169026903690469056906690769086909691069116912691369146915691669176918691969206921692269236924692569266927692869296930693169326933693469356936693769386939694069416942694369446945694669476948694969506951695269536954695569566957695869596960696169626963696469656966696769686969697069716972697369746975697669776978697969806981698269836984698569866987698869896990699169926993699469956996699769986999700070017002700370047005700670077008700970107011701270137014701570167017701870197020702170227023702470257026702770287029703070317032703370347035703670377038703970407041704270437044704570467047704870497050705170527053705470557056705770587059706070617062706370647065706670677068706970707071707270737074707570767077707870797080708170827083708470857086708770887089709070917092709370947095709670977098709971007101710271037104710571067107710871097110711171127113711471157116711771187119712071217122712371247125712671277128712971307131713271337134713571367137713871397140714171427143714471457146714771487149715071517152715371547155715671577158715971607161716271637164716571667167716871697170717171727173717471757176717771787179718071817182718371847185718671877188718971907191719271937194719571967197719871997200720172027203720472057206720772087209721072117212721372147215721672177218721972207221722272237224722572267227722872297230723172327233723472357236723772387239724072417242724372447245724672477248724972507251725272537254725572567257725872597260726172627263726472657266726772687269727072717272727372747275727672777278727972807281728272837284728572867287728872897290729172927293729472957296729772987299730073017302730373047305730673077308730973107311731273137314731573167317731873197320732173227323732473257326732773287329733073317332733373347335733673377338733973407341734273437344734573467347734873497350735173527353735473557356735773587359736073617362736373647365736673677368736973707371737273737374737573767377737873797380738173827383738473857386738773887389739073917392739373947395739673977398739974007401740274037404740574067407740874097410741174127413741474157416741774187419742074217422742374247425742674277428742974307431743274337434743574367437743874397440744174427443744474457446744774487449745074517452745374547455745674577458745974607461746274637464746574667467746874697470747174727473747474757476747774787479748074817482748374847485748674877488748974907491749274937494749574967497749874997500750175027503750475057506750775087509751075117512751375147515751675177518751975207521752275237524752575267527752875297530753175327533753475357536753775387539754075417542754375447545754675477548754975507551755275537554755575567557755875597560756175627563756475657566756775687569757075717572757375747575757675777578757975807581758275837584758575867587758875897590759175927593759475957596759775987599760076017602760376047605760676077608760976107611761276137614761576167617761876197620762176227623762476257626762776287629763076317632763376347635763676377638763976407641764276437644764576467647764876497650765176527653765476557656765776587659766076617662766376647665766676677668766976707671767276737674767576767677767876797680768176827683768476857686768776887689769076917692769376947695769676977698769977007701770277037704770577067707770877097710771177127713771477157716771777187719772077217722772377247725772677277728772977307731773277337734773577367737773877397740774177427743774477457746774777487749775077517752775377547755775677577758775977607761776277637764776577667767776877697770777177727773777477757776777777787779778077817782778377847785778677877788778977907791779277937794779577967797779877997800780178027803780478057806780778087809781078117812781378147815781678177818781978207821782278237824782578267827782878297830783178327833783478357836783778387839784078417842784378447845784678477848784978507851785278537854785578567857785878597860786178627863786478657866786778687869787078717872787378747875787678777878787978807881788278837884788578867887788878897890789178927893789478957896789778987899790079017902790379047905790679077908790979107911791279137914791579167917791879197920792179227923792479257926792779287929793079317932793379347935793679377938793979407941794279437944794579467947794879497950795179527953795479557956795779587959796079617962796379647965796679677968796979707971797279737974797579767977797879797980798179827983798479857986798779887989799079917992799379947995799679977998799980008001800280038004800580068007800880098010801180128013801480158016801780188019802080218022802380248025802680278028802980308031803280338034803580368037803880398040804180428043804480458046804780488049805080518052805380548055805680578058805980608061806280638064806580668067806880698070807180728073807480758076807780788079808080818082808380848085808680878088808980908091809280938094809580968097809880998100810181028103810481058106810781088109811081118112811381148115811681178118811981208121812281238124812581268127812881298130813181328133813481358136813781388139814081418142814381448145814681478148814981508151815281538154815581568157815881598160816181628163816481658166816781688169817081718172817381748175817681778178817981808181818281838184818581868187818881898190819181928193819481958196819781988199820082018202820382048205820682078208820982108211821282138214821582168217821882198220822182228223822482258226822782288229823082318232823382348235823682378238823982408241824282438244824582468247824882498250825182528253825482558256825782588259826082618262826382648265826682678268826982708271827282738274827582768277827882798280828182828283828482858286828782888289829082918292829382948295829682978298829983008301830283038304830583068307830883098310831183128313831483158316831783188319832083218322832383248325832683278328832983308331833283338334833583368337833883398340834183428343834483458346834783488349835083518352835383548355835683578358835983608361836283638364836583668367836883698370837183728373837483758376837783788379838083818382838383848385838683878388838983908391839283938394839583968397839883998400840184028403840484058406840784088409841084118412841384148415841684178418841984208421842284238424842584268427842884298430843184328433843484358436843784388439844084418442844384448445844684478448844984508451845284538454845584568457845884598460846184628463846484658466846784688469847084718472847384748475847684778478847984808481848284838484848584868487848884898490849184928493849484958496849784988499850085018502850385048505850685078508850985108511851285138514851585168517851885198520852185228523852485258526852785288529853085318532853385348535853685378538853985408541854285438544854585468547854885498550855185528553855485558556855785588559856085618562856385648565856685678568856985708571857285738574857585768577857885798580858185828583858485858586858785888589859085918592859385948595859685978598859986008601860286038604860586068607860886098610861186128613861486158616861786188619862086218622862386248625862686278628862986308631863286338634863586368637863886398640864186428643864486458646864786488649865086518652865386548655865686578658865986608661866286638664866586668667866886698670867186728673867486758676867786788679868086818682868386848685868686878688868986908691869286938694869586968697869886998700870187028703870487058706870787088709871087118712871387148715871687178718871987208721872287238724872587268727872887298730873187328733873487358736873787388739874087418742874387448745874687478748874987508751875287538754875587568757875887598760876187628763876487658766876787688769877087718772877387748775877687778778877987808781878287838784878587868787878887898790879187928793879487958796879787988799880088018802880388048805880688078808880988108811881288138814881588168817881888198820882188228823882488258826882788288829883088318832883388348835883688378838883988408841884288438844884588468847884888498850885188528853885488558856885788588859886088618862886388648865886688678868886988708871887288738874887588768877887888798880888188828883888488858886888788888889889088918892889388948895889688978898889989008901890289038904890589068907890889098910891189128913891489158916891789188919892089218922892389248925892689278928892989308931893289338934893589368937893889398940894189428943894489458946894789488949895089518952895389548955895689578958895989608961896289638964896589668967896889698970897189728973897489758976897789788979898089818982898389848985898689878988898989908991899289938994899589968997899889999000900190029003900490059006900790089009901090119012901390149015901690179018901990209021902290239024902590269027902890299030903190329033903490359036903790389039904090419042904390449045904690479048904990509051905290539054905590569057905890599060906190629063906490659066906790689069907090719072907390749075907690779078907990809081908290839084908590869087908890899090909190929093909490959096909790989099910091019102910391049105910691079108910991109111911291139114911591169117911891199120912191229123912491259126912791289129913091319132913391349135913691379138913991409141914291439144914591469147914891499150915191529153915491559156915791589159916091619162916391649165916691679168916991709171917291739174917591769177917891799180918191829183918491859186918791889189919091919192919391949195919691979198919992009201920292039204920592069207920892099210921192129213921492159216921792189219922092219222922392249225922692279228922992309231923292339234923592369237923892399240924192429243924492459246924792489249925092519252925392549255925692579258925992609261926292639264926592669267926892699270927192729273927492759276927792789279928092819282928392849285928692879288928992909291929292939294929592969297929892999300930193029303930493059306930793089309931093119312931393149315931693179318931993209321932293239324932593269327932893299330933193329333933493359336933793389339934093419342934393449345934693479348934993509351935293539354935593569357935893599360936193629363936493659366936793689369937093719372937393749375937693779378937993809381938293839384938593869387938893899390939193929393939493959396939793989399940094019402940394049405940694079408940994109411941294139414941594169417941894199420942194229423942494259426942794289429943094319432943394349435943694379438943994409441944294439444944594469447944894499450945194529453945494559456945794589459946094619462946394649465946694679468946994709471947294739474947594769477947894799480948194829483948494859486948794889489949094919492949394949495949694979498949995009501950295039504950595069507950895099510951195129513951495159516951795189519952095219522952395249525952695279528952995309531953295339534953595369537953895399540954195429543954495459546954795489549955095519552955395549555955695579558955995609561956295639564956595669567956895699570957195729573957495759576957795789579958095819582958395849585958695879588958995909591959295939594959595969597959895999600960196029603960496059606960796089609961096119612961396149615961696179618961996209621962296239624962596269627962896299630963196329633963496359636963796389639964096419642964396449645964696479648964996509651965296539654965596569657965896599660966196629663966496659666966796689669967096719672967396749675967696779678967996809681968296839684968596869687968896899690969196929693969496959696969796989699970097019702970397049705970697079708970997109711971297139714971597169717971897199720972197229723972497259726972797289729973097319732973397349735973697379738973997409741974297439744974597469747974897499750975197529753975497559756975797589759976097619762976397649765976697679768976997709771977297739774977597769777977897799780978197829783978497859786978797889789979097919792979397949795979697979798979998009801980298039804980598069807980898099810981198129813981498159816981798189819982098219822982398249825982698279828982998309831983298339834983598369837983898399840984198429843984498459846984798489849985098519852985398549855985698579858985998609861986298639864986598669867986898699870987198729873987498759876987798789879988098819882988398849885988698879888988998909891989298939894989598969897989898999900990199029903990499059906990799089909991099119912991399149915991699179918991999209921992299239924992599269927992899299930993199329933993499359936993799389939994099419942994399449945994699479948994999509951995299539954995599569957995899599960996199629963996499659966996799689969997099719972997399749975997699779978997999809981998299839984998599869987998899899990999199929993999499959996999799989999100001000110002100031000410005100061000710008100091001010011100121001310014100151001610017100181001910020100211002210023100241002510026100271002810029100301003110032100331003410035100361003710038100391004010041100421004310044100451004610047100481004910050100511005210053100541005510056100571005810059100601006110062100631006410065100661006710068100691007010071100721007310074100751007610077100781007910080100811008210083100841008510086100871008810089100901009110092100931009410095100961009710098100991010010101101021010310104101051010610107101081010910110101111011210113101141011510116101171011810119101201012110122101231012410125101261012710128101291013010131101321013310134101351013610137101381013910140101411014210143101441014510146101471014810149101501015110152101531015410155101561015710158101591016010161101621016310164101651016610167101681016910170101711017210173101741017510176101771017810179101801018110182101831018410185101861018710188101891019010191101921019310194101951019610197101981019910200102011020210203102041020510206102071020810209102101021110212102131021410215102161021710218102191022010221102221022310224102251022610227102281022910230102311023210233102341023510236102371023810239102401024110242102431024410245102461024710248102491025010251102521025310254102551025610257102581025910260102611026210263102641026510266102671026810269102701027110272102731027410275102761027710278102791028010281102821028310284102851028610287102881028910290102911029210293102941029510296102971029810299103001030110302103031030410305103061030710308103091031010311103121031310314103151031610317103181031910320103211032210323103241032510326103271032810329103301033110332103331033410335103361033710338103391034010341103421034310344103451034610347103481034910350103511035210353103541035510356103571035810359103601036110362103631036410365103661036710368103691037010371103721037310374103751037610377103781037910380103811038210383103841038510386103871038810389103901039110392103931039410395103961039710398103991040010401104021040310404104051040610407104081040910410104111041210413104141041510416104171041810419104201042110422104231042410425104261042710428104291043010431104321043310434104351043610437104381043910440104411044210443104441044510446104471044810449104501045110452104531045410455104561045710458104591046010461104621046310464104651046610467104681046910470104711047210473104741047510476104771047810479104801048110482104831048410485104861048710488104891049010491104921049310494104951049610497104981049910500105011050210503105041050510506105071050810509105101051110512105131051410515105161051710518105191052010521105221052310524105251052610527105281052910530105311053210533105341053510536105371053810539105401054110542105431054410545105461054710548105491055010551105521055310554105551055610557105581055910560105611056210563105641056510566105671056810569105701057110572105731057410575105761057710578105791058010581105821058310584105851058610587105881058910590105911059210593105941059510596105971059810599106001060110602106031060410605106061060710608106091061010611106121061310614106151061610617106181061910620106211062210623106241062510626106271062810629106301063110632106331063410635106361063710638106391064010641106421064310644106451064610647106481064910650106511065210653106541065510656106571065810659106601066110662106631066410665106661066710668106691067010671106721067310674106751067610677106781067910680106811068210683106841068510686106871068810689106901069110692106931069410695106961069710698106991070010701107021070310704107051070610707107081070910710107111071210713107141071510716107171071810719107201072110722107231072410725107261072710728107291073010731107321073310734107351073610737107381073910740107411074210743107441074510746107471074810749107501075110752107531075410755107561075710758107591076010761107621076310764107651076610767107681076910770107711077210773107741077510776107771077810779107801078110782107831078410785107861078710788107891079010791107921079310794107951079610797107981079910800108011080210803108041080510806108071080810809108101081110812108131081410815108161081710818108191082010821108221082310824108251082610827108281082910830108311083210833108341083510836108371083810839108401084110842108431084410845108461084710848108491085010851108521085310854108551085610857108581085910860108611086210863108641086510866108671086810869108701087110872108731087410875108761087710878108791088010881108821088310884108851088610887108881088910890108911089210893108941089510896108971089810899109001090110902109031090410905109061090710908109091091010911109121091310914109151091610917109181091910920109211092210923109241092510926109271092810929109301093110932109331093410935109361093710938109391094010941109421094310944109451094610947109481094910950109511095210953109541095510956109571095810959109601096110962109631096410965109661096710968109691097010971109721097310974109751097610977109781097910980109811098210983109841098510986109871098810989109901099110992109931099410995109961099710998109991100011001110021100311004110051100611007110081100911010110111101211013110141101511016110171101811019110201102111022110231102411025110261102711028110291103011031110321103311034110351103611037110381103911040110411104211043110441104511046110471104811049110501105111052110531105411055110561105711058110591106011061110621106311064110651106611067110681106911070110711107211073110741107511076110771107811079110801108111082110831108411085110861108711088110891109011091110921109311094110951109611097110981109911100111011110211103111041110511106111071110811109111101111111112111131111411115111161111711118111191112011121111221112311124111251112611127111281112911130111311113211133111341113511136111371113811139111401114111142111431114411145111461114711148111491115011151111521115311154111551115611157111581115911160111611116211163111641116511166111671116811169111701117111172111731117411175111761117711178111791118011181111821118311184111851118611187111881118911190111911119211193111941119511196111971119811199112001120111202112031120411205112061120711208112091121011211112121121311214112151121611217112181121911220112211122211223112241122511226112271122811229112301123111232112331123411235112361123711238112391124011241112421124311244112451124611247112481124911250112511125211253112541125511256112571125811259112601126111262112631126411265112661126711268112691127011271112721127311274112751127611277112781127911280112811128211283112841128511286112871128811289112901129111292112931129411295112961129711298112991130011301113021130311304113051130611307113081130911310113111131211313113141131511316113171131811319113201132111322113231132411325113261132711328113291133011331113321133311334113351133611337113381133911340113411134211343113441134511346113471134811349113501135111352113531135411355113561135711358113591136011361113621136311364113651136611367113681136911370113711137211373113741137511376113771137811379113801138111382113831138411385113861138711388113891139011391113921139311394113951139611397113981139911400114011140211403114041140511406114071140811409114101141111412114131141411415114161141711418114191142011421114221142311424114251142611427114281142911430114311143211433114341143511436114371143811439114401144111442114431144411445114461144711448114491145011451114521145311454114551145611457114581145911460114611146211463114641146511466114671146811469114701147111472114731147411475114761147711478114791148011481114821148311484114851148611487114881148911490114911149211493114941149511496114971149811499115001150111502115031150411505115061150711508115091151011511115121151311514115151151611517115181151911520115211152211523115241152511526115271152811529115301153111532115331153411535115361153711538115391154011541115421154311544115451154611547115481154911550115511155211553115541155511556115571155811559115601156111562115631156411565115661156711568115691157011571115721157311574115751157611577115781157911580115811158211583115841158511586115871158811589115901159111592115931159411595115961159711598115991160011601116021160311604116051160611607116081160911610116111161211613116141161511616116171161811619116201162111622116231162411625116261162711628116291163011631116321163311634116351163611637116381163911640116411164211643116441164511646116471164811649116501165111652116531165411655116561165711658116591166011661116621166311664116651166611667116681166911670116711167211673116741167511676116771167811679116801168111682116831168411685116861168711688116891169011691116921169311694116951169611697116981169911700117011170211703117041170511706117071170811709117101171111712117131171411715117161171711718117191172011721117221172311724117251172611727117281172911730117311173211733117341173511736117371173811739117401174111742117431174411745117461174711748117491175011751117521175311754117551175611757117581175911760117611176211763117641176511766117671176811769117701177111772117731177411775117761177711778117791178011781117821178311784117851178611787117881178911790117911179211793117941179511796117971179811799118001180111802118031180411805118061180711808118091181011811118121181311814118151181611817118181181911820118211182211823118241182511826118271182811829118301183111832118331183411835118361183711838118391184011841118421184311844118451184611847118481184911850118511185211853118541185511856118571185811859118601186111862118631186411865118661186711868118691187011871118721187311874118751187611877118781187911880118811188211883118841188511886118871188811889118901189111892118931189411895118961189711898118991190011901119021190311904119051190611907119081190911910119111191211913119141191511916119171191811919119201192111922119231192411925119261192711928119291193011931119321193311934119351193611937119381193911940119411194211943119441194511946119471194811949119501195111952119531195411955119561195711958119591196011961119621196311964119651196611967119681196911970119711197211973119741197511976119771197811979119801198111982119831198411985119861198711988119891199011991119921199311994119951199611997119981199912000120011200212003120041200512006120071200812009120101201112012120131201412015120161201712018120191202012021120221202312024120251202612027120281202912030120311203212033120341203512036120371203812039120401204112042120431204412045120461204712048120491205012051120521205312054120551205612057120581205912060120611206212063120641206512066120671206812069120701207112072120731207412075120761207712078120791208012081120821208312084120851208612087120881208912090120911209212093120941209512096120971209812099121001210112102121031210412105121061210712108121091211012111121121211312114121151211612117121181211912120121211212212123121241212512126121271212812129121301213112132121331213412135121361213712138121391214012141121421214312144121451214612147121481214912150121511215212153121541215512156121571215812159121601216112162121631216412165121661216712168121691217012171121721217312174121751217612177121781217912180121811218212183121841218512186121871218812189121901219112192121931219412195121961219712198121991220012201122021220312204122051220612207122081220912210122111221212213122141221512216122171221812219122201222112222122231222412225122261222712228122291223012231122321223312234122351223612237122381223912240122411224212243122441224512246122471224812249122501225112252122531225412255122561225712258122591226012261122621226312264122651226612267122681226912270122711227212273122741227512276122771227812279122801228112282122831228412285122861228712288122891229012291122921229312294122951229612297122981229912300123011230212303123041230512306123071230812309123101231112312123131231412315123161231712318123191232012321123221232312324123251232612327123281232912330123311233212333123341233512336123371233812339123401234112342123431234412345123461234712348123491235012351123521235312354123551235612357123581235912360123611236212363123641236512366123671236812369123701237112372123731237412375123761237712378123791238012381123821238312384123851238612387123881238912390123911239212393123941239512396123971239812399124001240112402124031240412405124061240712408124091241012411124121241312414124151241612417124181241912420124211242212423124241242512426124271242812429124301243112432124331243412435124361243712438124391244012441124421244312444124451244612447124481244912450124511245212453124541245512456124571245812459124601246112462124631246412465124661246712468124691247012471124721247312474124751247612477124781247912480124811248212483124841248512486124871248812489124901249112492124931249412495124961249712498124991250012501125021250312504125051250612507125081250912510125111251212513125141251512516125171251812519125201252112522125231252412525125261252712528125291253012531125321253312534125351253612537125381253912540125411254212543125441254512546125471254812549125501255112552125531255412555125561255712558125591256012561125621256312564125651256612567125681256912570125711257212573125741257512576125771257812579125801258112582125831258412585125861258712588125891259012591125921259312594125951259612597125981259912600126011260212603126041260512606126071260812609126101261112612126131261412615126161261712618126191262012621126221262312624126251262612627126281262912630126311263212633126341263512636126371263812639126401264112642126431264412645126461264712648126491265012651126521265312654126551265612657126581265912660126611266212663126641266512666126671266812669126701267112672126731267412675126761267712678126791268012681126821268312684126851268612687126881268912690126911269212693126941269512696126971269812699127001270112702127031270412705127061270712708127091271012711127121271312714127151271612717127181271912720127211272212723127241272512726127271272812729127301273112732127331273412735127361273712738127391274012741127421274312744127451274612747127481274912750127511275212753127541275512756127571275812759127601276112762127631276412765127661276712768127691277012771127721277312774127751277612777127781277912780127811278212783127841278512786127871278812789127901279112792127931279412795127961279712798127991280012801128021280312804128051280612807128081280912810128111281212813128141281512816128171281812819128201282112822128231282412825128261282712828128291283012831128321283312834128351283612837128381283912840128411284212843128441284512846128471284812849128501285112852128531285412855128561285712858128591286012861128621286312864128651286612867128681286912870128711287212873128741287512876128771287812879128801288112882128831288412885128861288712888128891289012891128921289312894128951289612897128981289912900129011290212903129041290512906129071290812909129101291112912129131291412915129161291712918129191292012921129221292312924129251292612927129281292912930129311293212933129341293512936129371293812939129401294112942129431294412945129461294712948129491295012951129521295312954129551295612957129581295912960129611296212963129641296512966129671296812969129701297112972129731297412975129761297712978129791298012981129821298312984129851298612987129881298912990129911299212993129941299512996129971299812999130001300113002130031300413005130061300713008130091301013011130121301313014130151301613017130181301913020130211302213023130241302513026130271302813029130301303113032130331303413035130361303713038130391304013041130421304313044130451304613047130481304913050130511305213053130541305513056130571305813059130601306113062130631306413065130661306713068130691307013071130721307313074130751307613077130781307913080130811308213083130841308513086130871308813089130901309113092130931309413095130961309713098130991310013101131021310313104131051310613107131081310913110131111311213113131141311513116131171311813119131201312113122131231312413125131261312713128131291313013131131321313313134131351313613137131381313913140131411314213143131441314513146131471314813149131501315113152131531315413155131561315713158131591316013161131621316313164131651316613167131681316913170131711317213173131741317513176131771317813179131801318113182131831318413185131861318713188131891319013191131921319313194131951319613197131981319913200132011320213203132041320513206132071320813209132101321113212132131321413215132161321713218132191322013221132221322313224132251322613227132281322913230132311323213233132341323513236132371323813239132401324113242132431324413245132461324713248132491325013251132521325313254132551325613257132581325913260132611326213263132641326513266132671326813269132701327113272132731327413275132761327713278132791328013281132821328313284132851328613287132881328913290132911329213293132941329513296132971329813299133001330113302133031330413305133061330713308133091331013311133121331313314133151331613317133181331913320133211332213323133241332513326133271332813329133301333113332133331333413335133361333713338133391334013341133421334313344133451334613347133481334913350133511335213353133541335513356133571335813359133601336113362133631336413365133661336713368133691337013371133721337313374133751337613377133781337913380133811338213383133841338513386133871338813389133901339113392133931339413395133961339713398133991340013401134021340313404134051340613407134081340913410134111341213413134141341513416134171341813419134201342113422134231342413425134261342713428134291343013431134321343313434134351343613437134381343913440134411344213443134441344513446134471344813449134501345113452134531345413455134561345713458134591346013461134621346313464134651346613467134681346913470134711347213473134741347513476134771347813479134801348113482134831348413485134861348713488134891349013491134921349313494134951349613497134981349913500135011350213503135041350513506135071350813509135101351113512135131351413515135161351713518135191352013521135221352313524135251352613527135281352913530135311353213533135341353513536135371353813539135401354113542135431354413545135461354713548135491355013551135521355313554135551355613557135581355913560135611356213563135641356513566135671356813569135701357113572135731357413575135761357713578135791358013581135821358313584135851358613587135881358913590135911359213593135941359513596135971359813599136001360113602136031360413605136061360713608136091361013611136121361313614136151361613617136181361913620136211362213623136241362513626136271362813629136301363113632136331363413635136361363713638136391364013641136421364313644136451364613647136481364913650136511365213653136541365513656136571365813659136601366113662136631366413665136661366713668136691367013671136721367313674136751367613677136781367913680136811368213683136841368513686136871368813689136901369113692136931369413695136961369713698136991370013701137021370313704137051370613707137081370913710137111371213713137141371513716137171371813719137201372113722137231372413725137261372713728137291373013731137321373313734137351373613737137381373913740137411374213743137441374513746137471374813749137501375113752137531375413755137561375713758137591376013761137621376313764137651376613767137681376913770137711377213773137741377513776137771377813779137801378113782137831378413785137861378713788137891379013791137921379313794137951379613797137981379913800138011380213803138041380513806138071380813809138101381113812138131381413815138161381713818138191382013821138221382313824138251382613827138281382913830138311383213833138341383513836138371383813839138401384113842138431384413845138461384713848138491385013851138521385313854138551385613857138581385913860138611386213863138641386513866138671386813869138701387113872138731387413875138761387713878138791388013881138821388313884138851388613887138881388913890138911389213893138941389513896138971389813899139001390113902139031390413905139061390713908139091391013911139121391313914139151391613917139181391913920139211392213923139241392513926139271392813929139301393113932139331393413935139361393713938139391394013941139421394313944139451394613947139481394913950139511395213953139541395513956139571395813959139601396113962139631396413965139661396713968139691397013971139721397313974139751397613977139781397913980139811398213983139841398513986139871398813989139901399113992139931399413995139961399713998139991400014001140021400314004140051400614007140081400914010140111401214013140141401514016140171401814019140201402114022140231402414025140261402714028140291403014031140321403314034140351403614037140381403914040140411404214043140441404514046140471404814049140501405114052140531405414055140561405714058140591406014061140621406314064140651406614067140681406914070140711407214073140741407514076140771407814079140801408114082140831408414085140861408714088140891409014091140921409314094140951409614097140981409914100141011410214103141041410514106141071410814109141101411114112141131411414115141161411714118141191412014121141221412314124141251412614127141281412914130141311413214133141341413514136141371413814139141401414114142141431414414145141461414714148141491415014151141521415314154141551415614157141581415914160141611416214163141641416514166141671416814169141701417114172141731417414175141761417714178141791418014181141821418314184141851418614187141881418914190141911419214193141941419514196141971419814199142001420114202142031420414205142061420714208142091421014211142121421314214142151421614217142181421914220142211422214223142241422514226142271422814229142301423114232142331423414235142361423714238142391424014241142421424314244142451424614247142481424914250142511425214253142541425514256142571425814259142601426114262142631426414265142661426714268142691427014271142721427314274142751427614277142781427914280142811428214283142841428514286142871428814289142901429114292142931429414295142961429714298142991430014301143021430314304143051430614307143081430914310143111431214313143141431514316143171431814319143201432114322143231432414325143261432714328143291433014331143321433314334143351433614337143381433914340143411434214343143441434514346143471434814349143501435114352143531435414355143561435714358143591436014361143621436314364143651436614367143681436914370143711437214373143741437514376143771437814379143801438114382143831438414385143861438714388143891439014391143921439314394143951439614397143981439914400144011440214403144041440514406144071440814409144101441114412144131441414415144161441714418144191442014421144221442314424144251442614427144281442914430144311443214433144341443514436144371443814439144401444114442144431444414445144461444714448144491445014451144521445314454144551445614457144581445914460144611446214463144641446514466144671446814469144701447114472144731447414475144761447714478144791448014481144821448314484144851448614487144881448914490144911449214493144941449514496144971449814499145001450114502145031450414505145061450714508145091451014511145121451314514145151451614517145181451914520145211452214523145241452514526145271452814529145301453114532145331453414535145361453714538145391454014541145421454314544145451454614547145481454914550145511455214553145541455514556145571455814559145601456114562145631456414565145661456714568145691457014571145721457314574145751457614577145781457914580145811458214583145841458514586145871458814589145901459114592145931459414595145961459714598145991460014601146021460314604146051460614607146081460914610146111461214613146141461514616146171461814619146201462114622146231462414625146261462714628146291463014631146321463314634146351463614637146381463914640146411464214643146441464514646146471464814649146501465114652146531465414655146561465714658146591466014661146621466314664146651466614667146681466914670146711467214673146741467514676146771467814679146801468114682146831468414685146861468714688146891469014691146921469314694146951469614697146981469914700147011470214703147041470514706147071470814709147101471114712147131471414715147161471714718147191472014721147221472314724147251472614727147281472914730147311473214733147341473514736147371473814739147401474114742147431474414745147461474714748147491475014751147521475314754147551475614757147581475914760147611476214763147641476514766147671476814769147701477114772147731477414775147761477714778147791478014781147821478314784147851478614787147881478914790147911479214793147941479514796147971479814799148001480114802148031480414805148061480714808148091481014811148121481314814148151481614817148181481914820148211482214823148241482514826148271482814829148301483114832148331483414835148361483714838148391484014841148421484314844148451484614847148481484914850148511485214853148541485514856148571485814859148601486114862148631486414865148661486714868148691487014871148721487314874148751487614877148781487914880148811488214883148841488514886148871488814889148901489114892148931489414895148961489714898148991490014901149021490314904149051490614907149081490914910149111491214913149141491514916149171491814919149201492114922149231492414925149261492714928149291493014931149321493314934149351493614937149381493914940149411494214943149441494514946149471494814949149501495114952149531495414955149561495714958149591496014961149621496314964149651496614967149681496914970149711497214973149741497514976149771497814979149801498114982149831498414985149861498714988149891499014991149921499314994149951499614997149981499915000150011500215003150041500515006150071500815009150101501115012150131501415015150161501715018150191502015021150221502315024150251502615027150281502915030150311503215033150341503515036150371503815039150401504115042150431504415045150461504715048150491505015051150521505315054150551505615057150581505915060150611506215063150641506515066150671506815069150701507115072150731507415075150761507715078150791508015081150821508315084150851508615087150881508915090150911509215093150941509515096150971509815099151001510115102151031510415105151061510715108151091511015111151121511315114151151511615117151181511915120151211512215123151241512515126151271512815129151301513115132151331513415135151361513715138151391514015141151421514315144151451514615147151481514915150151511515215153151541515515156151571515815159151601516115162151631516415165151661516715168151691517015171151721517315174151751517615177151781517915180151811518215183151841518515186151871518815189151901519115192151931519415195151961519715198151991520015201152021520315204152051520615207152081520915210152111521215213152141521515216152171521815219152201522115222152231522415225152261522715228152291523015231152321523315234152351523615237152381523915240152411524215243152441524515246152471524815249152501525115252152531525415255152561525715258152591526015261152621526315264152651526615267152681526915270152711527215273152741527515276152771527815279152801528115282152831528415285152861528715288152891529015291152921529315294152951529615297152981529915300153011530215303153041530515306153071530815309153101531115312153131531415315153161531715318153191532015321153221532315324153251532615327153281532915330153311533215333153341533515336153371533815339153401534115342153431534415345153461534715348153491535015351153521535315354153551535615357153581535915360153611536215363153641536515366153671536815369153701537115372153731537415375153761537715378153791538015381153821538315384153851538615387153881538915390153911539215393153941539515396153971539815399154001540115402154031540415405154061540715408154091541015411154121541315414154151541615417154181541915420154211542215423154241542515426154271542815429154301543115432154331543415435154361543715438154391544015441154421544315444154451544615447154481544915450154511545215453154541545515456154571545815459154601546115462154631546415465154661546715468154691547015471154721547315474154751547615477154781547915480154811548215483154841548515486154871548815489154901549115492154931549415495154961549715498154991550015501155021550315504155051550615507155081550915510155111551215513155141551515516155171551815519155201552115522155231552415525155261552715528155291553015531155321553315534155351553615537155381553915540155411554215543155441554515546155471554815549155501555115552155531555415555155561555715558155591556015561155621556315564155651556615567155681556915570155711557215573155741557515576155771557815579155801558115582155831558415585155861558715588155891559015591155921559315594155951559615597155981559915600156011560215603156041560515606156071560815609156101561115612156131561415615156161561715618156191562015621156221562315624156251562615627156281562915630156311563215633156341563515636156371563815639156401564115642156431564415645156461564715648156491565015651156521565315654156551565615657156581565915660156611566215663156641566515666156671566815669156701567115672156731567415675156761567715678156791568015681156821568315684156851568615687156881568915690156911569215693156941569515696156971569815699157001570115702157031570415705157061570715708157091571015711157121571315714157151571615717157181571915720157211572215723157241572515726157271572815729157301573115732157331573415735157361573715738157391574015741157421574315744157451574615747157481574915750157511575215753157541575515756157571575815759157601576115762157631576415765157661576715768157691577015771157721577315774157751577615777157781577915780157811578215783157841578515786157871578815789157901579115792157931579415795157961579715798157991580015801158021580315804158051580615807158081580915810158111581215813158141581515816158171581815819158201582115822158231582415825158261582715828158291583015831158321583315834158351583615837158381583915840158411584215843158441584515846158471584815849158501585115852158531585415855158561585715858158591586015861158621586315864158651586615867158681586915870158711587215873158741587515876158771587815879158801588115882158831588415885158861588715888158891589015891158921589315894158951589615897158981589915900159011590215903159041590515906159071590815909159101591115912159131591415915159161591715918159191592015921159221592315924159251592615927159281592915930159311593215933159341593515936159371593815939159401594115942159431594415945159461594715948159491595015951159521595315954159551595615957159581595915960159611596215963159641596515966159671596815969159701597115972159731597415975159761597715978159791598015981159821598315984159851598615987159881598915990159911599215993159941599515996159971599815999160001600116002160031600416005160061600716008160091601016011160121601316014160151601616017160181601916020160211602216023160241602516026160271602816029160301603116032160331603416035160361603716038160391604016041160421604316044160451604616047160481604916050160511605216053160541605516056160571605816059160601606116062160631606416065160661606716068160691607016071160721607316074160751607616077160781607916080160811608216083160841608516086160871608816089160901609116092160931609416095160961609716098160991610016101161021610316104161051610616107161081610916110161111611216113161141611516116161171611816119161201612116122161231612416125161261612716128161291613016131161321613316134161351613616137161381613916140161411614216143161441614516146161471614816149161501615116152161531615416155161561615716158161591616016161161621616316164161651616616167161681616916170161711617216173161741617516176161771617816179161801618116182161831618416185161861618716188161891619016191161921619316194161951619616197161981619916200162011620216203162041620516206162071620816209162101621116212162131621416215162161621716218162191622016221162221622316224162251622616227162281622916230162311623216233162341623516236162371623816239162401624116242162431624416245162461624716248162491625016251162521625316254162551625616257162581625916260162611626216263162641626516266162671626816269162701627116272162731627416275162761627716278162791628016281162821628316284162851628616287162881628916290162911629216293162941629516296162971629816299163001630116302163031630416305163061630716308163091631016311163121631316314163151631616317163181631916320163211632216323163241632516326163271632816329163301633116332163331633416335163361633716338163391634016341163421634316344
  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_dsi.h"
  39. #include "i915_trace.h"
  40. #include <drm/drm_atomic.h>
  41. #include <drm/drm_atomic_helper.h>
  42. #include <drm/drm_dp_helper.h>
  43. #include <drm/drm_crtc_helper.h>
  44. #include <drm/drm_plane_helper.h>
  45. #include <drm/drm_rect.h>
  46. #include <linux/dma_remapping.h>
  47. #include <linux/reservation.h>
  48. #include <linux/dma-buf.h>
  49. /* Primary plane formats for gen <= 3 */
  50. static const uint32_t i8xx_primary_formats[] = {
  51. DRM_FORMAT_C8,
  52. DRM_FORMAT_RGB565,
  53. DRM_FORMAT_XRGB1555,
  54. DRM_FORMAT_XRGB8888,
  55. };
  56. /* Primary plane formats for gen >= 4 */
  57. static const uint32_t i965_primary_formats[] = {
  58. DRM_FORMAT_C8,
  59. DRM_FORMAT_RGB565,
  60. DRM_FORMAT_XRGB8888,
  61. DRM_FORMAT_XBGR8888,
  62. DRM_FORMAT_XRGB2101010,
  63. DRM_FORMAT_XBGR2101010,
  64. };
  65. static const uint32_t skl_primary_formats[] = {
  66. DRM_FORMAT_C8,
  67. DRM_FORMAT_RGB565,
  68. DRM_FORMAT_XRGB8888,
  69. DRM_FORMAT_XBGR8888,
  70. DRM_FORMAT_ARGB8888,
  71. DRM_FORMAT_ABGR8888,
  72. DRM_FORMAT_XRGB2101010,
  73. DRM_FORMAT_XBGR2101010,
  74. DRM_FORMAT_YUYV,
  75. DRM_FORMAT_YVYU,
  76. DRM_FORMAT_UYVY,
  77. DRM_FORMAT_VYUY,
  78. };
  79. /* Cursor formats */
  80. static const uint32_t intel_cursor_formats[] = {
  81. DRM_FORMAT_ARGB8888,
  82. };
  83. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  84. struct intel_crtc_state *pipe_config);
  85. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  86. struct intel_crtc_state *pipe_config);
  87. static int intel_framebuffer_init(struct drm_device *dev,
  88. struct intel_framebuffer *ifb,
  89. struct drm_mode_fb_cmd2 *mode_cmd,
  90. struct drm_i915_gem_object *obj);
  91. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  92. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  93. static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
  94. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  95. struct intel_link_m_n *m_n,
  96. struct intel_link_m_n *m2_n2);
  97. static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  98. static void haswell_set_pipeconf(struct drm_crtc *crtc);
  99. static void haswell_set_pipemisc(struct drm_crtc *crtc);
  100. static void vlv_prepare_pll(struct intel_crtc *crtc,
  101. const struct intel_crtc_state *pipe_config);
  102. static void chv_prepare_pll(struct intel_crtc *crtc,
  103. const struct intel_crtc_state *pipe_config);
  104. static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
  105. static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
  106. static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
  107. struct intel_crtc_state *crtc_state);
  108. static void skylake_pfit_enable(struct intel_crtc *crtc);
  109. static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
  110. static void ironlake_pfit_enable(struct intel_crtc *crtc);
  111. static void intel_modeset_setup_hw_state(struct drm_device *dev);
  112. static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
  113. struct intel_limit {
  114. struct {
  115. int min, max;
  116. } dot, vco, n, m, m1, m2, p, p1;
  117. struct {
  118. int dot_limit;
  119. int p2_slow, p2_fast;
  120. } p2;
  121. };
  122. /* returns HPLL frequency in kHz */
  123. static int valleyview_get_vco(struct drm_i915_private *dev_priv)
  124. {
  125. int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
  126. /* Obtain SKU information */
  127. mutex_lock(&dev_priv->sb_lock);
  128. hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
  129. CCK_FUSE_HPLL_FREQ_MASK;
  130. mutex_unlock(&dev_priv->sb_lock);
  131. return vco_freq[hpll_freq] * 1000;
  132. }
  133. int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
  134. const char *name, u32 reg, int ref_freq)
  135. {
  136. u32 val;
  137. int divider;
  138. mutex_lock(&dev_priv->sb_lock);
  139. val = vlv_cck_read(dev_priv, reg);
  140. mutex_unlock(&dev_priv->sb_lock);
  141. divider = val & CCK_FREQUENCY_VALUES;
  142. WARN((val & CCK_FREQUENCY_STATUS) !=
  143. (divider << CCK_FREQUENCY_STATUS_SHIFT),
  144. "%s change in progress\n", name);
  145. return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
  146. }
  147. static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
  148. const char *name, u32 reg)
  149. {
  150. if (dev_priv->hpll_freq == 0)
  151. dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
  152. return vlv_get_cck_clock(dev_priv, name, reg,
  153. dev_priv->hpll_freq);
  154. }
  155. static int
  156. intel_pch_rawclk(struct drm_i915_private *dev_priv)
  157. {
  158. return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
  159. }
  160. static int
  161. intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
  162. {
  163. /* RAWCLK_FREQ_VLV register updated from power well code */
  164. return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
  165. CCK_DISPLAY_REF_CLOCK_CONTROL);
  166. }
  167. static int
  168. intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
  169. {
  170. uint32_t clkcfg;
  171. /* hrawclock is 1/4 the FSB frequency */
  172. clkcfg = I915_READ(CLKCFG);
  173. switch (clkcfg & CLKCFG_FSB_MASK) {
  174. case CLKCFG_FSB_400:
  175. return 100000;
  176. case CLKCFG_FSB_533:
  177. return 133333;
  178. case CLKCFG_FSB_667:
  179. return 166667;
  180. case CLKCFG_FSB_800:
  181. return 200000;
  182. case CLKCFG_FSB_1067:
  183. return 266667;
  184. case CLKCFG_FSB_1333:
  185. return 333333;
  186. /* these two are just a guess; one of them might be right */
  187. case CLKCFG_FSB_1600:
  188. case CLKCFG_FSB_1600_ALT:
  189. return 400000;
  190. default:
  191. return 133333;
  192. }
  193. }
  194. void intel_update_rawclk(struct drm_i915_private *dev_priv)
  195. {
  196. if (HAS_PCH_SPLIT(dev_priv))
  197. dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
  198. else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
  199. dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
  200. else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
  201. dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
  202. else
  203. return; /* no rawclk on other platforms, or no need to know it */
  204. DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
  205. }
  206. static void intel_update_czclk(struct drm_i915_private *dev_priv)
  207. {
  208. if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
  209. return;
  210. dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
  211. CCK_CZ_CLOCK_CONTROL);
  212. DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
  213. }
  214. static inline u32 /* units of 100MHz */
  215. intel_fdi_link_freq(struct drm_i915_private *dev_priv,
  216. const struct intel_crtc_state *pipe_config)
  217. {
  218. if (HAS_DDI(dev_priv))
  219. return pipe_config->port_clock; /* SPLL */
  220. else if (IS_GEN5(dev_priv))
  221. return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
  222. else
  223. return 270000;
  224. }
  225. static const struct intel_limit intel_limits_i8xx_dac = {
  226. .dot = { .min = 25000, .max = 350000 },
  227. .vco = { .min = 908000, .max = 1512000 },
  228. .n = { .min = 2, .max = 16 },
  229. .m = { .min = 96, .max = 140 },
  230. .m1 = { .min = 18, .max = 26 },
  231. .m2 = { .min = 6, .max = 16 },
  232. .p = { .min = 4, .max = 128 },
  233. .p1 = { .min = 2, .max = 33 },
  234. .p2 = { .dot_limit = 165000,
  235. .p2_slow = 4, .p2_fast = 2 },
  236. };
  237. static const struct intel_limit intel_limits_i8xx_dvo = {
  238. .dot = { .min = 25000, .max = 350000 },
  239. .vco = { .min = 908000, .max = 1512000 },
  240. .n = { .min = 2, .max = 16 },
  241. .m = { .min = 96, .max = 140 },
  242. .m1 = { .min = 18, .max = 26 },
  243. .m2 = { .min = 6, .max = 16 },
  244. .p = { .min = 4, .max = 128 },
  245. .p1 = { .min = 2, .max = 33 },
  246. .p2 = { .dot_limit = 165000,
  247. .p2_slow = 4, .p2_fast = 4 },
  248. };
  249. static const struct intel_limit intel_limits_i8xx_lvds = {
  250. .dot = { .min = 25000, .max = 350000 },
  251. .vco = { .min = 908000, .max = 1512000 },
  252. .n = { .min = 2, .max = 16 },
  253. .m = { .min = 96, .max = 140 },
  254. .m1 = { .min = 18, .max = 26 },
  255. .m2 = { .min = 6, .max = 16 },
  256. .p = { .min = 4, .max = 128 },
  257. .p1 = { .min = 1, .max = 6 },
  258. .p2 = { .dot_limit = 165000,
  259. .p2_slow = 14, .p2_fast = 7 },
  260. };
  261. static const struct intel_limit intel_limits_i9xx_sdvo = {
  262. .dot = { .min = 20000, .max = 400000 },
  263. .vco = { .min = 1400000, .max = 2800000 },
  264. .n = { .min = 1, .max = 6 },
  265. .m = { .min = 70, .max = 120 },
  266. .m1 = { .min = 8, .max = 18 },
  267. .m2 = { .min = 3, .max = 7 },
  268. .p = { .min = 5, .max = 80 },
  269. .p1 = { .min = 1, .max = 8 },
  270. .p2 = { .dot_limit = 200000,
  271. .p2_slow = 10, .p2_fast = 5 },
  272. };
  273. static const struct intel_limit intel_limits_i9xx_lvds = {
  274. .dot = { .min = 20000, .max = 400000 },
  275. .vco = { .min = 1400000, .max = 2800000 },
  276. .n = { .min = 1, .max = 6 },
  277. .m = { .min = 70, .max = 120 },
  278. .m1 = { .min = 8, .max = 18 },
  279. .m2 = { .min = 3, .max = 7 },
  280. .p = { .min = 7, .max = 98 },
  281. .p1 = { .min = 1, .max = 8 },
  282. .p2 = { .dot_limit = 112000,
  283. .p2_slow = 14, .p2_fast = 7 },
  284. };
  285. static const struct intel_limit intel_limits_g4x_sdvo = {
  286. .dot = { .min = 25000, .max = 270000 },
  287. .vco = { .min = 1750000, .max = 3500000},
  288. .n = { .min = 1, .max = 4 },
  289. .m = { .min = 104, .max = 138 },
  290. .m1 = { .min = 17, .max = 23 },
  291. .m2 = { .min = 5, .max = 11 },
  292. .p = { .min = 10, .max = 30 },
  293. .p1 = { .min = 1, .max = 3},
  294. .p2 = { .dot_limit = 270000,
  295. .p2_slow = 10,
  296. .p2_fast = 10
  297. },
  298. };
  299. static const struct intel_limit intel_limits_g4x_hdmi = {
  300. .dot = { .min = 22000, .max = 400000 },
  301. .vco = { .min = 1750000, .max = 3500000},
  302. .n = { .min = 1, .max = 4 },
  303. .m = { .min = 104, .max = 138 },
  304. .m1 = { .min = 16, .max = 23 },
  305. .m2 = { .min = 5, .max = 11 },
  306. .p = { .min = 5, .max = 80 },
  307. .p1 = { .min = 1, .max = 8},
  308. .p2 = { .dot_limit = 165000,
  309. .p2_slow = 10, .p2_fast = 5 },
  310. };
  311. static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
  312. .dot = { .min = 20000, .max = 115000 },
  313. .vco = { .min = 1750000, .max = 3500000 },
  314. .n = { .min = 1, .max = 3 },
  315. .m = { .min = 104, .max = 138 },
  316. .m1 = { .min = 17, .max = 23 },
  317. .m2 = { .min = 5, .max = 11 },
  318. .p = { .min = 28, .max = 112 },
  319. .p1 = { .min = 2, .max = 8 },
  320. .p2 = { .dot_limit = 0,
  321. .p2_slow = 14, .p2_fast = 14
  322. },
  323. };
  324. static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
  325. .dot = { .min = 80000, .max = 224000 },
  326. .vco = { .min = 1750000, .max = 3500000 },
  327. .n = { .min = 1, .max = 3 },
  328. .m = { .min = 104, .max = 138 },
  329. .m1 = { .min = 17, .max = 23 },
  330. .m2 = { .min = 5, .max = 11 },
  331. .p = { .min = 14, .max = 42 },
  332. .p1 = { .min = 2, .max = 6 },
  333. .p2 = { .dot_limit = 0,
  334. .p2_slow = 7, .p2_fast = 7
  335. },
  336. };
  337. static const struct intel_limit intel_limits_pineview_sdvo = {
  338. .dot = { .min = 20000, .max = 400000},
  339. .vco = { .min = 1700000, .max = 3500000 },
  340. /* Pineview's Ncounter is a ring counter */
  341. .n = { .min = 3, .max = 6 },
  342. .m = { .min = 2, .max = 256 },
  343. /* Pineview only has one combined m divider, which we treat as m2. */
  344. .m1 = { .min = 0, .max = 0 },
  345. .m2 = { .min = 0, .max = 254 },
  346. .p = { .min = 5, .max = 80 },
  347. .p1 = { .min = 1, .max = 8 },
  348. .p2 = { .dot_limit = 200000,
  349. .p2_slow = 10, .p2_fast = 5 },
  350. };
  351. static const struct intel_limit intel_limits_pineview_lvds = {
  352. .dot = { .min = 20000, .max = 400000 },
  353. .vco = { .min = 1700000, .max = 3500000 },
  354. .n = { .min = 3, .max = 6 },
  355. .m = { .min = 2, .max = 256 },
  356. .m1 = { .min = 0, .max = 0 },
  357. .m2 = { .min = 0, .max = 254 },
  358. .p = { .min = 7, .max = 112 },
  359. .p1 = { .min = 1, .max = 8 },
  360. .p2 = { .dot_limit = 112000,
  361. .p2_slow = 14, .p2_fast = 14 },
  362. };
  363. /* Ironlake / Sandybridge
  364. *
  365. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  366. * the range value for them is (actual_value - 2).
  367. */
  368. static const struct intel_limit intel_limits_ironlake_dac = {
  369. .dot = { .min = 25000, .max = 350000 },
  370. .vco = { .min = 1760000, .max = 3510000 },
  371. .n = { .min = 1, .max = 5 },
  372. .m = { .min = 79, .max = 127 },
  373. .m1 = { .min = 12, .max = 22 },
  374. .m2 = { .min = 5, .max = 9 },
  375. .p = { .min = 5, .max = 80 },
  376. .p1 = { .min = 1, .max = 8 },
  377. .p2 = { .dot_limit = 225000,
  378. .p2_slow = 10, .p2_fast = 5 },
  379. };
  380. static const struct intel_limit intel_limits_ironlake_single_lvds = {
  381. .dot = { .min = 25000, .max = 350000 },
  382. .vco = { .min = 1760000, .max = 3510000 },
  383. .n = { .min = 1, .max = 3 },
  384. .m = { .min = 79, .max = 118 },
  385. .m1 = { .min = 12, .max = 22 },
  386. .m2 = { .min = 5, .max = 9 },
  387. .p = { .min = 28, .max = 112 },
  388. .p1 = { .min = 2, .max = 8 },
  389. .p2 = { .dot_limit = 225000,
  390. .p2_slow = 14, .p2_fast = 14 },
  391. };
  392. static const struct intel_limit intel_limits_ironlake_dual_lvds = {
  393. .dot = { .min = 25000, .max = 350000 },
  394. .vco = { .min = 1760000, .max = 3510000 },
  395. .n = { .min = 1, .max = 3 },
  396. .m = { .min = 79, .max = 127 },
  397. .m1 = { .min = 12, .max = 22 },
  398. .m2 = { .min = 5, .max = 9 },
  399. .p = { .min = 14, .max = 56 },
  400. .p1 = { .min = 2, .max = 8 },
  401. .p2 = { .dot_limit = 225000,
  402. .p2_slow = 7, .p2_fast = 7 },
  403. };
  404. /* LVDS 100mhz refclk limits. */
  405. static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
  406. .dot = { .min = 25000, .max = 350000 },
  407. .vco = { .min = 1760000, .max = 3510000 },
  408. .n = { .min = 1, .max = 2 },
  409. .m = { .min = 79, .max = 126 },
  410. .m1 = { .min = 12, .max = 22 },
  411. .m2 = { .min = 5, .max = 9 },
  412. .p = { .min = 28, .max = 112 },
  413. .p1 = { .min = 2, .max = 8 },
  414. .p2 = { .dot_limit = 225000,
  415. .p2_slow = 14, .p2_fast = 14 },
  416. };
  417. static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
  418. .dot = { .min = 25000, .max = 350000 },
  419. .vco = { .min = 1760000, .max = 3510000 },
  420. .n = { .min = 1, .max = 3 },
  421. .m = { .min = 79, .max = 126 },
  422. .m1 = { .min = 12, .max = 22 },
  423. .m2 = { .min = 5, .max = 9 },
  424. .p = { .min = 14, .max = 42 },
  425. .p1 = { .min = 2, .max = 6 },
  426. .p2 = { .dot_limit = 225000,
  427. .p2_slow = 7, .p2_fast = 7 },
  428. };
  429. static const struct intel_limit intel_limits_vlv = {
  430. /*
  431. * These are the data rate limits (measured in fast clocks)
  432. * since those are the strictest limits we have. The fast
  433. * clock and actual rate limits are more relaxed, so checking
  434. * them would make no difference.
  435. */
  436. .dot = { .min = 25000 * 5, .max = 270000 * 5 },
  437. .vco = { .min = 4000000, .max = 6000000 },
  438. .n = { .min = 1, .max = 7 },
  439. .m1 = { .min = 2, .max = 3 },
  440. .m2 = { .min = 11, .max = 156 },
  441. .p1 = { .min = 2, .max = 3 },
  442. .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
  443. };
  444. static const struct intel_limit intel_limits_chv = {
  445. /*
  446. * These are the data rate limits (measured in fast clocks)
  447. * since those are the strictest limits we have. The fast
  448. * clock and actual rate limits are more relaxed, so checking
  449. * them would make no difference.
  450. */
  451. .dot = { .min = 25000 * 5, .max = 540000 * 5},
  452. .vco = { .min = 4800000, .max = 6480000 },
  453. .n = { .min = 1, .max = 1 },
  454. .m1 = { .min = 2, .max = 2 },
  455. .m2 = { .min = 24 << 22, .max = 175 << 22 },
  456. .p1 = { .min = 2, .max = 4 },
  457. .p2 = { .p2_slow = 1, .p2_fast = 14 },
  458. };
  459. static const struct intel_limit intel_limits_bxt = {
  460. /* FIXME: find real dot limits */
  461. .dot = { .min = 0, .max = INT_MAX },
  462. .vco = { .min = 4800000, .max = 6700000 },
  463. .n = { .min = 1, .max = 1 },
  464. .m1 = { .min = 2, .max = 2 },
  465. /* FIXME: find real m2 limits */
  466. .m2 = { .min = 2 << 22, .max = 255 << 22 },
  467. .p1 = { .min = 2, .max = 4 },
  468. .p2 = { .p2_slow = 1, .p2_fast = 20 },
  469. };
  470. static bool
  471. needs_modeset(struct drm_crtc_state *state)
  472. {
  473. return drm_atomic_crtc_needs_modeset(state);
  474. }
  475. /**
  476. * Returns whether any output on the specified pipe is of the specified type
  477. */
  478. bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
  479. {
  480. struct drm_device *dev = crtc->base.dev;
  481. struct intel_encoder *encoder;
  482. for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  483. if (encoder->type == type)
  484. return true;
  485. return false;
  486. }
  487. /**
  488. * Returns whether any output on the specified pipe will have the specified
  489. * type after a staged modeset is complete, i.e., the same as
  490. * intel_pipe_has_type() but looking at encoder->new_crtc instead of
  491. * encoder->crtc.
  492. */
  493. static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
  494. int type)
  495. {
  496. struct drm_atomic_state *state = crtc_state->base.state;
  497. struct drm_connector *connector;
  498. struct drm_connector_state *connector_state;
  499. struct intel_encoder *encoder;
  500. int i, num_connectors = 0;
  501. for_each_connector_in_state(state, connector, connector_state, i) {
  502. if (connector_state->crtc != crtc_state->base.crtc)
  503. continue;
  504. num_connectors++;
  505. encoder = to_intel_encoder(connector_state->best_encoder);
  506. if (encoder->type == type)
  507. return true;
  508. }
  509. WARN_ON(num_connectors == 0);
  510. return false;
  511. }
  512. /*
  513. * Platform specific helpers to calculate the port PLL loopback- (clock.m),
  514. * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
  515. * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
  516. * The helpers' return value is the rate of the clock that is fed to the
  517. * display engine's pipe which can be the above fast dot clock rate or a
  518. * divided-down version of it.
  519. */
  520. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  521. static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
  522. {
  523. clock->m = clock->m2 + 2;
  524. clock->p = clock->p1 * clock->p2;
  525. if (WARN_ON(clock->n == 0 || clock->p == 0))
  526. return 0;
  527. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  528. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  529. return clock->dot;
  530. }
  531. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  532. {
  533. return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  534. }
  535. static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
  536. {
  537. clock->m = i9xx_dpll_compute_m(clock);
  538. clock->p = clock->p1 * clock->p2;
  539. if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
  540. return 0;
  541. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
  542. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  543. return clock->dot;
  544. }
  545. static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
  546. {
  547. clock->m = clock->m1 * clock->m2;
  548. clock->p = clock->p1 * clock->p2;
  549. if (WARN_ON(clock->n == 0 || clock->p == 0))
  550. return 0;
  551. clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  552. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  553. return clock->dot / 5;
  554. }
  555. int chv_calc_dpll_params(int refclk, struct dpll *clock)
  556. {
  557. clock->m = clock->m1 * clock->m2;
  558. clock->p = clock->p1 * clock->p2;
  559. if (WARN_ON(clock->n == 0 || clock->p == 0))
  560. return 0;
  561. clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
  562. clock->n << 22);
  563. clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  564. return clock->dot / 5;
  565. }
  566. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  567. /**
  568. * Returns whether the given set of divisors are valid for a given refclk with
  569. * the given connectors.
  570. */
  571. static bool intel_PLL_is_valid(struct drm_device *dev,
  572. const struct intel_limit *limit,
  573. const struct dpll *clock)
  574. {
  575. if (clock->n < limit->n.min || limit->n.max < clock->n)
  576. INTELPllInvalid("n out of range\n");
  577. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  578. INTELPllInvalid("p1 out of range\n");
  579. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  580. INTELPllInvalid("m2 out of range\n");
  581. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  582. INTELPllInvalid("m1 out of range\n");
  583. if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
  584. !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
  585. if (clock->m1 <= clock->m2)
  586. INTELPllInvalid("m1 <= m2\n");
  587. if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
  588. if (clock->p < limit->p.min || limit->p.max < clock->p)
  589. INTELPllInvalid("p out of range\n");
  590. if (clock->m < limit->m.min || limit->m.max < clock->m)
  591. INTELPllInvalid("m out of range\n");
  592. }
  593. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  594. INTELPllInvalid("vco out of range\n");
  595. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  596. * connector, etc., rather than just a single range.
  597. */
  598. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  599. INTELPllInvalid("dot out of range\n");
  600. return true;
  601. }
  602. static int
  603. i9xx_select_p2_div(const struct intel_limit *limit,
  604. const struct intel_crtc_state *crtc_state,
  605. int target)
  606. {
  607. struct drm_device *dev = crtc_state->base.crtc->dev;
  608. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  609. /*
  610. * For LVDS just rely on its current settings for dual-channel.
  611. * We haven't figured out how to reliably set up different
  612. * single/dual channel state, if we even can.
  613. */
  614. if (intel_is_dual_link_lvds(dev))
  615. return limit->p2.p2_fast;
  616. else
  617. return limit->p2.p2_slow;
  618. } else {
  619. if (target < limit->p2.dot_limit)
  620. return limit->p2.p2_slow;
  621. else
  622. return limit->p2.p2_fast;
  623. }
  624. }
  625. /*
  626. * Returns a set of divisors for the desired target clock with the given
  627. * refclk, or FALSE. The returned values represent the clock equation:
  628. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  629. *
  630. * Target and reference clocks are specified in kHz.
  631. *
  632. * If match_clock is provided, then best_clock P divider must match the P
  633. * divider from @match_clock used for LVDS downclocking.
  634. */
  635. static bool
  636. i9xx_find_best_dpll(const struct intel_limit *limit,
  637. struct intel_crtc_state *crtc_state,
  638. int target, int refclk, struct dpll *match_clock,
  639. struct dpll *best_clock)
  640. {
  641. struct drm_device *dev = crtc_state->base.crtc->dev;
  642. struct dpll clock;
  643. int err = target;
  644. memset(best_clock, 0, sizeof(*best_clock));
  645. clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  646. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  647. clock.m1++) {
  648. for (clock.m2 = limit->m2.min;
  649. clock.m2 <= limit->m2.max; clock.m2++) {
  650. if (clock.m2 >= clock.m1)
  651. break;
  652. for (clock.n = limit->n.min;
  653. clock.n <= limit->n.max; clock.n++) {
  654. for (clock.p1 = limit->p1.min;
  655. clock.p1 <= limit->p1.max; clock.p1++) {
  656. int this_err;
  657. i9xx_calc_dpll_params(refclk, &clock);
  658. if (!intel_PLL_is_valid(dev, limit,
  659. &clock))
  660. continue;
  661. if (match_clock &&
  662. clock.p != match_clock->p)
  663. continue;
  664. this_err = abs(clock.dot - target);
  665. if (this_err < err) {
  666. *best_clock = clock;
  667. err = this_err;
  668. }
  669. }
  670. }
  671. }
  672. }
  673. return (err != target);
  674. }
  675. /*
  676. * Returns a set of divisors for the desired target clock with the given
  677. * refclk, or FALSE. The returned values represent the clock equation:
  678. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  679. *
  680. * Target and reference clocks are specified in kHz.
  681. *
  682. * If match_clock is provided, then best_clock P divider must match the P
  683. * divider from @match_clock used for LVDS downclocking.
  684. */
  685. static bool
  686. pnv_find_best_dpll(const struct intel_limit *limit,
  687. struct intel_crtc_state *crtc_state,
  688. int target, int refclk, struct dpll *match_clock,
  689. struct dpll *best_clock)
  690. {
  691. struct drm_device *dev = crtc_state->base.crtc->dev;
  692. struct dpll clock;
  693. int err = target;
  694. memset(best_clock, 0, sizeof(*best_clock));
  695. clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  696. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  697. clock.m1++) {
  698. for (clock.m2 = limit->m2.min;
  699. clock.m2 <= limit->m2.max; clock.m2++) {
  700. for (clock.n = limit->n.min;
  701. clock.n <= limit->n.max; clock.n++) {
  702. for (clock.p1 = limit->p1.min;
  703. clock.p1 <= limit->p1.max; clock.p1++) {
  704. int this_err;
  705. pnv_calc_dpll_params(refclk, &clock);
  706. if (!intel_PLL_is_valid(dev, limit,
  707. &clock))
  708. continue;
  709. if (match_clock &&
  710. clock.p != match_clock->p)
  711. continue;
  712. this_err = abs(clock.dot - target);
  713. if (this_err < err) {
  714. *best_clock = clock;
  715. err = this_err;
  716. }
  717. }
  718. }
  719. }
  720. }
  721. return (err != target);
  722. }
  723. /*
  724. * Returns a set of divisors for the desired target clock with the given
  725. * refclk, or FALSE. The returned values represent the clock equation:
  726. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  727. *
  728. * Target and reference clocks are specified in kHz.
  729. *
  730. * If match_clock is provided, then best_clock P divider must match the P
  731. * divider from @match_clock used for LVDS downclocking.
  732. */
  733. static bool
  734. g4x_find_best_dpll(const struct intel_limit *limit,
  735. struct intel_crtc_state *crtc_state,
  736. int target, int refclk, struct dpll *match_clock,
  737. struct dpll *best_clock)
  738. {
  739. struct drm_device *dev = crtc_state->base.crtc->dev;
  740. struct dpll clock;
  741. int max_n;
  742. bool found = false;
  743. /* approximately equals target * 0.00585 */
  744. int err_most = (target >> 8) + (target >> 9);
  745. memset(best_clock, 0, sizeof(*best_clock));
  746. clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  747. max_n = limit->n.max;
  748. /* based on hardware requirement, prefer smaller n to precision */
  749. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  750. /* based on hardware requirement, prefere larger m1,m2 */
  751. for (clock.m1 = limit->m1.max;
  752. clock.m1 >= limit->m1.min; clock.m1--) {
  753. for (clock.m2 = limit->m2.max;
  754. clock.m2 >= limit->m2.min; clock.m2--) {
  755. for (clock.p1 = limit->p1.max;
  756. clock.p1 >= limit->p1.min; clock.p1--) {
  757. int this_err;
  758. i9xx_calc_dpll_params(refclk, &clock);
  759. if (!intel_PLL_is_valid(dev, limit,
  760. &clock))
  761. continue;
  762. this_err = abs(clock.dot - target);
  763. if (this_err < err_most) {
  764. *best_clock = clock;
  765. err_most = this_err;
  766. max_n = clock.n;
  767. found = true;
  768. }
  769. }
  770. }
  771. }
  772. }
  773. return found;
  774. }
  775. /*
  776. * Check if the calculated PLL configuration is more optimal compared to the
  777. * best configuration and error found so far. Return the calculated error.
  778. */
  779. static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
  780. const struct dpll *calculated_clock,
  781. const struct dpll *best_clock,
  782. unsigned int best_error_ppm,
  783. unsigned int *error_ppm)
  784. {
  785. /*
  786. * For CHV ignore the error and consider only the P value.
  787. * Prefer a bigger P value based on HW requirements.
  788. */
  789. if (IS_CHERRYVIEW(dev)) {
  790. *error_ppm = 0;
  791. return calculated_clock->p > best_clock->p;
  792. }
  793. if (WARN_ON_ONCE(!target_freq))
  794. return false;
  795. *error_ppm = div_u64(1000000ULL *
  796. abs(target_freq - calculated_clock->dot),
  797. target_freq);
  798. /*
  799. * Prefer a better P value over a better (smaller) error if the error
  800. * is small. Ensure this preference for future configurations too by
  801. * setting the error to 0.
  802. */
  803. if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
  804. *error_ppm = 0;
  805. return true;
  806. }
  807. return *error_ppm + 10 < best_error_ppm;
  808. }
  809. /*
  810. * Returns a set of divisors for the desired target clock with the given
  811. * refclk, or FALSE. The returned values represent the clock equation:
  812. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  813. */
  814. static bool
  815. vlv_find_best_dpll(const struct intel_limit *limit,
  816. struct intel_crtc_state *crtc_state,
  817. int target, int refclk, struct dpll *match_clock,
  818. struct dpll *best_clock)
  819. {
  820. struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
  821. struct drm_device *dev = crtc->base.dev;
  822. struct dpll clock;
  823. unsigned int bestppm = 1000000;
  824. /* min update 19.2 MHz */
  825. int max_n = min(limit->n.max, refclk / 19200);
  826. bool found = false;
  827. target *= 5; /* fast clock */
  828. memset(best_clock, 0, sizeof(*best_clock));
  829. /* based on hardware requirement, prefer smaller n to precision */
  830. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  831. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  832. for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
  833. clock.p2 -= clock.p2 > 10 ? 2 : 1) {
  834. clock.p = clock.p1 * clock.p2;
  835. /* based on hardware requirement, prefer bigger m1,m2 values */
  836. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  837. unsigned int ppm;
  838. clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
  839. refclk * clock.m1);
  840. vlv_calc_dpll_params(refclk, &clock);
  841. if (!intel_PLL_is_valid(dev, limit,
  842. &clock))
  843. continue;
  844. if (!vlv_PLL_is_optimal(dev, target,
  845. &clock,
  846. best_clock,
  847. bestppm, &ppm))
  848. continue;
  849. *best_clock = clock;
  850. bestppm = ppm;
  851. found = true;
  852. }
  853. }
  854. }
  855. }
  856. return found;
  857. }
  858. /*
  859. * Returns a set of divisors for the desired target clock with the given
  860. * refclk, or FALSE. The returned values represent the clock equation:
  861. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  862. */
  863. static bool
  864. chv_find_best_dpll(const struct intel_limit *limit,
  865. struct intel_crtc_state *crtc_state,
  866. int target, int refclk, struct dpll *match_clock,
  867. struct dpll *best_clock)
  868. {
  869. struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
  870. struct drm_device *dev = crtc->base.dev;
  871. unsigned int best_error_ppm;
  872. struct dpll clock;
  873. uint64_t m2;
  874. int found = false;
  875. memset(best_clock, 0, sizeof(*best_clock));
  876. best_error_ppm = 1000000;
  877. /*
  878. * Based on hardware doc, the n always set to 1, and m1 always
  879. * set to 2. If requires to support 200Mhz refclk, we need to
  880. * revisit this because n may not 1 anymore.
  881. */
  882. clock.n = 1, clock.m1 = 2;
  883. target *= 5; /* fast clock */
  884. for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  885. for (clock.p2 = limit->p2.p2_fast;
  886. clock.p2 >= limit->p2.p2_slow;
  887. clock.p2 -= clock.p2 > 10 ? 2 : 1) {
  888. unsigned int error_ppm;
  889. clock.p = clock.p1 * clock.p2;
  890. m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
  891. clock.n) << 22, refclk * clock.m1);
  892. if (m2 > INT_MAX/clock.m1)
  893. continue;
  894. clock.m2 = m2;
  895. chv_calc_dpll_params(refclk, &clock);
  896. if (!intel_PLL_is_valid(dev, limit, &clock))
  897. continue;
  898. if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
  899. best_error_ppm, &error_ppm))
  900. continue;
  901. *best_clock = clock;
  902. best_error_ppm = error_ppm;
  903. found = true;
  904. }
  905. }
  906. return found;
  907. }
  908. bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
  909. struct dpll *best_clock)
  910. {
  911. int refclk = 100000;
  912. const struct intel_limit *limit = &intel_limits_bxt;
  913. return chv_find_best_dpll(limit, crtc_state,
  914. target_clock, refclk, NULL, best_clock);
  915. }
  916. bool intel_crtc_active(struct drm_crtc *crtc)
  917. {
  918. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  919. /* Be paranoid as we can arrive here with only partial
  920. * state retrieved from the hardware during setup.
  921. *
  922. * We can ditch the adjusted_mode.crtc_clock check as soon
  923. * as Haswell has gained clock readout/fastboot support.
  924. *
  925. * We can ditch the crtc->primary->fb check as soon as we can
  926. * properly reconstruct framebuffers.
  927. *
  928. * FIXME: The intel_crtc->active here should be switched to
  929. * crtc->state->active once we have proper CRTC states wired up
  930. * for atomic.
  931. */
  932. return intel_crtc->active && crtc->primary->state->fb &&
  933. intel_crtc->config->base.adjusted_mode.crtc_clock;
  934. }
  935. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  936. enum pipe pipe)
  937. {
  938. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  939. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  940. return intel_crtc->config->cpu_transcoder;
  941. }
  942. static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
  943. {
  944. struct drm_i915_private *dev_priv = dev->dev_private;
  945. i915_reg_t reg = PIPEDSL(pipe);
  946. u32 line1, line2;
  947. u32 line_mask;
  948. if (IS_GEN2(dev))
  949. line_mask = DSL_LINEMASK_GEN2;
  950. else
  951. line_mask = DSL_LINEMASK_GEN3;
  952. line1 = I915_READ(reg) & line_mask;
  953. msleep(5);
  954. line2 = I915_READ(reg) & line_mask;
  955. return line1 == line2;
  956. }
  957. /*
  958. * intel_wait_for_pipe_off - wait for pipe to turn off
  959. * @crtc: crtc whose pipe to wait for
  960. *
  961. * After disabling a pipe, we can't wait for vblank in the usual way,
  962. * spinning on the vblank interrupt status bit, since we won't actually
  963. * see an interrupt when the pipe is disabled.
  964. *
  965. * On Gen4 and above:
  966. * wait for the pipe register state bit to turn off
  967. *
  968. * Otherwise:
  969. * wait for the display line value to settle (it usually
  970. * ends up stopping at the start of the next frame).
  971. *
  972. */
  973. static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
  974. {
  975. struct drm_device *dev = crtc->base.dev;
  976. struct drm_i915_private *dev_priv = dev->dev_private;
  977. enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  978. enum pipe pipe = crtc->pipe;
  979. if (INTEL_INFO(dev)->gen >= 4) {
  980. i915_reg_t reg = PIPECONF(cpu_transcoder);
  981. /* Wait for the Pipe State to go off */
  982. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  983. 100))
  984. WARN(1, "pipe_off wait timed out\n");
  985. } else {
  986. /* Wait for the display line to settle */
  987. if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
  988. WARN(1, "pipe_off wait timed out\n");
  989. }
  990. }
  991. /* Only for pre-ILK configs */
  992. void assert_pll(struct drm_i915_private *dev_priv,
  993. enum pipe pipe, bool state)
  994. {
  995. u32 val;
  996. bool cur_state;
  997. val = I915_READ(DPLL(pipe));
  998. cur_state = !!(val & DPLL_VCO_ENABLE);
  999. I915_STATE_WARN(cur_state != state,
  1000. "PLL state assertion failure (expected %s, current %s)\n",
  1001. onoff(state), onoff(cur_state));
  1002. }
  1003. /* XXX: the dsi pll is shared between MIPI DSI ports */
  1004. void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
  1005. {
  1006. u32 val;
  1007. bool cur_state;
  1008. mutex_lock(&dev_priv->sb_lock);
  1009. val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
  1010. mutex_unlock(&dev_priv->sb_lock);
  1011. cur_state = val & DSI_PLL_VCO_EN;
  1012. I915_STATE_WARN(cur_state != state,
  1013. "DSI PLL state assertion failure (expected %s, current %s)\n",
  1014. onoff(state), onoff(cur_state));
  1015. }
  1016. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  1017. enum pipe pipe, bool state)
  1018. {
  1019. bool cur_state;
  1020. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1021. pipe);
  1022. if (HAS_DDI(dev_priv)) {
  1023. /* DDI does not have a specific FDI_TX register */
  1024. u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  1025. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  1026. } else {
  1027. u32 val = I915_READ(FDI_TX_CTL(pipe));
  1028. cur_state = !!(val & FDI_TX_ENABLE);
  1029. }
  1030. I915_STATE_WARN(cur_state != state,
  1031. "FDI TX state assertion failure (expected %s, current %s)\n",
  1032. onoff(state), onoff(cur_state));
  1033. }
  1034. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1035. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1036. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1037. enum pipe pipe, bool state)
  1038. {
  1039. u32 val;
  1040. bool cur_state;
  1041. val = I915_READ(FDI_RX_CTL(pipe));
  1042. cur_state = !!(val & FDI_RX_ENABLE);
  1043. I915_STATE_WARN(cur_state != state,
  1044. "FDI RX state assertion failure (expected %s, current %s)\n",
  1045. onoff(state), onoff(cur_state));
  1046. }
  1047. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1048. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1049. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1050. enum pipe pipe)
  1051. {
  1052. u32 val;
  1053. /* ILK FDI PLL is always enabled */
  1054. if (IS_GEN5(dev_priv))
  1055. return;
  1056. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1057. if (HAS_DDI(dev_priv))
  1058. return;
  1059. val = I915_READ(FDI_TX_CTL(pipe));
  1060. I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1061. }
  1062. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1063. enum pipe pipe, bool state)
  1064. {
  1065. u32 val;
  1066. bool cur_state;
  1067. val = I915_READ(FDI_RX_CTL(pipe));
  1068. cur_state = !!(val & FDI_RX_PLL_ENABLE);
  1069. I915_STATE_WARN(cur_state != state,
  1070. "FDI RX PLL assertion failure (expected %s, current %s)\n",
  1071. onoff(state), onoff(cur_state));
  1072. }
  1073. void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1074. enum pipe pipe)
  1075. {
  1076. struct drm_device *dev = dev_priv->dev;
  1077. i915_reg_t pp_reg;
  1078. u32 val;
  1079. enum pipe panel_pipe = PIPE_A;
  1080. bool locked = true;
  1081. if (WARN_ON(HAS_DDI(dev)))
  1082. return;
  1083. if (HAS_PCH_SPLIT(dev)) {
  1084. u32 port_sel;
  1085. pp_reg = PCH_PP_CONTROL;
  1086. port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
  1087. if (port_sel == PANEL_PORT_SELECT_LVDS &&
  1088. I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
  1089. panel_pipe = PIPE_B;
  1090. /* XXX: else fix for eDP */
  1091. } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  1092. /* presumably write lock depends on pipe, not port select */
  1093. pp_reg = VLV_PIPE_PP_CONTROL(pipe);
  1094. panel_pipe = pipe;
  1095. } else {
  1096. pp_reg = PP_CONTROL;
  1097. if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
  1098. panel_pipe = PIPE_B;
  1099. }
  1100. val = I915_READ(pp_reg);
  1101. if (!(val & PANEL_POWER_ON) ||
  1102. ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
  1103. locked = false;
  1104. I915_STATE_WARN(panel_pipe == pipe && locked,
  1105. "panel assertion failure, pipe %c regs locked\n",
  1106. pipe_name(pipe));
  1107. }
  1108. static void assert_cursor(struct drm_i915_private *dev_priv,
  1109. enum pipe pipe, bool state)
  1110. {
  1111. struct drm_device *dev = dev_priv->dev;
  1112. bool cur_state;
  1113. if (IS_845G(dev) || IS_I865G(dev))
  1114. cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
  1115. else
  1116. cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
  1117. I915_STATE_WARN(cur_state != state,
  1118. "cursor on pipe %c assertion failure (expected %s, current %s)\n",
  1119. pipe_name(pipe), onoff(state), onoff(cur_state));
  1120. }
  1121. #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
  1122. #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
  1123. void assert_pipe(struct drm_i915_private *dev_priv,
  1124. enum pipe pipe, bool state)
  1125. {
  1126. bool cur_state;
  1127. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1128. pipe);
  1129. enum intel_display_power_domain power_domain;
  1130. /* if we need the pipe quirk it must be always on */
  1131. if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  1132. (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  1133. state = true;
  1134. power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
  1135. if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
  1136. u32 val = I915_READ(PIPECONF(cpu_transcoder));
  1137. cur_state = !!(val & PIPECONF_ENABLE);
  1138. intel_display_power_put(dev_priv, power_domain);
  1139. } else {
  1140. cur_state = false;
  1141. }
  1142. I915_STATE_WARN(cur_state != state,
  1143. "pipe %c assertion failure (expected %s, current %s)\n",
  1144. pipe_name(pipe), onoff(state), onoff(cur_state));
  1145. }
  1146. static void assert_plane(struct drm_i915_private *dev_priv,
  1147. enum plane plane, bool state)
  1148. {
  1149. u32 val;
  1150. bool cur_state;
  1151. val = I915_READ(DSPCNTR(plane));
  1152. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1153. I915_STATE_WARN(cur_state != state,
  1154. "plane %c assertion failure (expected %s, current %s)\n",
  1155. plane_name(plane), onoff(state), onoff(cur_state));
  1156. }
  1157. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1158. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1159. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1160. enum pipe pipe)
  1161. {
  1162. struct drm_device *dev = dev_priv->dev;
  1163. int i;
  1164. /* Primary planes are fixed to pipes on gen4+ */
  1165. if (INTEL_INFO(dev)->gen >= 4) {
  1166. u32 val = I915_READ(DSPCNTR(pipe));
  1167. I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
  1168. "plane %c assertion failure, should be disabled but not\n",
  1169. plane_name(pipe));
  1170. return;
  1171. }
  1172. /* Need to check both planes against the pipe */
  1173. for_each_pipe(dev_priv, i) {
  1174. u32 val = I915_READ(DSPCNTR(i));
  1175. enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1176. DISPPLANE_SEL_PIPE_SHIFT;
  1177. I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1178. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1179. plane_name(i), pipe_name(pipe));
  1180. }
  1181. }
  1182. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1183. enum pipe pipe)
  1184. {
  1185. struct drm_device *dev = dev_priv->dev;
  1186. int sprite;
  1187. if (INTEL_INFO(dev)->gen >= 9) {
  1188. for_each_sprite(dev_priv, pipe, sprite) {
  1189. u32 val = I915_READ(PLANE_CTL(pipe, sprite));
  1190. I915_STATE_WARN(val & PLANE_CTL_ENABLE,
  1191. "plane %d assertion failure, should be off on pipe %c but is still active\n",
  1192. sprite, pipe_name(pipe));
  1193. }
  1194. } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  1195. for_each_sprite(dev_priv, pipe, sprite) {
  1196. u32 val = I915_READ(SPCNTR(pipe, sprite));
  1197. I915_STATE_WARN(val & SP_ENABLE,
  1198. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1199. sprite_name(pipe, sprite), pipe_name(pipe));
  1200. }
  1201. } else if (INTEL_INFO(dev)->gen >= 7) {
  1202. u32 val = I915_READ(SPRCTL(pipe));
  1203. I915_STATE_WARN(val & SPRITE_ENABLE,
  1204. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1205. plane_name(pipe), pipe_name(pipe));
  1206. } else if (INTEL_INFO(dev)->gen >= 5) {
  1207. u32 val = I915_READ(DVSCNTR(pipe));
  1208. I915_STATE_WARN(val & DVS_ENABLE,
  1209. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1210. plane_name(pipe), pipe_name(pipe));
  1211. }
  1212. }
  1213. static void assert_vblank_disabled(struct drm_crtc *crtc)
  1214. {
  1215. if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
  1216. drm_crtc_vblank_put(crtc);
  1217. }
  1218. void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1219. enum pipe pipe)
  1220. {
  1221. u32 val;
  1222. bool enabled;
  1223. val = I915_READ(PCH_TRANSCONF(pipe));
  1224. enabled = !!(val & TRANS_ENABLE);
  1225. I915_STATE_WARN(enabled,
  1226. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1227. pipe_name(pipe));
  1228. }
  1229. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1230. enum pipe pipe, u32 port_sel, u32 val)
  1231. {
  1232. if ((val & DP_PORT_EN) == 0)
  1233. return false;
  1234. if (HAS_PCH_CPT(dev_priv)) {
  1235. u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
  1236. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1237. return false;
  1238. } else if (IS_CHERRYVIEW(dev_priv)) {
  1239. if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
  1240. return false;
  1241. } else {
  1242. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1243. return false;
  1244. }
  1245. return true;
  1246. }
  1247. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1248. enum pipe pipe, u32 val)
  1249. {
  1250. if ((val & SDVO_ENABLE) == 0)
  1251. return false;
  1252. if (HAS_PCH_CPT(dev_priv)) {
  1253. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1254. return false;
  1255. } else if (IS_CHERRYVIEW(dev_priv)) {
  1256. if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
  1257. return false;
  1258. } else {
  1259. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1260. return false;
  1261. }
  1262. return true;
  1263. }
  1264. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1265. enum pipe pipe, u32 val)
  1266. {
  1267. if ((val & LVDS_PORT_EN) == 0)
  1268. return false;
  1269. if (HAS_PCH_CPT(dev_priv)) {
  1270. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1271. return false;
  1272. } else {
  1273. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1274. return false;
  1275. }
  1276. return true;
  1277. }
  1278. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1279. enum pipe pipe, u32 val)
  1280. {
  1281. if ((val & ADPA_DAC_ENABLE) == 0)
  1282. return false;
  1283. if (HAS_PCH_CPT(dev_priv)) {
  1284. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1285. return false;
  1286. } else {
  1287. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1288. return false;
  1289. }
  1290. return true;
  1291. }
  1292. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1293. enum pipe pipe, i915_reg_t reg,
  1294. u32 port_sel)
  1295. {
  1296. u32 val = I915_READ(reg);
  1297. I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1298. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1299. i915_mmio_reg_offset(reg), pipe_name(pipe));
  1300. I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
  1301. && (val & DP_PIPEB_SELECT),
  1302. "IBX PCH dp port still using transcoder B\n");
  1303. }
  1304. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1305. enum pipe pipe, i915_reg_t reg)
  1306. {
  1307. u32 val = I915_READ(reg);
  1308. I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1309. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1310. i915_mmio_reg_offset(reg), pipe_name(pipe));
  1311. I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
  1312. && (val & SDVO_PIPE_B_SELECT),
  1313. "IBX PCH hdmi port still using transcoder B\n");
  1314. }
  1315. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1316. enum pipe pipe)
  1317. {
  1318. u32 val;
  1319. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1320. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1321. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1322. val = I915_READ(PCH_ADPA);
  1323. I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1324. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1325. pipe_name(pipe));
  1326. val = I915_READ(PCH_LVDS);
  1327. I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1328. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1329. pipe_name(pipe));
  1330. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1331. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1332. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1333. }
  1334. static void _vlv_enable_pll(struct intel_crtc *crtc,
  1335. const struct intel_crtc_state *pipe_config)
  1336. {
  1337. struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1338. enum pipe pipe = crtc->pipe;
  1339. I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
  1340. POSTING_READ(DPLL(pipe));
  1341. udelay(150);
  1342. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1343. DRM_ERROR("DPLL %d failed to lock\n", pipe);
  1344. }
  1345. static void vlv_enable_pll(struct intel_crtc *crtc,
  1346. const struct intel_crtc_state *pipe_config)
  1347. {
  1348. struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1349. enum pipe pipe = crtc->pipe;
  1350. assert_pipe_disabled(dev_priv, pipe);
  1351. /* PLL is protected by panel, make sure we can write it */
  1352. assert_panel_unlocked(dev_priv, pipe);
  1353. if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
  1354. _vlv_enable_pll(crtc, pipe_config);
  1355. I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
  1356. POSTING_READ(DPLL_MD(pipe));
  1357. }
  1358. static void _chv_enable_pll(struct intel_crtc *crtc,
  1359. const struct intel_crtc_state *pipe_config)
  1360. {
  1361. struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1362. enum pipe pipe = crtc->pipe;
  1363. enum dpio_channel port = vlv_pipe_to_channel(pipe);
  1364. u32 tmp;
  1365. mutex_lock(&dev_priv->sb_lock);
  1366. /* Enable back the 10bit clock to display controller */
  1367. tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
  1368. tmp |= DPIO_DCLKP_EN;
  1369. vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
  1370. mutex_unlock(&dev_priv->sb_lock);
  1371. /*
  1372. * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
  1373. */
  1374. udelay(1);
  1375. /* Enable PLL */
  1376. I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
  1377. /* Check PLL is locked */
  1378. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1379. DRM_ERROR("PLL %d failed to lock\n", pipe);
  1380. }
  1381. static void chv_enable_pll(struct intel_crtc *crtc,
  1382. const struct intel_crtc_state *pipe_config)
  1383. {
  1384. struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1385. enum pipe pipe = crtc->pipe;
  1386. assert_pipe_disabled(dev_priv, pipe);
  1387. /* PLL is protected by panel, make sure we can write it */
  1388. assert_panel_unlocked(dev_priv, pipe);
  1389. if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
  1390. _chv_enable_pll(crtc, pipe_config);
  1391. if (pipe != PIPE_A) {
  1392. /*
  1393. * WaPixelRepeatModeFixForC0:chv
  1394. *
  1395. * DPLLCMD is AWOL. Use chicken bits to propagate
  1396. * the value from DPLLBMD to either pipe B or C.
  1397. */
  1398. I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
  1399. I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
  1400. I915_WRITE(CBR4_VLV, 0);
  1401. dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
  1402. /*
  1403. * DPLLB VGA mode also seems to cause problems.
  1404. * We should always have it disabled.
  1405. */
  1406. WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
  1407. } else {
  1408. I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
  1409. POSTING_READ(DPLL_MD(pipe));
  1410. }
  1411. }
  1412. static int intel_num_dvo_pipes(struct drm_device *dev)
  1413. {
  1414. struct intel_crtc *crtc;
  1415. int count = 0;
  1416. for_each_intel_crtc(dev, crtc)
  1417. count += crtc->base.state->active &&
  1418. intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
  1419. return count;
  1420. }
  1421. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1422. {
  1423. struct drm_device *dev = crtc->base.dev;
  1424. struct drm_i915_private *dev_priv = dev->dev_private;
  1425. i915_reg_t reg = DPLL(crtc->pipe);
  1426. u32 dpll = crtc->config->dpll_hw_state.dpll;
  1427. assert_pipe_disabled(dev_priv, crtc->pipe);
  1428. /* PLL is protected by panel, make sure we can write it */
  1429. if (IS_MOBILE(dev) && !IS_I830(dev))
  1430. assert_panel_unlocked(dev_priv, crtc->pipe);
  1431. /* Enable DVO 2x clock on both PLLs if necessary */
  1432. if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
  1433. /*
  1434. * It appears to be important that we don't enable this
  1435. * for the current pipe before otherwise configuring the
  1436. * PLL. No idea how this should be handled if multiple
  1437. * DVO outputs are enabled simultaneosly.
  1438. */
  1439. dpll |= DPLL_DVO_2X_MODE;
  1440. I915_WRITE(DPLL(!crtc->pipe),
  1441. I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
  1442. }
  1443. /*
  1444. * Apparently we need to have VGA mode enabled prior to changing
  1445. * the P1/P2 dividers. Otherwise the DPLL will keep using the old
  1446. * dividers, even though the register value does change.
  1447. */
  1448. I915_WRITE(reg, 0);
  1449. I915_WRITE(reg, dpll);
  1450. /* Wait for the clocks to stabilize. */
  1451. POSTING_READ(reg);
  1452. udelay(150);
  1453. if (INTEL_INFO(dev)->gen >= 4) {
  1454. I915_WRITE(DPLL_MD(crtc->pipe),
  1455. crtc->config->dpll_hw_state.dpll_md);
  1456. } else {
  1457. /* The pixel multiplier can only be updated once the
  1458. * DPLL is enabled and the clocks are stable.
  1459. *
  1460. * So write it again.
  1461. */
  1462. I915_WRITE(reg, dpll);
  1463. }
  1464. /* We do this three times for luck */
  1465. I915_WRITE(reg, dpll);
  1466. POSTING_READ(reg);
  1467. udelay(150); /* wait for warmup */
  1468. I915_WRITE(reg, dpll);
  1469. POSTING_READ(reg);
  1470. udelay(150); /* wait for warmup */
  1471. I915_WRITE(reg, dpll);
  1472. POSTING_READ(reg);
  1473. udelay(150); /* wait for warmup */
  1474. }
  1475. /**
  1476. * i9xx_disable_pll - disable a PLL
  1477. * @dev_priv: i915 private structure
  1478. * @pipe: pipe PLL to disable
  1479. *
  1480. * Disable the PLL for @pipe, making sure the pipe is off first.
  1481. *
  1482. * Note! This is for pre-ILK only.
  1483. */
  1484. static void i9xx_disable_pll(struct intel_crtc *crtc)
  1485. {
  1486. struct drm_device *dev = crtc->base.dev;
  1487. struct drm_i915_private *dev_priv = dev->dev_private;
  1488. enum pipe pipe = crtc->pipe;
  1489. /* Disable DVO 2x clock on both PLLs if necessary */
  1490. if (IS_I830(dev) &&
  1491. intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
  1492. !intel_num_dvo_pipes(dev)) {
  1493. I915_WRITE(DPLL(PIPE_B),
  1494. I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
  1495. I915_WRITE(DPLL(PIPE_A),
  1496. I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
  1497. }
  1498. /* Don't disable pipe or pipe PLLs if needed */
  1499. if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  1500. (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  1501. return;
  1502. /* Make sure the pipe isn't still relying on us */
  1503. assert_pipe_disabled(dev_priv, pipe);
  1504. I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
  1505. POSTING_READ(DPLL(pipe));
  1506. }
  1507. static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1508. {
  1509. u32 val;
  1510. /* Make sure the pipe isn't still relying on us */
  1511. assert_pipe_disabled(dev_priv, pipe);
  1512. val = DPLL_INTEGRATED_REF_CLK_VLV |
  1513. DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
  1514. if (pipe != PIPE_A)
  1515. val |= DPLL_INTEGRATED_CRI_CLK_VLV;
  1516. I915_WRITE(DPLL(pipe), val);
  1517. POSTING_READ(DPLL(pipe));
  1518. }
  1519. static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1520. {
  1521. enum dpio_channel port = vlv_pipe_to_channel(pipe);
  1522. u32 val;
  1523. /* Make sure the pipe isn't still relying on us */
  1524. assert_pipe_disabled(dev_priv, pipe);
  1525. val = DPLL_SSC_REF_CLK_CHV |
  1526. DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
  1527. if (pipe != PIPE_A)
  1528. val |= DPLL_INTEGRATED_CRI_CLK_VLV;
  1529. I915_WRITE(DPLL(pipe), val);
  1530. POSTING_READ(DPLL(pipe));
  1531. mutex_lock(&dev_priv->sb_lock);
  1532. /* Disable 10bit clock to display controller */
  1533. val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
  1534. val &= ~DPIO_DCLKP_EN;
  1535. vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
  1536. mutex_unlock(&dev_priv->sb_lock);
  1537. }
  1538. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  1539. struct intel_digital_port *dport,
  1540. unsigned int expected_mask)
  1541. {
  1542. u32 port_mask;
  1543. i915_reg_t dpll_reg;
  1544. switch (dport->port) {
  1545. case PORT_B:
  1546. port_mask = DPLL_PORTB_READY_MASK;
  1547. dpll_reg = DPLL(0);
  1548. break;
  1549. case PORT_C:
  1550. port_mask = DPLL_PORTC_READY_MASK;
  1551. dpll_reg = DPLL(0);
  1552. expected_mask <<= 4;
  1553. break;
  1554. case PORT_D:
  1555. port_mask = DPLL_PORTD_READY_MASK;
  1556. dpll_reg = DPIO_PHY_STATUS;
  1557. break;
  1558. default:
  1559. BUG();
  1560. }
  1561. if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
  1562. WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
  1563. port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
  1564. }
  1565. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1566. enum pipe pipe)
  1567. {
  1568. struct drm_device *dev = dev_priv->dev;
  1569. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1570. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1571. i915_reg_t reg;
  1572. uint32_t val, pipeconf_val;
  1573. /* Make sure PCH DPLL is enabled */
  1574. assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
  1575. /* FDI must be feeding us bits for PCH ports */
  1576. assert_fdi_tx_enabled(dev_priv, pipe);
  1577. assert_fdi_rx_enabled(dev_priv, pipe);
  1578. if (HAS_PCH_CPT(dev)) {
  1579. /* Workaround: Set the timing override bit before enabling the
  1580. * pch transcoder. */
  1581. reg = TRANS_CHICKEN2(pipe);
  1582. val = I915_READ(reg);
  1583. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1584. I915_WRITE(reg, val);
  1585. }
  1586. reg = PCH_TRANSCONF(pipe);
  1587. val = I915_READ(reg);
  1588. pipeconf_val = I915_READ(PIPECONF(pipe));
  1589. if (HAS_PCH_IBX(dev_priv)) {
  1590. /*
  1591. * Make the BPC in transcoder be consistent with
  1592. * that in pipeconf reg. For HDMI we must use 8bpc
  1593. * here for both 8bpc and 12bpc.
  1594. */
  1595. val &= ~PIPECONF_BPC_MASK;
  1596. if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
  1597. val |= PIPECONF_8BPC;
  1598. else
  1599. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1600. }
  1601. val &= ~TRANS_INTERLACE_MASK;
  1602. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1603. if (HAS_PCH_IBX(dev_priv) &&
  1604. intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  1605. val |= TRANS_LEGACY_INTERLACED_ILK;
  1606. else
  1607. val |= TRANS_INTERLACED;
  1608. else
  1609. val |= TRANS_PROGRESSIVE;
  1610. I915_WRITE(reg, val | TRANS_ENABLE);
  1611. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1612. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1613. }
  1614. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1615. enum transcoder cpu_transcoder)
  1616. {
  1617. u32 val, pipeconf_val;
  1618. /* FDI must be feeding us bits for PCH ports */
  1619. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1620. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1621. /* Workaround: set timing override bit. */
  1622. val = I915_READ(TRANS_CHICKEN2(PIPE_A));
  1623. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1624. I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
  1625. val = TRANS_ENABLE;
  1626. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1627. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1628. PIPECONF_INTERLACED_ILK)
  1629. val |= TRANS_INTERLACED;
  1630. else
  1631. val |= TRANS_PROGRESSIVE;
  1632. I915_WRITE(LPT_TRANSCONF, val);
  1633. if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1634. DRM_ERROR("Failed to enable PCH transcoder\n");
  1635. }
  1636. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1637. enum pipe pipe)
  1638. {
  1639. struct drm_device *dev = dev_priv->dev;
  1640. i915_reg_t reg;
  1641. uint32_t val;
  1642. /* FDI relies on the transcoder */
  1643. assert_fdi_tx_disabled(dev_priv, pipe);
  1644. assert_fdi_rx_disabled(dev_priv, pipe);
  1645. /* Ports must be off as well */
  1646. assert_pch_ports_disabled(dev_priv, pipe);
  1647. reg = PCH_TRANSCONF(pipe);
  1648. val = I915_READ(reg);
  1649. val &= ~TRANS_ENABLE;
  1650. I915_WRITE(reg, val);
  1651. /* wait for PCH transcoder off, transcoder state */
  1652. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1653. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1654. if (HAS_PCH_CPT(dev)) {
  1655. /* Workaround: Clear the timing override chicken bit again. */
  1656. reg = TRANS_CHICKEN2(pipe);
  1657. val = I915_READ(reg);
  1658. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1659. I915_WRITE(reg, val);
  1660. }
  1661. }
  1662. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1663. {
  1664. u32 val;
  1665. val = I915_READ(LPT_TRANSCONF);
  1666. val &= ~TRANS_ENABLE;
  1667. I915_WRITE(LPT_TRANSCONF, val);
  1668. /* wait for PCH transcoder off, transcoder state */
  1669. if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1670. DRM_ERROR("Failed to disable PCH transcoder\n");
  1671. /* Workaround: clear timing override bit. */
  1672. val = I915_READ(TRANS_CHICKEN2(PIPE_A));
  1673. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1674. I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
  1675. }
  1676. /**
  1677. * intel_enable_pipe - enable a pipe, asserting requirements
  1678. * @crtc: crtc responsible for the pipe
  1679. *
  1680. * Enable @crtc's pipe, making sure that various hardware specific requirements
  1681. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1682. */
  1683. static void intel_enable_pipe(struct intel_crtc *crtc)
  1684. {
  1685. struct drm_device *dev = crtc->base.dev;
  1686. struct drm_i915_private *dev_priv = dev->dev_private;
  1687. enum pipe pipe = crtc->pipe;
  1688. enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  1689. enum pipe pch_transcoder;
  1690. i915_reg_t reg;
  1691. u32 val;
  1692. DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
  1693. assert_planes_disabled(dev_priv, pipe);
  1694. assert_cursor_disabled(dev_priv, pipe);
  1695. assert_sprites_disabled(dev_priv, pipe);
  1696. if (HAS_PCH_LPT(dev_priv))
  1697. pch_transcoder = TRANSCODER_A;
  1698. else
  1699. pch_transcoder = pipe;
  1700. /*
  1701. * A pipe without a PLL won't actually be able to drive bits from
  1702. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1703. * need the check.
  1704. */
  1705. if (HAS_GMCH_DISPLAY(dev_priv))
  1706. if (crtc->config->has_dsi_encoder)
  1707. assert_dsi_pll_enabled(dev_priv);
  1708. else
  1709. assert_pll_enabled(dev_priv, pipe);
  1710. else {
  1711. if (crtc->config->has_pch_encoder) {
  1712. /* if driving the PCH, we need FDI enabled */
  1713. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1714. assert_fdi_tx_pll_enabled(dev_priv,
  1715. (enum pipe) cpu_transcoder);
  1716. }
  1717. /* FIXME: assert CPU port conditions for SNB+ */
  1718. }
  1719. reg = PIPECONF(cpu_transcoder);
  1720. val = I915_READ(reg);
  1721. if (val & PIPECONF_ENABLE) {
  1722. WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  1723. (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
  1724. return;
  1725. }
  1726. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1727. POSTING_READ(reg);
  1728. /*
  1729. * Until the pipe starts DSL will read as 0, which would cause
  1730. * an apparent vblank timestamp jump, which messes up also the
  1731. * frame count when it's derived from the timestamps. So let's
  1732. * wait for the pipe to start properly before we call
  1733. * drm_crtc_vblank_on()
  1734. */
  1735. if (dev->max_vblank_count == 0 &&
  1736. wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
  1737. DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
  1738. }
  1739. /**
  1740. * intel_disable_pipe - disable a pipe, asserting requirements
  1741. * @crtc: crtc whose pipes is to be disabled
  1742. *
  1743. * Disable the pipe of @crtc, making sure that various hardware
  1744. * specific requirements are met, if applicable, e.g. plane
  1745. * disabled, panel fitter off, etc.
  1746. *
  1747. * Will wait until the pipe has shut down before returning.
  1748. */
  1749. static void intel_disable_pipe(struct intel_crtc *crtc)
  1750. {
  1751. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1752. enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  1753. enum pipe pipe = crtc->pipe;
  1754. i915_reg_t reg;
  1755. u32 val;
  1756. DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
  1757. /*
  1758. * Make sure planes won't keep trying to pump pixels to us,
  1759. * or we might hang the display.
  1760. */
  1761. assert_planes_disabled(dev_priv, pipe);
  1762. assert_cursor_disabled(dev_priv, pipe);
  1763. assert_sprites_disabled(dev_priv, pipe);
  1764. reg = PIPECONF(cpu_transcoder);
  1765. val = I915_READ(reg);
  1766. if ((val & PIPECONF_ENABLE) == 0)
  1767. return;
  1768. /*
  1769. * Double wide has implications for planes
  1770. * so best keep it disabled when not needed.
  1771. */
  1772. if (crtc->config->double_wide)
  1773. val &= ~PIPECONF_DOUBLE_WIDE;
  1774. /* Don't disable pipe or pipe PLLs if needed */
  1775. if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
  1776. !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  1777. val &= ~PIPECONF_ENABLE;
  1778. I915_WRITE(reg, val);
  1779. if ((val & PIPECONF_ENABLE) == 0)
  1780. intel_wait_for_pipe_off(crtc);
  1781. }
  1782. static bool need_vtd_wa(struct drm_device *dev)
  1783. {
  1784. #ifdef CONFIG_INTEL_IOMMU
  1785. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1786. return true;
  1787. #endif
  1788. return false;
  1789. }
  1790. static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
  1791. {
  1792. return IS_GEN2(dev_priv) ? 2048 : 4096;
  1793. }
  1794. static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
  1795. uint64_t fb_modifier, unsigned int cpp)
  1796. {
  1797. switch (fb_modifier) {
  1798. case DRM_FORMAT_MOD_NONE:
  1799. return cpp;
  1800. case I915_FORMAT_MOD_X_TILED:
  1801. if (IS_GEN2(dev_priv))
  1802. return 128;
  1803. else
  1804. return 512;
  1805. case I915_FORMAT_MOD_Y_TILED:
  1806. if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
  1807. return 128;
  1808. else
  1809. return 512;
  1810. case I915_FORMAT_MOD_Yf_TILED:
  1811. switch (cpp) {
  1812. case 1:
  1813. return 64;
  1814. case 2:
  1815. case 4:
  1816. return 128;
  1817. case 8:
  1818. case 16:
  1819. return 256;
  1820. default:
  1821. MISSING_CASE(cpp);
  1822. return cpp;
  1823. }
  1824. break;
  1825. default:
  1826. MISSING_CASE(fb_modifier);
  1827. return cpp;
  1828. }
  1829. }
  1830. unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
  1831. uint64_t fb_modifier, unsigned int cpp)
  1832. {
  1833. if (fb_modifier == DRM_FORMAT_MOD_NONE)
  1834. return 1;
  1835. else
  1836. return intel_tile_size(dev_priv) /
  1837. intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
  1838. }
  1839. /* Return the tile dimensions in pixel units */
  1840. static void intel_tile_dims(const struct drm_i915_private *dev_priv,
  1841. unsigned int *tile_width,
  1842. unsigned int *tile_height,
  1843. uint64_t fb_modifier,
  1844. unsigned int cpp)
  1845. {
  1846. unsigned int tile_width_bytes =
  1847. intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
  1848. *tile_width = tile_width_bytes / cpp;
  1849. *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
  1850. }
  1851. unsigned int
  1852. intel_fb_align_height(struct drm_device *dev, unsigned int height,
  1853. uint32_t pixel_format, uint64_t fb_modifier)
  1854. {
  1855. unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
  1856. unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
  1857. return ALIGN(height, tile_height);
  1858. }
  1859. unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
  1860. {
  1861. unsigned int size = 0;
  1862. int i;
  1863. for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
  1864. size += rot_info->plane[i].width * rot_info->plane[i].height;
  1865. return size;
  1866. }
  1867. static void
  1868. intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
  1869. const struct drm_framebuffer *fb,
  1870. unsigned int rotation)
  1871. {
  1872. if (intel_rotation_90_or_270(rotation)) {
  1873. *view = i915_ggtt_view_rotated;
  1874. view->params.rotated = to_intel_framebuffer(fb)->rot_info;
  1875. } else {
  1876. *view = i915_ggtt_view_normal;
  1877. }
  1878. }
  1879. static void
  1880. intel_fill_fb_info(struct drm_i915_private *dev_priv,
  1881. struct drm_framebuffer *fb)
  1882. {
  1883. struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
  1884. unsigned int tile_size, tile_width, tile_height, cpp;
  1885. tile_size = intel_tile_size(dev_priv);
  1886. cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  1887. intel_tile_dims(dev_priv, &tile_width, &tile_height,
  1888. fb->modifier[0], cpp);
  1889. info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
  1890. info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
  1891. if (info->pixel_format == DRM_FORMAT_NV12) {
  1892. cpp = drm_format_plane_cpp(fb->pixel_format, 1);
  1893. intel_tile_dims(dev_priv, &tile_width, &tile_height,
  1894. fb->modifier[1], cpp);
  1895. info->uv_offset = fb->offsets[1];
  1896. info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
  1897. info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
  1898. }
  1899. }
  1900. static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
  1901. {
  1902. if (INTEL_INFO(dev_priv)->gen >= 9)
  1903. return 256 * 1024;
  1904. else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
  1905. IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
  1906. return 128 * 1024;
  1907. else if (INTEL_INFO(dev_priv)->gen >= 4)
  1908. return 4 * 1024;
  1909. else
  1910. return 0;
  1911. }
  1912. static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
  1913. uint64_t fb_modifier)
  1914. {
  1915. switch (fb_modifier) {
  1916. case DRM_FORMAT_MOD_NONE:
  1917. return intel_linear_alignment(dev_priv);
  1918. case I915_FORMAT_MOD_X_TILED:
  1919. if (INTEL_INFO(dev_priv)->gen >= 9)
  1920. return 256 * 1024;
  1921. return 0;
  1922. case I915_FORMAT_MOD_Y_TILED:
  1923. case I915_FORMAT_MOD_Yf_TILED:
  1924. return 1 * 1024 * 1024;
  1925. default:
  1926. MISSING_CASE(fb_modifier);
  1927. return 0;
  1928. }
  1929. }
  1930. int
  1931. intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
  1932. unsigned int rotation)
  1933. {
  1934. struct drm_device *dev = fb->dev;
  1935. struct drm_i915_private *dev_priv = dev->dev_private;
  1936. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  1937. struct i915_ggtt_view view;
  1938. u32 alignment;
  1939. int ret;
  1940. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  1941. alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
  1942. intel_fill_fb_ggtt_view(&view, fb, rotation);
  1943. /* Note that the w/a also requires 64 PTE of padding following the
  1944. * bo. We currently fill all unused PTE with the shadow page and so
  1945. * we should always have valid PTE following the scanout preventing
  1946. * the VT-d warning.
  1947. */
  1948. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1949. alignment = 256 * 1024;
  1950. /*
  1951. * Global gtt pte registers are special registers which actually forward
  1952. * writes to a chunk of system memory. Which means that there is no risk
  1953. * that the register values disappear as soon as we call
  1954. * intel_runtime_pm_put(), so it is correct to wrap only the
  1955. * pin/unpin/fence and not more.
  1956. */
  1957. intel_runtime_pm_get(dev_priv);
  1958. ret = i915_gem_object_pin_to_display_plane(obj, alignment,
  1959. &view);
  1960. if (ret)
  1961. goto err_pm;
  1962. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1963. * fence, whereas 965+ only requires a fence if using
  1964. * framebuffer compression. For simplicity, we always install
  1965. * a fence as the cost is not that onerous.
  1966. */
  1967. if (view.type == I915_GGTT_VIEW_NORMAL) {
  1968. ret = i915_gem_object_get_fence(obj);
  1969. if (ret == -EDEADLK) {
  1970. /*
  1971. * -EDEADLK means there are no free fences
  1972. * no pending flips.
  1973. *
  1974. * This is propagated to atomic, but it uses
  1975. * -EDEADLK to force a locking recovery, so
  1976. * change the returned error to -EBUSY.
  1977. */
  1978. ret = -EBUSY;
  1979. goto err_unpin;
  1980. } else if (ret)
  1981. goto err_unpin;
  1982. i915_gem_object_pin_fence(obj);
  1983. }
  1984. intel_runtime_pm_put(dev_priv);
  1985. return 0;
  1986. err_unpin:
  1987. i915_gem_object_unpin_from_display_plane(obj, &view);
  1988. err_pm:
  1989. intel_runtime_pm_put(dev_priv);
  1990. return ret;
  1991. }
  1992. void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
  1993. {
  1994. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  1995. struct i915_ggtt_view view;
  1996. WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
  1997. intel_fill_fb_ggtt_view(&view, fb, rotation);
  1998. if (view.type == I915_GGTT_VIEW_NORMAL)
  1999. i915_gem_object_unpin_fence(obj);
  2000. i915_gem_object_unpin_from_display_plane(obj, &view);
  2001. }
  2002. /*
  2003. * Adjust the tile offset by moving the difference into
  2004. * the x/y offsets.
  2005. *
  2006. * Input tile dimensions and pitch must already be
  2007. * rotated to match x and y, and in pixel units.
  2008. */
  2009. static u32 intel_adjust_tile_offset(int *x, int *y,
  2010. unsigned int tile_width,
  2011. unsigned int tile_height,
  2012. unsigned int tile_size,
  2013. unsigned int pitch_tiles,
  2014. u32 old_offset,
  2015. u32 new_offset)
  2016. {
  2017. unsigned int tiles;
  2018. WARN_ON(old_offset & (tile_size - 1));
  2019. WARN_ON(new_offset & (tile_size - 1));
  2020. WARN_ON(new_offset > old_offset);
  2021. tiles = (old_offset - new_offset) / tile_size;
  2022. *y += tiles / pitch_tiles * tile_height;
  2023. *x += tiles % pitch_tiles * tile_width;
  2024. return new_offset;
  2025. }
  2026. /*
  2027. * Computes the linear offset to the base tile and adjusts
  2028. * x, y. bytes per pixel is assumed to be a power-of-two.
  2029. *
  2030. * In the 90/270 rotated case, x and y are assumed
  2031. * to be already rotated to match the rotated GTT view, and
  2032. * pitch is the tile_height aligned framebuffer height.
  2033. */
  2034. u32 intel_compute_tile_offset(int *x, int *y,
  2035. const struct drm_framebuffer *fb, int plane,
  2036. unsigned int pitch,
  2037. unsigned int rotation)
  2038. {
  2039. const struct drm_i915_private *dev_priv = to_i915(fb->dev);
  2040. uint64_t fb_modifier = fb->modifier[plane];
  2041. unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
  2042. u32 offset, offset_aligned, alignment;
  2043. alignment = intel_surf_alignment(dev_priv, fb_modifier);
  2044. if (alignment)
  2045. alignment--;
  2046. if (fb_modifier != DRM_FORMAT_MOD_NONE) {
  2047. unsigned int tile_size, tile_width, tile_height;
  2048. unsigned int tile_rows, tiles, pitch_tiles;
  2049. tile_size = intel_tile_size(dev_priv);
  2050. intel_tile_dims(dev_priv, &tile_width, &tile_height,
  2051. fb_modifier, cpp);
  2052. if (intel_rotation_90_or_270(rotation)) {
  2053. pitch_tiles = pitch / tile_height;
  2054. swap(tile_width, tile_height);
  2055. } else {
  2056. pitch_tiles = pitch / (tile_width * cpp);
  2057. }
  2058. tile_rows = *y / tile_height;
  2059. *y %= tile_height;
  2060. tiles = *x / tile_width;
  2061. *x %= tile_width;
  2062. offset = (tile_rows * pitch_tiles + tiles) * tile_size;
  2063. offset_aligned = offset & ~alignment;
  2064. intel_adjust_tile_offset(x, y, tile_width, tile_height,
  2065. tile_size, pitch_tiles,
  2066. offset, offset_aligned);
  2067. } else {
  2068. offset = *y * pitch + *x * cpp;
  2069. offset_aligned = offset & ~alignment;
  2070. *y = (offset & alignment) / pitch;
  2071. *x = ((offset & alignment) - *y * pitch) / cpp;
  2072. }
  2073. return offset_aligned;
  2074. }
  2075. static int i9xx_format_to_fourcc(int format)
  2076. {
  2077. switch (format) {
  2078. case DISPPLANE_8BPP:
  2079. return DRM_FORMAT_C8;
  2080. case DISPPLANE_BGRX555:
  2081. return DRM_FORMAT_XRGB1555;
  2082. case DISPPLANE_BGRX565:
  2083. return DRM_FORMAT_RGB565;
  2084. default:
  2085. case DISPPLANE_BGRX888:
  2086. return DRM_FORMAT_XRGB8888;
  2087. case DISPPLANE_RGBX888:
  2088. return DRM_FORMAT_XBGR8888;
  2089. case DISPPLANE_BGRX101010:
  2090. return DRM_FORMAT_XRGB2101010;
  2091. case DISPPLANE_RGBX101010:
  2092. return DRM_FORMAT_XBGR2101010;
  2093. }
  2094. }
  2095. static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
  2096. {
  2097. switch (format) {
  2098. case PLANE_CTL_FORMAT_RGB_565:
  2099. return DRM_FORMAT_RGB565;
  2100. default:
  2101. case PLANE_CTL_FORMAT_XRGB_8888:
  2102. if (rgb_order) {
  2103. if (alpha)
  2104. return DRM_FORMAT_ABGR8888;
  2105. else
  2106. return DRM_FORMAT_XBGR8888;
  2107. } else {
  2108. if (alpha)
  2109. return DRM_FORMAT_ARGB8888;
  2110. else
  2111. return DRM_FORMAT_XRGB8888;
  2112. }
  2113. case PLANE_CTL_FORMAT_XRGB_2101010:
  2114. if (rgb_order)
  2115. return DRM_FORMAT_XBGR2101010;
  2116. else
  2117. return DRM_FORMAT_XRGB2101010;
  2118. }
  2119. }
  2120. static bool
  2121. intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
  2122. struct intel_initial_plane_config *plane_config)
  2123. {
  2124. struct drm_device *dev = crtc->base.dev;
  2125. struct drm_i915_private *dev_priv = to_i915(dev);
  2126. struct i915_ggtt *ggtt = &dev_priv->ggtt;
  2127. struct drm_i915_gem_object *obj = NULL;
  2128. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  2129. struct drm_framebuffer *fb = &plane_config->fb->base;
  2130. u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
  2131. u32 size_aligned = round_up(plane_config->base + plane_config->size,
  2132. PAGE_SIZE);
  2133. size_aligned -= base_aligned;
  2134. if (plane_config->size == 0)
  2135. return false;
  2136. /* If the FB is too big, just don't use it since fbdev is not very
  2137. * important and we should probably use that space with FBC or other
  2138. * features. */
  2139. if (size_aligned * 2 > ggtt->stolen_usable_size)
  2140. return false;
  2141. mutex_lock(&dev->struct_mutex);
  2142. obj = i915_gem_object_create_stolen_for_preallocated(dev,
  2143. base_aligned,
  2144. base_aligned,
  2145. size_aligned);
  2146. if (!obj) {
  2147. mutex_unlock(&dev->struct_mutex);
  2148. return false;
  2149. }
  2150. obj->tiling_mode = plane_config->tiling;
  2151. if (obj->tiling_mode == I915_TILING_X)
  2152. obj->stride = fb->pitches[0];
  2153. mode_cmd.pixel_format = fb->pixel_format;
  2154. mode_cmd.width = fb->width;
  2155. mode_cmd.height = fb->height;
  2156. mode_cmd.pitches[0] = fb->pitches[0];
  2157. mode_cmd.modifier[0] = fb->modifier[0];
  2158. mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
  2159. if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
  2160. &mode_cmd, obj)) {
  2161. DRM_DEBUG_KMS("intel fb init failed\n");
  2162. goto out_unref_obj;
  2163. }
  2164. mutex_unlock(&dev->struct_mutex);
  2165. DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
  2166. return true;
  2167. out_unref_obj:
  2168. drm_gem_object_unreference(&obj->base);
  2169. mutex_unlock(&dev->struct_mutex);
  2170. return false;
  2171. }
  2172. /* Update plane->state->fb to match plane->fb after driver-internal updates */
  2173. static void
  2174. update_state_fb(struct drm_plane *plane)
  2175. {
  2176. if (plane->fb == plane->state->fb)
  2177. return;
  2178. if (plane->state->fb)
  2179. drm_framebuffer_unreference(plane->state->fb);
  2180. plane->state->fb = plane->fb;
  2181. if (plane->state->fb)
  2182. drm_framebuffer_reference(plane->state->fb);
  2183. }
  2184. static void
  2185. intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
  2186. struct intel_initial_plane_config *plane_config)
  2187. {
  2188. struct drm_device *dev = intel_crtc->base.dev;
  2189. struct drm_i915_private *dev_priv = dev->dev_private;
  2190. struct drm_crtc *c;
  2191. struct intel_crtc *i;
  2192. struct drm_i915_gem_object *obj;
  2193. struct drm_plane *primary = intel_crtc->base.primary;
  2194. struct drm_plane_state *plane_state = primary->state;
  2195. struct drm_crtc_state *crtc_state = intel_crtc->base.state;
  2196. struct intel_plane *intel_plane = to_intel_plane(primary);
  2197. struct intel_plane_state *intel_state =
  2198. to_intel_plane_state(plane_state);
  2199. struct drm_framebuffer *fb;
  2200. if (!plane_config->fb)
  2201. return;
  2202. if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
  2203. fb = &plane_config->fb->base;
  2204. goto valid_fb;
  2205. }
  2206. kfree(plane_config->fb);
  2207. /*
  2208. * Failed to alloc the obj, check to see if we should share
  2209. * an fb with another CRTC instead
  2210. */
  2211. for_each_crtc(dev, c) {
  2212. i = to_intel_crtc(c);
  2213. if (c == &intel_crtc->base)
  2214. continue;
  2215. if (!i->active)
  2216. continue;
  2217. fb = c->primary->fb;
  2218. if (!fb)
  2219. continue;
  2220. obj = intel_fb_obj(fb);
  2221. if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
  2222. drm_framebuffer_reference(fb);
  2223. goto valid_fb;
  2224. }
  2225. }
  2226. /*
  2227. * We've failed to reconstruct the BIOS FB. Current display state
  2228. * indicates that the primary plane is visible, but has a NULL FB,
  2229. * which will lead to problems later if we don't fix it up. The
  2230. * simplest solution is to just disable the primary plane now and
  2231. * pretend the BIOS never had it enabled.
  2232. */
  2233. to_intel_plane_state(plane_state)->visible = false;
  2234. crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
  2235. intel_pre_disable_primary_noatomic(&intel_crtc->base);
  2236. intel_plane->disable_plane(primary, &intel_crtc->base);
  2237. return;
  2238. valid_fb:
  2239. plane_state->src_x = 0;
  2240. plane_state->src_y = 0;
  2241. plane_state->src_w = fb->width << 16;
  2242. plane_state->src_h = fb->height << 16;
  2243. plane_state->crtc_x = 0;
  2244. plane_state->crtc_y = 0;
  2245. plane_state->crtc_w = fb->width;
  2246. plane_state->crtc_h = fb->height;
  2247. intel_state->src.x1 = plane_state->src_x;
  2248. intel_state->src.y1 = plane_state->src_y;
  2249. intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
  2250. intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
  2251. intel_state->dst.x1 = plane_state->crtc_x;
  2252. intel_state->dst.y1 = plane_state->crtc_y;
  2253. intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
  2254. intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
  2255. obj = intel_fb_obj(fb);
  2256. if (obj->tiling_mode != I915_TILING_NONE)
  2257. dev_priv->preserve_bios_swizzle = true;
  2258. drm_framebuffer_reference(fb);
  2259. primary->fb = primary->state->fb = fb;
  2260. primary->crtc = primary->state->crtc = &intel_crtc->base;
  2261. intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
  2262. obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
  2263. }
  2264. static void i9xx_update_primary_plane(struct drm_plane *primary,
  2265. const struct intel_crtc_state *crtc_state,
  2266. const struct intel_plane_state *plane_state)
  2267. {
  2268. struct drm_device *dev = primary->dev;
  2269. struct drm_i915_private *dev_priv = dev->dev_private;
  2270. struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
  2271. struct drm_framebuffer *fb = plane_state->base.fb;
  2272. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  2273. int plane = intel_crtc->plane;
  2274. u32 linear_offset;
  2275. u32 dspcntr;
  2276. i915_reg_t reg = DSPCNTR(plane);
  2277. unsigned int rotation = plane_state->base.rotation;
  2278. int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  2279. int x = plane_state->src.x1 >> 16;
  2280. int y = plane_state->src.y1 >> 16;
  2281. dspcntr = DISPPLANE_GAMMA_ENABLE;
  2282. dspcntr |= DISPLAY_PLANE_ENABLE;
  2283. if (INTEL_INFO(dev)->gen < 4) {
  2284. if (intel_crtc->pipe == PIPE_B)
  2285. dspcntr |= DISPPLANE_SEL_PIPE_B;
  2286. /* pipesrc and dspsize control the size that is scaled from,
  2287. * which should always be the user's requested size.
  2288. */
  2289. I915_WRITE(DSPSIZE(plane),
  2290. ((crtc_state->pipe_src_h - 1) << 16) |
  2291. (crtc_state->pipe_src_w - 1));
  2292. I915_WRITE(DSPPOS(plane), 0);
  2293. } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
  2294. I915_WRITE(PRIMSIZE(plane),
  2295. ((crtc_state->pipe_src_h - 1) << 16) |
  2296. (crtc_state->pipe_src_w - 1));
  2297. I915_WRITE(PRIMPOS(plane), 0);
  2298. I915_WRITE(PRIMCNSTALPHA(plane), 0);
  2299. }
  2300. switch (fb->pixel_format) {
  2301. case DRM_FORMAT_C8:
  2302. dspcntr |= DISPPLANE_8BPP;
  2303. break;
  2304. case DRM_FORMAT_XRGB1555:
  2305. dspcntr |= DISPPLANE_BGRX555;
  2306. break;
  2307. case DRM_FORMAT_RGB565:
  2308. dspcntr |= DISPPLANE_BGRX565;
  2309. break;
  2310. case DRM_FORMAT_XRGB8888:
  2311. dspcntr |= DISPPLANE_BGRX888;
  2312. break;
  2313. case DRM_FORMAT_XBGR8888:
  2314. dspcntr |= DISPPLANE_RGBX888;
  2315. break;
  2316. case DRM_FORMAT_XRGB2101010:
  2317. dspcntr |= DISPPLANE_BGRX101010;
  2318. break;
  2319. case DRM_FORMAT_XBGR2101010:
  2320. dspcntr |= DISPPLANE_RGBX101010;
  2321. break;
  2322. default:
  2323. BUG();
  2324. }
  2325. if (INTEL_INFO(dev)->gen >= 4 &&
  2326. obj->tiling_mode != I915_TILING_NONE)
  2327. dspcntr |= DISPPLANE_TILED;
  2328. if (IS_G4X(dev))
  2329. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2330. linear_offset = y * fb->pitches[0] + x * cpp;
  2331. if (INTEL_INFO(dev)->gen >= 4) {
  2332. intel_crtc->dspaddr_offset =
  2333. intel_compute_tile_offset(&x, &y, fb, 0,
  2334. fb->pitches[0], rotation);
  2335. linear_offset -= intel_crtc->dspaddr_offset;
  2336. } else {
  2337. intel_crtc->dspaddr_offset = linear_offset;
  2338. }
  2339. if (rotation == BIT(DRM_ROTATE_180)) {
  2340. dspcntr |= DISPPLANE_ROTATE_180;
  2341. x += (crtc_state->pipe_src_w - 1);
  2342. y += (crtc_state->pipe_src_h - 1);
  2343. /* Finding the last pixel of the last line of the display
  2344. data and adding to linear_offset*/
  2345. linear_offset +=
  2346. (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
  2347. (crtc_state->pipe_src_w - 1) * cpp;
  2348. }
  2349. intel_crtc->adjusted_x = x;
  2350. intel_crtc->adjusted_y = y;
  2351. I915_WRITE(reg, dspcntr);
  2352. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2353. if (INTEL_INFO(dev)->gen >= 4) {
  2354. I915_WRITE(DSPSURF(plane),
  2355. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2356. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2357. I915_WRITE(DSPLINOFF(plane), linear_offset);
  2358. } else
  2359. I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  2360. POSTING_READ(reg);
  2361. }
  2362. static void i9xx_disable_primary_plane(struct drm_plane *primary,
  2363. struct drm_crtc *crtc)
  2364. {
  2365. struct drm_device *dev = crtc->dev;
  2366. struct drm_i915_private *dev_priv = dev->dev_private;
  2367. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2368. int plane = intel_crtc->plane;
  2369. I915_WRITE(DSPCNTR(plane), 0);
  2370. if (INTEL_INFO(dev_priv)->gen >= 4)
  2371. I915_WRITE(DSPSURF(plane), 0);
  2372. else
  2373. I915_WRITE(DSPADDR(plane), 0);
  2374. POSTING_READ(DSPCNTR(plane));
  2375. }
  2376. static void ironlake_update_primary_plane(struct drm_plane *primary,
  2377. const struct intel_crtc_state *crtc_state,
  2378. const struct intel_plane_state *plane_state)
  2379. {
  2380. struct drm_device *dev = primary->dev;
  2381. struct drm_i915_private *dev_priv = dev->dev_private;
  2382. struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
  2383. struct drm_framebuffer *fb = plane_state->base.fb;
  2384. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  2385. int plane = intel_crtc->plane;
  2386. u32 linear_offset;
  2387. u32 dspcntr;
  2388. i915_reg_t reg = DSPCNTR(plane);
  2389. unsigned int rotation = plane_state->base.rotation;
  2390. int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  2391. int x = plane_state->src.x1 >> 16;
  2392. int y = plane_state->src.y1 >> 16;
  2393. dspcntr = DISPPLANE_GAMMA_ENABLE;
  2394. dspcntr |= DISPLAY_PLANE_ENABLE;
  2395. if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  2396. dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
  2397. switch (fb->pixel_format) {
  2398. case DRM_FORMAT_C8:
  2399. dspcntr |= DISPPLANE_8BPP;
  2400. break;
  2401. case DRM_FORMAT_RGB565:
  2402. dspcntr |= DISPPLANE_BGRX565;
  2403. break;
  2404. case DRM_FORMAT_XRGB8888:
  2405. dspcntr |= DISPPLANE_BGRX888;
  2406. break;
  2407. case DRM_FORMAT_XBGR8888:
  2408. dspcntr |= DISPPLANE_RGBX888;
  2409. break;
  2410. case DRM_FORMAT_XRGB2101010:
  2411. dspcntr |= DISPPLANE_BGRX101010;
  2412. break;
  2413. case DRM_FORMAT_XBGR2101010:
  2414. dspcntr |= DISPPLANE_RGBX101010;
  2415. break;
  2416. default:
  2417. BUG();
  2418. }
  2419. if (obj->tiling_mode != I915_TILING_NONE)
  2420. dspcntr |= DISPPLANE_TILED;
  2421. if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
  2422. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2423. linear_offset = y * fb->pitches[0] + x * cpp;
  2424. intel_crtc->dspaddr_offset =
  2425. intel_compute_tile_offset(&x, &y, fb, 0,
  2426. fb->pitches[0], rotation);
  2427. linear_offset -= intel_crtc->dspaddr_offset;
  2428. if (rotation == BIT(DRM_ROTATE_180)) {
  2429. dspcntr |= DISPPLANE_ROTATE_180;
  2430. if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  2431. x += (crtc_state->pipe_src_w - 1);
  2432. y += (crtc_state->pipe_src_h - 1);
  2433. /* Finding the last pixel of the last line of the display
  2434. data and adding to linear_offset*/
  2435. linear_offset +=
  2436. (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
  2437. (crtc_state->pipe_src_w - 1) * cpp;
  2438. }
  2439. }
  2440. intel_crtc->adjusted_x = x;
  2441. intel_crtc->adjusted_y = y;
  2442. I915_WRITE(reg, dspcntr);
  2443. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2444. I915_WRITE(DSPSURF(plane),
  2445. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2446. if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  2447. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  2448. } else {
  2449. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2450. I915_WRITE(DSPLINOFF(plane), linear_offset);
  2451. }
  2452. POSTING_READ(reg);
  2453. }
  2454. u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
  2455. uint64_t fb_modifier, uint32_t pixel_format)
  2456. {
  2457. if (fb_modifier == DRM_FORMAT_MOD_NONE) {
  2458. return 64;
  2459. } else {
  2460. int cpp = drm_format_plane_cpp(pixel_format, 0);
  2461. return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
  2462. }
  2463. }
  2464. u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
  2465. struct drm_i915_gem_object *obj,
  2466. unsigned int plane)
  2467. {
  2468. struct i915_ggtt_view view;
  2469. struct i915_vma *vma;
  2470. u64 offset;
  2471. intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
  2472. intel_plane->base.state->rotation);
  2473. vma = i915_gem_obj_to_ggtt_view(obj, &view);
  2474. if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
  2475. view.type))
  2476. return -1;
  2477. offset = vma->node.start;
  2478. if (plane == 1) {
  2479. offset += vma->ggtt_view.params.rotated.uv_start_page *
  2480. PAGE_SIZE;
  2481. }
  2482. WARN_ON(upper_32_bits(offset));
  2483. return lower_32_bits(offset);
  2484. }
  2485. static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
  2486. {
  2487. struct drm_device *dev = intel_crtc->base.dev;
  2488. struct drm_i915_private *dev_priv = dev->dev_private;
  2489. I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
  2490. I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
  2491. I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
  2492. }
  2493. /*
  2494. * This function detaches (aka. unbinds) unused scalers in hardware
  2495. */
  2496. static void skl_detach_scalers(struct intel_crtc *intel_crtc)
  2497. {
  2498. struct intel_crtc_scaler_state *scaler_state;
  2499. int i;
  2500. scaler_state = &intel_crtc->config->scaler_state;
  2501. /* loop through and disable scalers that aren't in use */
  2502. for (i = 0; i < intel_crtc->num_scalers; i++) {
  2503. if (!scaler_state->scalers[i].in_use)
  2504. skl_detach_scaler(intel_crtc, i);
  2505. }
  2506. }
  2507. u32 skl_plane_ctl_format(uint32_t pixel_format)
  2508. {
  2509. switch (pixel_format) {
  2510. case DRM_FORMAT_C8:
  2511. return PLANE_CTL_FORMAT_INDEXED;
  2512. case DRM_FORMAT_RGB565:
  2513. return PLANE_CTL_FORMAT_RGB_565;
  2514. case DRM_FORMAT_XBGR8888:
  2515. return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
  2516. case DRM_FORMAT_XRGB8888:
  2517. return PLANE_CTL_FORMAT_XRGB_8888;
  2518. /*
  2519. * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
  2520. * to be already pre-multiplied. We need to add a knob (or a different
  2521. * DRM_FORMAT) for user-space to configure that.
  2522. */
  2523. case DRM_FORMAT_ABGR8888:
  2524. return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
  2525. PLANE_CTL_ALPHA_SW_PREMULTIPLY;
  2526. case DRM_FORMAT_ARGB8888:
  2527. return PLANE_CTL_FORMAT_XRGB_8888 |
  2528. PLANE_CTL_ALPHA_SW_PREMULTIPLY;
  2529. case DRM_FORMAT_XRGB2101010:
  2530. return PLANE_CTL_FORMAT_XRGB_2101010;
  2531. case DRM_FORMAT_XBGR2101010:
  2532. return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
  2533. case DRM_FORMAT_YUYV:
  2534. return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
  2535. case DRM_FORMAT_YVYU:
  2536. return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
  2537. case DRM_FORMAT_UYVY:
  2538. return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
  2539. case DRM_FORMAT_VYUY:
  2540. return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
  2541. default:
  2542. MISSING_CASE(pixel_format);
  2543. }
  2544. return 0;
  2545. }
  2546. u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
  2547. {
  2548. switch (fb_modifier) {
  2549. case DRM_FORMAT_MOD_NONE:
  2550. break;
  2551. case I915_FORMAT_MOD_X_TILED:
  2552. return PLANE_CTL_TILED_X;
  2553. case I915_FORMAT_MOD_Y_TILED:
  2554. return PLANE_CTL_TILED_Y;
  2555. case I915_FORMAT_MOD_Yf_TILED:
  2556. return PLANE_CTL_TILED_YF;
  2557. default:
  2558. MISSING_CASE(fb_modifier);
  2559. }
  2560. return 0;
  2561. }
  2562. u32 skl_plane_ctl_rotation(unsigned int rotation)
  2563. {
  2564. switch (rotation) {
  2565. case BIT(DRM_ROTATE_0):
  2566. break;
  2567. /*
  2568. * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
  2569. * while i915 HW rotation is clockwise, thats why this swapping.
  2570. */
  2571. case BIT(DRM_ROTATE_90):
  2572. return PLANE_CTL_ROTATE_270;
  2573. case BIT(DRM_ROTATE_180):
  2574. return PLANE_CTL_ROTATE_180;
  2575. case BIT(DRM_ROTATE_270):
  2576. return PLANE_CTL_ROTATE_90;
  2577. default:
  2578. MISSING_CASE(rotation);
  2579. }
  2580. return 0;
  2581. }
  2582. static void skylake_update_primary_plane(struct drm_plane *plane,
  2583. const struct intel_crtc_state *crtc_state,
  2584. const struct intel_plane_state *plane_state)
  2585. {
  2586. struct drm_device *dev = plane->dev;
  2587. struct drm_i915_private *dev_priv = dev->dev_private;
  2588. struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
  2589. struct drm_framebuffer *fb = plane_state->base.fb;
  2590. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  2591. int pipe = intel_crtc->pipe;
  2592. u32 plane_ctl, stride_div, stride;
  2593. u32 tile_height, plane_offset, plane_size;
  2594. unsigned int rotation = plane_state->base.rotation;
  2595. int x_offset, y_offset;
  2596. u32 surf_addr;
  2597. int scaler_id = plane_state->scaler_id;
  2598. int src_x = plane_state->src.x1 >> 16;
  2599. int src_y = plane_state->src.y1 >> 16;
  2600. int src_w = drm_rect_width(&plane_state->src) >> 16;
  2601. int src_h = drm_rect_height(&plane_state->src) >> 16;
  2602. int dst_x = plane_state->dst.x1;
  2603. int dst_y = plane_state->dst.y1;
  2604. int dst_w = drm_rect_width(&plane_state->dst);
  2605. int dst_h = drm_rect_height(&plane_state->dst);
  2606. plane_ctl = PLANE_CTL_ENABLE |
  2607. PLANE_CTL_PIPE_GAMMA_ENABLE |
  2608. PLANE_CTL_PIPE_CSC_ENABLE;
  2609. plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  2610. plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  2611. plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
  2612. plane_ctl |= skl_plane_ctl_rotation(rotation);
  2613. stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
  2614. fb->pixel_format);
  2615. surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
  2616. WARN_ON(drm_rect_width(&plane_state->src) == 0);
  2617. if (intel_rotation_90_or_270(rotation)) {
  2618. int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  2619. /* stride = Surface height in tiles */
  2620. tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
  2621. stride = DIV_ROUND_UP(fb->height, tile_height);
  2622. x_offset = stride * tile_height - src_y - src_h;
  2623. y_offset = src_x;
  2624. plane_size = (src_w - 1) << 16 | (src_h - 1);
  2625. } else {
  2626. stride = fb->pitches[0] / stride_div;
  2627. x_offset = src_x;
  2628. y_offset = src_y;
  2629. plane_size = (src_h - 1) << 16 | (src_w - 1);
  2630. }
  2631. plane_offset = y_offset << 16 | x_offset;
  2632. intel_crtc->adjusted_x = x_offset;
  2633. intel_crtc->adjusted_y = y_offset;
  2634. I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
  2635. I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
  2636. I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
  2637. I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
  2638. if (scaler_id >= 0) {
  2639. uint32_t ps_ctrl = 0;
  2640. WARN_ON(!dst_w || !dst_h);
  2641. ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
  2642. crtc_state->scaler_state.scalers[scaler_id].mode;
  2643. I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  2644. I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  2645. I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
  2646. I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
  2647. I915_WRITE(PLANE_POS(pipe, 0), 0);
  2648. } else {
  2649. I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
  2650. }
  2651. I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
  2652. POSTING_READ(PLANE_SURF(pipe, 0));
  2653. }
  2654. static void skylake_disable_primary_plane(struct drm_plane *primary,
  2655. struct drm_crtc *crtc)
  2656. {
  2657. struct drm_device *dev = crtc->dev;
  2658. struct drm_i915_private *dev_priv = dev->dev_private;
  2659. int pipe = to_intel_crtc(crtc)->pipe;
  2660. I915_WRITE(PLANE_CTL(pipe, 0), 0);
  2661. I915_WRITE(PLANE_SURF(pipe, 0), 0);
  2662. POSTING_READ(PLANE_SURF(pipe, 0));
  2663. }
  2664. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  2665. static int
  2666. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  2667. int x, int y, enum mode_set_atomic state)
  2668. {
  2669. /* Support for kgdboc is disabled, this needs a major rework. */
  2670. DRM_ERROR("legacy panic handler not supported any more.\n");
  2671. return -ENODEV;
  2672. }
  2673. static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
  2674. {
  2675. struct drm_crtc *crtc;
  2676. for_each_crtc(dev_priv->dev, crtc) {
  2677. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2678. enum plane plane = intel_crtc->plane;
  2679. intel_prepare_page_flip(dev_priv, plane);
  2680. intel_finish_page_flip_plane(dev_priv, plane);
  2681. }
  2682. }
  2683. static void intel_update_primary_planes(struct drm_device *dev)
  2684. {
  2685. struct drm_crtc *crtc;
  2686. for_each_crtc(dev, crtc) {
  2687. struct intel_plane *plane = to_intel_plane(crtc->primary);
  2688. struct intel_plane_state *plane_state;
  2689. drm_modeset_lock_crtc(crtc, &plane->base);
  2690. plane_state = to_intel_plane_state(plane->base.state);
  2691. if (plane_state->visible)
  2692. plane->update_plane(&plane->base,
  2693. to_intel_crtc_state(crtc->state),
  2694. plane_state);
  2695. drm_modeset_unlock_crtc(crtc);
  2696. }
  2697. }
  2698. void intel_prepare_reset(struct drm_i915_private *dev_priv)
  2699. {
  2700. /* no reset support for gen2 */
  2701. if (IS_GEN2(dev_priv))
  2702. return;
  2703. /* reset doesn't touch the display */
  2704. if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
  2705. return;
  2706. drm_modeset_lock_all(dev_priv->dev);
  2707. /*
  2708. * Disabling the crtcs gracefully seems nicer. Also the
  2709. * g33 docs say we should at least disable all the planes.
  2710. */
  2711. intel_display_suspend(dev_priv->dev);
  2712. }
  2713. void intel_finish_reset(struct drm_i915_private *dev_priv)
  2714. {
  2715. /*
  2716. * Flips in the rings will be nuked by the reset,
  2717. * so complete all pending flips so that user space
  2718. * will get its events and not get stuck.
  2719. */
  2720. intel_complete_page_flips(dev_priv);
  2721. /* no reset support for gen2 */
  2722. if (IS_GEN2(dev_priv))
  2723. return;
  2724. /* reset doesn't touch the display */
  2725. if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
  2726. /*
  2727. * Flips in the rings have been nuked by the reset,
  2728. * so update the base address of all primary
  2729. * planes to the the last fb to make sure we're
  2730. * showing the correct fb after a reset.
  2731. *
  2732. * FIXME: Atomic will make this obsolete since we won't schedule
  2733. * CS-based flips (which might get lost in gpu resets) any more.
  2734. */
  2735. intel_update_primary_planes(dev_priv->dev);
  2736. return;
  2737. }
  2738. /*
  2739. * The display has been reset as well,
  2740. * so need a full re-initialization.
  2741. */
  2742. intel_runtime_pm_disable_interrupts(dev_priv);
  2743. intel_runtime_pm_enable_interrupts(dev_priv);
  2744. intel_modeset_init_hw(dev_priv->dev);
  2745. spin_lock_irq(&dev_priv->irq_lock);
  2746. if (dev_priv->display.hpd_irq_setup)
  2747. dev_priv->display.hpd_irq_setup(dev_priv);
  2748. spin_unlock_irq(&dev_priv->irq_lock);
  2749. intel_display_resume(dev_priv->dev);
  2750. intel_hpd_init(dev_priv);
  2751. drm_modeset_unlock_all(dev_priv->dev);
  2752. }
  2753. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2754. {
  2755. struct drm_device *dev = crtc->dev;
  2756. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2757. unsigned reset_counter;
  2758. bool pending;
  2759. reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
  2760. if (intel_crtc->reset_counter != reset_counter)
  2761. return false;
  2762. spin_lock_irq(&dev->event_lock);
  2763. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2764. spin_unlock_irq(&dev->event_lock);
  2765. return pending;
  2766. }
  2767. static void intel_update_pipe_config(struct intel_crtc *crtc,
  2768. struct intel_crtc_state *old_crtc_state)
  2769. {
  2770. struct drm_device *dev = crtc->base.dev;
  2771. struct drm_i915_private *dev_priv = dev->dev_private;
  2772. struct intel_crtc_state *pipe_config =
  2773. to_intel_crtc_state(crtc->base.state);
  2774. /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
  2775. crtc->base.mode = crtc->base.state->mode;
  2776. DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
  2777. old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
  2778. pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  2779. /*
  2780. * Update pipe size and adjust fitter if needed: the reason for this is
  2781. * that in compute_mode_changes we check the native mode (not the pfit
  2782. * mode) to see if we can flip rather than do a full mode set. In the
  2783. * fastboot case, we'll flip, but if we don't update the pipesrc and
  2784. * pfit state, we'll end up with a big fb scanned out into the wrong
  2785. * sized surface.
  2786. */
  2787. I915_WRITE(PIPESRC(crtc->pipe),
  2788. ((pipe_config->pipe_src_w - 1) << 16) |
  2789. (pipe_config->pipe_src_h - 1));
  2790. /* on skylake this is done by detaching scalers */
  2791. if (INTEL_INFO(dev)->gen >= 9) {
  2792. skl_detach_scalers(crtc);
  2793. if (pipe_config->pch_pfit.enabled)
  2794. skylake_pfit_enable(crtc);
  2795. } else if (HAS_PCH_SPLIT(dev)) {
  2796. if (pipe_config->pch_pfit.enabled)
  2797. ironlake_pfit_enable(crtc);
  2798. else if (old_crtc_state->pch_pfit.enabled)
  2799. ironlake_pfit_disable(crtc, true);
  2800. }
  2801. }
  2802. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2803. {
  2804. struct drm_device *dev = crtc->dev;
  2805. struct drm_i915_private *dev_priv = dev->dev_private;
  2806. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2807. int pipe = intel_crtc->pipe;
  2808. i915_reg_t reg;
  2809. u32 temp;
  2810. /* enable normal train */
  2811. reg = FDI_TX_CTL(pipe);
  2812. temp = I915_READ(reg);
  2813. if (IS_IVYBRIDGE(dev)) {
  2814. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2815. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2816. } else {
  2817. temp &= ~FDI_LINK_TRAIN_NONE;
  2818. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2819. }
  2820. I915_WRITE(reg, temp);
  2821. reg = FDI_RX_CTL(pipe);
  2822. temp = I915_READ(reg);
  2823. if (HAS_PCH_CPT(dev)) {
  2824. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2825. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2826. } else {
  2827. temp &= ~FDI_LINK_TRAIN_NONE;
  2828. temp |= FDI_LINK_TRAIN_NONE;
  2829. }
  2830. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2831. /* wait one idle pattern time */
  2832. POSTING_READ(reg);
  2833. udelay(1000);
  2834. /* IVB wants error correction enabled */
  2835. if (IS_IVYBRIDGE(dev))
  2836. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2837. FDI_FE_ERRC_ENABLE);
  2838. }
  2839. /* The FDI link training functions for ILK/Ibexpeak. */
  2840. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2841. {
  2842. struct drm_device *dev = crtc->dev;
  2843. struct drm_i915_private *dev_priv = dev->dev_private;
  2844. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2845. int pipe = intel_crtc->pipe;
  2846. i915_reg_t reg;
  2847. u32 temp, tries;
  2848. /* FDI needs bits from pipe first */
  2849. assert_pipe_enabled(dev_priv, pipe);
  2850. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2851. for train result */
  2852. reg = FDI_RX_IMR(pipe);
  2853. temp = I915_READ(reg);
  2854. temp &= ~FDI_RX_SYMBOL_LOCK;
  2855. temp &= ~FDI_RX_BIT_LOCK;
  2856. I915_WRITE(reg, temp);
  2857. I915_READ(reg);
  2858. udelay(150);
  2859. /* enable CPU FDI TX and PCH FDI RX */
  2860. reg = FDI_TX_CTL(pipe);
  2861. temp = I915_READ(reg);
  2862. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2863. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  2864. temp &= ~FDI_LINK_TRAIN_NONE;
  2865. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2866. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2867. reg = FDI_RX_CTL(pipe);
  2868. temp = I915_READ(reg);
  2869. temp &= ~FDI_LINK_TRAIN_NONE;
  2870. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2871. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2872. POSTING_READ(reg);
  2873. udelay(150);
  2874. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2875. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2876. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2877. FDI_RX_PHASE_SYNC_POINTER_EN);
  2878. reg = FDI_RX_IIR(pipe);
  2879. for (tries = 0; tries < 5; tries++) {
  2880. temp = I915_READ(reg);
  2881. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2882. if ((temp & FDI_RX_BIT_LOCK)) {
  2883. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2884. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2885. break;
  2886. }
  2887. }
  2888. if (tries == 5)
  2889. DRM_ERROR("FDI train 1 fail!\n");
  2890. /* Train 2 */
  2891. reg = FDI_TX_CTL(pipe);
  2892. temp = I915_READ(reg);
  2893. temp &= ~FDI_LINK_TRAIN_NONE;
  2894. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2895. I915_WRITE(reg, temp);
  2896. reg = FDI_RX_CTL(pipe);
  2897. temp = I915_READ(reg);
  2898. temp &= ~FDI_LINK_TRAIN_NONE;
  2899. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2900. I915_WRITE(reg, temp);
  2901. POSTING_READ(reg);
  2902. udelay(150);
  2903. reg = FDI_RX_IIR(pipe);
  2904. for (tries = 0; tries < 5; tries++) {
  2905. temp = I915_READ(reg);
  2906. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2907. if (temp & FDI_RX_SYMBOL_LOCK) {
  2908. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2909. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2910. break;
  2911. }
  2912. }
  2913. if (tries == 5)
  2914. DRM_ERROR("FDI train 2 fail!\n");
  2915. DRM_DEBUG_KMS("FDI train done\n");
  2916. }
  2917. static const int snb_b_fdi_train_param[] = {
  2918. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2919. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2920. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2921. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2922. };
  2923. /* The FDI link training functions for SNB/Cougarpoint. */
  2924. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2925. {
  2926. struct drm_device *dev = crtc->dev;
  2927. struct drm_i915_private *dev_priv = dev->dev_private;
  2928. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2929. int pipe = intel_crtc->pipe;
  2930. i915_reg_t reg;
  2931. u32 temp, i, retry;
  2932. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2933. for train result */
  2934. reg = FDI_RX_IMR(pipe);
  2935. temp = I915_READ(reg);
  2936. temp &= ~FDI_RX_SYMBOL_LOCK;
  2937. temp &= ~FDI_RX_BIT_LOCK;
  2938. I915_WRITE(reg, temp);
  2939. POSTING_READ(reg);
  2940. udelay(150);
  2941. /* enable CPU FDI TX and PCH FDI RX */
  2942. reg = FDI_TX_CTL(pipe);
  2943. temp = I915_READ(reg);
  2944. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2945. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  2946. temp &= ~FDI_LINK_TRAIN_NONE;
  2947. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2948. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2949. /* SNB-B */
  2950. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2951. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2952. I915_WRITE(FDI_RX_MISC(pipe),
  2953. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2954. reg = FDI_RX_CTL(pipe);
  2955. temp = I915_READ(reg);
  2956. if (HAS_PCH_CPT(dev)) {
  2957. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2958. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2959. } else {
  2960. temp &= ~FDI_LINK_TRAIN_NONE;
  2961. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2962. }
  2963. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2964. POSTING_READ(reg);
  2965. udelay(150);
  2966. for (i = 0; i < 4; i++) {
  2967. reg = FDI_TX_CTL(pipe);
  2968. temp = I915_READ(reg);
  2969. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2970. temp |= snb_b_fdi_train_param[i];
  2971. I915_WRITE(reg, temp);
  2972. POSTING_READ(reg);
  2973. udelay(500);
  2974. for (retry = 0; retry < 5; retry++) {
  2975. reg = FDI_RX_IIR(pipe);
  2976. temp = I915_READ(reg);
  2977. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2978. if (temp & FDI_RX_BIT_LOCK) {
  2979. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2980. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2981. break;
  2982. }
  2983. udelay(50);
  2984. }
  2985. if (retry < 5)
  2986. break;
  2987. }
  2988. if (i == 4)
  2989. DRM_ERROR("FDI train 1 fail!\n");
  2990. /* Train 2 */
  2991. reg = FDI_TX_CTL(pipe);
  2992. temp = I915_READ(reg);
  2993. temp &= ~FDI_LINK_TRAIN_NONE;
  2994. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2995. if (IS_GEN6(dev)) {
  2996. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2997. /* SNB-B */
  2998. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2999. }
  3000. I915_WRITE(reg, temp);
  3001. reg = FDI_RX_CTL(pipe);
  3002. temp = I915_READ(reg);
  3003. if (HAS_PCH_CPT(dev)) {
  3004. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3005. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  3006. } else {
  3007. temp &= ~FDI_LINK_TRAIN_NONE;
  3008. temp |= FDI_LINK_TRAIN_PATTERN_2;
  3009. }
  3010. I915_WRITE(reg, temp);
  3011. POSTING_READ(reg);
  3012. udelay(150);
  3013. for (i = 0; i < 4; i++) {
  3014. reg = FDI_TX_CTL(pipe);
  3015. temp = I915_READ(reg);
  3016. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3017. temp |= snb_b_fdi_train_param[i];
  3018. I915_WRITE(reg, temp);
  3019. POSTING_READ(reg);
  3020. udelay(500);
  3021. for (retry = 0; retry < 5; retry++) {
  3022. reg = FDI_RX_IIR(pipe);
  3023. temp = I915_READ(reg);
  3024. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3025. if (temp & FDI_RX_SYMBOL_LOCK) {
  3026. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  3027. DRM_DEBUG_KMS("FDI train 2 done.\n");
  3028. break;
  3029. }
  3030. udelay(50);
  3031. }
  3032. if (retry < 5)
  3033. break;
  3034. }
  3035. if (i == 4)
  3036. DRM_ERROR("FDI train 2 fail!\n");
  3037. DRM_DEBUG_KMS("FDI train done.\n");
  3038. }
  3039. /* Manual link training for Ivy Bridge A0 parts */
  3040. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  3041. {
  3042. struct drm_device *dev = crtc->dev;
  3043. struct drm_i915_private *dev_priv = dev->dev_private;
  3044. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3045. int pipe = intel_crtc->pipe;
  3046. i915_reg_t reg;
  3047. u32 temp, i, j;
  3048. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  3049. for train result */
  3050. reg = FDI_RX_IMR(pipe);
  3051. temp = I915_READ(reg);
  3052. temp &= ~FDI_RX_SYMBOL_LOCK;
  3053. temp &= ~FDI_RX_BIT_LOCK;
  3054. I915_WRITE(reg, temp);
  3055. POSTING_READ(reg);
  3056. udelay(150);
  3057. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  3058. I915_READ(FDI_RX_IIR(pipe)));
  3059. /* Try each vswing and preemphasis setting twice before moving on */
  3060. for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  3061. /* disable first in case we need to retry */
  3062. reg = FDI_TX_CTL(pipe);
  3063. temp = I915_READ(reg);
  3064. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  3065. temp &= ~FDI_TX_ENABLE;
  3066. I915_WRITE(reg, temp);
  3067. reg = FDI_RX_CTL(pipe);
  3068. temp = I915_READ(reg);
  3069. temp &= ~FDI_LINK_TRAIN_AUTO;
  3070. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3071. temp &= ~FDI_RX_ENABLE;
  3072. I915_WRITE(reg, temp);
  3073. /* enable CPU FDI TX and PCH FDI RX */
  3074. reg = FDI_TX_CTL(pipe);
  3075. temp = I915_READ(reg);
  3076. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  3077. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3078. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  3079. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3080. temp |= snb_b_fdi_train_param[j/2];
  3081. temp |= FDI_COMPOSITE_SYNC;
  3082. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  3083. I915_WRITE(FDI_RX_MISC(pipe),
  3084. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  3085. reg = FDI_RX_CTL(pipe);
  3086. temp = I915_READ(reg);
  3087. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  3088. temp |= FDI_COMPOSITE_SYNC;
  3089. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  3090. POSTING_READ(reg);
  3091. udelay(1); /* should be 0.5us */
  3092. for (i = 0; i < 4; i++) {
  3093. reg = FDI_RX_IIR(pipe);
  3094. temp = I915_READ(reg);
  3095. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3096. if (temp & FDI_RX_BIT_LOCK ||
  3097. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  3098. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  3099. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  3100. i);
  3101. break;
  3102. }
  3103. udelay(1); /* should be 0.5us */
  3104. }
  3105. if (i == 4) {
  3106. DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  3107. continue;
  3108. }
  3109. /* Train 2 */
  3110. reg = FDI_TX_CTL(pipe);
  3111. temp = I915_READ(reg);
  3112. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  3113. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  3114. I915_WRITE(reg, temp);
  3115. reg = FDI_RX_CTL(pipe);
  3116. temp = I915_READ(reg);
  3117. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3118. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  3119. I915_WRITE(reg, temp);
  3120. POSTING_READ(reg);
  3121. udelay(2); /* should be 1.5us */
  3122. for (i = 0; i < 4; i++) {
  3123. reg = FDI_RX_IIR(pipe);
  3124. temp = I915_READ(reg);
  3125. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3126. if (temp & FDI_RX_SYMBOL_LOCK ||
  3127. (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  3128. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  3129. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  3130. i);
  3131. goto train_done;
  3132. }
  3133. udelay(2); /* should be 1.5us */
  3134. }
  3135. if (i == 4)
  3136. DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  3137. }
  3138. train_done:
  3139. DRM_DEBUG_KMS("FDI train done.\n");
  3140. }
  3141. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  3142. {
  3143. struct drm_device *dev = intel_crtc->base.dev;
  3144. struct drm_i915_private *dev_priv = dev->dev_private;
  3145. int pipe = intel_crtc->pipe;
  3146. i915_reg_t reg;
  3147. u32 temp;
  3148. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  3149. reg = FDI_RX_CTL(pipe);
  3150. temp = I915_READ(reg);
  3151. temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  3152. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3153. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3154. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  3155. POSTING_READ(reg);
  3156. udelay(200);
  3157. /* Switch from Rawclk to PCDclk */
  3158. temp = I915_READ(reg);
  3159. I915_WRITE(reg, temp | FDI_PCDCLK);
  3160. POSTING_READ(reg);
  3161. udelay(200);
  3162. /* Enable CPU FDI TX PLL, always on for Ironlake */
  3163. reg = FDI_TX_CTL(pipe);
  3164. temp = I915_READ(reg);
  3165. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  3166. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  3167. POSTING_READ(reg);
  3168. udelay(100);
  3169. }
  3170. }
  3171. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  3172. {
  3173. struct drm_device *dev = intel_crtc->base.dev;
  3174. struct drm_i915_private *dev_priv = dev->dev_private;
  3175. int pipe = intel_crtc->pipe;
  3176. i915_reg_t reg;
  3177. u32 temp;
  3178. /* Switch from PCDclk to Rawclk */
  3179. reg = FDI_RX_CTL(pipe);
  3180. temp = I915_READ(reg);
  3181. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  3182. /* Disable CPU FDI TX PLL */
  3183. reg = FDI_TX_CTL(pipe);
  3184. temp = I915_READ(reg);
  3185. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  3186. POSTING_READ(reg);
  3187. udelay(100);
  3188. reg = FDI_RX_CTL(pipe);
  3189. temp = I915_READ(reg);
  3190. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  3191. /* Wait for the clocks to turn off. */
  3192. POSTING_READ(reg);
  3193. udelay(100);
  3194. }
  3195. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  3196. {
  3197. struct drm_device *dev = crtc->dev;
  3198. struct drm_i915_private *dev_priv = dev->dev_private;
  3199. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3200. int pipe = intel_crtc->pipe;
  3201. i915_reg_t reg;
  3202. u32 temp;
  3203. /* disable CPU FDI tx and PCH FDI rx */
  3204. reg = FDI_TX_CTL(pipe);
  3205. temp = I915_READ(reg);
  3206. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  3207. POSTING_READ(reg);
  3208. reg = FDI_RX_CTL(pipe);
  3209. temp = I915_READ(reg);
  3210. temp &= ~(0x7 << 16);
  3211. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3212. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  3213. POSTING_READ(reg);
  3214. udelay(100);
  3215. /* Ironlake workaround, disable clock pointer after downing FDI */
  3216. if (HAS_PCH_IBX(dev))
  3217. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  3218. /* still set train pattern 1 */
  3219. reg = FDI_TX_CTL(pipe);
  3220. temp = I915_READ(reg);
  3221. temp &= ~FDI_LINK_TRAIN_NONE;
  3222. temp |= FDI_LINK_TRAIN_PATTERN_1;
  3223. I915_WRITE(reg, temp);
  3224. reg = FDI_RX_CTL(pipe);
  3225. temp = I915_READ(reg);
  3226. if (HAS_PCH_CPT(dev)) {
  3227. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3228. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  3229. } else {
  3230. temp &= ~FDI_LINK_TRAIN_NONE;
  3231. temp |= FDI_LINK_TRAIN_PATTERN_1;
  3232. }
  3233. /* BPC in FDI rx is consistent with that in PIPECONF */
  3234. temp &= ~(0x07 << 16);
  3235. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3236. I915_WRITE(reg, temp);
  3237. POSTING_READ(reg);
  3238. udelay(100);
  3239. }
  3240. bool intel_has_pending_fb_unpin(struct drm_device *dev)
  3241. {
  3242. struct intel_crtc *crtc;
  3243. /* Note that we don't need to be called with mode_config.lock here
  3244. * as our list of CRTC objects is static for the lifetime of the
  3245. * device and so cannot disappear as we iterate. Similarly, we can
  3246. * happily treat the predicates as racy, atomic checks as userspace
  3247. * cannot claim and pin a new fb without at least acquring the
  3248. * struct_mutex and so serialising with us.
  3249. */
  3250. for_each_intel_crtc(dev, crtc) {
  3251. if (atomic_read(&crtc->unpin_work_count) == 0)
  3252. continue;
  3253. if (crtc->unpin_work)
  3254. intel_wait_for_vblank(dev, crtc->pipe);
  3255. return true;
  3256. }
  3257. return false;
  3258. }
  3259. static void page_flip_completed(struct intel_crtc *intel_crtc)
  3260. {
  3261. struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
  3262. struct intel_unpin_work *work = intel_crtc->unpin_work;
  3263. /* ensure that the unpin work is consistent wrt ->pending. */
  3264. smp_rmb();
  3265. intel_crtc->unpin_work = NULL;
  3266. if (work->event)
  3267. drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
  3268. drm_crtc_vblank_put(&intel_crtc->base);
  3269. wake_up_all(&dev_priv->pending_flip_queue);
  3270. queue_work(dev_priv->wq, &work->work);
  3271. trace_i915_flip_complete(intel_crtc->plane,
  3272. work->pending_flip_obj);
  3273. }
  3274. static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  3275. {
  3276. struct drm_device *dev = crtc->dev;
  3277. struct drm_i915_private *dev_priv = dev->dev_private;
  3278. long ret;
  3279. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  3280. ret = wait_event_interruptible_timeout(
  3281. dev_priv->pending_flip_queue,
  3282. !intel_crtc_has_pending_flip(crtc),
  3283. 60*HZ);
  3284. if (ret < 0)
  3285. return ret;
  3286. if (ret == 0) {
  3287. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3288. spin_lock_irq(&dev->event_lock);
  3289. if (intel_crtc->unpin_work) {
  3290. WARN_ONCE(1, "Removing stuck page flip\n");
  3291. page_flip_completed(intel_crtc);
  3292. }
  3293. spin_unlock_irq(&dev->event_lock);
  3294. }
  3295. return 0;
  3296. }
  3297. static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
  3298. {
  3299. u32 temp;
  3300. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  3301. mutex_lock(&dev_priv->sb_lock);
  3302. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  3303. temp |= SBI_SSCCTL_DISABLE;
  3304. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  3305. mutex_unlock(&dev_priv->sb_lock);
  3306. }
  3307. /* Program iCLKIP clock to the desired frequency */
  3308. static void lpt_program_iclkip(struct drm_crtc *crtc)
  3309. {
  3310. struct drm_i915_private *dev_priv = to_i915(crtc->dev);
  3311. int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
  3312. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  3313. u32 temp;
  3314. lpt_disable_iclkip(dev_priv);
  3315. /* The iCLK virtual clock root frequency is in MHz,
  3316. * but the adjusted_mode->crtc_clock in in KHz. To get the
  3317. * divisors, it is necessary to divide one by another, so we
  3318. * convert the virtual clock precision to KHz here for higher
  3319. * precision.
  3320. */
  3321. for (auxdiv = 0; auxdiv < 2; auxdiv++) {
  3322. u32 iclk_virtual_root_freq = 172800 * 1000;
  3323. u32 iclk_pi_range = 64;
  3324. u32 desired_divisor;
  3325. desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
  3326. clock << auxdiv);
  3327. divsel = (desired_divisor / iclk_pi_range) - 2;
  3328. phaseinc = desired_divisor % iclk_pi_range;
  3329. /*
  3330. * Near 20MHz is a corner case which is
  3331. * out of range for the 7-bit divisor
  3332. */
  3333. if (divsel <= 0x7f)
  3334. break;
  3335. }
  3336. /* This should not happen with any sane values */
  3337. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  3338. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  3339. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  3340. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  3341. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  3342. clock,
  3343. auxdiv,
  3344. divsel,
  3345. phasedir,
  3346. phaseinc);
  3347. mutex_lock(&dev_priv->sb_lock);
  3348. /* Program SSCDIVINTPHASE6 */
  3349. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  3350. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  3351. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  3352. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  3353. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  3354. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  3355. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  3356. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  3357. /* Program SSCAUXDIV */
  3358. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  3359. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  3360. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  3361. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  3362. /* Enable modulator and associated divider */
  3363. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  3364. temp &= ~SBI_SSCCTL_DISABLE;
  3365. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  3366. mutex_unlock(&dev_priv->sb_lock);
  3367. /* Wait for initialization time */
  3368. udelay(24);
  3369. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  3370. }
  3371. int lpt_get_iclkip(struct drm_i915_private *dev_priv)
  3372. {
  3373. u32 divsel, phaseinc, auxdiv;
  3374. u32 iclk_virtual_root_freq = 172800 * 1000;
  3375. u32 iclk_pi_range = 64;
  3376. u32 desired_divisor;
  3377. u32 temp;
  3378. if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
  3379. return 0;
  3380. mutex_lock(&dev_priv->sb_lock);
  3381. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  3382. if (temp & SBI_SSCCTL_DISABLE) {
  3383. mutex_unlock(&dev_priv->sb_lock);
  3384. return 0;
  3385. }
  3386. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  3387. divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
  3388. SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
  3389. phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
  3390. SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
  3391. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  3392. auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
  3393. SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
  3394. mutex_unlock(&dev_priv->sb_lock);
  3395. desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
  3396. return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
  3397. desired_divisor << auxdiv);
  3398. }
  3399. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  3400. enum pipe pch_transcoder)
  3401. {
  3402. struct drm_device *dev = crtc->base.dev;
  3403. struct drm_i915_private *dev_priv = dev->dev_private;
  3404. enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  3405. I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  3406. I915_READ(HTOTAL(cpu_transcoder)));
  3407. I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  3408. I915_READ(HBLANK(cpu_transcoder)));
  3409. I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  3410. I915_READ(HSYNC(cpu_transcoder)));
  3411. I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  3412. I915_READ(VTOTAL(cpu_transcoder)));
  3413. I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  3414. I915_READ(VBLANK(cpu_transcoder)));
  3415. I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  3416. I915_READ(VSYNC(cpu_transcoder)));
  3417. I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  3418. I915_READ(VSYNCSHIFT(cpu_transcoder)));
  3419. }
  3420. static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
  3421. {
  3422. struct drm_i915_private *dev_priv = dev->dev_private;
  3423. uint32_t temp;
  3424. temp = I915_READ(SOUTH_CHICKEN1);
  3425. if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
  3426. return;
  3427. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  3428. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  3429. temp &= ~FDI_BC_BIFURCATION_SELECT;
  3430. if (enable)
  3431. temp |= FDI_BC_BIFURCATION_SELECT;
  3432. DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
  3433. I915_WRITE(SOUTH_CHICKEN1, temp);
  3434. POSTING_READ(SOUTH_CHICKEN1);
  3435. }
  3436. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  3437. {
  3438. struct drm_device *dev = intel_crtc->base.dev;
  3439. switch (intel_crtc->pipe) {
  3440. case PIPE_A:
  3441. break;
  3442. case PIPE_B:
  3443. if (intel_crtc->config->fdi_lanes > 2)
  3444. cpt_set_fdi_bc_bifurcation(dev, false);
  3445. else
  3446. cpt_set_fdi_bc_bifurcation(dev, true);
  3447. break;
  3448. case PIPE_C:
  3449. cpt_set_fdi_bc_bifurcation(dev, true);
  3450. break;
  3451. default:
  3452. BUG();
  3453. }
  3454. }
  3455. /* Return which DP Port should be selected for Transcoder DP control */
  3456. static enum port
  3457. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  3458. {
  3459. struct drm_device *dev = crtc->dev;
  3460. struct intel_encoder *encoder;
  3461. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3462. if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  3463. encoder->type == INTEL_OUTPUT_EDP)
  3464. return enc_to_dig_port(&encoder->base)->port;
  3465. }
  3466. return -1;
  3467. }
  3468. /*
  3469. * Enable PCH resources required for PCH ports:
  3470. * - PCH PLLs
  3471. * - FDI training & RX/TX
  3472. * - update transcoder timings
  3473. * - DP transcoding bits
  3474. * - transcoder
  3475. */
  3476. static void ironlake_pch_enable(struct drm_crtc *crtc)
  3477. {
  3478. struct drm_device *dev = crtc->dev;
  3479. struct drm_i915_private *dev_priv = dev->dev_private;
  3480. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3481. int pipe = intel_crtc->pipe;
  3482. u32 temp;
  3483. assert_pch_transcoder_disabled(dev_priv, pipe);
  3484. if (IS_IVYBRIDGE(dev))
  3485. ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  3486. /* Write the TU size bits before fdi link training, so that error
  3487. * detection works. */
  3488. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  3489. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  3490. /* For PCH output, training FDI link */
  3491. dev_priv->display.fdi_link_train(crtc);
  3492. /* We need to program the right clock selection before writing the pixel
  3493. * mutliplier into the DPLL. */
  3494. if (HAS_PCH_CPT(dev)) {
  3495. u32 sel;
  3496. temp = I915_READ(PCH_DPLL_SEL);
  3497. temp |= TRANS_DPLL_ENABLE(pipe);
  3498. sel = TRANS_DPLLB_SEL(pipe);
  3499. if (intel_crtc->config->shared_dpll ==
  3500. intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
  3501. temp |= sel;
  3502. else
  3503. temp &= ~sel;
  3504. I915_WRITE(PCH_DPLL_SEL, temp);
  3505. }
  3506. /* XXX: pch pll's can be enabled any time before we enable the PCH
  3507. * transcoder, and we actually should do this to not upset any PCH
  3508. * transcoder that already use the clock when we share it.
  3509. *
  3510. * Note that enable_shared_dpll tries to do the right thing, but
  3511. * get_shared_dpll unconditionally resets the pll - we need that to have
  3512. * the right LVDS enable sequence. */
  3513. intel_enable_shared_dpll(intel_crtc);
  3514. /* set transcoder timing, panel must allow it */
  3515. assert_panel_unlocked(dev_priv, pipe);
  3516. ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  3517. intel_fdi_normal_train(crtc);
  3518. /* For PCH DP, enable TRANS_DP_CTL */
  3519. if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
  3520. const struct drm_display_mode *adjusted_mode =
  3521. &intel_crtc->config->base.adjusted_mode;
  3522. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  3523. i915_reg_t reg = TRANS_DP_CTL(pipe);
  3524. temp = I915_READ(reg);
  3525. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  3526. TRANS_DP_SYNC_MASK |
  3527. TRANS_DP_BPC_MASK);
  3528. temp |= TRANS_DP_OUTPUT_ENABLE;
  3529. temp |= bpc << 9; /* same format but at 11:9 */
  3530. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  3531. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  3532. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  3533. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  3534. switch (intel_trans_dp_port_sel(crtc)) {
  3535. case PORT_B:
  3536. temp |= TRANS_DP_PORT_SEL_B;
  3537. break;
  3538. case PORT_C:
  3539. temp |= TRANS_DP_PORT_SEL_C;
  3540. break;
  3541. case PORT_D:
  3542. temp |= TRANS_DP_PORT_SEL_D;
  3543. break;
  3544. default:
  3545. BUG();
  3546. }
  3547. I915_WRITE(reg, temp);
  3548. }
  3549. ironlake_enable_pch_transcoder(dev_priv, pipe);
  3550. }
  3551. static void lpt_pch_enable(struct drm_crtc *crtc)
  3552. {
  3553. struct drm_device *dev = crtc->dev;
  3554. struct drm_i915_private *dev_priv = dev->dev_private;
  3555. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3556. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  3557. assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  3558. lpt_program_iclkip(crtc);
  3559. /* Set transcoder timing. */
  3560. ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  3561. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  3562. }
  3563. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  3564. {
  3565. struct drm_i915_private *dev_priv = dev->dev_private;
  3566. i915_reg_t dslreg = PIPEDSL(pipe);
  3567. u32 temp;
  3568. temp = I915_READ(dslreg);
  3569. udelay(500);
  3570. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  3571. if (wait_for(I915_READ(dslreg) != temp, 5))
  3572. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  3573. }
  3574. }
  3575. static int
  3576. skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  3577. unsigned scaler_user, int *scaler_id, unsigned int rotation,
  3578. int src_w, int src_h, int dst_w, int dst_h)
  3579. {
  3580. struct intel_crtc_scaler_state *scaler_state =
  3581. &crtc_state->scaler_state;
  3582. struct intel_crtc *intel_crtc =
  3583. to_intel_crtc(crtc_state->base.crtc);
  3584. int need_scaling;
  3585. need_scaling = intel_rotation_90_or_270(rotation) ?
  3586. (src_h != dst_w || src_w != dst_h):
  3587. (src_w != dst_w || src_h != dst_h);
  3588. /*
  3589. * if plane is being disabled or scaler is no more required or force detach
  3590. * - free scaler binded to this plane/crtc
  3591. * - in order to do this, update crtc->scaler_usage
  3592. *
  3593. * Here scaler state in crtc_state is set free so that
  3594. * scaler can be assigned to other user. Actual register
  3595. * update to free the scaler is done in plane/panel-fit programming.
  3596. * For this purpose crtc/plane_state->scaler_id isn't reset here.
  3597. */
  3598. if (force_detach || !need_scaling) {
  3599. if (*scaler_id >= 0) {
  3600. scaler_state->scaler_users &= ~(1 << scaler_user);
  3601. scaler_state->scalers[*scaler_id].in_use = 0;
  3602. DRM_DEBUG_KMS("scaler_user index %u.%u: "
  3603. "Staged freeing scaler id %d scaler_users = 0x%x\n",
  3604. intel_crtc->pipe, scaler_user, *scaler_id,
  3605. scaler_state->scaler_users);
  3606. *scaler_id = -1;
  3607. }
  3608. return 0;
  3609. }
  3610. /* range checks */
  3611. if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
  3612. dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
  3613. src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
  3614. dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
  3615. DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
  3616. "size is out of scaler range\n",
  3617. intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
  3618. return -EINVAL;
  3619. }
  3620. /* mark this plane as a scaler user in crtc_state */
  3621. scaler_state->scaler_users |= (1 << scaler_user);
  3622. DRM_DEBUG_KMS("scaler_user index %u.%u: "
  3623. "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
  3624. intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
  3625. scaler_state->scaler_users);
  3626. return 0;
  3627. }
  3628. /**
  3629. * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
  3630. *
  3631. * @state: crtc's scaler state
  3632. *
  3633. * Return
  3634. * 0 - scaler_usage updated successfully
  3635. * error - requested scaling cannot be supported or other error condition
  3636. */
  3637. int skl_update_scaler_crtc(struct intel_crtc_state *state)
  3638. {
  3639. struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
  3640. const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
  3641. DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
  3642. intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
  3643. return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
  3644. &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
  3645. state->pipe_src_w, state->pipe_src_h,
  3646. adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
  3647. }
  3648. /**
  3649. * skl_update_scaler_plane - Stages update to scaler state for a given plane.
  3650. *
  3651. * @state: crtc's scaler state
  3652. * @plane_state: atomic plane state to update
  3653. *
  3654. * Return
  3655. * 0 - scaler_usage updated successfully
  3656. * error - requested scaling cannot be supported or other error condition
  3657. */
  3658. static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
  3659. struct intel_plane_state *plane_state)
  3660. {
  3661. struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
  3662. struct intel_plane *intel_plane =
  3663. to_intel_plane(plane_state->base.plane);
  3664. struct drm_framebuffer *fb = plane_state->base.fb;
  3665. int ret;
  3666. bool force_detach = !fb || !plane_state->visible;
  3667. DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
  3668. intel_plane->base.base.id, intel_crtc->pipe,
  3669. drm_plane_index(&intel_plane->base));
  3670. ret = skl_update_scaler(crtc_state, force_detach,
  3671. drm_plane_index(&intel_plane->base),
  3672. &plane_state->scaler_id,
  3673. plane_state->base.rotation,
  3674. drm_rect_width(&plane_state->src) >> 16,
  3675. drm_rect_height(&plane_state->src) >> 16,
  3676. drm_rect_width(&plane_state->dst),
  3677. drm_rect_height(&plane_state->dst));
  3678. if (ret || plane_state->scaler_id < 0)
  3679. return ret;
  3680. /* check colorkey */
  3681. if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
  3682. DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
  3683. intel_plane->base.base.id);
  3684. return -EINVAL;
  3685. }
  3686. /* Check src format */
  3687. switch (fb->pixel_format) {
  3688. case DRM_FORMAT_RGB565:
  3689. case DRM_FORMAT_XBGR8888:
  3690. case DRM_FORMAT_XRGB8888:
  3691. case DRM_FORMAT_ABGR8888:
  3692. case DRM_FORMAT_ARGB8888:
  3693. case DRM_FORMAT_XRGB2101010:
  3694. case DRM_FORMAT_XBGR2101010:
  3695. case DRM_FORMAT_YUYV:
  3696. case DRM_FORMAT_YVYU:
  3697. case DRM_FORMAT_UYVY:
  3698. case DRM_FORMAT_VYUY:
  3699. break;
  3700. default:
  3701. DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
  3702. intel_plane->base.base.id, fb->base.id, fb->pixel_format);
  3703. return -EINVAL;
  3704. }
  3705. return 0;
  3706. }
  3707. static void skylake_scaler_disable(struct intel_crtc *crtc)
  3708. {
  3709. int i;
  3710. for (i = 0; i < crtc->num_scalers; i++)
  3711. skl_detach_scaler(crtc, i);
  3712. }
  3713. static void skylake_pfit_enable(struct intel_crtc *crtc)
  3714. {
  3715. struct drm_device *dev = crtc->base.dev;
  3716. struct drm_i915_private *dev_priv = dev->dev_private;
  3717. int pipe = crtc->pipe;
  3718. struct intel_crtc_scaler_state *scaler_state =
  3719. &crtc->config->scaler_state;
  3720. DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
  3721. if (crtc->config->pch_pfit.enabled) {
  3722. int id;
  3723. if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
  3724. DRM_ERROR("Requesting pfit without getting a scaler first\n");
  3725. return;
  3726. }
  3727. id = scaler_state->scaler_id;
  3728. I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
  3729. PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
  3730. I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
  3731. I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
  3732. DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
  3733. }
  3734. }
  3735. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  3736. {
  3737. struct drm_device *dev = crtc->base.dev;
  3738. struct drm_i915_private *dev_priv = dev->dev_private;
  3739. int pipe = crtc->pipe;
  3740. if (crtc->config->pch_pfit.enabled) {
  3741. /* Force use of hard-coded filter coefficients
  3742. * as some pre-programmed values are broken,
  3743. * e.g. x201.
  3744. */
  3745. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  3746. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  3747. PF_PIPE_SEL_IVB(pipe));
  3748. else
  3749. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  3750. I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
  3751. I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
  3752. }
  3753. }
  3754. void hsw_enable_ips(struct intel_crtc *crtc)
  3755. {
  3756. struct drm_device *dev = crtc->base.dev;
  3757. struct drm_i915_private *dev_priv = dev->dev_private;
  3758. if (!crtc->config->ips_enabled)
  3759. return;
  3760. /*
  3761. * We can only enable IPS after we enable a plane and wait for a vblank
  3762. * This function is called from post_plane_update, which is run after
  3763. * a vblank wait.
  3764. */
  3765. assert_plane_enabled(dev_priv, crtc->plane);
  3766. if (IS_BROADWELL(dev)) {
  3767. mutex_lock(&dev_priv->rps.hw_lock);
  3768. WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
  3769. mutex_unlock(&dev_priv->rps.hw_lock);
  3770. /* Quoting Art Runyan: "its not safe to expect any particular
  3771. * value in IPS_CTL bit 31 after enabling IPS through the
  3772. * mailbox." Moreover, the mailbox may return a bogus state,
  3773. * so we need to just enable it and continue on.
  3774. */
  3775. } else {
  3776. I915_WRITE(IPS_CTL, IPS_ENABLE);
  3777. /* The bit only becomes 1 in the next vblank, so this wait here
  3778. * is essentially intel_wait_for_vblank. If we don't have this
  3779. * and don't wait for vblanks until the end of crtc_enable, then
  3780. * the HW state readout code will complain that the expected
  3781. * IPS_CTL value is not the one we read. */
  3782. if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
  3783. DRM_ERROR("Timed out waiting for IPS enable\n");
  3784. }
  3785. }
  3786. void hsw_disable_ips(struct intel_crtc *crtc)
  3787. {
  3788. struct drm_device *dev = crtc->base.dev;
  3789. struct drm_i915_private *dev_priv = dev->dev_private;
  3790. if (!crtc->config->ips_enabled)
  3791. return;
  3792. assert_plane_enabled(dev_priv, crtc->plane);
  3793. if (IS_BROADWELL(dev)) {
  3794. mutex_lock(&dev_priv->rps.hw_lock);
  3795. WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
  3796. mutex_unlock(&dev_priv->rps.hw_lock);
  3797. /* wait for pcode to finish disabling IPS, which may take up to 42ms */
  3798. if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
  3799. DRM_ERROR("Timed out waiting for IPS disable\n");
  3800. } else {
  3801. I915_WRITE(IPS_CTL, 0);
  3802. POSTING_READ(IPS_CTL);
  3803. }
  3804. /* We need to wait for a vblank before we can disable the plane. */
  3805. intel_wait_for_vblank(dev, crtc->pipe);
  3806. }
  3807. static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
  3808. {
  3809. if (intel_crtc->overlay) {
  3810. struct drm_device *dev = intel_crtc->base.dev;
  3811. struct drm_i915_private *dev_priv = dev->dev_private;
  3812. mutex_lock(&dev->struct_mutex);
  3813. dev_priv->mm.interruptible = false;
  3814. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3815. dev_priv->mm.interruptible = true;
  3816. mutex_unlock(&dev->struct_mutex);
  3817. }
  3818. /* Let userspace switch the overlay on again. In most cases userspace
  3819. * has to recompute where to put it anyway.
  3820. */
  3821. }
  3822. /**
  3823. * intel_post_enable_primary - Perform operations after enabling primary plane
  3824. * @crtc: the CRTC whose primary plane was just enabled
  3825. *
  3826. * Performs potentially sleeping operations that must be done after the primary
  3827. * plane is enabled, such as updating FBC and IPS. Note that this may be
  3828. * called due to an explicit primary plane update, or due to an implicit
  3829. * re-enable that is caused when a sprite plane is updated to no longer
  3830. * completely hide the primary plane.
  3831. */
  3832. static void
  3833. intel_post_enable_primary(struct drm_crtc *crtc)
  3834. {
  3835. struct drm_device *dev = crtc->dev;
  3836. struct drm_i915_private *dev_priv = dev->dev_private;
  3837. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3838. int pipe = intel_crtc->pipe;
  3839. /*
  3840. * FIXME IPS should be fine as long as one plane is
  3841. * enabled, but in practice it seems to have problems
  3842. * when going from primary only to sprite only and vice
  3843. * versa.
  3844. */
  3845. hsw_enable_ips(intel_crtc);
  3846. /*
  3847. * Gen2 reports pipe underruns whenever all planes are disabled.
  3848. * So don't enable underrun reporting before at least some planes
  3849. * are enabled.
  3850. * FIXME: Need to fix the logic to work when we turn off all planes
  3851. * but leave the pipe running.
  3852. */
  3853. if (IS_GEN2(dev))
  3854. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  3855. /* Underruns don't always raise interrupts, so check manually. */
  3856. intel_check_cpu_fifo_underruns(dev_priv);
  3857. intel_check_pch_fifo_underruns(dev_priv);
  3858. }
  3859. /* FIXME move all this to pre_plane_update() with proper state tracking */
  3860. static void
  3861. intel_pre_disable_primary(struct drm_crtc *crtc)
  3862. {
  3863. struct drm_device *dev = crtc->dev;
  3864. struct drm_i915_private *dev_priv = dev->dev_private;
  3865. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3866. int pipe = intel_crtc->pipe;
  3867. /*
  3868. * Gen2 reports pipe underruns whenever all planes are disabled.
  3869. * So diasble underrun reporting before all the planes get disabled.
  3870. * FIXME: Need to fix the logic to work when we turn off all planes
  3871. * but leave the pipe running.
  3872. */
  3873. if (IS_GEN2(dev))
  3874. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  3875. /*
  3876. * FIXME IPS should be fine as long as one plane is
  3877. * enabled, but in practice it seems to have problems
  3878. * when going from primary only to sprite only and vice
  3879. * versa.
  3880. */
  3881. hsw_disable_ips(intel_crtc);
  3882. }
  3883. /* FIXME get rid of this and use pre_plane_update */
  3884. static void
  3885. intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
  3886. {
  3887. struct drm_device *dev = crtc->dev;
  3888. struct drm_i915_private *dev_priv = dev->dev_private;
  3889. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3890. int pipe = intel_crtc->pipe;
  3891. intel_pre_disable_primary(crtc);
  3892. /*
  3893. * Vblank time updates from the shadow to live plane control register
  3894. * are blocked if the memory self-refresh mode is active at that
  3895. * moment. So to make sure the plane gets truly disabled, disable
  3896. * first the self-refresh mode. The self-refresh enable bit in turn
  3897. * will be checked/applied by the HW only at the next frame start
  3898. * event which is after the vblank start event, so we need to have a
  3899. * wait-for-vblank between disabling the plane and the pipe.
  3900. */
  3901. if (HAS_GMCH_DISPLAY(dev)) {
  3902. intel_set_memory_cxsr(dev_priv, false);
  3903. dev_priv->wm.vlv.cxsr = false;
  3904. intel_wait_for_vblank(dev, pipe);
  3905. }
  3906. }
  3907. static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
  3908. {
  3909. struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
  3910. struct drm_atomic_state *old_state = old_crtc_state->base.state;
  3911. struct intel_crtc_state *pipe_config =
  3912. to_intel_crtc_state(crtc->base.state);
  3913. struct drm_device *dev = crtc->base.dev;
  3914. struct drm_plane *primary = crtc->base.primary;
  3915. struct drm_plane_state *old_pri_state =
  3916. drm_atomic_get_existing_plane_state(old_state, primary);
  3917. intel_frontbuffer_flip(dev, pipe_config->fb_bits);
  3918. crtc->wm.cxsr_allowed = true;
  3919. if (pipe_config->update_wm_post && pipe_config->base.active)
  3920. intel_update_watermarks(&crtc->base);
  3921. if (old_pri_state) {
  3922. struct intel_plane_state *primary_state =
  3923. to_intel_plane_state(primary->state);
  3924. struct intel_plane_state *old_primary_state =
  3925. to_intel_plane_state(old_pri_state);
  3926. intel_fbc_post_update(crtc);
  3927. if (primary_state->visible &&
  3928. (needs_modeset(&pipe_config->base) ||
  3929. !old_primary_state->visible))
  3930. intel_post_enable_primary(&crtc->base);
  3931. }
  3932. }
  3933. static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
  3934. {
  3935. struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
  3936. struct drm_device *dev = crtc->base.dev;
  3937. struct drm_i915_private *dev_priv = dev->dev_private;
  3938. struct intel_crtc_state *pipe_config =
  3939. to_intel_crtc_state(crtc->base.state);
  3940. struct drm_atomic_state *old_state = old_crtc_state->base.state;
  3941. struct drm_plane *primary = crtc->base.primary;
  3942. struct drm_plane_state *old_pri_state =
  3943. drm_atomic_get_existing_plane_state(old_state, primary);
  3944. bool modeset = needs_modeset(&pipe_config->base);
  3945. if (old_pri_state) {
  3946. struct intel_plane_state *primary_state =
  3947. to_intel_plane_state(primary->state);
  3948. struct intel_plane_state *old_primary_state =
  3949. to_intel_plane_state(old_pri_state);
  3950. intel_fbc_pre_update(crtc);
  3951. if (old_primary_state->visible &&
  3952. (modeset || !primary_state->visible))
  3953. intel_pre_disable_primary(&crtc->base);
  3954. }
  3955. if (pipe_config->disable_cxsr) {
  3956. crtc->wm.cxsr_allowed = false;
  3957. /*
  3958. * Vblank time updates from the shadow to live plane control register
  3959. * are blocked if the memory self-refresh mode is active at that
  3960. * moment. So to make sure the plane gets truly disabled, disable
  3961. * first the self-refresh mode. The self-refresh enable bit in turn
  3962. * will be checked/applied by the HW only at the next frame start
  3963. * event which is after the vblank start event, so we need to have a
  3964. * wait-for-vblank between disabling the plane and the pipe.
  3965. */
  3966. if (old_crtc_state->base.active) {
  3967. intel_set_memory_cxsr(dev_priv, false);
  3968. dev_priv->wm.vlv.cxsr = false;
  3969. intel_wait_for_vblank(dev, crtc->pipe);
  3970. }
  3971. }
  3972. /*
  3973. * IVB workaround: must disable low power watermarks for at least
  3974. * one frame before enabling scaling. LP watermarks can be re-enabled
  3975. * when scaling is disabled.
  3976. *
  3977. * WaCxSRDisabledForSpriteScaling:ivb
  3978. */
  3979. if (pipe_config->disable_lp_wm) {
  3980. ilk_disable_lp_wm(dev);
  3981. intel_wait_for_vblank(dev, crtc->pipe);
  3982. }
  3983. /*
  3984. * If we're doing a modeset, we're done. No need to do any pre-vblank
  3985. * watermark programming here.
  3986. */
  3987. if (needs_modeset(&pipe_config->base))
  3988. return;
  3989. /*
  3990. * For platforms that support atomic watermarks, program the
  3991. * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
  3992. * will be the intermediate values that are safe for both pre- and
  3993. * post- vblank; when vblank happens, the 'active' values will be set
  3994. * to the final 'target' values and we'll do this again to get the
  3995. * optimal watermarks. For gen9+ platforms, the values we program here
  3996. * will be the final target values which will get automatically latched
  3997. * at vblank time; no further programming will be necessary.
  3998. *
  3999. * If a platform hasn't been transitioned to atomic watermarks yet,
  4000. * we'll continue to update watermarks the old way, if flags tell
  4001. * us to.
  4002. */
  4003. if (dev_priv->display.initial_watermarks != NULL)
  4004. dev_priv->display.initial_watermarks(pipe_config);
  4005. else if (pipe_config->update_wm_pre)
  4006. intel_update_watermarks(&crtc->base);
  4007. }
  4008. static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
  4009. {
  4010. struct drm_device *dev = crtc->dev;
  4011. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4012. struct drm_plane *p;
  4013. int pipe = intel_crtc->pipe;
  4014. intel_crtc_dpms_overlay_disable(intel_crtc);
  4015. drm_for_each_plane_mask(p, dev, plane_mask)
  4016. to_intel_plane(p)->disable_plane(p, crtc);
  4017. /*
  4018. * FIXME: Once we grow proper nuclear flip support out of this we need
  4019. * to compute the mask of flip planes precisely. For the time being
  4020. * consider this a flip to a NULL plane.
  4021. */
  4022. intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
  4023. }
  4024. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  4025. {
  4026. struct drm_device *dev = crtc->dev;
  4027. struct drm_i915_private *dev_priv = dev->dev_private;
  4028. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4029. struct intel_encoder *encoder;
  4030. int pipe = intel_crtc->pipe;
  4031. struct intel_crtc_state *pipe_config =
  4032. to_intel_crtc_state(crtc->state);
  4033. if (WARN_ON(intel_crtc->active))
  4034. return;
  4035. /*
  4036. * Sometimes spurious CPU pipe underruns happen during FDI
  4037. * training, at least with VGA+HDMI cloning. Suppress them.
  4038. *
  4039. * On ILK we get an occasional spurious CPU pipe underruns
  4040. * between eDP port A enable and vdd enable. Also PCH port
  4041. * enable seems to result in the occasional CPU pipe underrun.
  4042. *
  4043. * Spurious PCH underruns also occur during PCH enabling.
  4044. */
  4045. if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
  4046. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  4047. if (intel_crtc->config->has_pch_encoder)
  4048. intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
  4049. if (intel_crtc->config->has_pch_encoder)
  4050. intel_prepare_shared_dpll(intel_crtc);
  4051. if (intel_crtc->config->has_dp_encoder)
  4052. intel_dp_set_m_n(intel_crtc, M1_N1);
  4053. intel_set_pipe_timings(intel_crtc);
  4054. intel_set_pipe_src_size(intel_crtc);
  4055. if (intel_crtc->config->has_pch_encoder) {
  4056. intel_cpu_transcoder_set_m_n(intel_crtc,
  4057. &intel_crtc->config->fdi_m_n, NULL);
  4058. }
  4059. ironlake_set_pipeconf(crtc);
  4060. intel_crtc->active = true;
  4061. for_each_encoder_on_crtc(dev, crtc, encoder)
  4062. if (encoder->pre_enable)
  4063. encoder->pre_enable(encoder);
  4064. if (intel_crtc->config->has_pch_encoder) {
  4065. /* Note: FDI PLL enabling _must_ be done before we enable the
  4066. * cpu pipes, hence this is separate from all the other fdi/pch
  4067. * enabling. */
  4068. ironlake_fdi_pll_enable(intel_crtc);
  4069. } else {
  4070. assert_fdi_tx_disabled(dev_priv, pipe);
  4071. assert_fdi_rx_disabled(dev_priv, pipe);
  4072. }
  4073. ironlake_pfit_enable(intel_crtc);
  4074. /*
  4075. * On ILK+ LUT must be loaded before the pipe is running but with
  4076. * clocks enabled
  4077. */
  4078. intel_color_load_luts(&pipe_config->base);
  4079. if (dev_priv->display.initial_watermarks != NULL)
  4080. dev_priv->display.initial_watermarks(intel_crtc->config);
  4081. intel_enable_pipe(intel_crtc);
  4082. if (intel_crtc->config->has_pch_encoder)
  4083. ironlake_pch_enable(crtc);
  4084. assert_vblank_disabled(crtc);
  4085. drm_crtc_vblank_on(crtc);
  4086. for_each_encoder_on_crtc(dev, crtc, encoder)
  4087. encoder->enable(encoder);
  4088. if (HAS_PCH_CPT(dev))
  4089. cpt_verify_modeset(dev, intel_crtc->pipe);
  4090. /* Must wait for vblank to avoid spurious PCH FIFO underruns */
  4091. if (intel_crtc->config->has_pch_encoder)
  4092. intel_wait_for_vblank(dev, pipe);
  4093. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4094. intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
  4095. }
  4096. /* IPS only exists on ULT machines and is tied to pipe A. */
  4097. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  4098. {
  4099. return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  4100. }
  4101. static void haswell_crtc_enable(struct drm_crtc *crtc)
  4102. {
  4103. struct drm_device *dev = crtc->dev;
  4104. struct drm_i915_private *dev_priv = dev->dev_private;
  4105. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4106. struct intel_encoder *encoder;
  4107. int pipe = intel_crtc->pipe, hsw_workaround_pipe;
  4108. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  4109. struct intel_crtc_state *pipe_config =
  4110. to_intel_crtc_state(crtc->state);
  4111. if (WARN_ON(intel_crtc->active))
  4112. return;
  4113. if (intel_crtc->config->has_pch_encoder)
  4114. intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  4115. false);
  4116. if (intel_crtc->config->shared_dpll)
  4117. intel_enable_shared_dpll(intel_crtc);
  4118. if (intel_crtc->config->has_dp_encoder)
  4119. intel_dp_set_m_n(intel_crtc, M1_N1);
  4120. if (!intel_crtc->config->has_dsi_encoder)
  4121. intel_set_pipe_timings(intel_crtc);
  4122. intel_set_pipe_src_size(intel_crtc);
  4123. if (cpu_transcoder != TRANSCODER_EDP &&
  4124. !transcoder_is_dsi(cpu_transcoder)) {
  4125. I915_WRITE(PIPE_MULT(cpu_transcoder),
  4126. intel_crtc->config->pixel_multiplier - 1);
  4127. }
  4128. if (intel_crtc->config->has_pch_encoder) {
  4129. intel_cpu_transcoder_set_m_n(intel_crtc,
  4130. &intel_crtc->config->fdi_m_n, NULL);
  4131. }
  4132. if (!intel_crtc->config->has_dsi_encoder)
  4133. haswell_set_pipeconf(crtc);
  4134. haswell_set_pipemisc(crtc);
  4135. intel_color_set_csc(&pipe_config->base);
  4136. intel_crtc->active = true;
  4137. if (intel_crtc->config->has_pch_encoder)
  4138. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  4139. else
  4140. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4141. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4142. if (encoder->pre_enable)
  4143. encoder->pre_enable(encoder);
  4144. }
  4145. if (intel_crtc->config->has_pch_encoder)
  4146. dev_priv->display.fdi_link_train(crtc);
  4147. if (!intel_crtc->config->has_dsi_encoder)
  4148. intel_ddi_enable_pipe_clock(intel_crtc);
  4149. if (INTEL_INFO(dev)->gen >= 9)
  4150. skylake_pfit_enable(intel_crtc);
  4151. else
  4152. ironlake_pfit_enable(intel_crtc);
  4153. /*
  4154. * On ILK+ LUT must be loaded before the pipe is running but with
  4155. * clocks enabled
  4156. */
  4157. intel_color_load_luts(&pipe_config->base);
  4158. intel_ddi_set_pipe_settings(crtc);
  4159. if (!intel_crtc->config->has_dsi_encoder)
  4160. intel_ddi_enable_transcoder_func(crtc);
  4161. if (dev_priv->display.initial_watermarks != NULL)
  4162. dev_priv->display.initial_watermarks(pipe_config);
  4163. else
  4164. intel_update_watermarks(crtc);
  4165. /* XXX: Do the pipe assertions at the right place for BXT DSI. */
  4166. if (!intel_crtc->config->has_dsi_encoder)
  4167. intel_enable_pipe(intel_crtc);
  4168. if (intel_crtc->config->has_pch_encoder)
  4169. lpt_pch_enable(crtc);
  4170. if (intel_crtc->config->dp_encoder_is_mst)
  4171. intel_ddi_set_vc_payload_alloc(crtc, true);
  4172. assert_vblank_disabled(crtc);
  4173. drm_crtc_vblank_on(crtc);
  4174. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4175. encoder->enable(encoder);
  4176. intel_opregion_notify_encoder(encoder, true);
  4177. }
  4178. if (intel_crtc->config->has_pch_encoder) {
  4179. intel_wait_for_vblank(dev, pipe);
  4180. intel_wait_for_vblank(dev, pipe);
  4181. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4182. intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  4183. true);
  4184. }
  4185. /* If we change the relative order between pipe/planes enabling, we need
  4186. * to change the workaround. */
  4187. hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
  4188. if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
  4189. intel_wait_for_vblank(dev, hsw_workaround_pipe);
  4190. intel_wait_for_vblank(dev, hsw_workaround_pipe);
  4191. }
  4192. }
  4193. static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
  4194. {
  4195. struct drm_device *dev = crtc->base.dev;
  4196. struct drm_i915_private *dev_priv = dev->dev_private;
  4197. int pipe = crtc->pipe;
  4198. /* To avoid upsetting the power well on haswell only disable the pfit if
  4199. * it's in use. The hw state code will make sure we get this right. */
  4200. if (force || crtc->config->pch_pfit.enabled) {
  4201. I915_WRITE(PF_CTL(pipe), 0);
  4202. I915_WRITE(PF_WIN_POS(pipe), 0);
  4203. I915_WRITE(PF_WIN_SZ(pipe), 0);
  4204. }
  4205. }
  4206. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  4207. {
  4208. struct drm_device *dev = crtc->dev;
  4209. struct drm_i915_private *dev_priv = dev->dev_private;
  4210. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4211. struct intel_encoder *encoder;
  4212. int pipe = intel_crtc->pipe;
  4213. /*
  4214. * Sometimes spurious CPU pipe underruns happen when the
  4215. * pipe is already disabled, but FDI RX/TX is still enabled.
  4216. * Happens at least with VGA+HDMI cloning. Suppress them.
  4217. */
  4218. if (intel_crtc->config->has_pch_encoder) {
  4219. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  4220. intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
  4221. }
  4222. for_each_encoder_on_crtc(dev, crtc, encoder)
  4223. encoder->disable(encoder);
  4224. drm_crtc_vblank_off(crtc);
  4225. assert_vblank_disabled(crtc);
  4226. intel_disable_pipe(intel_crtc);
  4227. ironlake_pfit_disable(intel_crtc, false);
  4228. if (intel_crtc->config->has_pch_encoder)
  4229. ironlake_fdi_disable(crtc);
  4230. for_each_encoder_on_crtc(dev, crtc, encoder)
  4231. if (encoder->post_disable)
  4232. encoder->post_disable(encoder);
  4233. if (intel_crtc->config->has_pch_encoder) {
  4234. ironlake_disable_pch_transcoder(dev_priv, pipe);
  4235. if (HAS_PCH_CPT(dev)) {
  4236. i915_reg_t reg;
  4237. u32 temp;
  4238. /* disable TRANS_DP_CTL */
  4239. reg = TRANS_DP_CTL(pipe);
  4240. temp = I915_READ(reg);
  4241. temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  4242. TRANS_DP_PORT_SEL_MASK);
  4243. temp |= TRANS_DP_PORT_SEL_NONE;
  4244. I915_WRITE(reg, temp);
  4245. /* disable DPLL_SEL */
  4246. temp = I915_READ(PCH_DPLL_SEL);
  4247. temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  4248. I915_WRITE(PCH_DPLL_SEL, temp);
  4249. }
  4250. ironlake_fdi_pll_disable(intel_crtc);
  4251. }
  4252. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4253. intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
  4254. }
  4255. static void haswell_crtc_disable(struct drm_crtc *crtc)
  4256. {
  4257. struct drm_device *dev = crtc->dev;
  4258. struct drm_i915_private *dev_priv = dev->dev_private;
  4259. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4260. struct intel_encoder *encoder;
  4261. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  4262. if (intel_crtc->config->has_pch_encoder)
  4263. intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  4264. false);
  4265. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4266. intel_opregion_notify_encoder(encoder, false);
  4267. encoder->disable(encoder);
  4268. }
  4269. drm_crtc_vblank_off(crtc);
  4270. assert_vblank_disabled(crtc);
  4271. /* XXX: Do the pipe assertions at the right place for BXT DSI. */
  4272. if (!intel_crtc->config->has_dsi_encoder)
  4273. intel_disable_pipe(intel_crtc);
  4274. if (intel_crtc->config->dp_encoder_is_mst)
  4275. intel_ddi_set_vc_payload_alloc(crtc, false);
  4276. if (!intel_crtc->config->has_dsi_encoder)
  4277. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  4278. if (INTEL_INFO(dev)->gen >= 9)
  4279. skylake_scaler_disable(intel_crtc);
  4280. else
  4281. ironlake_pfit_disable(intel_crtc, false);
  4282. if (!intel_crtc->config->has_dsi_encoder)
  4283. intel_ddi_disable_pipe_clock(intel_crtc);
  4284. for_each_encoder_on_crtc(dev, crtc, encoder)
  4285. if (encoder->post_disable)
  4286. encoder->post_disable(encoder);
  4287. if (intel_crtc->config->has_pch_encoder) {
  4288. lpt_disable_pch_transcoder(dev_priv);
  4289. lpt_disable_iclkip(dev_priv);
  4290. intel_ddi_fdi_disable(crtc);
  4291. intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  4292. true);
  4293. }
  4294. }
  4295. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  4296. {
  4297. struct drm_device *dev = crtc->base.dev;
  4298. struct drm_i915_private *dev_priv = dev->dev_private;
  4299. struct intel_crtc_state *pipe_config = crtc->config;
  4300. if (!pipe_config->gmch_pfit.control)
  4301. return;
  4302. /*
  4303. * The panel fitter should only be adjusted whilst the pipe is disabled,
  4304. * according to register description and PRM.
  4305. */
  4306. WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  4307. assert_pipe_disabled(dev_priv, crtc->pipe);
  4308. I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  4309. I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  4310. /* Border color in case we don't scale up to the full screen. Black by
  4311. * default, change to something else for debugging. */
  4312. I915_WRITE(BCLRPAT(crtc->pipe), 0);
  4313. }
  4314. static enum intel_display_power_domain port_to_power_domain(enum port port)
  4315. {
  4316. switch (port) {
  4317. case PORT_A:
  4318. return POWER_DOMAIN_PORT_DDI_A_LANES;
  4319. case PORT_B:
  4320. return POWER_DOMAIN_PORT_DDI_B_LANES;
  4321. case PORT_C:
  4322. return POWER_DOMAIN_PORT_DDI_C_LANES;
  4323. case PORT_D:
  4324. return POWER_DOMAIN_PORT_DDI_D_LANES;
  4325. case PORT_E:
  4326. return POWER_DOMAIN_PORT_DDI_E_LANES;
  4327. default:
  4328. MISSING_CASE(port);
  4329. return POWER_DOMAIN_PORT_OTHER;
  4330. }
  4331. }
  4332. static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
  4333. {
  4334. switch (port) {
  4335. case PORT_A:
  4336. return POWER_DOMAIN_AUX_A;
  4337. case PORT_B:
  4338. return POWER_DOMAIN_AUX_B;
  4339. case PORT_C:
  4340. return POWER_DOMAIN_AUX_C;
  4341. case PORT_D:
  4342. return POWER_DOMAIN_AUX_D;
  4343. case PORT_E:
  4344. /* FIXME: Check VBT for actual wiring of PORT E */
  4345. return POWER_DOMAIN_AUX_D;
  4346. default:
  4347. MISSING_CASE(port);
  4348. return POWER_DOMAIN_AUX_A;
  4349. }
  4350. }
  4351. enum intel_display_power_domain
  4352. intel_display_port_power_domain(struct intel_encoder *intel_encoder)
  4353. {
  4354. struct drm_device *dev = intel_encoder->base.dev;
  4355. struct intel_digital_port *intel_dig_port;
  4356. switch (intel_encoder->type) {
  4357. case INTEL_OUTPUT_UNKNOWN:
  4358. /* Only DDI platforms should ever use this output type */
  4359. WARN_ON_ONCE(!HAS_DDI(dev));
  4360. case INTEL_OUTPUT_DISPLAYPORT:
  4361. case INTEL_OUTPUT_HDMI:
  4362. case INTEL_OUTPUT_EDP:
  4363. intel_dig_port = enc_to_dig_port(&intel_encoder->base);
  4364. return port_to_power_domain(intel_dig_port->port);
  4365. case INTEL_OUTPUT_DP_MST:
  4366. intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
  4367. return port_to_power_domain(intel_dig_port->port);
  4368. case INTEL_OUTPUT_ANALOG:
  4369. return POWER_DOMAIN_PORT_CRT;
  4370. case INTEL_OUTPUT_DSI:
  4371. return POWER_DOMAIN_PORT_DSI;
  4372. default:
  4373. return POWER_DOMAIN_PORT_OTHER;
  4374. }
  4375. }
  4376. enum intel_display_power_domain
  4377. intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
  4378. {
  4379. struct drm_device *dev = intel_encoder->base.dev;
  4380. struct intel_digital_port *intel_dig_port;
  4381. switch (intel_encoder->type) {
  4382. case INTEL_OUTPUT_UNKNOWN:
  4383. case INTEL_OUTPUT_HDMI:
  4384. /*
  4385. * Only DDI platforms should ever use these output types.
  4386. * We can get here after the HDMI detect code has already set
  4387. * the type of the shared encoder. Since we can't be sure
  4388. * what's the status of the given connectors, play safe and
  4389. * run the DP detection too.
  4390. */
  4391. WARN_ON_ONCE(!HAS_DDI(dev));
  4392. case INTEL_OUTPUT_DISPLAYPORT:
  4393. case INTEL_OUTPUT_EDP:
  4394. intel_dig_port = enc_to_dig_port(&intel_encoder->base);
  4395. return port_to_aux_power_domain(intel_dig_port->port);
  4396. case INTEL_OUTPUT_DP_MST:
  4397. intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
  4398. return port_to_aux_power_domain(intel_dig_port->port);
  4399. default:
  4400. MISSING_CASE(intel_encoder->type);
  4401. return POWER_DOMAIN_AUX_A;
  4402. }
  4403. }
  4404. static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
  4405. struct intel_crtc_state *crtc_state)
  4406. {
  4407. struct drm_device *dev = crtc->dev;
  4408. struct drm_encoder *encoder;
  4409. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4410. enum pipe pipe = intel_crtc->pipe;
  4411. unsigned long mask;
  4412. enum transcoder transcoder = crtc_state->cpu_transcoder;
  4413. if (!crtc_state->base.active)
  4414. return 0;
  4415. mask = BIT(POWER_DOMAIN_PIPE(pipe));
  4416. mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
  4417. if (crtc_state->pch_pfit.enabled ||
  4418. crtc_state->pch_pfit.force_thru)
  4419. mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
  4420. drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
  4421. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  4422. mask |= BIT(intel_display_port_power_domain(intel_encoder));
  4423. }
  4424. if (crtc_state->shared_dpll)
  4425. mask |= BIT(POWER_DOMAIN_PLLS);
  4426. return mask;
  4427. }
  4428. static unsigned long
  4429. modeset_get_crtc_power_domains(struct drm_crtc *crtc,
  4430. struct intel_crtc_state *crtc_state)
  4431. {
  4432. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4433. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4434. enum intel_display_power_domain domain;
  4435. unsigned long domains, new_domains, old_domains;
  4436. old_domains = intel_crtc->enabled_power_domains;
  4437. intel_crtc->enabled_power_domains = new_domains =
  4438. get_crtc_power_domains(crtc, crtc_state);
  4439. domains = new_domains & ~old_domains;
  4440. for_each_power_domain(domain, domains)
  4441. intel_display_power_get(dev_priv, domain);
  4442. return old_domains & ~new_domains;
  4443. }
  4444. static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
  4445. unsigned long domains)
  4446. {
  4447. enum intel_display_power_domain domain;
  4448. for_each_power_domain(domain, domains)
  4449. intel_display_power_put(dev_priv, domain);
  4450. }
  4451. static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  4452. {
  4453. int max_cdclk_freq = dev_priv->max_cdclk_freq;
  4454. if (INTEL_INFO(dev_priv)->gen >= 9 ||
  4455. IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  4456. return max_cdclk_freq;
  4457. else if (IS_CHERRYVIEW(dev_priv))
  4458. return max_cdclk_freq*95/100;
  4459. else if (INTEL_INFO(dev_priv)->gen < 4)
  4460. return 2*max_cdclk_freq*90/100;
  4461. else
  4462. return max_cdclk_freq*90/100;
  4463. }
  4464. static void intel_update_max_cdclk(struct drm_device *dev)
  4465. {
  4466. struct drm_i915_private *dev_priv = dev->dev_private;
  4467. if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
  4468. u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
  4469. if (limit == SKL_DFSM_CDCLK_LIMIT_675)
  4470. dev_priv->max_cdclk_freq = 675000;
  4471. else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
  4472. dev_priv->max_cdclk_freq = 540000;
  4473. else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
  4474. dev_priv->max_cdclk_freq = 450000;
  4475. else
  4476. dev_priv->max_cdclk_freq = 337500;
  4477. } else if (IS_BROXTON(dev)) {
  4478. dev_priv->max_cdclk_freq = 624000;
  4479. } else if (IS_BROADWELL(dev)) {
  4480. /*
  4481. * FIXME with extra cooling we can allow
  4482. * 540 MHz for ULX and 675 Mhz for ULT.
  4483. * How can we know if extra cooling is
  4484. * available? PCI ID, VTB, something else?
  4485. */
  4486. if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  4487. dev_priv->max_cdclk_freq = 450000;
  4488. else if (IS_BDW_ULX(dev))
  4489. dev_priv->max_cdclk_freq = 450000;
  4490. else if (IS_BDW_ULT(dev))
  4491. dev_priv->max_cdclk_freq = 540000;
  4492. else
  4493. dev_priv->max_cdclk_freq = 675000;
  4494. } else if (IS_CHERRYVIEW(dev)) {
  4495. dev_priv->max_cdclk_freq = 320000;
  4496. } else if (IS_VALLEYVIEW(dev)) {
  4497. dev_priv->max_cdclk_freq = 400000;
  4498. } else {
  4499. /* otherwise assume cdclk is fixed */
  4500. dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
  4501. }
  4502. dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
  4503. DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
  4504. dev_priv->max_cdclk_freq);
  4505. DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
  4506. dev_priv->max_dotclk_freq);
  4507. }
  4508. static void intel_update_cdclk(struct drm_device *dev)
  4509. {
  4510. struct drm_i915_private *dev_priv = dev->dev_private;
  4511. dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
  4512. DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
  4513. dev_priv->cdclk_freq);
  4514. /*
  4515. * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
  4516. * Programmng [sic] note: bit[9:2] should be programmed to the number
  4517. * of cdclk that generates 4MHz reference clock freq which is used to
  4518. * generate GMBus clock. This will vary with the cdclk freq.
  4519. */
  4520. if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
  4521. I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
  4522. if (dev_priv->max_cdclk_freq == 0)
  4523. intel_update_max_cdclk(dev);
  4524. }
  4525. static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
  4526. {
  4527. uint32_t divider;
  4528. uint32_t ratio;
  4529. uint32_t current_freq;
  4530. int ret;
  4531. /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
  4532. switch (frequency) {
  4533. case 144000:
  4534. divider = BXT_CDCLK_CD2X_DIV_SEL_4;
  4535. ratio = BXT_DE_PLL_RATIO(60);
  4536. break;
  4537. case 288000:
  4538. divider = BXT_CDCLK_CD2X_DIV_SEL_2;
  4539. ratio = BXT_DE_PLL_RATIO(60);
  4540. break;
  4541. case 384000:
  4542. divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
  4543. ratio = BXT_DE_PLL_RATIO(60);
  4544. break;
  4545. case 576000:
  4546. divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  4547. ratio = BXT_DE_PLL_RATIO(60);
  4548. break;
  4549. case 624000:
  4550. divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  4551. ratio = BXT_DE_PLL_RATIO(65);
  4552. break;
  4553. case 19200:
  4554. /*
  4555. * Bypass frequency with DE PLL disabled. Init ratio, divider
  4556. * to suppress GCC warning.
  4557. */
  4558. ratio = 0;
  4559. divider = 0;
  4560. break;
  4561. default:
  4562. DRM_ERROR("unsupported CDCLK freq %d", frequency);
  4563. return;
  4564. }
  4565. mutex_lock(&dev_priv->rps.hw_lock);
  4566. /* Inform power controller of upcoming frequency change */
  4567. ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
  4568. 0x80000000);
  4569. mutex_unlock(&dev_priv->rps.hw_lock);
  4570. if (ret) {
  4571. DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
  4572. ret, frequency);
  4573. return;
  4574. }
  4575. current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
  4576. /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
  4577. current_freq = current_freq * 500 + 1000;
  4578. /*
  4579. * DE PLL has to be disabled when
  4580. * - setting to 19.2MHz (bypass, PLL isn't used)
  4581. * - before setting to 624MHz (PLL needs toggling)
  4582. * - before setting to any frequency from 624MHz (PLL needs toggling)
  4583. */
  4584. if (frequency == 19200 || frequency == 624000 ||
  4585. current_freq == 624000) {
  4586. I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
  4587. /* Timeout 200us */
  4588. if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
  4589. 1))
  4590. DRM_ERROR("timout waiting for DE PLL unlock\n");
  4591. }
  4592. if (frequency != 19200) {
  4593. uint32_t val;
  4594. val = I915_READ(BXT_DE_PLL_CTL);
  4595. val &= ~BXT_DE_PLL_RATIO_MASK;
  4596. val |= ratio;
  4597. I915_WRITE(BXT_DE_PLL_CTL, val);
  4598. I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
  4599. /* Timeout 200us */
  4600. if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
  4601. DRM_ERROR("timeout waiting for DE PLL lock\n");
  4602. val = I915_READ(CDCLK_CTL);
  4603. val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
  4604. val |= divider;
  4605. /*
  4606. * Disable SSA Precharge when CD clock frequency < 500 MHz,
  4607. * enable otherwise.
  4608. */
  4609. val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
  4610. if (frequency >= 500000)
  4611. val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
  4612. val &= ~CDCLK_FREQ_DECIMAL_MASK;
  4613. /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
  4614. val |= (frequency - 1000) / 500;
  4615. I915_WRITE(CDCLK_CTL, val);
  4616. }
  4617. mutex_lock(&dev_priv->rps.hw_lock);
  4618. ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
  4619. DIV_ROUND_UP(frequency, 25000));
  4620. mutex_unlock(&dev_priv->rps.hw_lock);
  4621. if (ret) {
  4622. DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
  4623. ret, frequency);
  4624. return;
  4625. }
  4626. intel_update_cdclk(dev_priv->dev);
  4627. }
  4628. static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
  4629. {
  4630. if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
  4631. return false;
  4632. /* TODO: Check for a valid CDCLK rate */
  4633. if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
  4634. DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
  4635. return false;
  4636. }
  4637. if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
  4638. DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
  4639. return false;
  4640. }
  4641. return true;
  4642. }
  4643. bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
  4644. {
  4645. return broxton_cdclk_is_enabled(dev_priv);
  4646. }
  4647. void broxton_init_cdclk(struct drm_i915_private *dev_priv)
  4648. {
  4649. /* check if cd clock is enabled */
  4650. if (broxton_cdclk_is_enabled(dev_priv)) {
  4651. DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
  4652. return;
  4653. }
  4654. DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
  4655. /*
  4656. * FIXME:
  4657. * - The initial CDCLK needs to be read from VBT.
  4658. * Need to make this change after VBT has changes for BXT.
  4659. * - check if setting the max (or any) cdclk freq is really necessary
  4660. * here, it belongs to modeset time
  4661. */
  4662. broxton_set_cdclk(dev_priv, 624000);
  4663. I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
  4664. POSTING_READ(DBUF_CTL);
  4665. udelay(10);
  4666. if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
  4667. DRM_ERROR("DBuf power enable timeout!\n");
  4668. }
  4669. void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
  4670. {
  4671. I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
  4672. POSTING_READ(DBUF_CTL);
  4673. udelay(10);
  4674. if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
  4675. DRM_ERROR("DBuf power disable timeout!\n");
  4676. /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
  4677. broxton_set_cdclk(dev_priv, 19200);
  4678. }
  4679. static const struct skl_cdclk_entry {
  4680. unsigned int freq;
  4681. unsigned int vco;
  4682. } skl_cdclk_frequencies[] = {
  4683. { .freq = 308570, .vco = 8640 },
  4684. { .freq = 337500, .vco = 8100 },
  4685. { .freq = 432000, .vco = 8640 },
  4686. { .freq = 450000, .vco = 8100 },
  4687. { .freq = 540000, .vco = 8100 },
  4688. { .freq = 617140, .vco = 8640 },
  4689. { .freq = 675000, .vco = 8100 },
  4690. };
  4691. static unsigned int skl_cdclk_decimal(unsigned int freq)
  4692. {
  4693. return (freq - 1000) / 500;
  4694. }
  4695. static unsigned int skl_cdclk_get_vco(unsigned int freq)
  4696. {
  4697. unsigned int i;
  4698. for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
  4699. const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
  4700. if (e->freq == freq)
  4701. return e->vco;
  4702. }
  4703. return 8100;
  4704. }
  4705. static void
  4706. skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
  4707. {
  4708. unsigned int min_freq;
  4709. u32 val;
  4710. /* select the minimum CDCLK before enabling DPLL 0 */
  4711. val = I915_READ(CDCLK_CTL);
  4712. val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
  4713. val |= CDCLK_FREQ_337_308;
  4714. if (required_vco == 8640)
  4715. min_freq = 308570;
  4716. else
  4717. min_freq = 337500;
  4718. val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
  4719. I915_WRITE(CDCLK_CTL, val);
  4720. POSTING_READ(CDCLK_CTL);
  4721. /*
  4722. * We always enable DPLL0 with the lowest link rate possible, but still
  4723. * taking into account the VCO required to operate the eDP panel at the
  4724. * desired frequency. The usual DP link rates operate with a VCO of
  4725. * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
  4726. * The modeset code is responsible for the selection of the exact link
  4727. * rate later on, with the constraint of choosing a frequency that
  4728. * works with required_vco.
  4729. */
  4730. val = I915_READ(DPLL_CTRL1);
  4731. val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
  4732. DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
  4733. val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
  4734. if (required_vco == 8640)
  4735. val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
  4736. SKL_DPLL0);
  4737. else
  4738. val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
  4739. SKL_DPLL0);
  4740. I915_WRITE(DPLL_CTRL1, val);
  4741. POSTING_READ(DPLL_CTRL1);
  4742. I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
  4743. if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
  4744. DRM_ERROR("DPLL0 not locked\n");
  4745. }
  4746. static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
  4747. {
  4748. int ret;
  4749. u32 val;
  4750. /* inform PCU we want to change CDCLK */
  4751. val = SKL_CDCLK_PREPARE_FOR_CHANGE;
  4752. mutex_lock(&dev_priv->rps.hw_lock);
  4753. ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
  4754. mutex_unlock(&dev_priv->rps.hw_lock);
  4755. return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
  4756. }
  4757. static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
  4758. {
  4759. unsigned int i;
  4760. for (i = 0; i < 15; i++) {
  4761. if (skl_cdclk_pcu_ready(dev_priv))
  4762. return true;
  4763. udelay(10);
  4764. }
  4765. return false;
  4766. }
  4767. static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
  4768. {
  4769. struct drm_device *dev = dev_priv->dev;
  4770. u32 freq_select, pcu_ack;
  4771. DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
  4772. if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
  4773. DRM_ERROR("failed to inform PCU about cdclk change\n");
  4774. return;
  4775. }
  4776. /* set CDCLK_CTL */
  4777. switch(freq) {
  4778. case 450000:
  4779. case 432000:
  4780. freq_select = CDCLK_FREQ_450_432;
  4781. pcu_ack = 1;
  4782. break;
  4783. case 540000:
  4784. freq_select = CDCLK_FREQ_540;
  4785. pcu_ack = 2;
  4786. break;
  4787. case 308570:
  4788. case 337500:
  4789. default:
  4790. freq_select = CDCLK_FREQ_337_308;
  4791. pcu_ack = 0;
  4792. break;
  4793. case 617140:
  4794. case 675000:
  4795. freq_select = CDCLK_FREQ_675_617;
  4796. pcu_ack = 3;
  4797. break;
  4798. }
  4799. I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
  4800. POSTING_READ(CDCLK_CTL);
  4801. /* inform PCU of the change */
  4802. mutex_lock(&dev_priv->rps.hw_lock);
  4803. sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
  4804. mutex_unlock(&dev_priv->rps.hw_lock);
  4805. intel_update_cdclk(dev);
  4806. }
  4807. void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
  4808. {
  4809. /* disable DBUF power */
  4810. I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
  4811. POSTING_READ(DBUF_CTL);
  4812. udelay(10);
  4813. if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
  4814. DRM_ERROR("DBuf power disable timeout\n");
  4815. /* disable DPLL0 */
  4816. I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
  4817. if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
  4818. DRM_ERROR("Couldn't disable DPLL0\n");
  4819. }
  4820. void skl_init_cdclk(struct drm_i915_private *dev_priv)
  4821. {
  4822. unsigned int required_vco;
  4823. /* DPLL0 not enabled (happens on early BIOS versions) */
  4824. if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
  4825. /* enable DPLL0 */
  4826. required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
  4827. skl_dpll0_enable(dev_priv, required_vco);
  4828. }
  4829. /* set CDCLK to the frequency the BIOS chose */
  4830. skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
  4831. /* enable DBUF power */
  4832. I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
  4833. POSTING_READ(DBUF_CTL);
  4834. udelay(10);
  4835. if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
  4836. DRM_ERROR("DBuf power enable timeout\n");
  4837. }
  4838. int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
  4839. {
  4840. uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
  4841. uint32_t cdctl = I915_READ(CDCLK_CTL);
  4842. int freq = dev_priv->skl_boot_cdclk;
  4843. /*
  4844. * check if the pre-os intialized the display
  4845. * There is SWF18 scratchpad register defined which is set by the
  4846. * pre-os which can be used by the OS drivers to check the status
  4847. */
  4848. if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
  4849. goto sanitize;
  4850. /* Is PLL enabled and locked ? */
  4851. if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
  4852. goto sanitize;
  4853. /* DPLL okay; verify the cdclock
  4854. *
  4855. * Noticed in some instances that the freq selection is correct but
  4856. * decimal part is programmed wrong from BIOS where pre-os does not
  4857. * enable display. Verify the same as well.
  4858. */
  4859. if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
  4860. /* All well; nothing to sanitize */
  4861. return false;
  4862. sanitize:
  4863. /*
  4864. * As of now initialize with max cdclk till
  4865. * we get dynamic cdclk support
  4866. * */
  4867. dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
  4868. skl_init_cdclk(dev_priv);
  4869. /* we did have to sanitize */
  4870. return true;
  4871. }
  4872. /* Adjust CDclk dividers to allow high res or save power if possible */
  4873. static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
  4874. {
  4875. struct drm_i915_private *dev_priv = dev->dev_private;
  4876. u32 val, cmd;
  4877. WARN_ON(dev_priv->display.get_display_clock_speed(dev)
  4878. != dev_priv->cdclk_freq);
  4879. if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
  4880. cmd = 2;
  4881. else if (cdclk == 266667)
  4882. cmd = 1;
  4883. else
  4884. cmd = 0;
  4885. mutex_lock(&dev_priv->rps.hw_lock);
  4886. val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
  4887. val &= ~DSPFREQGUAR_MASK;
  4888. val |= (cmd << DSPFREQGUAR_SHIFT);
  4889. vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
  4890. if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
  4891. DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
  4892. 50)) {
  4893. DRM_ERROR("timed out waiting for CDclk change\n");
  4894. }
  4895. mutex_unlock(&dev_priv->rps.hw_lock);
  4896. mutex_lock(&dev_priv->sb_lock);
  4897. if (cdclk == 400000) {
  4898. u32 divider;
  4899. divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
  4900. /* adjust cdclk divider */
  4901. val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
  4902. val &= ~CCK_FREQUENCY_VALUES;
  4903. val |= divider;
  4904. vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
  4905. if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
  4906. CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
  4907. 50))
  4908. DRM_ERROR("timed out waiting for CDclk change\n");
  4909. }
  4910. /* adjust self-refresh exit latency value */
  4911. val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
  4912. val &= ~0x7f;
  4913. /*
  4914. * For high bandwidth configs, we set a higher latency in the bunit
  4915. * so that the core display fetch happens in time to avoid underruns.
  4916. */
  4917. if (cdclk == 400000)
  4918. val |= 4500 / 250; /* 4.5 usec */
  4919. else
  4920. val |= 3000 / 250; /* 3.0 usec */
  4921. vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
  4922. mutex_unlock(&dev_priv->sb_lock);
  4923. intel_update_cdclk(dev);
  4924. }
  4925. static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
  4926. {
  4927. struct drm_i915_private *dev_priv = dev->dev_private;
  4928. u32 val, cmd;
  4929. WARN_ON(dev_priv->display.get_display_clock_speed(dev)
  4930. != dev_priv->cdclk_freq);
  4931. switch (cdclk) {
  4932. case 333333:
  4933. case 320000:
  4934. case 266667:
  4935. case 200000:
  4936. break;
  4937. default:
  4938. MISSING_CASE(cdclk);
  4939. return;
  4940. }
  4941. /*
  4942. * Specs are full of misinformation, but testing on actual
  4943. * hardware has shown that we just need to write the desired
  4944. * CCK divider into the Punit register.
  4945. */
  4946. cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
  4947. mutex_lock(&dev_priv->rps.hw_lock);
  4948. val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
  4949. val &= ~DSPFREQGUAR_MASK_CHV;
  4950. val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
  4951. vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
  4952. if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
  4953. DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
  4954. 50)) {
  4955. DRM_ERROR("timed out waiting for CDclk change\n");
  4956. }
  4957. mutex_unlock(&dev_priv->rps.hw_lock);
  4958. intel_update_cdclk(dev);
  4959. }
  4960. static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
  4961. int max_pixclk)
  4962. {
  4963. int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
  4964. int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
  4965. /*
  4966. * Really only a few cases to deal with, as only 4 CDclks are supported:
  4967. * 200MHz
  4968. * 267MHz
  4969. * 320/333MHz (depends on HPLL freq)
  4970. * 400MHz (VLV only)
  4971. * So we check to see whether we're above 90% (VLV) or 95% (CHV)
  4972. * of the lower bin and adjust if needed.
  4973. *
  4974. * We seem to get an unstable or solid color picture at 200MHz.
  4975. * Not sure what's wrong. For now use 200MHz only when all pipes
  4976. * are off.
  4977. */
  4978. if (!IS_CHERRYVIEW(dev_priv) &&
  4979. max_pixclk > freq_320*limit/100)
  4980. return 400000;
  4981. else if (max_pixclk > 266667*limit/100)
  4982. return freq_320;
  4983. else if (max_pixclk > 0)
  4984. return 266667;
  4985. else
  4986. return 200000;
  4987. }
  4988. static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
  4989. int max_pixclk)
  4990. {
  4991. /*
  4992. * FIXME:
  4993. * - remove the guardband, it's not needed on BXT
  4994. * - set 19.2MHz bypass frequency if there are no active pipes
  4995. */
  4996. if (max_pixclk > 576000*9/10)
  4997. return 624000;
  4998. else if (max_pixclk > 384000*9/10)
  4999. return 576000;
  5000. else if (max_pixclk > 288000*9/10)
  5001. return 384000;
  5002. else if (max_pixclk > 144000*9/10)
  5003. return 288000;
  5004. else
  5005. return 144000;
  5006. }
  5007. /* Compute the max pixel clock for new configuration. */
  5008. static int intel_mode_max_pixclk(struct drm_device *dev,
  5009. struct drm_atomic_state *state)
  5010. {
  5011. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  5012. struct drm_i915_private *dev_priv = dev->dev_private;
  5013. struct drm_crtc *crtc;
  5014. struct drm_crtc_state *crtc_state;
  5015. unsigned max_pixclk = 0, i;
  5016. enum pipe pipe;
  5017. memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
  5018. sizeof(intel_state->min_pixclk));
  5019. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  5020. int pixclk = 0;
  5021. if (crtc_state->enable)
  5022. pixclk = crtc_state->adjusted_mode.crtc_clock;
  5023. intel_state->min_pixclk[i] = pixclk;
  5024. }
  5025. for_each_pipe(dev_priv, pipe)
  5026. max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
  5027. return max_pixclk;
  5028. }
  5029. static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
  5030. {
  5031. struct drm_device *dev = state->dev;
  5032. struct drm_i915_private *dev_priv = dev->dev_private;
  5033. int max_pixclk = intel_mode_max_pixclk(dev, state);
  5034. struct intel_atomic_state *intel_state =
  5035. to_intel_atomic_state(state);
  5036. if (max_pixclk < 0)
  5037. return max_pixclk;
  5038. intel_state->cdclk = intel_state->dev_cdclk =
  5039. valleyview_calc_cdclk(dev_priv, max_pixclk);
  5040. if (!intel_state->active_crtcs)
  5041. intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
  5042. return 0;
  5043. }
  5044. static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
  5045. {
  5046. struct drm_device *dev = state->dev;
  5047. struct drm_i915_private *dev_priv = dev->dev_private;
  5048. int max_pixclk = intel_mode_max_pixclk(dev, state);
  5049. struct intel_atomic_state *intel_state =
  5050. to_intel_atomic_state(state);
  5051. if (max_pixclk < 0)
  5052. return max_pixclk;
  5053. intel_state->cdclk = intel_state->dev_cdclk =
  5054. broxton_calc_cdclk(dev_priv, max_pixclk);
  5055. if (!intel_state->active_crtcs)
  5056. intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
  5057. return 0;
  5058. }
  5059. static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
  5060. {
  5061. unsigned int credits, default_credits;
  5062. if (IS_CHERRYVIEW(dev_priv))
  5063. default_credits = PFI_CREDIT(12);
  5064. else
  5065. default_credits = PFI_CREDIT(8);
  5066. if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
  5067. /* CHV suggested value is 31 or 63 */
  5068. if (IS_CHERRYVIEW(dev_priv))
  5069. credits = PFI_CREDIT_63;
  5070. else
  5071. credits = PFI_CREDIT(15);
  5072. } else {
  5073. credits = default_credits;
  5074. }
  5075. /*
  5076. * WA - write default credits before re-programming
  5077. * FIXME: should we also set the resend bit here?
  5078. */
  5079. I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
  5080. default_credits);
  5081. I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
  5082. credits | PFI_CREDIT_RESEND);
  5083. /*
  5084. * FIXME is this guaranteed to clear
  5085. * immediately or should we poll for it?
  5086. */
  5087. WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
  5088. }
  5089. static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  5090. {
  5091. struct drm_device *dev = old_state->dev;
  5092. struct drm_i915_private *dev_priv = dev->dev_private;
  5093. struct intel_atomic_state *old_intel_state =
  5094. to_intel_atomic_state(old_state);
  5095. unsigned req_cdclk = old_intel_state->dev_cdclk;
  5096. /*
  5097. * FIXME: We can end up here with all power domains off, yet
  5098. * with a CDCLK frequency other than the minimum. To account
  5099. * for this take the PIPE-A power domain, which covers the HW
  5100. * blocks needed for the following programming. This can be
  5101. * removed once it's guaranteed that we get here either with
  5102. * the minimum CDCLK set, or the required power domains
  5103. * enabled.
  5104. */
  5105. intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
  5106. if (IS_CHERRYVIEW(dev))
  5107. cherryview_set_cdclk(dev, req_cdclk);
  5108. else
  5109. valleyview_set_cdclk(dev, req_cdclk);
  5110. vlv_program_pfi_credits(dev_priv);
  5111. intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
  5112. }
  5113. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  5114. {
  5115. struct drm_device *dev = crtc->dev;
  5116. struct drm_i915_private *dev_priv = to_i915(dev);
  5117. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5118. struct intel_encoder *encoder;
  5119. struct intel_crtc_state *pipe_config =
  5120. to_intel_crtc_state(crtc->state);
  5121. int pipe = intel_crtc->pipe;
  5122. if (WARN_ON(intel_crtc->active))
  5123. return;
  5124. if (intel_crtc->config->has_dp_encoder)
  5125. intel_dp_set_m_n(intel_crtc, M1_N1);
  5126. intel_set_pipe_timings(intel_crtc);
  5127. intel_set_pipe_src_size(intel_crtc);
  5128. if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
  5129. struct drm_i915_private *dev_priv = dev->dev_private;
  5130. I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
  5131. I915_WRITE(CHV_CANVAS(pipe), 0);
  5132. }
  5133. i9xx_set_pipeconf(intel_crtc);
  5134. intel_crtc->active = true;
  5135. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  5136. for_each_encoder_on_crtc(dev, crtc, encoder)
  5137. if (encoder->pre_pll_enable)
  5138. encoder->pre_pll_enable(encoder);
  5139. if (IS_CHERRYVIEW(dev)) {
  5140. chv_prepare_pll(intel_crtc, intel_crtc->config);
  5141. chv_enable_pll(intel_crtc, intel_crtc->config);
  5142. } else {
  5143. vlv_prepare_pll(intel_crtc, intel_crtc->config);
  5144. vlv_enable_pll(intel_crtc, intel_crtc->config);
  5145. }
  5146. for_each_encoder_on_crtc(dev, crtc, encoder)
  5147. if (encoder->pre_enable)
  5148. encoder->pre_enable(encoder);
  5149. i9xx_pfit_enable(intel_crtc);
  5150. intel_color_load_luts(&pipe_config->base);
  5151. intel_update_watermarks(crtc);
  5152. intel_enable_pipe(intel_crtc);
  5153. assert_vblank_disabled(crtc);
  5154. drm_crtc_vblank_on(crtc);
  5155. for_each_encoder_on_crtc(dev, crtc, encoder)
  5156. encoder->enable(encoder);
  5157. }
  5158. static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
  5159. {
  5160. struct drm_device *dev = crtc->base.dev;
  5161. struct drm_i915_private *dev_priv = dev->dev_private;
  5162. I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
  5163. I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
  5164. }
  5165. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  5166. {
  5167. struct drm_device *dev = crtc->dev;
  5168. struct drm_i915_private *dev_priv = to_i915(dev);
  5169. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5170. struct intel_encoder *encoder;
  5171. struct intel_crtc_state *pipe_config =
  5172. to_intel_crtc_state(crtc->state);
  5173. enum pipe pipe = intel_crtc->pipe;
  5174. if (WARN_ON(intel_crtc->active))
  5175. return;
  5176. i9xx_set_pll_dividers(intel_crtc);
  5177. if (intel_crtc->config->has_dp_encoder)
  5178. intel_dp_set_m_n(intel_crtc, M1_N1);
  5179. intel_set_pipe_timings(intel_crtc);
  5180. intel_set_pipe_src_size(intel_crtc);
  5181. i9xx_set_pipeconf(intel_crtc);
  5182. intel_crtc->active = true;
  5183. if (!IS_GEN2(dev))
  5184. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  5185. for_each_encoder_on_crtc(dev, crtc, encoder)
  5186. if (encoder->pre_enable)
  5187. encoder->pre_enable(encoder);
  5188. i9xx_enable_pll(intel_crtc);
  5189. i9xx_pfit_enable(intel_crtc);
  5190. intel_color_load_luts(&pipe_config->base);
  5191. intel_update_watermarks(crtc);
  5192. intel_enable_pipe(intel_crtc);
  5193. assert_vblank_disabled(crtc);
  5194. drm_crtc_vblank_on(crtc);
  5195. for_each_encoder_on_crtc(dev, crtc, encoder)
  5196. encoder->enable(encoder);
  5197. }
  5198. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  5199. {
  5200. struct drm_device *dev = crtc->base.dev;
  5201. struct drm_i915_private *dev_priv = dev->dev_private;
  5202. if (!crtc->config->gmch_pfit.control)
  5203. return;
  5204. assert_pipe_disabled(dev_priv, crtc->pipe);
  5205. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  5206. I915_READ(PFIT_CONTROL));
  5207. I915_WRITE(PFIT_CONTROL, 0);
  5208. }
  5209. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  5210. {
  5211. struct drm_device *dev = crtc->dev;
  5212. struct drm_i915_private *dev_priv = dev->dev_private;
  5213. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5214. struct intel_encoder *encoder;
  5215. int pipe = intel_crtc->pipe;
  5216. /*
  5217. * On gen2 planes are double buffered but the pipe isn't, so we must
  5218. * wait for planes to fully turn off before disabling the pipe.
  5219. */
  5220. if (IS_GEN2(dev))
  5221. intel_wait_for_vblank(dev, pipe);
  5222. for_each_encoder_on_crtc(dev, crtc, encoder)
  5223. encoder->disable(encoder);
  5224. drm_crtc_vblank_off(crtc);
  5225. assert_vblank_disabled(crtc);
  5226. intel_disable_pipe(intel_crtc);
  5227. i9xx_pfit_disable(intel_crtc);
  5228. for_each_encoder_on_crtc(dev, crtc, encoder)
  5229. if (encoder->post_disable)
  5230. encoder->post_disable(encoder);
  5231. if (!intel_crtc->config->has_dsi_encoder) {
  5232. if (IS_CHERRYVIEW(dev))
  5233. chv_disable_pll(dev_priv, pipe);
  5234. else if (IS_VALLEYVIEW(dev))
  5235. vlv_disable_pll(dev_priv, pipe);
  5236. else
  5237. i9xx_disable_pll(intel_crtc);
  5238. }
  5239. for_each_encoder_on_crtc(dev, crtc, encoder)
  5240. if (encoder->post_pll_disable)
  5241. encoder->post_pll_disable(encoder);
  5242. if (!IS_GEN2(dev))
  5243. intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  5244. }
  5245. static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
  5246. {
  5247. struct intel_encoder *encoder;
  5248. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5249. struct drm_i915_private *dev_priv = to_i915(crtc->dev);
  5250. enum intel_display_power_domain domain;
  5251. unsigned long domains;
  5252. if (!intel_crtc->active)
  5253. return;
  5254. if (to_intel_plane_state(crtc->primary->state)->visible) {
  5255. WARN_ON(intel_crtc->unpin_work);
  5256. intel_pre_disable_primary_noatomic(crtc);
  5257. intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
  5258. to_intel_plane_state(crtc->primary->state)->visible = false;
  5259. }
  5260. dev_priv->display.crtc_disable(crtc);
  5261. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
  5262. crtc->base.id);
  5263. WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
  5264. crtc->state->active = false;
  5265. intel_crtc->active = false;
  5266. crtc->enabled = false;
  5267. crtc->state->connector_mask = 0;
  5268. crtc->state->encoder_mask = 0;
  5269. for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
  5270. encoder->base.crtc = NULL;
  5271. intel_fbc_disable(intel_crtc);
  5272. intel_update_watermarks(crtc);
  5273. intel_disable_shared_dpll(intel_crtc);
  5274. domains = intel_crtc->enabled_power_domains;
  5275. for_each_power_domain(domain, domains)
  5276. intel_display_power_put(dev_priv, domain);
  5277. intel_crtc->enabled_power_domains = 0;
  5278. dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
  5279. dev_priv->min_pixclk[intel_crtc->pipe] = 0;
  5280. }
  5281. /*
  5282. * turn all crtc's off, but do not adjust state
  5283. * This has to be paired with a call to intel_modeset_setup_hw_state.
  5284. */
  5285. int intel_display_suspend(struct drm_device *dev)
  5286. {
  5287. struct drm_i915_private *dev_priv = to_i915(dev);
  5288. struct drm_atomic_state *state;
  5289. int ret;
  5290. state = drm_atomic_helper_suspend(dev);
  5291. ret = PTR_ERR_OR_ZERO(state);
  5292. if (ret)
  5293. DRM_ERROR("Suspending crtc's failed with %i\n", ret);
  5294. else
  5295. dev_priv->modeset_restore_state = state;
  5296. return ret;
  5297. }
  5298. void intel_encoder_destroy(struct drm_encoder *encoder)
  5299. {
  5300. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  5301. drm_encoder_cleanup(encoder);
  5302. kfree(intel_encoder);
  5303. }
  5304. /* Cross check the actual hw state with our own modeset state tracking (and it's
  5305. * internal consistency). */
  5306. static void intel_connector_verify_state(struct intel_connector *connector)
  5307. {
  5308. struct drm_crtc *crtc = connector->base.state->crtc;
  5309. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  5310. connector->base.base.id,
  5311. connector->base.name);
  5312. if (connector->get_hw_state(connector)) {
  5313. struct intel_encoder *encoder = connector->encoder;
  5314. struct drm_connector_state *conn_state = connector->base.state;
  5315. I915_STATE_WARN(!crtc,
  5316. "connector enabled without attached crtc\n");
  5317. if (!crtc)
  5318. return;
  5319. I915_STATE_WARN(!crtc->state->active,
  5320. "connector is active, but attached crtc isn't\n");
  5321. if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
  5322. return;
  5323. I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
  5324. "atomic encoder doesn't match attached encoder\n");
  5325. I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
  5326. "attached encoder crtc differs from connector crtc\n");
  5327. } else {
  5328. I915_STATE_WARN(crtc && crtc->state->active,
  5329. "attached crtc is active, but connector isn't\n");
  5330. I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
  5331. "best encoder set without crtc!\n");
  5332. }
  5333. }
  5334. int intel_connector_init(struct intel_connector *connector)
  5335. {
  5336. drm_atomic_helper_connector_reset(&connector->base);
  5337. if (!connector->base.state)
  5338. return -ENOMEM;
  5339. return 0;
  5340. }
  5341. struct intel_connector *intel_connector_alloc(void)
  5342. {
  5343. struct intel_connector *connector;
  5344. connector = kzalloc(sizeof *connector, GFP_KERNEL);
  5345. if (!connector)
  5346. return NULL;
  5347. if (intel_connector_init(connector) < 0) {
  5348. kfree(connector);
  5349. return NULL;
  5350. }
  5351. return connector;
  5352. }
  5353. /* Simple connector->get_hw_state implementation for encoders that support only
  5354. * one connector and no cloning and hence the encoder state determines the state
  5355. * of the connector. */
  5356. bool intel_connector_get_hw_state(struct intel_connector *connector)
  5357. {
  5358. enum pipe pipe = 0;
  5359. struct intel_encoder *encoder = connector->encoder;
  5360. return encoder->get_hw_state(encoder, &pipe);
  5361. }
  5362. static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
  5363. {
  5364. if (crtc_state->base.enable && crtc_state->has_pch_encoder)
  5365. return crtc_state->fdi_lanes;
  5366. return 0;
  5367. }
  5368. static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  5369. struct intel_crtc_state *pipe_config)
  5370. {
  5371. struct drm_atomic_state *state = pipe_config->base.state;
  5372. struct intel_crtc *other_crtc;
  5373. struct intel_crtc_state *other_crtc_state;
  5374. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  5375. pipe_name(pipe), pipe_config->fdi_lanes);
  5376. if (pipe_config->fdi_lanes > 4) {
  5377. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  5378. pipe_name(pipe), pipe_config->fdi_lanes);
  5379. return -EINVAL;
  5380. }
  5381. if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  5382. if (pipe_config->fdi_lanes > 2) {
  5383. DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  5384. pipe_config->fdi_lanes);
  5385. return -EINVAL;
  5386. } else {
  5387. return 0;
  5388. }
  5389. }
  5390. if (INTEL_INFO(dev)->num_pipes == 2)
  5391. return 0;
  5392. /* Ivybridge 3 pipe is really complicated */
  5393. switch (pipe) {
  5394. case PIPE_A:
  5395. return 0;
  5396. case PIPE_B:
  5397. if (pipe_config->fdi_lanes <= 2)
  5398. return 0;
  5399. other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
  5400. other_crtc_state =
  5401. intel_atomic_get_crtc_state(state, other_crtc);
  5402. if (IS_ERR(other_crtc_state))
  5403. return PTR_ERR(other_crtc_state);
  5404. if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
  5405. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  5406. pipe_name(pipe), pipe_config->fdi_lanes);
  5407. return -EINVAL;
  5408. }
  5409. return 0;
  5410. case PIPE_C:
  5411. if (pipe_config->fdi_lanes > 2) {
  5412. DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
  5413. pipe_name(pipe), pipe_config->fdi_lanes);
  5414. return -EINVAL;
  5415. }
  5416. other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
  5417. other_crtc_state =
  5418. intel_atomic_get_crtc_state(state, other_crtc);
  5419. if (IS_ERR(other_crtc_state))
  5420. return PTR_ERR(other_crtc_state);
  5421. if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
  5422. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  5423. return -EINVAL;
  5424. }
  5425. return 0;
  5426. default:
  5427. BUG();
  5428. }
  5429. }
  5430. #define RETRY 1
  5431. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  5432. struct intel_crtc_state *pipe_config)
  5433. {
  5434. struct drm_device *dev = intel_crtc->base.dev;
  5435. const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  5436. int lane, link_bw, fdi_dotclock, ret;
  5437. bool needs_recompute = false;
  5438. retry:
  5439. /* FDI is a binary signal running at ~2.7GHz, encoding
  5440. * each output octet as 10 bits. The actual frequency
  5441. * is stored as a divider into a 100MHz clock, and the
  5442. * mode pixel clock is stored in units of 1KHz.
  5443. * Hence the bw of each lane in terms of the mode signal
  5444. * is:
  5445. */
  5446. link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
  5447. fdi_dotclock = adjusted_mode->crtc_clock;
  5448. lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  5449. pipe_config->pipe_bpp);
  5450. pipe_config->fdi_lanes = lane;
  5451. intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  5452. link_bw, &pipe_config->fdi_m_n);
  5453. ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
  5454. if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
  5455. pipe_config->pipe_bpp -= 2*3;
  5456. DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  5457. pipe_config->pipe_bpp);
  5458. needs_recompute = true;
  5459. pipe_config->bw_constrained = true;
  5460. goto retry;
  5461. }
  5462. if (needs_recompute)
  5463. return RETRY;
  5464. return ret;
  5465. }
  5466. static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
  5467. struct intel_crtc_state *pipe_config)
  5468. {
  5469. if (pipe_config->pipe_bpp > 24)
  5470. return false;
  5471. /* HSW can handle pixel rate up to cdclk? */
  5472. if (IS_HASWELL(dev_priv))
  5473. return true;
  5474. /*
  5475. * We compare against max which means we must take
  5476. * the increased cdclk requirement into account when
  5477. * calculating the new cdclk.
  5478. *
  5479. * Should measure whether using a lower cdclk w/o IPS
  5480. */
  5481. return ilk_pipe_pixel_rate(pipe_config) <=
  5482. dev_priv->max_cdclk_freq * 95 / 100;
  5483. }
  5484. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  5485. struct intel_crtc_state *pipe_config)
  5486. {
  5487. struct drm_device *dev = crtc->base.dev;
  5488. struct drm_i915_private *dev_priv = dev->dev_private;
  5489. pipe_config->ips_enabled = i915.enable_ips &&
  5490. hsw_crtc_supports_ips(crtc) &&
  5491. pipe_config_supports_ips(dev_priv, pipe_config);
  5492. }
  5493. static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
  5494. {
  5495. const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  5496. /* GDG double wide on either pipe, otherwise pipe A only */
  5497. return INTEL_INFO(dev_priv)->gen < 4 &&
  5498. (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
  5499. }
  5500. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  5501. struct intel_crtc_state *pipe_config)
  5502. {
  5503. struct drm_device *dev = crtc->base.dev;
  5504. struct drm_i915_private *dev_priv = dev->dev_private;
  5505. const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  5506. /* FIXME should check pixel clock limits on all platforms */
  5507. if (INTEL_INFO(dev)->gen < 4) {
  5508. int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
  5509. /*
  5510. * Enable double wide mode when the dot clock
  5511. * is > 90% of the (display) core speed.
  5512. */
  5513. if (intel_crtc_supports_double_wide(crtc) &&
  5514. adjusted_mode->crtc_clock > clock_limit) {
  5515. clock_limit *= 2;
  5516. pipe_config->double_wide = true;
  5517. }
  5518. if (adjusted_mode->crtc_clock > clock_limit) {
  5519. DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
  5520. adjusted_mode->crtc_clock, clock_limit,
  5521. yesno(pipe_config->double_wide));
  5522. return -EINVAL;
  5523. }
  5524. }
  5525. /*
  5526. * Pipe horizontal size must be even in:
  5527. * - DVO ganged mode
  5528. * - LVDS dual channel mode
  5529. * - Double wide pipe
  5530. */
  5531. if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
  5532. intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
  5533. pipe_config->pipe_src_w &= ~1;
  5534. /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  5535. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  5536. */
  5537. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  5538. adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
  5539. return -EINVAL;
  5540. if (HAS_IPS(dev))
  5541. hsw_compute_ips_config(crtc, pipe_config);
  5542. if (pipe_config->has_pch_encoder)
  5543. return ironlake_fdi_compute_config(crtc, pipe_config);
  5544. return 0;
  5545. }
  5546. static int skylake_get_display_clock_speed(struct drm_device *dev)
  5547. {
  5548. struct drm_i915_private *dev_priv = to_i915(dev);
  5549. uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
  5550. uint32_t cdctl = I915_READ(CDCLK_CTL);
  5551. uint32_t linkrate;
  5552. if (!(lcpll1 & LCPLL_PLL_ENABLE))
  5553. return 24000; /* 24MHz is the cd freq with NSSC ref */
  5554. if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
  5555. return 540000;
  5556. linkrate = (I915_READ(DPLL_CTRL1) &
  5557. DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
  5558. if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
  5559. linkrate == DPLL_CTRL1_LINK_RATE_1080) {
  5560. /* vco 8640 */
  5561. switch (cdctl & CDCLK_FREQ_SEL_MASK) {
  5562. case CDCLK_FREQ_450_432:
  5563. return 432000;
  5564. case CDCLK_FREQ_337_308:
  5565. return 308570;
  5566. case CDCLK_FREQ_675_617:
  5567. return 617140;
  5568. default:
  5569. WARN(1, "Unknown cd freq selection\n");
  5570. }
  5571. } else {
  5572. /* vco 8100 */
  5573. switch (cdctl & CDCLK_FREQ_SEL_MASK) {
  5574. case CDCLK_FREQ_450_432:
  5575. return 450000;
  5576. case CDCLK_FREQ_337_308:
  5577. return 337500;
  5578. case CDCLK_FREQ_675_617:
  5579. return 675000;
  5580. default:
  5581. WARN(1, "Unknown cd freq selection\n");
  5582. }
  5583. }
  5584. /* error case, do as if DPLL0 isn't enabled */
  5585. return 24000;
  5586. }
  5587. static int broxton_get_display_clock_speed(struct drm_device *dev)
  5588. {
  5589. struct drm_i915_private *dev_priv = to_i915(dev);
  5590. uint32_t cdctl = I915_READ(CDCLK_CTL);
  5591. uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
  5592. uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
  5593. int cdclk;
  5594. if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
  5595. return 19200;
  5596. cdclk = 19200 * pll_ratio / 2;
  5597. switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
  5598. case BXT_CDCLK_CD2X_DIV_SEL_1:
  5599. return cdclk; /* 576MHz or 624MHz */
  5600. case BXT_CDCLK_CD2X_DIV_SEL_1_5:
  5601. return cdclk * 2 / 3; /* 384MHz */
  5602. case BXT_CDCLK_CD2X_DIV_SEL_2:
  5603. return cdclk / 2; /* 288MHz */
  5604. case BXT_CDCLK_CD2X_DIV_SEL_4:
  5605. return cdclk / 4; /* 144MHz */
  5606. }
  5607. /* error case, do as if DE PLL isn't enabled */
  5608. return 19200;
  5609. }
  5610. static int broadwell_get_display_clock_speed(struct drm_device *dev)
  5611. {
  5612. struct drm_i915_private *dev_priv = dev->dev_private;
  5613. uint32_t lcpll = I915_READ(LCPLL_CTL);
  5614. uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
  5615. if (lcpll & LCPLL_CD_SOURCE_FCLK)
  5616. return 800000;
  5617. else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  5618. return 450000;
  5619. else if (freq == LCPLL_CLK_FREQ_450)
  5620. return 450000;
  5621. else if (freq == LCPLL_CLK_FREQ_54O_BDW)
  5622. return 540000;
  5623. else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
  5624. return 337500;
  5625. else
  5626. return 675000;
  5627. }
  5628. static int haswell_get_display_clock_speed(struct drm_device *dev)
  5629. {
  5630. struct drm_i915_private *dev_priv = dev->dev_private;
  5631. uint32_t lcpll = I915_READ(LCPLL_CTL);
  5632. uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
  5633. if (lcpll & LCPLL_CD_SOURCE_FCLK)
  5634. return 800000;
  5635. else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  5636. return 450000;
  5637. else if (freq == LCPLL_CLK_FREQ_450)
  5638. return 450000;
  5639. else if (IS_HSW_ULT(dev))
  5640. return 337500;
  5641. else
  5642. return 540000;
  5643. }
  5644. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  5645. {
  5646. return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
  5647. CCK_DISPLAY_CLOCK_CONTROL);
  5648. }
  5649. static int ilk_get_display_clock_speed(struct drm_device *dev)
  5650. {
  5651. return 450000;
  5652. }
  5653. static int i945_get_display_clock_speed(struct drm_device *dev)
  5654. {
  5655. return 400000;
  5656. }
  5657. static int i915_get_display_clock_speed(struct drm_device *dev)
  5658. {
  5659. return 333333;
  5660. }
  5661. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  5662. {
  5663. return 200000;
  5664. }
  5665. static int pnv_get_display_clock_speed(struct drm_device *dev)
  5666. {
  5667. u16 gcfgc = 0;
  5668. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  5669. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  5670. case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  5671. return 266667;
  5672. case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  5673. return 333333;
  5674. case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  5675. return 444444;
  5676. case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  5677. return 200000;
  5678. default:
  5679. DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  5680. case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  5681. return 133333;
  5682. case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  5683. return 166667;
  5684. }
  5685. }
  5686. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  5687. {
  5688. u16 gcfgc = 0;
  5689. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  5690. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  5691. return 133333;
  5692. else {
  5693. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  5694. case GC_DISPLAY_CLOCK_333_MHZ:
  5695. return 333333;
  5696. default:
  5697. case GC_DISPLAY_CLOCK_190_200_MHZ:
  5698. return 190000;
  5699. }
  5700. }
  5701. }
  5702. static int i865_get_display_clock_speed(struct drm_device *dev)
  5703. {
  5704. return 266667;
  5705. }
  5706. static int i85x_get_display_clock_speed(struct drm_device *dev)
  5707. {
  5708. u16 hpllcc = 0;
  5709. /*
  5710. * 852GM/852GMV only supports 133 MHz and the HPLLCC
  5711. * encoding is different :(
  5712. * FIXME is this the right way to detect 852GM/852GMV?
  5713. */
  5714. if (dev->pdev->revision == 0x1)
  5715. return 133333;
  5716. pci_bus_read_config_word(dev->pdev->bus,
  5717. PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
  5718. /* Assume that the hardware is in the high speed state. This
  5719. * should be the default.
  5720. */
  5721. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  5722. case GC_CLOCK_133_200:
  5723. case GC_CLOCK_133_200_2:
  5724. case GC_CLOCK_100_200:
  5725. return 200000;
  5726. case GC_CLOCK_166_250:
  5727. return 250000;
  5728. case GC_CLOCK_100_133:
  5729. return 133333;
  5730. case GC_CLOCK_133_266:
  5731. case GC_CLOCK_133_266_2:
  5732. case GC_CLOCK_166_266:
  5733. return 266667;
  5734. }
  5735. /* Shouldn't happen */
  5736. return 0;
  5737. }
  5738. static int i830_get_display_clock_speed(struct drm_device *dev)
  5739. {
  5740. return 133333;
  5741. }
  5742. static unsigned int intel_hpll_vco(struct drm_device *dev)
  5743. {
  5744. struct drm_i915_private *dev_priv = dev->dev_private;
  5745. static const unsigned int blb_vco[8] = {
  5746. [0] = 3200000,
  5747. [1] = 4000000,
  5748. [2] = 5333333,
  5749. [3] = 4800000,
  5750. [4] = 6400000,
  5751. };
  5752. static const unsigned int pnv_vco[8] = {
  5753. [0] = 3200000,
  5754. [1] = 4000000,
  5755. [2] = 5333333,
  5756. [3] = 4800000,
  5757. [4] = 2666667,
  5758. };
  5759. static const unsigned int cl_vco[8] = {
  5760. [0] = 3200000,
  5761. [1] = 4000000,
  5762. [2] = 5333333,
  5763. [3] = 6400000,
  5764. [4] = 3333333,
  5765. [5] = 3566667,
  5766. [6] = 4266667,
  5767. };
  5768. static const unsigned int elk_vco[8] = {
  5769. [0] = 3200000,
  5770. [1] = 4000000,
  5771. [2] = 5333333,
  5772. [3] = 4800000,
  5773. };
  5774. static const unsigned int ctg_vco[8] = {
  5775. [0] = 3200000,
  5776. [1] = 4000000,
  5777. [2] = 5333333,
  5778. [3] = 6400000,
  5779. [4] = 2666667,
  5780. [5] = 4266667,
  5781. };
  5782. const unsigned int *vco_table;
  5783. unsigned int vco;
  5784. uint8_t tmp = 0;
  5785. /* FIXME other chipsets? */
  5786. if (IS_GM45(dev))
  5787. vco_table = ctg_vco;
  5788. else if (IS_G4X(dev))
  5789. vco_table = elk_vco;
  5790. else if (IS_CRESTLINE(dev))
  5791. vco_table = cl_vco;
  5792. else if (IS_PINEVIEW(dev))
  5793. vco_table = pnv_vco;
  5794. else if (IS_G33(dev))
  5795. vco_table = blb_vco;
  5796. else
  5797. return 0;
  5798. tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
  5799. vco = vco_table[tmp & 0x7];
  5800. if (vco == 0)
  5801. DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
  5802. else
  5803. DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
  5804. return vco;
  5805. }
  5806. static int gm45_get_display_clock_speed(struct drm_device *dev)
  5807. {
  5808. unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  5809. uint16_t tmp = 0;
  5810. pci_read_config_word(dev->pdev, GCFGC, &tmp);
  5811. cdclk_sel = (tmp >> 12) & 0x1;
  5812. switch (vco) {
  5813. case 2666667:
  5814. case 4000000:
  5815. case 5333333:
  5816. return cdclk_sel ? 333333 : 222222;
  5817. case 3200000:
  5818. return cdclk_sel ? 320000 : 228571;
  5819. default:
  5820. DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
  5821. return 222222;
  5822. }
  5823. }
  5824. static int i965gm_get_display_clock_speed(struct drm_device *dev)
  5825. {
  5826. static const uint8_t div_3200[] = { 16, 10, 8 };
  5827. static const uint8_t div_4000[] = { 20, 12, 10 };
  5828. static const uint8_t div_5333[] = { 24, 16, 14 };
  5829. const uint8_t *div_table;
  5830. unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  5831. uint16_t tmp = 0;
  5832. pci_read_config_word(dev->pdev, GCFGC, &tmp);
  5833. cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
  5834. if (cdclk_sel >= ARRAY_SIZE(div_3200))
  5835. goto fail;
  5836. switch (vco) {
  5837. case 3200000:
  5838. div_table = div_3200;
  5839. break;
  5840. case 4000000:
  5841. div_table = div_4000;
  5842. break;
  5843. case 5333333:
  5844. div_table = div_5333;
  5845. break;
  5846. default:
  5847. goto fail;
  5848. }
  5849. return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
  5850. fail:
  5851. DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
  5852. return 200000;
  5853. }
  5854. static int g33_get_display_clock_speed(struct drm_device *dev)
  5855. {
  5856. static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
  5857. static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
  5858. static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
  5859. static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
  5860. const uint8_t *div_table;
  5861. unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  5862. uint16_t tmp = 0;
  5863. pci_read_config_word(dev->pdev, GCFGC, &tmp);
  5864. cdclk_sel = (tmp >> 4) & 0x7;
  5865. if (cdclk_sel >= ARRAY_SIZE(div_3200))
  5866. goto fail;
  5867. switch (vco) {
  5868. case 3200000:
  5869. div_table = div_3200;
  5870. break;
  5871. case 4000000:
  5872. div_table = div_4000;
  5873. break;
  5874. case 4800000:
  5875. div_table = div_4800;
  5876. break;
  5877. case 5333333:
  5878. div_table = div_5333;
  5879. break;
  5880. default:
  5881. goto fail;
  5882. }
  5883. return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
  5884. fail:
  5885. DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
  5886. return 190476;
  5887. }
  5888. static void
  5889. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  5890. {
  5891. while (*num > DATA_LINK_M_N_MASK ||
  5892. *den > DATA_LINK_M_N_MASK) {
  5893. *num >>= 1;
  5894. *den >>= 1;
  5895. }
  5896. }
  5897. static void compute_m_n(unsigned int m, unsigned int n,
  5898. uint32_t *ret_m, uint32_t *ret_n)
  5899. {
  5900. *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  5901. *ret_m = div_u64((uint64_t) m * *ret_n, n);
  5902. intel_reduce_m_n_ratio(ret_m, ret_n);
  5903. }
  5904. void
  5905. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  5906. int pixel_clock, int link_clock,
  5907. struct intel_link_m_n *m_n)
  5908. {
  5909. m_n->tu = 64;
  5910. compute_m_n(bits_per_pixel * pixel_clock,
  5911. link_clock * nlanes * 8,
  5912. &m_n->gmch_m, &m_n->gmch_n);
  5913. compute_m_n(pixel_clock, link_clock,
  5914. &m_n->link_m, &m_n->link_n);
  5915. }
  5916. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  5917. {
  5918. if (i915.panel_use_ssc >= 0)
  5919. return i915.panel_use_ssc != 0;
  5920. return dev_priv->vbt.lvds_use_ssc
  5921. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  5922. }
  5923. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  5924. {
  5925. return (1 << dpll->n) << 16 | dpll->m2;
  5926. }
  5927. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  5928. {
  5929. return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  5930. }
  5931. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  5932. struct intel_crtc_state *crtc_state,
  5933. struct dpll *reduced_clock)
  5934. {
  5935. struct drm_device *dev = crtc->base.dev;
  5936. u32 fp, fp2 = 0;
  5937. if (IS_PINEVIEW(dev)) {
  5938. fp = pnv_dpll_compute_fp(&crtc_state->dpll);
  5939. if (reduced_clock)
  5940. fp2 = pnv_dpll_compute_fp(reduced_clock);
  5941. } else {
  5942. fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
  5943. if (reduced_clock)
  5944. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  5945. }
  5946. crtc_state->dpll_hw_state.fp0 = fp;
  5947. crtc->lowfreq_avail = false;
  5948. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  5949. reduced_clock) {
  5950. crtc_state->dpll_hw_state.fp1 = fp2;
  5951. crtc->lowfreq_avail = true;
  5952. } else {
  5953. crtc_state->dpll_hw_state.fp1 = fp;
  5954. }
  5955. }
  5956. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
  5957. pipe)
  5958. {
  5959. u32 reg_val;
  5960. /*
  5961. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  5962. * and set it to a reasonable value instead.
  5963. */
  5964. reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
  5965. reg_val &= 0xffffff00;
  5966. reg_val |= 0x00000030;
  5967. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
  5968. reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
  5969. reg_val &= 0x8cffffff;
  5970. reg_val = 0x8c000000;
  5971. vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
  5972. reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
  5973. reg_val &= 0xffffff00;
  5974. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
  5975. reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
  5976. reg_val &= 0x00ffffff;
  5977. reg_val |= 0xb0000000;
  5978. vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
  5979. }
  5980. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  5981. struct intel_link_m_n *m_n)
  5982. {
  5983. struct drm_device *dev = crtc->base.dev;
  5984. struct drm_i915_private *dev_priv = dev->dev_private;
  5985. int pipe = crtc->pipe;
  5986. I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  5987. I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  5988. I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  5989. I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  5990. }
  5991. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  5992. struct intel_link_m_n *m_n,
  5993. struct intel_link_m_n *m2_n2)
  5994. {
  5995. struct drm_device *dev = crtc->base.dev;
  5996. struct drm_i915_private *dev_priv = dev->dev_private;
  5997. int pipe = crtc->pipe;
  5998. enum transcoder transcoder = crtc->config->cpu_transcoder;
  5999. if (INTEL_INFO(dev)->gen >= 5) {
  6000. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  6001. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  6002. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  6003. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  6004. /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
  6005. * for gen < 8) and if DRRS is supported (to make sure the
  6006. * registers are not unnecessarily accessed).
  6007. */
  6008. if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
  6009. crtc->config->has_drrs) {
  6010. I915_WRITE(PIPE_DATA_M2(transcoder),
  6011. TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
  6012. I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
  6013. I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
  6014. I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
  6015. }
  6016. } else {
  6017. I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  6018. I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  6019. I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  6020. I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  6021. }
  6022. }
  6023. void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
  6024. {
  6025. struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
  6026. if (m_n == M1_N1) {
  6027. dp_m_n = &crtc->config->dp_m_n;
  6028. dp_m2_n2 = &crtc->config->dp_m2_n2;
  6029. } else if (m_n == M2_N2) {
  6030. /*
  6031. * M2_N2 registers are not supported. Hence m2_n2 divider value
  6032. * needs to be programmed into M1_N1.
  6033. */
  6034. dp_m_n = &crtc->config->dp_m2_n2;
  6035. } else {
  6036. DRM_ERROR("Unsupported divider value\n");
  6037. return;
  6038. }
  6039. if (crtc->config->has_pch_encoder)
  6040. intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
  6041. else
  6042. intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
  6043. }
  6044. static void vlv_compute_dpll(struct intel_crtc *crtc,
  6045. struct intel_crtc_state *pipe_config)
  6046. {
  6047. pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
  6048. DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
  6049. if (crtc->pipe != PIPE_A)
  6050. pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  6051. /* DPLL not used with DSI, but still need the rest set up */
  6052. if (!pipe_config->has_dsi_encoder)
  6053. pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
  6054. DPLL_EXT_BUFFER_ENABLE_VLV;
  6055. pipe_config->dpll_hw_state.dpll_md =
  6056. (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  6057. }
  6058. static void chv_compute_dpll(struct intel_crtc *crtc,
  6059. struct intel_crtc_state *pipe_config)
  6060. {
  6061. pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
  6062. DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
  6063. if (crtc->pipe != PIPE_A)
  6064. pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  6065. /* DPLL not used with DSI, but still need the rest set up */
  6066. if (!pipe_config->has_dsi_encoder)
  6067. pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
  6068. pipe_config->dpll_hw_state.dpll_md =
  6069. (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  6070. }
  6071. static void vlv_prepare_pll(struct intel_crtc *crtc,
  6072. const struct intel_crtc_state *pipe_config)
  6073. {
  6074. struct drm_device *dev = crtc->base.dev;
  6075. struct drm_i915_private *dev_priv = dev->dev_private;
  6076. enum pipe pipe = crtc->pipe;
  6077. u32 mdiv;
  6078. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  6079. u32 coreclk, reg_val;
  6080. /* Enable Refclk */
  6081. I915_WRITE(DPLL(pipe),
  6082. pipe_config->dpll_hw_state.dpll &
  6083. ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
  6084. /* No need to actually set up the DPLL with DSI */
  6085. if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
  6086. return;
  6087. mutex_lock(&dev_priv->sb_lock);
  6088. bestn = pipe_config->dpll.n;
  6089. bestm1 = pipe_config->dpll.m1;
  6090. bestm2 = pipe_config->dpll.m2;
  6091. bestp1 = pipe_config->dpll.p1;
  6092. bestp2 = pipe_config->dpll.p2;
  6093. /* See eDP HDMI DPIO driver vbios notes doc */
  6094. /* PLL B needs special handling */
  6095. if (pipe == PIPE_B)
  6096. vlv_pllb_recal_opamp(dev_priv, pipe);
  6097. /* Set up Tx target for periodic Rcomp update */
  6098. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
  6099. /* Disable target IRef on PLL */
  6100. reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
  6101. reg_val &= 0x00ffffff;
  6102. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
  6103. /* Disable fast lock */
  6104. vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
  6105. /* Set idtafcrecal before PLL is enabled */
  6106. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  6107. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  6108. mdiv |= ((bestn << DPIO_N_SHIFT));
  6109. mdiv |= (1 << DPIO_K_SHIFT);
  6110. /*
  6111. * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  6112. * but we don't support that).
  6113. * Note: don't use the DAC post divider as it seems unstable.
  6114. */
  6115. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  6116. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
  6117. mdiv |= DPIO_ENABLE_CALIBRATION;
  6118. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
  6119. /* Set HBR and RBR LPF coefficients */
  6120. if (pipe_config->port_clock == 162000 ||
  6121. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
  6122. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  6123. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
  6124. 0x009f0003);
  6125. else
  6126. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
  6127. 0x00d0000f);
  6128. if (pipe_config->has_dp_encoder) {
  6129. /* Use SSC source */
  6130. if (pipe == PIPE_A)
  6131. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  6132. 0x0df40000);
  6133. else
  6134. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  6135. 0x0df70000);
  6136. } else { /* HDMI or VGA */
  6137. /* Use bend source */
  6138. if (pipe == PIPE_A)
  6139. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  6140. 0x0df70000);
  6141. else
  6142. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  6143. 0x0df40000);
  6144. }
  6145. coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
  6146. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  6147. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  6148. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  6149. coreclk |= 0x01000000;
  6150. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
  6151. vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
  6152. mutex_unlock(&dev_priv->sb_lock);
  6153. }
  6154. static void chv_prepare_pll(struct intel_crtc *crtc,
  6155. const struct intel_crtc_state *pipe_config)
  6156. {
  6157. struct drm_device *dev = crtc->base.dev;
  6158. struct drm_i915_private *dev_priv = dev->dev_private;
  6159. enum pipe pipe = crtc->pipe;
  6160. enum dpio_channel port = vlv_pipe_to_channel(pipe);
  6161. u32 loopfilter, tribuf_calcntr;
  6162. u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
  6163. u32 dpio_val;
  6164. int vco;
  6165. /* Enable Refclk and SSC */
  6166. I915_WRITE(DPLL(pipe),
  6167. pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
  6168. /* No need to actually set up the DPLL with DSI */
  6169. if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
  6170. return;
  6171. bestn = pipe_config->dpll.n;
  6172. bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
  6173. bestm1 = pipe_config->dpll.m1;
  6174. bestm2 = pipe_config->dpll.m2 >> 22;
  6175. bestp1 = pipe_config->dpll.p1;
  6176. bestp2 = pipe_config->dpll.p2;
  6177. vco = pipe_config->dpll.vco;
  6178. dpio_val = 0;
  6179. loopfilter = 0;
  6180. mutex_lock(&dev_priv->sb_lock);
  6181. /* p1 and p2 divider */
  6182. vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
  6183. 5 << DPIO_CHV_S1_DIV_SHIFT |
  6184. bestp1 << DPIO_CHV_P1_DIV_SHIFT |
  6185. bestp2 << DPIO_CHV_P2_DIV_SHIFT |
  6186. 1 << DPIO_CHV_K_DIV_SHIFT);
  6187. /* Feedback post-divider - m2 */
  6188. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
  6189. /* Feedback refclk divider - n and m1 */
  6190. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
  6191. DPIO_CHV_M1_DIV_BY_2 |
  6192. 1 << DPIO_CHV_N_DIV_SHIFT);
  6193. /* M2 fraction division */
  6194. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
  6195. /* M2 fraction division enable */
  6196. dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
  6197. dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
  6198. dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
  6199. if (bestm2_frac)
  6200. dpio_val |= DPIO_CHV_FRAC_DIV_EN;
  6201. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
  6202. /* Program digital lock detect threshold */
  6203. dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
  6204. dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
  6205. DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
  6206. dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
  6207. if (!bestm2_frac)
  6208. dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
  6209. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
  6210. /* Loop filter */
  6211. if (vco == 5400000) {
  6212. loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
  6213. loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
  6214. loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
  6215. tribuf_calcntr = 0x9;
  6216. } else if (vco <= 6200000) {
  6217. loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
  6218. loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
  6219. loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  6220. tribuf_calcntr = 0x9;
  6221. } else if (vco <= 6480000) {
  6222. loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
  6223. loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
  6224. loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  6225. tribuf_calcntr = 0x8;
  6226. } else {
  6227. /* Not supported. Apply the same limits as in the max case */
  6228. loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
  6229. loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
  6230. loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  6231. tribuf_calcntr = 0;
  6232. }
  6233. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
  6234. dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
  6235. dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
  6236. dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
  6237. vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
  6238. /* AFC Recal */
  6239. vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
  6240. vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
  6241. DPIO_AFC_RECAL);
  6242. mutex_unlock(&dev_priv->sb_lock);
  6243. }
  6244. /**
  6245. * vlv_force_pll_on - forcibly enable just the PLL
  6246. * @dev_priv: i915 private structure
  6247. * @pipe: pipe PLL to enable
  6248. * @dpll: PLL configuration
  6249. *
  6250. * Enable the PLL for @pipe using the supplied @dpll config. To be used
  6251. * in cases where we need the PLL enabled even when @pipe is not going to
  6252. * be enabled.
  6253. */
  6254. int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
  6255. const struct dpll *dpll)
  6256. {
  6257. struct intel_crtc *crtc =
  6258. to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
  6259. struct intel_crtc_state *pipe_config;
  6260. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  6261. if (!pipe_config)
  6262. return -ENOMEM;
  6263. pipe_config->base.crtc = &crtc->base;
  6264. pipe_config->pixel_multiplier = 1;
  6265. pipe_config->dpll = *dpll;
  6266. if (IS_CHERRYVIEW(dev)) {
  6267. chv_compute_dpll(crtc, pipe_config);
  6268. chv_prepare_pll(crtc, pipe_config);
  6269. chv_enable_pll(crtc, pipe_config);
  6270. } else {
  6271. vlv_compute_dpll(crtc, pipe_config);
  6272. vlv_prepare_pll(crtc, pipe_config);
  6273. vlv_enable_pll(crtc, pipe_config);
  6274. }
  6275. kfree(pipe_config);
  6276. return 0;
  6277. }
  6278. /**
  6279. * vlv_force_pll_off - forcibly disable just the PLL
  6280. * @dev_priv: i915 private structure
  6281. * @pipe: pipe PLL to disable
  6282. *
  6283. * Disable the PLL for @pipe. To be used in cases where we need
  6284. * the PLL enabled even when @pipe is not going to be enabled.
  6285. */
  6286. void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
  6287. {
  6288. if (IS_CHERRYVIEW(dev))
  6289. chv_disable_pll(to_i915(dev), pipe);
  6290. else
  6291. vlv_disable_pll(to_i915(dev), pipe);
  6292. }
  6293. static void i9xx_compute_dpll(struct intel_crtc *crtc,
  6294. struct intel_crtc_state *crtc_state,
  6295. struct dpll *reduced_clock)
  6296. {
  6297. struct drm_device *dev = crtc->base.dev;
  6298. struct drm_i915_private *dev_priv = dev->dev_private;
  6299. u32 dpll;
  6300. bool is_sdvo;
  6301. struct dpll *clock = &crtc_state->dpll;
  6302. i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
  6303. is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
  6304. intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
  6305. dpll = DPLL_VGA_MODE_DIS;
  6306. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
  6307. dpll |= DPLLB_MODE_LVDS;
  6308. else
  6309. dpll |= DPLLB_MODE_DAC_SERIAL;
  6310. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  6311. dpll |= (crtc_state->pixel_multiplier - 1)
  6312. << SDVO_MULTIPLIER_SHIFT_HIRES;
  6313. }
  6314. if (is_sdvo)
  6315. dpll |= DPLL_SDVO_HIGH_SPEED;
  6316. if (crtc_state->has_dp_encoder)
  6317. dpll |= DPLL_SDVO_HIGH_SPEED;
  6318. /* compute bitmask from p1 value */
  6319. if (IS_PINEVIEW(dev))
  6320. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  6321. else {
  6322. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  6323. if (IS_G4X(dev) && reduced_clock)
  6324. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  6325. }
  6326. switch (clock->p2) {
  6327. case 5:
  6328. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  6329. break;
  6330. case 7:
  6331. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  6332. break;
  6333. case 10:
  6334. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  6335. break;
  6336. case 14:
  6337. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  6338. break;
  6339. }
  6340. if (INTEL_INFO(dev)->gen >= 4)
  6341. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  6342. if (crtc_state->sdvo_tv_clock)
  6343. dpll |= PLL_REF_INPUT_TVCLKINBC;
  6344. else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  6345. intel_panel_use_ssc(dev_priv))
  6346. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  6347. else
  6348. dpll |= PLL_REF_INPUT_DREFCLK;
  6349. dpll |= DPLL_VCO_ENABLE;
  6350. crtc_state->dpll_hw_state.dpll = dpll;
  6351. if (INTEL_INFO(dev)->gen >= 4) {
  6352. u32 dpll_md = (crtc_state->pixel_multiplier - 1)
  6353. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  6354. crtc_state->dpll_hw_state.dpll_md = dpll_md;
  6355. }
  6356. }
  6357. static void i8xx_compute_dpll(struct intel_crtc *crtc,
  6358. struct intel_crtc_state *crtc_state,
  6359. struct dpll *reduced_clock)
  6360. {
  6361. struct drm_device *dev = crtc->base.dev;
  6362. struct drm_i915_private *dev_priv = dev->dev_private;
  6363. u32 dpll;
  6364. struct dpll *clock = &crtc_state->dpll;
  6365. i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
  6366. dpll = DPLL_VGA_MODE_DIS;
  6367. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  6368. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  6369. } else {
  6370. if (clock->p1 == 2)
  6371. dpll |= PLL_P1_DIVIDE_BY_TWO;
  6372. else
  6373. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  6374. if (clock->p2 == 4)
  6375. dpll |= PLL_P2_DIVIDE_BY_4;
  6376. }
  6377. if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
  6378. dpll |= DPLL_DVO_2X_MODE;
  6379. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  6380. intel_panel_use_ssc(dev_priv))
  6381. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  6382. else
  6383. dpll |= PLL_REF_INPUT_DREFCLK;
  6384. dpll |= DPLL_VCO_ENABLE;
  6385. crtc_state->dpll_hw_state.dpll = dpll;
  6386. }
  6387. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  6388. {
  6389. struct drm_device *dev = intel_crtc->base.dev;
  6390. struct drm_i915_private *dev_priv = dev->dev_private;
  6391. enum pipe pipe = intel_crtc->pipe;
  6392. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  6393. const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  6394. uint32_t crtc_vtotal, crtc_vblank_end;
  6395. int vsyncshift = 0;
  6396. /* We need to be careful not to changed the adjusted mode, for otherwise
  6397. * the hw state checker will get angry at the mismatch. */
  6398. crtc_vtotal = adjusted_mode->crtc_vtotal;
  6399. crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  6400. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  6401. /* the chip adds 2 halflines automatically */
  6402. crtc_vtotal -= 1;
  6403. crtc_vblank_end -= 1;
  6404. if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  6405. vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
  6406. else
  6407. vsyncshift = adjusted_mode->crtc_hsync_start -
  6408. adjusted_mode->crtc_htotal / 2;
  6409. if (vsyncshift < 0)
  6410. vsyncshift += adjusted_mode->crtc_htotal;
  6411. }
  6412. if (INTEL_INFO(dev)->gen > 3)
  6413. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  6414. I915_WRITE(HTOTAL(cpu_transcoder),
  6415. (adjusted_mode->crtc_hdisplay - 1) |
  6416. ((adjusted_mode->crtc_htotal - 1) << 16));
  6417. I915_WRITE(HBLANK(cpu_transcoder),
  6418. (adjusted_mode->crtc_hblank_start - 1) |
  6419. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  6420. I915_WRITE(HSYNC(cpu_transcoder),
  6421. (adjusted_mode->crtc_hsync_start - 1) |
  6422. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  6423. I915_WRITE(VTOTAL(cpu_transcoder),
  6424. (adjusted_mode->crtc_vdisplay - 1) |
  6425. ((crtc_vtotal - 1) << 16));
  6426. I915_WRITE(VBLANK(cpu_transcoder),
  6427. (adjusted_mode->crtc_vblank_start - 1) |
  6428. ((crtc_vblank_end - 1) << 16));
  6429. I915_WRITE(VSYNC(cpu_transcoder),
  6430. (adjusted_mode->crtc_vsync_start - 1) |
  6431. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  6432. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  6433. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  6434. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  6435. * bits. */
  6436. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  6437. (pipe == PIPE_B || pipe == PIPE_C))
  6438. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  6439. }
  6440. static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
  6441. {
  6442. struct drm_device *dev = intel_crtc->base.dev;
  6443. struct drm_i915_private *dev_priv = dev->dev_private;
  6444. enum pipe pipe = intel_crtc->pipe;
  6445. /* pipesrc controls the size that is scaled from, which should
  6446. * always be the user's requested size.
  6447. */
  6448. I915_WRITE(PIPESRC(pipe),
  6449. ((intel_crtc->config->pipe_src_w - 1) << 16) |
  6450. (intel_crtc->config->pipe_src_h - 1));
  6451. }
  6452. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  6453. struct intel_crtc_state *pipe_config)
  6454. {
  6455. struct drm_device *dev = crtc->base.dev;
  6456. struct drm_i915_private *dev_priv = dev->dev_private;
  6457. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  6458. uint32_t tmp;
  6459. tmp = I915_READ(HTOTAL(cpu_transcoder));
  6460. pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  6461. pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  6462. tmp = I915_READ(HBLANK(cpu_transcoder));
  6463. pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  6464. pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  6465. tmp = I915_READ(HSYNC(cpu_transcoder));
  6466. pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  6467. pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  6468. tmp = I915_READ(VTOTAL(cpu_transcoder));
  6469. pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  6470. pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  6471. tmp = I915_READ(VBLANK(cpu_transcoder));
  6472. pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  6473. pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  6474. tmp = I915_READ(VSYNC(cpu_transcoder));
  6475. pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  6476. pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  6477. if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  6478. pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  6479. pipe_config->base.adjusted_mode.crtc_vtotal += 1;
  6480. pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
  6481. }
  6482. }
  6483. static void intel_get_pipe_src_size(struct intel_crtc *crtc,
  6484. struct intel_crtc_state *pipe_config)
  6485. {
  6486. struct drm_device *dev = crtc->base.dev;
  6487. struct drm_i915_private *dev_priv = dev->dev_private;
  6488. u32 tmp;
  6489. tmp = I915_READ(PIPESRC(crtc->pipe));
  6490. pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
  6491. pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
  6492. pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
  6493. pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
  6494. }
  6495. void intel_mode_from_pipe_config(struct drm_display_mode *mode,
  6496. struct intel_crtc_state *pipe_config)
  6497. {
  6498. mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
  6499. mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
  6500. mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
  6501. mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
  6502. mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
  6503. mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
  6504. mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
  6505. mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
  6506. mode->flags = pipe_config->base.adjusted_mode.flags;
  6507. mode->type = DRM_MODE_TYPE_DRIVER;
  6508. mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
  6509. mode->flags |= pipe_config->base.adjusted_mode.flags;
  6510. mode->hsync = drm_mode_hsync(mode);
  6511. mode->vrefresh = drm_mode_vrefresh(mode);
  6512. drm_mode_set_name(mode);
  6513. }
  6514. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  6515. {
  6516. struct drm_device *dev = intel_crtc->base.dev;
  6517. struct drm_i915_private *dev_priv = dev->dev_private;
  6518. uint32_t pipeconf;
  6519. pipeconf = 0;
  6520. if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  6521. (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  6522. pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
  6523. if (intel_crtc->config->double_wide)
  6524. pipeconf |= PIPECONF_DOUBLE_WIDE;
  6525. /* only g4x and later have fancy bpc/dither controls */
  6526. if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  6527. /* Bspec claims that we can't use dithering for 30bpp pipes. */
  6528. if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
  6529. pipeconf |= PIPECONF_DITHER_EN |
  6530. PIPECONF_DITHER_TYPE_SP;
  6531. switch (intel_crtc->config->pipe_bpp) {
  6532. case 18:
  6533. pipeconf |= PIPECONF_6BPC;
  6534. break;
  6535. case 24:
  6536. pipeconf |= PIPECONF_8BPC;
  6537. break;
  6538. case 30:
  6539. pipeconf |= PIPECONF_10BPC;
  6540. break;
  6541. default:
  6542. /* Case prevented by intel_choose_pipe_bpp_dither. */
  6543. BUG();
  6544. }
  6545. }
  6546. if (HAS_PIPE_CXSR(dev)) {
  6547. if (intel_crtc->lowfreq_avail) {
  6548. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  6549. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  6550. } else {
  6551. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  6552. }
  6553. }
  6554. if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
  6555. if (INTEL_INFO(dev)->gen < 4 ||
  6556. intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  6557. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  6558. else
  6559. pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
  6560. } else
  6561. pipeconf |= PIPECONF_PROGRESSIVE;
  6562. if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
  6563. intel_crtc->config->limited_color_range)
  6564. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  6565. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  6566. POSTING_READ(PIPECONF(intel_crtc->pipe));
  6567. }
  6568. static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
  6569. struct intel_crtc_state *crtc_state)
  6570. {
  6571. struct drm_device *dev = crtc->base.dev;
  6572. struct drm_i915_private *dev_priv = dev->dev_private;
  6573. const struct intel_limit *limit;
  6574. int refclk = 48000;
  6575. memset(&crtc_state->dpll_hw_state, 0,
  6576. sizeof(crtc_state->dpll_hw_state));
  6577. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  6578. if (intel_panel_use_ssc(dev_priv)) {
  6579. refclk = dev_priv->vbt.lvds_ssc_freq;
  6580. DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
  6581. }
  6582. limit = &intel_limits_i8xx_lvds;
  6583. } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
  6584. limit = &intel_limits_i8xx_dvo;
  6585. } else {
  6586. limit = &intel_limits_i8xx_dac;
  6587. }
  6588. if (!crtc_state->clock_set &&
  6589. !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6590. refclk, NULL, &crtc_state->dpll)) {
  6591. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6592. return -EINVAL;
  6593. }
  6594. i8xx_compute_dpll(crtc, crtc_state, NULL);
  6595. return 0;
  6596. }
  6597. static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
  6598. struct intel_crtc_state *crtc_state)
  6599. {
  6600. struct drm_device *dev = crtc->base.dev;
  6601. struct drm_i915_private *dev_priv = dev->dev_private;
  6602. const struct intel_limit *limit;
  6603. int refclk = 96000;
  6604. memset(&crtc_state->dpll_hw_state, 0,
  6605. sizeof(crtc_state->dpll_hw_state));
  6606. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  6607. if (intel_panel_use_ssc(dev_priv)) {
  6608. refclk = dev_priv->vbt.lvds_ssc_freq;
  6609. DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
  6610. }
  6611. if (intel_is_dual_link_lvds(dev))
  6612. limit = &intel_limits_g4x_dual_channel_lvds;
  6613. else
  6614. limit = &intel_limits_g4x_single_channel_lvds;
  6615. } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
  6616. intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
  6617. limit = &intel_limits_g4x_hdmi;
  6618. } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
  6619. limit = &intel_limits_g4x_sdvo;
  6620. } else {
  6621. /* The option is for other outputs */
  6622. limit = &intel_limits_i9xx_sdvo;
  6623. }
  6624. if (!crtc_state->clock_set &&
  6625. !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6626. refclk, NULL, &crtc_state->dpll)) {
  6627. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6628. return -EINVAL;
  6629. }
  6630. i9xx_compute_dpll(crtc, crtc_state, NULL);
  6631. return 0;
  6632. }
  6633. static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
  6634. struct intel_crtc_state *crtc_state)
  6635. {
  6636. struct drm_device *dev = crtc->base.dev;
  6637. struct drm_i915_private *dev_priv = dev->dev_private;
  6638. const struct intel_limit *limit;
  6639. int refclk = 96000;
  6640. memset(&crtc_state->dpll_hw_state, 0,
  6641. sizeof(crtc_state->dpll_hw_state));
  6642. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  6643. if (intel_panel_use_ssc(dev_priv)) {
  6644. refclk = dev_priv->vbt.lvds_ssc_freq;
  6645. DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
  6646. }
  6647. limit = &intel_limits_pineview_lvds;
  6648. } else {
  6649. limit = &intel_limits_pineview_sdvo;
  6650. }
  6651. if (!crtc_state->clock_set &&
  6652. !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6653. refclk, NULL, &crtc_state->dpll)) {
  6654. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6655. return -EINVAL;
  6656. }
  6657. i9xx_compute_dpll(crtc, crtc_state, NULL);
  6658. return 0;
  6659. }
  6660. static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
  6661. struct intel_crtc_state *crtc_state)
  6662. {
  6663. struct drm_device *dev = crtc->base.dev;
  6664. struct drm_i915_private *dev_priv = dev->dev_private;
  6665. const struct intel_limit *limit;
  6666. int refclk = 96000;
  6667. memset(&crtc_state->dpll_hw_state, 0,
  6668. sizeof(crtc_state->dpll_hw_state));
  6669. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  6670. if (intel_panel_use_ssc(dev_priv)) {
  6671. refclk = dev_priv->vbt.lvds_ssc_freq;
  6672. DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
  6673. }
  6674. limit = &intel_limits_i9xx_lvds;
  6675. } else {
  6676. limit = &intel_limits_i9xx_sdvo;
  6677. }
  6678. if (!crtc_state->clock_set &&
  6679. !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6680. refclk, NULL, &crtc_state->dpll)) {
  6681. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6682. return -EINVAL;
  6683. }
  6684. i9xx_compute_dpll(crtc, crtc_state, NULL);
  6685. return 0;
  6686. }
  6687. static int chv_crtc_compute_clock(struct intel_crtc *crtc,
  6688. struct intel_crtc_state *crtc_state)
  6689. {
  6690. int refclk = 100000;
  6691. const struct intel_limit *limit = &intel_limits_chv;
  6692. memset(&crtc_state->dpll_hw_state, 0,
  6693. sizeof(crtc_state->dpll_hw_state));
  6694. if (!crtc_state->clock_set &&
  6695. !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6696. refclk, NULL, &crtc_state->dpll)) {
  6697. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6698. return -EINVAL;
  6699. }
  6700. chv_compute_dpll(crtc, crtc_state);
  6701. return 0;
  6702. }
  6703. static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
  6704. struct intel_crtc_state *crtc_state)
  6705. {
  6706. int refclk = 100000;
  6707. const struct intel_limit *limit = &intel_limits_vlv;
  6708. memset(&crtc_state->dpll_hw_state, 0,
  6709. sizeof(crtc_state->dpll_hw_state));
  6710. if (!crtc_state->clock_set &&
  6711. !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  6712. refclk, NULL, &crtc_state->dpll)) {
  6713. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  6714. return -EINVAL;
  6715. }
  6716. vlv_compute_dpll(crtc, crtc_state);
  6717. return 0;
  6718. }
  6719. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  6720. struct intel_crtc_state *pipe_config)
  6721. {
  6722. struct drm_device *dev = crtc->base.dev;
  6723. struct drm_i915_private *dev_priv = dev->dev_private;
  6724. uint32_t tmp;
  6725. if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
  6726. return;
  6727. tmp = I915_READ(PFIT_CONTROL);
  6728. if (!(tmp & PFIT_ENABLE))
  6729. return;
  6730. /* Check whether the pfit is attached to our pipe. */
  6731. if (INTEL_INFO(dev)->gen < 4) {
  6732. if (crtc->pipe != PIPE_B)
  6733. return;
  6734. } else {
  6735. if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  6736. return;
  6737. }
  6738. pipe_config->gmch_pfit.control = tmp;
  6739. pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  6740. }
  6741. static void vlv_crtc_clock_get(struct intel_crtc *crtc,
  6742. struct intel_crtc_state *pipe_config)
  6743. {
  6744. struct drm_device *dev = crtc->base.dev;
  6745. struct drm_i915_private *dev_priv = dev->dev_private;
  6746. int pipe = pipe_config->cpu_transcoder;
  6747. struct dpll clock;
  6748. u32 mdiv;
  6749. int refclk = 100000;
  6750. /* In case of DSI, DPLL will not be used */
  6751. if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
  6752. return;
  6753. mutex_lock(&dev_priv->sb_lock);
  6754. mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
  6755. mutex_unlock(&dev_priv->sb_lock);
  6756. clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
  6757. clock.m2 = mdiv & DPIO_M2DIV_MASK;
  6758. clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
  6759. clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
  6760. clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
  6761. pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
  6762. }
  6763. static void
  6764. i9xx_get_initial_plane_config(struct intel_crtc *crtc,
  6765. struct intel_initial_plane_config *plane_config)
  6766. {
  6767. struct drm_device *dev = crtc->base.dev;
  6768. struct drm_i915_private *dev_priv = dev->dev_private;
  6769. u32 val, base, offset;
  6770. int pipe = crtc->pipe, plane = crtc->plane;
  6771. int fourcc, pixel_format;
  6772. unsigned int aligned_height;
  6773. struct drm_framebuffer *fb;
  6774. struct intel_framebuffer *intel_fb;
  6775. val = I915_READ(DSPCNTR(plane));
  6776. if (!(val & DISPLAY_PLANE_ENABLE))
  6777. return;
  6778. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  6779. if (!intel_fb) {
  6780. DRM_DEBUG_KMS("failed to alloc fb\n");
  6781. return;
  6782. }
  6783. fb = &intel_fb->base;
  6784. if (INTEL_INFO(dev)->gen >= 4) {
  6785. if (val & DISPPLANE_TILED) {
  6786. plane_config->tiling = I915_TILING_X;
  6787. fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  6788. }
  6789. }
  6790. pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
  6791. fourcc = i9xx_format_to_fourcc(pixel_format);
  6792. fb->pixel_format = fourcc;
  6793. fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  6794. if (INTEL_INFO(dev)->gen >= 4) {
  6795. if (plane_config->tiling)
  6796. offset = I915_READ(DSPTILEOFF(plane));
  6797. else
  6798. offset = I915_READ(DSPLINOFF(plane));
  6799. base = I915_READ(DSPSURF(plane)) & 0xfffff000;
  6800. } else {
  6801. base = I915_READ(DSPADDR(plane));
  6802. }
  6803. plane_config->base = base;
  6804. val = I915_READ(PIPESRC(pipe));
  6805. fb->width = ((val >> 16) & 0xfff) + 1;
  6806. fb->height = ((val >> 0) & 0xfff) + 1;
  6807. val = I915_READ(DSPSTRIDE(pipe));
  6808. fb->pitches[0] = val & 0xffffffc0;
  6809. aligned_height = intel_fb_align_height(dev, fb->height,
  6810. fb->pixel_format,
  6811. fb->modifier[0]);
  6812. plane_config->size = fb->pitches[0] * aligned_height;
  6813. DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  6814. pipe_name(pipe), plane, fb->width, fb->height,
  6815. fb->bits_per_pixel, base, fb->pitches[0],
  6816. plane_config->size);
  6817. plane_config->fb = intel_fb;
  6818. }
  6819. static void chv_crtc_clock_get(struct intel_crtc *crtc,
  6820. struct intel_crtc_state *pipe_config)
  6821. {
  6822. struct drm_device *dev = crtc->base.dev;
  6823. struct drm_i915_private *dev_priv = dev->dev_private;
  6824. int pipe = pipe_config->cpu_transcoder;
  6825. enum dpio_channel port = vlv_pipe_to_channel(pipe);
  6826. struct dpll clock;
  6827. u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
  6828. int refclk = 100000;
  6829. /* In case of DSI, DPLL will not be used */
  6830. if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
  6831. return;
  6832. mutex_lock(&dev_priv->sb_lock);
  6833. cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
  6834. pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
  6835. pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
  6836. pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
  6837. pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
  6838. mutex_unlock(&dev_priv->sb_lock);
  6839. clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
  6840. clock.m2 = (pll_dw0 & 0xff) << 22;
  6841. if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
  6842. clock.m2 |= pll_dw2 & 0x3fffff;
  6843. clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
  6844. clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
  6845. clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
  6846. pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
  6847. }
  6848. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  6849. struct intel_crtc_state *pipe_config)
  6850. {
  6851. struct drm_device *dev = crtc->base.dev;
  6852. struct drm_i915_private *dev_priv = dev->dev_private;
  6853. enum intel_display_power_domain power_domain;
  6854. uint32_t tmp;
  6855. bool ret;
  6856. power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
  6857. if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  6858. return false;
  6859. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  6860. pipe_config->shared_dpll = NULL;
  6861. ret = false;
  6862. tmp = I915_READ(PIPECONF(crtc->pipe));
  6863. if (!(tmp & PIPECONF_ENABLE))
  6864. goto out;
  6865. if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  6866. switch (tmp & PIPECONF_BPC_MASK) {
  6867. case PIPECONF_6BPC:
  6868. pipe_config->pipe_bpp = 18;
  6869. break;
  6870. case PIPECONF_8BPC:
  6871. pipe_config->pipe_bpp = 24;
  6872. break;
  6873. case PIPECONF_10BPC:
  6874. pipe_config->pipe_bpp = 30;
  6875. break;
  6876. default:
  6877. break;
  6878. }
  6879. }
  6880. if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
  6881. (tmp & PIPECONF_COLOR_RANGE_SELECT))
  6882. pipe_config->limited_color_range = true;
  6883. if (INTEL_INFO(dev)->gen < 4)
  6884. pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
  6885. intel_get_pipe_timings(crtc, pipe_config);
  6886. intel_get_pipe_src_size(crtc, pipe_config);
  6887. i9xx_get_pfit_config(crtc, pipe_config);
  6888. if (INTEL_INFO(dev)->gen >= 4) {
  6889. /* No way to read it out on pipes B and C */
  6890. if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
  6891. tmp = dev_priv->chv_dpll_md[crtc->pipe];
  6892. else
  6893. tmp = I915_READ(DPLL_MD(crtc->pipe));
  6894. pipe_config->pixel_multiplier =
  6895. ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  6896. >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  6897. pipe_config->dpll_hw_state.dpll_md = tmp;
  6898. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  6899. tmp = I915_READ(DPLL(crtc->pipe));
  6900. pipe_config->pixel_multiplier =
  6901. ((tmp & SDVO_MULTIPLIER_MASK)
  6902. >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  6903. } else {
  6904. /* Note that on i915G/GM the pixel multiplier is in the sdvo
  6905. * port and will be fixed up in the encoder->get_config
  6906. * function. */
  6907. pipe_config->pixel_multiplier = 1;
  6908. }
  6909. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  6910. if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
  6911. /*
  6912. * DPLL_DVO_2X_MODE must be enabled for both DPLLs
  6913. * on 830. Filter it out here so that we don't
  6914. * report errors due to that.
  6915. */
  6916. if (IS_I830(dev))
  6917. pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
  6918. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  6919. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  6920. } else {
  6921. /* Mask out read-only status bits. */
  6922. pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  6923. DPLL_PORTC_READY_MASK |
  6924. DPLL_PORTB_READY_MASK);
  6925. }
  6926. if (IS_CHERRYVIEW(dev))
  6927. chv_crtc_clock_get(crtc, pipe_config);
  6928. else if (IS_VALLEYVIEW(dev))
  6929. vlv_crtc_clock_get(crtc, pipe_config);
  6930. else
  6931. i9xx_crtc_clock_get(crtc, pipe_config);
  6932. /*
  6933. * Normally the dotclock is filled in by the encoder .get_config()
  6934. * but in case the pipe is enabled w/o any ports we need a sane
  6935. * default.
  6936. */
  6937. pipe_config->base.adjusted_mode.crtc_clock =
  6938. pipe_config->port_clock / pipe_config->pixel_multiplier;
  6939. ret = true;
  6940. out:
  6941. intel_display_power_put(dev_priv, power_domain);
  6942. return ret;
  6943. }
  6944. static void ironlake_init_pch_refclk(struct drm_device *dev)
  6945. {
  6946. struct drm_i915_private *dev_priv = dev->dev_private;
  6947. struct intel_encoder *encoder;
  6948. u32 val, final;
  6949. bool has_lvds = false;
  6950. bool has_cpu_edp = false;
  6951. bool has_panel = false;
  6952. bool has_ck505 = false;
  6953. bool can_ssc = false;
  6954. /* We need to take the global config into account */
  6955. for_each_intel_encoder(dev, encoder) {
  6956. switch (encoder->type) {
  6957. case INTEL_OUTPUT_LVDS:
  6958. has_panel = true;
  6959. has_lvds = true;
  6960. break;
  6961. case INTEL_OUTPUT_EDP:
  6962. has_panel = true;
  6963. if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  6964. has_cpu_edp = true;
  6965. break;
  6966. default:
  6967. break;
  6968. }
  6969. }
  6970. if (HAS_PCH_IBX(dev)) {
  6971. has_ck505 = dev_priv->vbt.display_clock_mode;
  6972. can_ssc = has_ck505;
  6973. } else {
  6974. has_ck505 = false;
  6975. can_ssc = true;
  6976. }
  6977. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  6978. has_panel, has_lvds, has_ck505);
  6979. /* Ironlake: try to setup display ref clock before DPLL
  6980. * enabling. This is only under driver's control after
  6981. * PCH B stepping, previous chipset stepping should be
  6982. * ignoring this setting.
  6983. */
  6984. val = I915_READ(PCH_DREF_CONTROL);
  6985. /* As we must carefully and slowly disable/enable each source in turn,
  6986. * compute the final state we want first and check if we need to
  6987. * make any changes at all.
  6988. */
  6989. final = val;
  6990. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  6991. if (has_ck505)
  6992. final |= DREF_NONSPREAD_CK505_ENABLE;
  6993. else
  6994. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  6995. final &= ~DREF_SSC_SOURCE_MASK;
  6996. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  6997. final &= ~DREF_SSC1_ENABLE;
  6998. if (has_panel) {
  6999. final |= DREF_SSC_SOURCE_ENABLE;
  7000. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  7001. final |= DREF_SSC1_ENABLE;
  7002. if (has_cpu_edp) {
  7003. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  7004. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  7005. else
  7006. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  7007. } else
  7008. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  7009. } else {
  7010. final |= DREF_SSC_SOURCE_DISABLE;
  7011. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  7012. }
  7013. if (final == val)
  7014. return;
  7015. /* Always enable nonspread source */
  7016. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  7017. if (has_ck505)
  7018. val |= DREF_NONSPREAD_CK505_ENABLE;
  7019. else
  7020. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  7021. if (has_panel) {
  7022. val &= ~DREF_SSC_SOURCE_MASK;
  7023. val |= DREF_SSC_SOURCE_ENABLE;
  7024. /* SSC must be turned on before enabling the CPU output */
  7025. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  7026. DRM_DEBUG_KMS("Using SSC on panel\n");
  7027. val |= DREF_SSC1_ENABLE;
  7028. } else
  7029. val &= ~DREF_SSC1_ENABLE;
  7030. /* Get SSC going before enabling the outputs */
  7031. I915_WRITE(PCH_DREF_CONTROL, val);
  7032. POSTING_READ(PCH_DREF_CONTROL);
  7033. udelay(200);
  7034. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  7035. /* Enable CPU source on CPU attached eDP */
  7036. if (has_cpu_edp) {
  7037. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  7038. DRM_DEBUG_KMS("Using SSC on eDP\n");
  7039. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  7040. } else
  7041. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  7042. } else
  7043. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  7044. I915_WRITE(PCH_DREF_CONTROL, val);
  7045. POSTING_READ(PCH_DREF_CONTROL);
  7046. udelay(200);
  7047. } else {
  7048. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  7049. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  7050. /* Turn off CPU output */
  7051. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  7052. I915_WRITE(PCH_DREF_CONTROL, val);
  7053. POSTING_READ(PCH_DREF_CONTROL);
  7054. udelay(200);
  7055. /* Turn off the SSC source */
  7056. val &= ~DREF_SSC_SOURCE_MASK;
  7057. val |= DREF_SSC_SOURCE_DISABLE;
  7058. /* Turn off SSC1 */
  7059. val &= ~DREF_SSC1_ENABLE;
  7060. I915_WRITE(PCH_DREF_CONTROL, val);
  7061. POSTING_READ(PCH_DREF_CONTROL);
  7062. udelay(200);
  7063. }
  7064. BUG_ON(val != final);
  7065. }
  7066. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  7067. {
  7068. uint32_t tmp;
  7069. tmp = I915_READ(SOUTH_CHICKEN2);
  7070. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  7071. I915_WRITE(SOUTH_CHICKEN2, tmp);
  7072. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  7073. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  7074. DRM_ERROR("FDI mPHY reset assert timeout\n");
  7075. tmp = I915_READ(SOUTH_CHICKEN2);
  7076. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  7077. I915_WRITE(SOUTH_CHICKEN2, tmp);
  7078. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  7079. FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  7080. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  7081. }
  7082. /* WaMPhyProgramming:hsw */
  7083. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  7084. {
  7085. uint32_t tmp;
  7086. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  7087. tmp &= ~(0xFF << 24);
  7088. tmp |= (0x12 << 24);
  7089. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  7090. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  7091. tmp |= (1 << 11);
  7092. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  7093. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  7094. tmp |= (1 << 11);
  7095. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  7096. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  7097. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  7098. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  7099. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  7100. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  7101. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  7102. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  7103. tmp &= ~(7 << 13);
  7104. tmp |= (5 << 13);
  7105. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  7106. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  7107. tmp &= ~(7 << 13);
  7108. tmp |= (5 << 13);
  7109. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  7110. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  7111. tmp &= ~0xFF;
  7112. tmp |= 0x1C;
  7113. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  7114. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  7115. tmp &= ~0xFF;
  7116. tmp |= 0x1C;
  7117. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  7118. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  7119. tmp &= ~(0xFF << 16);
  7120. tmp |= (0x1C << 16);
  7121. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  7122. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  7123. tmp &= ~(0xFF << 16);
  7124. tmp |= (0x1C << 16);
  7125. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  7126. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  7127. tmp |= (1 << 27);
  7128. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  7129. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  7130. tmp |= (1 << 27);
  7131. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  7132. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  7133. tmp &= ~(0xF << 28);
  7134. tmp |= (4 << 28);
  7135. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  7136. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  7137. tmp &= ~(0xF << 28);
  7138. tmp |= (4 << 28);
  7139. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  7140. }
  7141. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  7142. * Programming" based on the parameters passed:
  7143. * - Sequence to enable CLKOUT_DP
  7144. * - Sequence to enable CLKOUT_DP without spread
  7145. * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  7146. */
  7147. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  7148. bool with_fdi)
  7149. {
  7150. struct drm_i915_private *dev_priv = dev->dev_private;
  7151. uint32_t reg, tmp;
  7152. if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  7153. with_spread = true;
  7154. if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
  7155. with_fdi = false;
  7156. mutex_lock(&dev_priv->sb_lock);
  7157. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  7158. tmp &= ~SBI_SSCCTL_DISABLE;
  7159. tmp |= SBI_SSCCTL_PATHALT;
  7160. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  7161. udelay(24);
  7162. if (with_spread) {
  7163. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  7164. tmp &= ~SBI_SSCCTL_PATHALT;
  7165. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  7166. if (with_fdi) {
  7167. lpt_reset_fdi_mphy(dev_priv);
  7168. lpt_program_fdi_mphy(dev_priv);
  7169. }
  7170. }
  7171. reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
  7172. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  7173. tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  7174. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  7175. mutex_unlock(&dev_priv->sb_lock);
  7176. }
  7177. /* Sequence to disable CLKOUT_DP */
  7178. static void lpt_disable_clkout_dp(struct drm_device *dev)
  7179. {
  7180. struct drm_i915_private *dev_priv = dev->dev_private;
  7181. uint32_t reg, tmp;
  7182. mutex_lock(&dev_priv->sb_lock);
  7183. reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
  7184. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  7185. tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  7186. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  7187. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  7188. if (!(tmp & SBI_SSCCTL_DISABLE)) {
  7189. if (!(tmp & SBI_SSCCTL_PATHALT)) {
  7190. tmp |= SBI_SSCCTL_PATHALT;
  7191. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  7192. udelay(32);
  7193. }
  7194. tmp |= SBI_SSCCTL_DISABLE;
  7195. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  7196. }
  7197. mutex_unlock(&dev_priv->sb_lock);
  7198. }
  7199. #define BEND_IDX(steps) ((50 + (steps)) / 5)
  7200. static const uint16_t sscdivintphase[] = {
  7201. [BEND_IDX( 50)] = 0x3B23,
  7202. [BEND_IDX( 45)] = 0x3B23,
  7203. [BEND_IDX( 40)] = 0x3C23,
  7204. [BEND_IDX( 35)] = 0x3C23,
  7205. [BEND_IDX( 30)] = 0x3D23,
  7206. [BEND_IDX( 25)] = 0x3D23,
  7207. [BEND_IDX( 20)] = 0x3E23,
  7208. [BEND_IDX( 15)] = 0x3E23,
  7209. [BEND_IDX( 10)] = 0x3F23,
  7210. [BEND_IDX( 5)] = 0x3F23,
  7211. [BEND_IDX( 0)] = 0x0025,
  7212. [BEND_IDX( -5)] = 0x0025,
  7213. [BEND_IDX(-10)] = 0x0125,
  7214. [BEND_IDX(-15)] = 0x0125,
  7215. [BEND_IDX(-20)] = 0x0225,
  7216. [BEND_IDX(-25)] = 0x0225,
  7217. [BEND_IDX(-30)] = 0x0325,
  7218. [BEND_IDX(-35)] = 0x0325,
  7219. [BEND_IDX(-40)] = 0x0425,
  7220. [BEND_IDX(-45)] = 0x0425,
  7221. [BEND_IDX(-50)] = 0x0525,
  7222. };
  7223. /*
  7224. * Bend CLKOUT_DP
  7225. * steps -50 to 50 inclusive, in steps of 5
  7226. * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
  7227. * change in clock period = -(steps / 10) * 5.787 ps
  7228. */
  7229. static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
  7230. {
  7231. uint32_t tmp;
  7232. int idx = BEND_IDX(steps);
  7233. if (WARN_ON(steps % 5 != 0))
  7234. return;
  7235. if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
  7236. return;
  7237. mutex_lock(&dev_priv->sb_lock);
  7238. if (steps % 10 != 0)
  7239. tmp = 0xAAAAAAAB;
  7240. else
  7241. tmp = 0x00000000;
  7242. intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
  7243. tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
  7244. tmp &= 0xffff0000;
  7245. tmp |= sscdivintphase[idx];
  7246. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
  7247. mutex_unlock(&dev_priv->sb_lock);
  7248. }
  7249. #undef BEND_IDX
  7250. static void lpt_init_pch_refclk(struct drm_device *dev)
  7251. {
  7252. struct intel_encoder *encoder;
  7253. bool has_vga = false;
  7254. for_each_intel_encoder(dev, encoder) {
  7255. switch (encoder->type) {
  7256. case INTEL_OUTPUT_ANALOG:
  7257. has_vga = true;
  7258. break;
  7259. default:
  7260. break;
  7261. }
  7262. }
  7263. if (has_vga) {
  7264. lpt_bend_clkout_dp(to_i915(dev), 0);
  7265. lpt_enable_clkout_dp(dev, true, true);
  7266. } else {
  7267. lpt_disable_clkout_dp(dev);
  7268. }
  7269. }
  7270. /*
  7271. * Initialize reference clocks when the driver loads
  7272. */
  7273. void intel_init_pch_refclk(struct drm_device *dev)
  7274. {
  7275. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  7276. ironlake_init_pch_refclk(dev);
  7277. else if (HAS_PCH_LPT(dev))
  7278. lpt_init_pch_refclk(dev);
  7279. }
  7280. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  7281. {
  7282. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  7283. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7284. int pipe = intel_crtc->pipe;
  7285. uint32_t val;
  7286. val = 0;
  7287. switch (intel_crtc->config->pipe_bpp) {
  7288. case 18:
  7289. val |= PIPECONF_6BPC;
  7290. break;
  7291. case 24:
  7292. val |= PIPECONF_8BPC;
  7293. break;
  7294. case 30:
  7295. val |= PIPECONF_10BPC;
  7296. break;
  7297. case 36:
  7298. val |= PIPECONF_12BPC;
  7299. break;
  7300. default:
  7301. /* Case prevented by intel_choose_pipe_bpp_dither. */
  7302. BUG();
  7303. }
  7304. if (intel_crtc->config->dither)
  7305. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  7306. if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  7307. val |= PIPECONF_INTERLACED_ILK;
  7308. else
  7309. val |= PIPECONF_PROGRESSIVE;
  7310. if (intel_crtc->config->limited_color_range)
  7311. val |= PIPECONF_COLOR_RANGE_SELECT;
  7312. I915_WRITE(PIPECONF(pipe), val);
  7313. POSTING_READ(PIPECONF(pipe));
  7314. }
  7315. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  7316. {
  7317. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  7318. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7319. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  7320. u32 val = 0;
  7321. if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
  7322. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  7323. if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  7324. val |= PIPECONF_INTERLACED_ILK;
  7325. else
  7326. val |= PIPECONF_PROGRESSIVE;
  7327. I915_WRITE(PIPECONF(cpu_transcoder), val);
  7328. POSTING_READ(PIPECONF(cpu_transcoder));
  7329. }
  7330. static void haswell_set_pipemisc(struct drm_crtc *crtc)
  7331. {
  7332. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  7333. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  7334. if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
  7335. u32 val = 0;
  7336. switch (intel_crtc->config->pipe_bpp) {
  7337. case 18:
  7338. val |= PIPEMISC_DITHER_6_BPC;
  7339. break;
  7340. case 24:
  7341. val |= PIPEMISC_DITHER_8_BPC;
  7342. break;
  7343. case 30:
  7344. val |= PIPEMISC_DITHER_10_BPC;
  7345. break;
  7346. case 36:
  7347. val |= PIPEMISC_DITHER_12_BPC;
  7348. break;
  7349. default:
  7350. /* Case prevented by pipe_config_set_bpp. */
  7351. BUG();
  7352. }
  7353. if (intel_crtc->config->dither)
  7354. val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
  7355. I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
  7356. }
  7357. }
  7358. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  7359. {
  7360. /*
  7361. * Account for spread spectrum to avoid
  7362. * oversubscribing the link. Max center spread
  7363. * is 2.5%; use 5% for safety's sake.
  7364. */
  7365. u32 bps = target_clock * bpp * 21 / 20;
  7366. return DIV_ROUND_UP(bps, link_bw * 8);
  7367. }
  7368. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  7369. {
  7370. return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  7371. }
  7372. static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  7373. struct intel_crtc_state *crtc_state,
  7374. struct dpll *reduced_clock)
  7375. {
  7376. struct drm_crtc *crtc = &intel_crtc->base;
  7377. struct drm_device *dev = crtc->dev;
  7378. struct drm_i915_private *dev_priv = dev->dev_private;
  7379. struct drm_atomic_state *state = crtc_state->base.state;
  7380. struct drm_connector *connector;
  7381. struct drm_connector_state *connector_state;
  7382. struct intel_encoder *encoder;
  7383. u32 dpll, fp, fp2;
  7384. int factor, i;
  7385. bool is_lvds = false, is_sdvo = false;
  7386. for_each_connector_in_state(state, connector, connector_state, i) {
  7387. if (connector_state->crtc != crtc_state->base.crtc)
  7388. continue;
  7389. encoder = to_intel_encoder(connector_state->best_encoder);
  7390. switch (encoder->type) {
  7391. case INTEL_OUTPUT_LVDS:
  7392. is_lvds = true;
  7393. break;
  7394. case INTEL_OUTPUT_SDVO:
  7395. case INTEL_OUTPUT_HDMI:
  7396. is_sdvo = true;
  7397. break;
  7398. default:
  7399. break;
  7400. }
  7401. }
  7402. /* Enable autotuning of the PLL clock (if permissible) */
  7403. factor = 21;
  7404. if (is_lvds) {
  7405. if ((intel_panel_use_ssc(dev_priv) &&
  7406. dev_priv->vbt.lvds_ssc_freq == 100000) ||
  7407. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  7408. factor = 25;
  7409. } else if (crtc_state->sdvo_tv_clock)
  7410. factor = 20;
  7411. fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
  7412. if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
  7413. fp |= FP_CB_TUNE;
  7414. if (reduced_clock) {
  7415. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  7416. if (reduced_clock->m < factor * reduced_clock->n)
  7417. fp2 |= FP_CB_TUNE;
  7418. } else {
  7419. fp2 = fp;
  7420. }
  7421. dpll = 0;
  7422. if (is_lvds)
  7423. dpll |= DPLLB_MODE_LVDS;
  7424. else
  7425. dpll |= DPLLB_MODE_DAC_SERIAL;
  7426. dpll |= (crtc_state->pixel_multiplier - 1)
  7427. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  7428. if (is_sdvo)
  7429. dpll |= DPLL_SDVO_HIGH_SPEED;
  7430. if (crtc_state->has_dp_encoder)
  7431. dpll |= DPLL_SDVO_HIGH_SPEED;
  7432. /* compute bitmask from p1 value */
  7433. dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  7434. /* also FPA1 */
  7435. dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  7436. switch (crtc_state->dpll.p2) {
  7437. case 5:
  7438. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  7439. break;
  7440. case 7:
  7441. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  7442. break;
  7443. case 10:
  7444. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  7445. break;
  7446. case 14:
  7447. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  7448. break;
  7449. }
  7450. if (is_lvds && intel_panel_use_ssc(dev_priv))
  7451. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  7452. else
  7453. dpll |= PLL_REF_INPUT_DREFCLK;
  7454. dpll |= DPLL_VCO_ENABLE;
  7455. crtc_state->dpll_hw_state.dpll = dpll;
  7456. crtc_state->dpll_hw_state.fp0 = fp;
  7457. crtc_state->dpll_hw_state.fp1 = fp2;
  7458. }
  7459. static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
  7460. struct intel_crtc_state *crtc_state)
  7461. {
  7462. struct drm_device *dev = crtc->base.dev;
  7463. struct drm_i915_private *dev_priv = dev->dev_private;
  7464. struct dpll reduced_clock;
  7465. bool has_reduced_clock = false;
  7466. struct intel_shared_dpll *pll;
  7467. const struct intel_limit *limit;
  7468. int refclk = 120000;
  7469. memset(&crtc_state->dpll_hw_state, 0,
  7470. sizeof(crtc_state->dpll_hw_state));
  7471. crtc->lowfreq_avail = false;
  7472. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  7473. if (!crtc_state->has_pch_encoder)
  7474. return 0;
  7475. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  7476. if (intel_panel_use_ssc(dev_priv)) {
  7477. DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
  7478. dev_priv->vbt.lvds_ssc_freq);
  7479. refclk = dev_priv->vbt.lvds_ssc_freq;
  7480. }
  7481. if (intel_is_dual_link_lvds(dev)) {
  7482. if (refclk == 100000)
  7483. limit = &intel_limits_ironlake_dual_lvds_100m;
  7484. else
  7485. limit = &intel_limits_ironlake_dual_lvds;
  7486. } else {
  7487. if (refclk == 100000)
  7488. limit = &intel_limits_ironlake_single_lvds_100m;
  7489. else
  7490. limit = &intel_limits_ironlake_single_lvds;
  7491. }
  7492. } else {
  7493. limit = &intel_limits_ironlake_dac;
  7494. }
  7495. if (!crtc_state->clock_set &&
  7496. !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
  7497. refclk, NULL, &crtc_state->dpll)) {
  7498. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  7499. return -EINVAL;
  7500. }
  7501. ironlake_compute_dpll(crtc, crtc_state,
  7502. has_reduced_clock ? &reduced_clock : NULL);
  7503. pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
  7504. if (pll == NULL) {
  7505. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  7506. pipe_name(crtc->pipe));
  7507. return -EINVAL;
  7508. }
  7509. if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  7510. has_reduced_clock)
  7511. crtc->lowfreq_avail = true;
  7512. return 0;
  7513. }
  7514. static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
  7515. struct intel_link_m_n *m_n)
  7516. {
  7517. struct drm_device *dev = crtc->base.dev;
  7518. struct drm_i915_private *dev_priv = dev->dev_private;
  7519. enum pipe pipe = crtc->pipe;
  7520. m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
  7521. m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
  7522. m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
  7523. & ~TU_SIZE_MASK;
  7524. m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
  7525. m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
  7526. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  7527. }
  7528. static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
  7529. enum transcoder transcoder,
  7530. struct intel_link_m_n *m_n,
  7531. struct intel_link_m_n *m2_n2)
  7532. {
  7533. struct drm_device *dev = crtc->base.dev;
  7534. struct drm_i915_private *dev_priv = dev->dev_private;
  7535. enum pipe pipe = crtc->pipe;
  7536. if (INTEL_INFO(dev)->gen >= 5) {
  7537. m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
  7538. m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
  7539. m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  7540. & ~TU_SIZE_MASK;
  7541. m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  7542. m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  7543. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  7544. /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
  7545. * gen < 8) and if DRRS is supported (to make sure the
  7546. * registers are not unnecessarily read).
  7547. */
  7548. if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
  7549. crtc->config->has_drrs) {
  7550. m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
  7551. m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
  7552. m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
  7553. & ~TU_SIZE_MASK;
  7554. m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
  7555. m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
  7556. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  7557. }
  7558. } else {
  7559. m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
  7560. m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
  7561. m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
  7562. & ~TU_SIZE_MASK;
  7563. m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
  7564. m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
  7565. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  7566. }
  7567. }
  7568. void intel_dp_get_m_n(struct intel_crtc *crtc,
  7569. struct intel_crtc_state *pipe_config)
  7570. {
  7571. if (pipe_config->has_pch_encoder)
  7572. intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
  7573. else
  7574. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  7575. &pipe_config->dp_m_n,
  7576. &pipe_config->dp_m2_n2);
  7577. }
  7578. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  7579. struct intel_crtc_state *pipe_config)
  7580. {
  7581. intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  7582. &pipe_config->fdi_m_n, NULL);
  7583. }
  7584. static void skylake_get_pfit_config(struct intel_crtc *crtc,
  7585. struct intel_crtc_state *pipe_config)
  7586. {
  7587. struct drm_device *dev = crtc->base.dev;
  7588. struct drm_i915_private *dev_priv = dev->dev_private;
  7589. struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
  7590. uint32_t ps_ctrl = 0;
  7591. int id = -1;
  7592. int i;
  7593. /* find scaler attached to this pipe */
  7594. for (i = 0; i < crtc->num_scalers; i++) {
  7595. ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
  7596. if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
  7597. id = i;
  7598. pipe_config->pch_pfit.enabled = true;
  7599. pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
  7600. pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
  7601. break;
  7602. }
  7603. }
  7604. scaler_state->scaler_id = id;
  7605. if (id >= 0) {
  7606. scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
  7607. } else {
  7608. scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
  7609. }
  7610. }
  7611. static void
  7612. skylake_get_initial_plane_config(struct intel_crtc *crtc,
  7613. struct intel_initial_plane_config *plane_config)
  7614. {
  7615. struct drm_device *dev = crtc->base.dev;
  7616. struct drm_i915_private *dev_priv = dev->dev_private;
  7617. u32 val, base, offset, stride_mult, tiling;
  7618. int pipe = crtc->pipe;
  7619. int fourcc, pixel_format;
  7620. unsigned int aligned_height;
  7621. struct drm_framebuffer *fb;
  7622. struct intel_framebuffer *intel_fb;
  7623. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  7624. if (!intel_fb) {
  7625. DRM_DEBUG_KMS("failed to alloc fb\n");
  7626. return;
  7627. }
  7628. fb = &intel_fb->base;
  7629. val = I915_READ(PLANE_CTL(pipe, 0));
  7630. if (!(val & PLANE_CTL_ENABLE))
  7631. goto error;
  7632. pixel_format = val & PLANE_CTL_FORMAT_MASK;
  7633. fourcc = skl_format_to_fourcc(pixel_format,
  7634. val & PLANE_CTL_ORDER_RGBX,
  7635. val & PLANE_CTL_ALPHA_MASK);
  7636. fb->pixel_format = fourcc;
  7637. fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  7638. tiling = val & PLANE_CTL_TILED_MASK;
  7639. switch (tiling) {
  7640. case PLANE_CTL_TILED_LINEAR:
  7641. fb->modifier[0] = DRM_FORMAT_MOD_NONE;
  7642. break;
  7643. case PLANE_CTL_TILED_X:
  7644. plane_config->tiling = I915_TILING_X;
  7645. fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  7646. break;
  7647. case PLANE_CTL_TILED_Y:
  7648. fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
  7649. break;
  7650. case PLANE_CTL_TILED_YF:
  7651. fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
  7652. break;
  7653. default:
  7654. MISSING_CASE(tiling);
  7655. goto error;
  7656. }
  7657. base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
  7658. plane_config->base = base;
  7659. offset = I915_READ(PLANE_OFFSET(pipe, 0));
  7660. val = I915_READ(PLANE_SIZE(pipe, 0));
  7661. fb->height = ((val >> 16) & 0xfff) + 1;
  7662. fb->width = ((val >> 0) & 0x1fff) + 1;
  7663. val = I915_READ(PLANE_STRIDE(pipe, 0));
  7664. stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
  7665. fb->pixel_format);
  7666. fb->pitches[0] = (val & 0x3ff) * stride_mult;
  7667. aligned_height = intel_fb_align_height(dev, fb->height,
  7668. fb->pixel_format,
  7669. fb->modifier[0]);
  7670. plane_config->size = fb->pitches[0] * aligned_height;
  7671. DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  7672. pipe_name(pipe), fb->width, fb->height,
  7673. fb->bits_per_pixel, base, fb->pitches[0],
  7674. plane_config->size);
  7675. plane_config->fb = intel_fb;
  7676. return;
  7677. error:
  7678. kfree(fb);
  7679. }
  7680. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  7681. struct intel_crtc_state *pipe_config)
  7682. {
  7683. struct drm_device *dev = crtc->base.dev;
  7684. struct drm_i915_private *dev_priv = dev->dev_private;
  7685. uint32_t tmp;
  7686. tmp = I915_READ(PF_CTL(crtc->pipe));
  7687. if (tmp & PF_ENABLE) {
  7688. pipe_config->pch_pfit.enabled = true;
  7689. pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  7690. pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  7691. /* We currently do not free assignements of panel fitters on
  7692. * ivb/hsw (since we don't use the higher upscaling modes which
  7693. * differentiates them) so just WARN about this case for now. */
  7694. if (IS_GEN7(dev)) {
  7695. WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  7696. PF_PIPE_SEL_IVB(crtc->pipe));
  7697. }
  7698. }
  7699. }
  7700. static void
  7701. ironlake_get_initial_plane_config(struct intel_crtc *crtc,
  7702. struct intel_initial_plane_config *plane_config)
  7703. {
  7704. struct drm_device *dev = crtc->base.dev;
  7705. struct drm_i915_private *dev_priv = dev->dev_private;
  7706. u32 val, base, offset;
  7707. int pipe = crtc->pipe;
  7708. int fourcc, pixel_format;
  7709. unsigned int aligned_height;
  7710. struct drm_framebuffer *fb;
  7711. struct intel_framebuffer *intel_fb;
  7712. val = I915_READ(DSPCNTR(pipe));
  7713. if (!(val & DISPLAY_PLANE_ENABLE))
  7714. return;
  7715. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  7716. if (!intel_fb) {
  7717. DRM_DEBUG_KMS("failed to alloc fb\n");
  7718. return;
  7719. }
  7720. fb = &intel_fb->base;
  7721. if (INTEL_INFO(dev)->gen >= 4) {
  7722. if (val & DISPPLANE_TILED) {
  7723. plane_config->tiling = I915_TILING_X;
  7724. fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  7725. }
  7726. }
  7727. pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
  7728. fourcc = i9xx_format_to_fourcc(pixel_format);
  7729. fb->pixel_format = fourcc;
  7730. fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  7731. base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
  7732. if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  7733. offset = I915_READ(DSPOFFSET(pipe));
  7734. } else {
  7735. if (plane_config->tiling)
  7736. offset = I915_READ(DSPTILEOFF(pipe));
  7737. else
  7738. offset = I915_READ(DSPLINOFF(pipe));
  7739. }
  7740. plane_config->base = base;
  7741. val = I915_READ(PIPESRC(pipe));
  7742. fb->width = ((val >> 16) & 0xfff) + 1;
  7743. fb->height = ((val >> 0) & 0xfff) + 1;
  7744. val = I915_READ(DSPSTRIDE(pipe));
  7745. fb->pitches[0] = val & 0xffffffc0;
  7746. aligned_height = intel_fb_align_height(dev, fb->height,
  7747. fb->pixel_format,
  7748. fb->modifier[0]);
  7749. plane_config->size = fb->pitches[0] * aligned_height;
  7750. DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  7751. pipe_name(pipe), fb->width, fb->height,
  7752. fb->bits_per_pixel, base, fb->pitches[0],
  7753. plane_config->size);
  7754. plane_config->fb = intel_fb;
  7755. }
  7756. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  7757. struct intel_crtc_state *pipe_config)
  7758. {
  7759. struct drm_device *dev = crtc->base.dev;
  7760. struct drm_i915_private *dev_priv = dev->dev_private;
  7761. enum intel_display_power_domain power_domain;
  7762. uint32_t tmp;
  7763. bool ret;
  7764. power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
  7765. if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  7766. return false;
  7767. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  7768. pipe_config->shared_dpll = NULL;
  7769. ret = false;
  7770. tmp = I915_READ(PIPECONF(crtc->pipe));
  7771. if (!(tmp & PIPECONF_ENABLE))
  7772. goto out;
  7773. switch (tmp & PIPECONF_BPC_MASK) {
  7774. case PIPECONF_6BPC:
  7775. pipe_config->pipe_bpp = 18;
  7776. break;
  7777. case PIPECONF_8BPC:
  7778. pipe_config->pipe_bpp = 24;
  7779. break;
  7780. case PIPECONF_10BPC:
  7781. pipe_config->pipe_bpp = 30;
  7782. break;
  7783. case PIPECONF_12BPC:
  7784. pipe_config->pipe_bpp = 36;
  7785. break;
  7786. default:
  7787. break;
  7788. }
  7789. if (tmp & PIPECONF_COLOR_RANGE_SELECT)
  7790. pipe_config->limited_color_range = true;
  7791. if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  7792. struct intel_shared_dpll *pll;
  7793. enum intel_dpll_id pll_id;
  7794. pipe_config->has_pch_encoder = true;
  7795. tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  7796. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  7797. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  7798. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  7799. if (HAS_PCH_IBX(dev_priv)) {
  7800. /*
  7801. * The pipe->pch transcoder and pch transcoder->pll
  7802. * mapping is fixed.
  7803. */
  7804. pll_id = (enum intel_dpll_id) crtc->pipe;
  7805. } else {
  7806. tmp = I915_READ(PCH_DPLL_SEL);
  7807. if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  7808. pll_id = DPLL_ID_PCH_PLL_B;
  7809. else
  7810. pll_id= DPLL_ID_PCH_PLL_A;
  7811. }
  7812. pipe_config->shared_dpll =
  7813. intel_get_shared_dpll_by_id(dev_priv, pll_id);
  7814. pll = pipe_config->shared_dpll;
  7815. WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
  7816. &pipe_config->dpll_hw_state));
  7817. tmp = pipe_config->dpll_hw_state.dpll;
  7818. pipe_config->pixel_multiplier =
  7819. ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  7820. >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  7821. ironlake_pch_clock_get(crtc, pipe_config);
  7822. } else {
  7823. pipe_config->pixel_multiplier = 1;
  7824. }
  7825. intel_get_pipe_timings(crtc, pipe_config);
  7826. intel_get_pipe_src_size(crtc, pipe_config);
  7827. ironlake_get_pfit_config(crtc, pipe_config);
  7828. ret = true;
  7829. out:
  7830. intel_display_power_put(dev_priv, power_domain);
  7831. return ret;
  7832. }
  7833. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  7834. {
  7835. struct drm_device *dev = dev_priv->dev;
  7836. struct intel_crtc *crtc;
  7837. for_each_intel_crtc(dev, crtc)
  7838. I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
  7839. pipe_name(crtc->pipe));
  7840. I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  7841. I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
  7842. I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
  7843. I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
  7844. I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  7845. I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  7846. "CPU PWM1 enabled\n");
  7847. if (IS_HASWELL(dev))
  7848. I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  7849. "CPU PWM2 enabled\n");
  7850. I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  7851. "PCH PWM1 enabled\n");
  7852. I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  7853. "Utility pin enabled\n");
  7854. I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  7855. /*
  7856. * In theory we can still leave IRQs enabled, as long as only the HPD
  7857. * interrupts remain enabled. We used to check for that, but since it's
  7858. * gen-specific and since we only disable LCPLL after we fully disable
  7859. * the interrupts, the check below should be enough.
  7860. */
  7861. I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
  7862. }
  7863. static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
  7864. {
  7865. struct drm_device *dev = dev_priv->dev;
  7866. if (IS_HASWELL(dev))
  7867. return I915_READ(D_COMP_HSW);
  7868. else
  7869. return I915_READ(D_COMP_BDW);
  7870. }
  7871. static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
  7872. {
  7873. struct drm_device *dev = dev_priv->dev;
  7874. if (IS_HASWELL(dev)) {
  7875. mutex_lock(&dev_priv->rps.hw_lock);
  7876. if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
  7877. val))
  7878. DRM_ERROR("Failed to write to D_COMP\n");
  7879. mutex_unlock(&dev_priv->rps.hw_lock);
  7880. } else {
  7881. I915_WRITE(D_COMP_BDW, val);
  7882. POSTING_READ(D_COMP_BDW);
  7883. }
  7884. }
  7885. /*
  7886. * This function implements pieces of two sequences from BSpec:
  7887. * - Sequence for display software to disable LCPLL
  7888. * - Sequence for display software to allow package C8+
  7889. * The steps implemented here are just the steps that actually touch the LCPLL
  7890. * register. Callers should take care of disabling all the display engine
  7891. * functions, doing the mode unset, fixing interrupts, etc.
  7892. */
  7893. static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  7894. bool switch_to_fclk, bool allow_power_down)
  7895. {
  7896. uint32_t val;
  7897. assert_can_disable_lcpll(dev_priv);
  7898. val = I915_READ(LCPLL_CTL);
  7899. if (switch_to_fclk) {
  7900. val |= LCPLL_CD_SOURCE_FCLK;
  7901. I915_WRITE(LCPLL_CTL, val);
  7902. if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  7903. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  7904. DRM_ERROR("Switching to FCLK failed\n");
  7905. val = I915_READ(LCPLL_CTL);
  7906. }
  7907. val |= LCPLL_PLL_DISABLE;
  7908. I915_WRITE(LCPLL_CTL, val);
  7909. POSTING_READ(LCPLL_CTL);
  7910. if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  7911. DRM_ERROR("LCPLL still locked\n");
  7912. val = hsw_read_dcomp(dev_priv);
  7913. val |= D_COMP_COMP_DISABLE;
  7914. hsw_write_dcomp(dev_priv, val);
  7915. ndelay(100);
  7916. if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
  7917. 1))
  7918. DRM_ERROR("D_COMP RCOMP still in progress\n");
  7919. if (allow_power_down) {
  7920. val = I915_READ(LCPLL_CTL);
  7921. val |= LCPLL_POWER_DOWN_ALLOW;
  7922. I915_WRITE(LCPLL_CTL, val);
  7923. POSTING_READ(LCPLL_CTL);
  7924. }
  7925. }
  7926. /*
  7927. * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  7928. * source.
  7929. */
  7930. static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  7931. {
  7932. uint32_t val;
  7933. val = I915_READ(LCPLL_CTL);
  7934. if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  7935. LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  7936. return;
  7937. /*
  7938. * Make sure we're not on PC8 state before disabling PC8, otherwise
  7939. * we'll hang the machine. To prevent PC8 state, just enable force_wake.
  7940. */
  7941. intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  7942. if (val & LCPLL_POWER_DOWN_ALLOW) {
  7943. val &= ~LCPLL_POWER_DOWN_ALLOW;
  7944. I915_WRITE(LCPLL_CTL, val);
  7945. POSTING_READ(LCPLL_CTL);
  7946. }
  7947. val = hsw_read_dcomp(dev_priv);
  7948. val |= D_COMP_COMP_FORCE;
  7949. val &= ~D_COMP_COMP_DISABLE;
  7950. hsw_write_dcomp(dev_priv, val);
  7951. val = I915_READ(LCPLL_CTL);
  7952. val &= ~LCPLL_PLL_DISABLE;
  7953. I915_WRITE(LCPLL_CTL, val);
  7954. if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  7955. DRM_ERROR("LCPLL not locked yet\n");
  7956. if (val & LCPLL_CD_SOURCE_FCLK) {
  7957. val = I915_READ(LCPLL_CTL);
  7958. val &= ~LCPLL_CD_SOURCE_FCLK;
  7959. I915_WRITE(LCPLL_CTL, val);
  7960. if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  7961. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  7962. DRM_ERROR("Switching back to LCPLL failed\n");
  7963. }
  7964. intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  7965. intel_update_cdclk(dev_priv->dev);
  7966. }
  7967. /*
  7968. * Package states C8 and deeper are really deep PC states that can only be
  7969. * reached when all the devices on the system allow it, so even if the graphics
  7970. * device allows PC8+, it doesn't mean the system will actually get to these
  7971. * states. Our driver only allows PC8+ when going into runtime PM.
  7972. *
  7973. * The requirements for PC8+ are that all the outputs are disabled, the power
  7974. * well is disabled and most interrupts are disabled, and these are also
  7975. * requirements for runtime PM. When these conditions are met, we manually do
  7976. * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
  7977. * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
  7978. * hang the machine.
  7979. *
  7980. * When we really reach PC8 or deeper states (not just when we allow it) we lose
  7981. * the state of some registers, so when we come back from PC8+ we need to
  7982. * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
  7983. * need to take care of the registers kept by RC6. Notice that this happens even
  7984. * if we don't put the device in PCI D3 state (which is what currently happens
  7985. * because of the runtime PM support).
  7986. *
  7987. * For more, read "Display Sequences for Package C8" on the hardware
  7988. * documentation.
  7989. */
  7990. void hsw_enable_pc8(struct drm_i915_private *dev_priv)
  7991. {
  7992. struct drm_device *dev = dev_priv->dev;
  7993. uint32_t val;
  7994. DRM_DEBUG_KMS("Enabling package C8+\n");
  7995. if (HAS_PCH_LPT_LP(dev)) {
  7996. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  7997. val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  7998. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  7999. }
  8000. lpt_disable_clkout_dp(dev);
  8001. hsw_disable_lcpll(dev_priv, true, true);
  8002. }
  8003. void hsw_disable_pc8(struct drm_i915_private *dev_priv)
  8004. {
  8005. struct drm_device *dev = dev_priv->dev;
  8006. uint32_t val;
  8007. DRM_DEBUG_KMS("Disabling package C8+\n");
  8008. hsw_restore_lcpll(dev_priv);
  8009. lpt_init_pch_refclk(dev);
  8010. if (HAS_PCH_LPT_LP(dev)) {
  8011. val = I915_READ(SOUTH_DSPCLK_GATE_D);
  8012. val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  8013. I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  8014. }
  8015. }
  8016. static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  8017. {
  8018. struct drm_device *dev = old_state->dev;
  8019. struct intel_atomic_state *old_intel_state =
  8020. to_intel_atomic_state(old_state);
  8021. unsigned int req_cdclk = old_intel_state->dev_cdclk;
  8022. broxton_set_cdclk(to_i915(dev), req_cdclk);
  8023. }
  8024. /* compute the max rate for new configuration */
  8025. static int ilk_max_pixel_rate(struct drm_atomic_state *state)
  8026. {
  8027. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  8028. struct drm_i915_private *dev_priv = state->dev->dev_private;
  8029. struct drm_crtc *crtc;
  8030. struct drm_crtc_state *cstate;
  8031. struct intel_crtc_state *crtc_state;
  8032. unsigned max_pixel_rate = 0, i;
  8033. enum pipe pipe;
  8034. memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
  8035. sizeof(intel_state->min_pixclk));
  8036. for_each_crtc_in_state(state, crtc, cstate, i) {
  8037. int pixel_rate;
  8038. crtc_state = to_intel_crtc_state(cstate);
  8039. if (!crtc_state->base.enable) {
  8040. intel_state->min_pixclk[i] = 0;
  8041. continue;
  8042. }
  8043. pixel_rate = ilk_pipe_pixel_rate(crtc_state);
  8044. /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
  8045. if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
  8046. pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
  8047. intel_state->min_pixclk[i] = pixel_rate;
  8048. }
  8049. for_each_pipe(dev_priv, pipe)
  8050. max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
  8051. return max_pixel_rate;
  8052. }
  8053. static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
  8054. {
  8055. struct drm_i915_private *dev_priv = dev->dev_private;
  8056. uint32_t val, data;
  8057. int ret;
  8058. if (WARN((I915_READ(LCPLL_CTL) &
  8059. (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
  8060. LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
  8061. LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
  8062. LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
  8063. "trying to change cdclk frequency with cdclk not enabled\n"))
  8064. return;
  8065. mutex_lock(&dev_priv->rps.hw_lock);
  8066. ret = sandybridge_pcode_write(dev_priv,
  8067. BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
  8068. mutex_unlock(&dev_priv->rps.hw_lock);
  8069. if (ret) {
  8070. DRM_ERROR("failed to inform pcode about cdclk change\n");
  8071. return;
  8072. }
  8073. val = I915_READ(LCPLL_CTL);
  8074. val |= LCPLL_CD_SOURCE_FCLK;
  8075. I915_WRITE(LCPLL_CTL, val);
  8076. if (wait_for_us(I915_READ(LCPLL_CTL) &
  8077. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  8078. DRM_ERROR("Switching to FCLK failed\n");
  8079. val = I915_READ(LCPLL_CTL);
  8080. val &= ~LCPLL_CLK_FREQ_MASK;
  8081. switch (cdclk) {
  8082. case 450000:
  8083. val |= LCPLL_CLK_FREQ_450;
  8084. data = 0;
  8085. break;
  8086. case 540000:
  8087. val |= LCPLL_CLK_FREQ_54O_BDW;
  8088. data = 1;
  8089. break;
  8090. case 337500:
  8091. val |= LCPLL_CLK_FREQ_337_5_BDW;
  8092. data = 2;
  8093. break;
  8094. case 675000:
  8095. val |= LCPLL_CLK_FREQ_675_BDW;
  8096. data = 3;
  8097. break;
  8098. default:
  8099. WARN(1, "invalid cdclk frequency\n");
  8100. return;
  8101. }
  8102. I915_WRITE(LCPLL_CTL, val);
  8103. val = I915_READ(LCPLL_CTL);
  8104. val &= ~LCPLL_CD_SOURCE_FCLK;
  8105. I915_WRITE(LCPLL_CTL, val);
  8106. if (wait_for_us((I915_READ(LCPLL_CTL) &
  8107. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  8108. DRM_ERROR("Switching back to LCPLL failed\n");
  8109. mutex_lock(&dev_priv->rps.hw_lock);
  8110. sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
  8111. mutex_unlock(&dev_priv->rps.hw_lock);
  8112. I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
  8113. intel_update_cdclk(dev);
  8114. WARN(cdclk != dev_priv->cdclk_freq,
  8115. "cdclk requested %d kHz but got %d kHz\n",
  8116. cdclk, dev_priv->cdclk_freq);
  8117. }
  8118. static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
  8119. {
  8120. struct drm_i915_private *dev_priv = to_i915(state->dev);
  8121. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  8122. int max_pixclk = ilk_max_pixel_rate(state);
  8123. int cdclk;
  8124. /*
  8125. * FIXME should also account for plane ratio
  8126. * once 64bpp pixel formats are supported.
  8127. */
  8128. if (max_pixclk > 540000)
  8129. cdclk = 675000;
  8130. else if (max_pixclk > 450000)
  8131. cdclk = 540000;
  8132. else if (max_pixclk > 337500)
  8133. cdclk = 450000;
  8134. else
  8135. cdclk = 337500;
  8136. if (cdclk > dev_priv->max_cdclk_freq) {
  8137. DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
  8138. cdclk, dev_priv->max_cdclk_freq);
  8139. return -EINVAL;
  8140. }
  8141. intel_state->cdclk = intel_state->dev_cdclk = cdclk;
  8142. if (!intel_state->active_crtcs)
  8143. intel_state->dev_cdclk = 337500;
  8144. return 0;
  8145. }
  8146. static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  8147. {
  8148. struct drm_device *dev = old_state->dev;
  8149. struct intel_atomic_state *old_intel_state =
  8150. to_intel_atomic_state(old_state);
  8151. unsigned req_cdclk = old_intel_state->dev_cdclk;
  8152. broadwell_set_cdclk(dev, req_cdclk);
  8153. }
  8154. static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
  8155. struct intel_crtc_state *crtc_state)
  8156. {
  8157. struct intel_encoder *intel_encoder =
  8158. intel_ddi_get_crtc_new_encoder(crtc_state);
  8159. if (intel_encoder->type != INTEL_OUTPUT_DSI) {
  8160. if (!intel_ddi_pll_select(crtc, crtc_state))
  8161. return -EINVAL;
  8162. }
  8163. crtc->lowfreq_avail = false;
  8164. return 0;
  8165. }
  8166. static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
  8167. enum port port,
  8168. struct intel_crtc_state *pipe_config)
  8169. {
  8170. enum intel_dpll_id id;
  8171. switch (port) {
  8172. case PORT_A:
  8173. pipe_config->ddi_pll_sel = SKL_DPLL0;
  8174. id = DPLL_ID_SKL_DPLL0;
  8175. break;
  8176. case PORT_B:
  8177. pipe_config->ddi_pll_sel = SKL_DPLL1;
  8178. id = DPLL_ID_SKL_DPLL1;
  8179. break;
  8180. case PORT_C:
  8181. pipe_config->ddi_pll_sel = SKL_DPLL2;
  8182. id = DPLL_ID_SKL_DPLL2;
  8183. break;
  8184. default:
  8185. DRM_ERROR("Incorrect port type\n");
  8186. return;
  8187. }
  8188. pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
  8189. }
  8190. static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
  8191. enum port port,
  8192. struct intel_crtc_state *pipe_config)
  8193. {
  8194. enum intel_dpll_id id;
  8195. u32 temp;
  8196. temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
  8197. pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
  8198. switch (pipe_config->ddi_pll_sel) {
  8199. case SKL_DPLL0:
  8200. id = DPLL_ID_SKL_DPLL0;
  8201. break;
  8202. case SKL_DPLL1:
  8203. id = DPLL_ID_SKL_DPLL1;
  8204. break;
  8205. case SKL_DPLL2:
  8206. id = DPLL_ID_SKL_DPLL2;
  8207. break;
  8208. case SKL_DPLL3:
  8209. id = DPLL_ID_SKL_DPLL3;
  8210. break;
  8211. default:
  8212. MISSING_CASE(pipe_config->ddi_pll_sel);
  8213. return;
  8214. }
  8215. pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
  8216. }
  8217. static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
  8218. enum port port,
  8219. struct intel_crtc_state *pipe_config)
  8220. {
  8221. enum intel_dpll_id id;
  8222. pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
  8223. switch (pipe_config->ddi_pll_sel) {
  8224. case PORT_CLK_SEL_WRPLL1:
  8225. id = DPLL_ID_WRPLL1;
  8226. break;
  8227. case PORT_CLK_SEL_WRPLL2:
  8228. id = DPLL_ID_WRPLL2;
  8229. break;
  8230. case PORT_CLK_SEL_SPLL:
  8231. id = DPLL_ID_SPLL;
  8232. break;
  8233. case PORT_CLK_SEL_LCPLL_810:
  8234. id = DPLL_ID_LCPLL_810;
  8235. break;
  8236. case PORT_CLK_SEL_LCPLL_1350:
  8237. id = DPLL_ID_LCPLL_1350;
  8238. break;
  8239. case PORT_CLK_SEL_LCPLL_2700:
  8240. id = DPLL_ID_LCPLL_2700;
  8241. break;
  8242. default:
  8243. MISSING_CASE(pipe_config->ddi_pll_sel);
  8244. /* fall through */
  8245. case PORT_CLK_SEL_NONE:
  8246. return;
  8247. }
  8248. pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
  8249. }
  8250. static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
  8251. struct intel_crtc_state *pipe_config,
  8252. unsigned long *power_domain_mask)
  8253. {
  8254. struct drm_device *dev = crtc->base.dev;
  8255. struct drm_i915_private *dev_priv = dev->dev_private;
  8256. enum intel_display_power_domain power_domain;
  8257. u32 tmp;
  8258. /*
  8259. * The pipe->transcoder mapping is fixed with the exception of the eDP
  8260. * transcoder handled below.
  8261. */
  8262. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  8263. /*
  8264. * XXX: Do intel_display_power_get_if_enabled before reading this (for
  8265. * consistency and less surprising code; it's in always on power).
  8266. */
  8267. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  8268. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  8269. enum pipe trans_edp_pipe;
  8270. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  8271. default:
  8272. WARN(1, "unknown pipe linked to edp transcoder\n");
  8273. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  8274. case TRANS_DDI_EDP_INPUT_A_ON:
  8275. trans_edp_pipe = PIPE_A;
  8276. break;
  8277. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  8278. trans_edp_pipe = PIPE_B;
  8279. break;
  8280. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  8281. trans_edp_pipe = PIPE_C;
  8282. break;
  8283. }
  8284. if (trans_edp_pipe == crtc->pipe)
  8285. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  8286. }
  8287. power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
  8288. if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  8289. return false;
  8290. *power_domain_mask |= BIT(power_domain);
  8291. tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  8292. return tmp & PIPECONF_ENABLE;
  8293. }
  8294. static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
  8295. struct intel_crtc_state *pipe_config,
  8296. unsigned long *power_domain_mask)
  8297. {
  8298. struct drm_device *dev = crtc->base.dev;
  8299. struct drm_i915_private *dev_priv = dev->dev_private;
  8300. enum intel_display_power_domain power_domain;
  8301. enum port port;
  8302. enum transcoder cpu_transcoder;
  8303. u32 tmp;
  8304. pipe_config->has_dsi_encoder = false;
  8305. for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
  8306. if (port == PORT_A)
  8307. cpu_transcoder = TRANSCODER_DSI_A;
  8308. else
  8309. cpu_transcoder = TRANSCODER_DSI_C;
  8310. power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
  8311. if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  8312. continue;
  8313. *power_domain_mask |= BIT(power_domain);
  8314. /*
  8315. * The PLL needs to be enabled with a valid divider
  8316. * configuration, otherwise accessing DSI registers will hang
  8317. * the machine. See BSpec North Display Engine
  8318. * registers/MIPI[BXT]. We can break out here early, since we
  8319. * need the same DSI PLL to be enabled for both DSI ports.
  8320. */
  8321. if (!intel_dsi_pll_is_enabled(dev_priv))
  8322. break;
  8323. /* XXX: this works for video mode only */
  8324. tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
  8325. if (!(tmp & DPI_ENABLE))
  8326. continue;
  8327. tmp = I915_READ(MIPI_CTRL(port));
  8328. if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
  8329. continue;
  8330. pipe_config->cpu_transcoder = cpu_transcoder;
  8331. pipe_config->has_dsi_encoder = true;
  8332. break;
  8333. }
  8334. return pipe_config->has_dsi_encoder;
  8335. }
  8336. static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
  8337. struct intel_crtc_state *pipe_config)
  8338. {
  8339. struct drm_device *dev = crtc->base.dev;
  8340. struct drm_i915_private *dev_priv = dev->dev_private;
  8341. struct intel_shared_dpll *pll;
  8342. enum port port;
  8343. uint32_t tmp;
  8344. tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  8345. port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
  8346. if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
  8347. skylake_get_ddi_pll(dev_priv, port, pipe_config);
  8348. else if (IS_BROXTON(dev))
  8349. bxt_get_ddi_pll(dev_priv, port, pipe_config);
  8350. else
  8351. haswell_get_ddi_pll(dev_priv, port, pipe_config);
  8352. pll = pipe_config->shared_dpll;
  8353. if (pll) {
  8354. WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
  8355. &pipe_config->dpll_hw_state));
  8356. }
  8357. /*
  8358. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  8359. * DDI E. So just check whether this pipe is wired to DDI E and whether
  8360. * the PCH transcoder is on.
  8361. */
  8362. if (INTEL_INFO(dev)->gen < 9 &&
  8363. (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  8364. pipe_config->has_pch_encoder = true;
  8365. tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  8366. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  8367. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  8368. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  8369. }
  8370. }
  8371. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  8372. struct intel_crtc_state *pipe_config)
  8373. {
  8374. struct drm_device *dev = crtc->base.dev;
  8375. struct drm_i915_private *dev_priv = dev->dev_private;
  8376. enum intel_display_power_domain power_domain;
  8377. unsigned long power_domain_mask;
  8378. bool active;
  8379. power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
  8380. if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  8381. return false;
  8382. power_domain_mask = BIT(power_domain);
  8383. pipe_config->shared_dpll = NULL;
  8384. active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
  8385. if (IS_BROXTON(dev_priv)) {
  8386. bxt_get_dsi_transcoder_state(crtc, pipe_config,
  8387. &power_domain_mask);
  8388. WARN_ON(active && pipe_config->has_dsi_encoder);
  8389. if (pipe_config->has_dsi_encoder)
  8390. active = true;
  8391. }
  8392. if (!active)
  8393. goto out;
  8394. if (!pipe_config->has_dsi_encoder) {
  8395. haswell_get_ddi_port_state(crtc, pipe_config);
  8396. intel_get_pipe_timings(crtc, pipe_config);
  8397. }
  8398. intel_get_pipe_src_size(crtc, pipe_config);
  8399. pipe_config->gamma_mode =
  8400. I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
  8401. if (INTEL_INFO(dev)->gen >= 9) {
  8402. skl_init_scalers(dev, crtc, pipe_config);
  8403. }
  8404. if (INTEL_INFO(dev)->gen >= 9) {
  8405. pipe_config->scaler_state.scaler_id = -1;
  8406. pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
  8407. }
  8408. power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  8409. if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
  8410. power_domain_mask |= BIT(power_domain);
  8411. if (INTEL_INFO(dev)->gen >= 9)
  8412. skylake_get_pfit_config(crtc, pipe_config);
  8413. else
  8414. ironlake_get_pfit_config(crtc, pipe_config);
  8415. }
  8416. if (IS_HASWELL(dev))
  8417. pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  8418. (I915_READ(IPS_CTL) & IPS_ENABLE);
  8419. if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
  8420. !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
  8421. pipe_config->pixel_multiplier =
  8422. I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
  8423. } else {
  8424. pipe_config->pixel_multiplier = 1;
  8425. }
  8426. out:
  8427. for_each_power_domain(power_domain, power_domain_mask)
  8428. intel_display_power_put(dev_priv, power_domain);
  8429. return active;
  8430. }
  8431. static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
  8432. const struct intel_plane_state *plane_state)
  8433. {
  8434. struct drm_device *dev = crtc->dev;
  8435. struct drm_i915_private *dev_priv = dev->dev_private;
  8436. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8437. uint32_t cntl = 0, size = 0;
  8438. if (plane_state && plane_state->visible) {
  8439. unsigned int width = plane_state->base.crtc_w;
  8440. unsigned int height = plane_state->base.crtc_h;
  8441. unsigned int stride = roundup_pow_of_two(width) * 4;
  8442. switch (stride) {
  8443. default:
  8444. WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
  8445. width, stride);
  8446. stride = 256;
  8447. /* fallthrough */
  8448. case 256:
  8449. case 512:
  8450. case 1024:
  8451. case 2048:
  8452. break;
  8453. }
  8454. cntl |= CURSOR_ENABLE |
  8455. CURSOR_GAMMA_ENABLE |
  8456. CURSOR_FORMAT_ARGB |
  8457. CURSOR_STRIDE(stride);
  8458. size = (height << 12) | width;
  8459. }
  8460. if (intel_crtc->cursor_cntl != 0 &&
  8461. (intel_crtc->cursor_base != base ||
  8462. intel_crtc->cursor_size != size ||
  8463. intel_crtc->cursor_cntl != cntl)) {
  8464. /* On these chipsets we can only modify the base/size/stride
  8465. * whilst the cursor is disabled.
  8466. */
  8467. I915_WRITE(CURCNTR(PIPE_A), 0);
  8468. POSTING_READ(CURCNTR(PIPE_A));
  8469. intel_crtc->cursor_cntl = 0;
  8470. }
  8471. if (intel_crtc->cursor_base != base) {
  8472. I915_WRITE(CURBASE(PIPE_A), base);
  8473. intel_crtc->cursor_base = base;
  8474. }
  8475. if (intel_crtc->cursor_size != size) {
  8476. I915_WRITE(CURSIZE, size);
  8477. intel_crtc->cursor_size = size;
  8478. }
  8479. if (intel_crtc->cursor_cntl != cntl) {
  8480. I915_WRITE(CURCNTR(PIPE_A), cntl);
  8481. POSTING_READ(CURCNTR(PIPE_A));
  8482. intel_crtc->cursor_cntl = cntl;
  8483. }
  8484. }
  8485. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
  8486. const struct intel_plane_state *plane_state)
  8487. {
  8488. struct drm_device *dev = crtc->dev;
  8489. struct drm_i915_private *dev_priv = dev->dev_private;
  8490. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8491. int pipe = intel_crtc->pipe;
  8492. uint32_t cntl = 0;
  8493. if (plane_state && plane_state->visible) {
  8494. cntl = MCURSOR_GAMMA_ENABLE;
  8495. switch (plane_state->base.crtc_w) {
  8496. case 64:
  8497. cntl |= CURSOR_MODE_64_ARGB_AX;
  8498. break;
  8499. case 128:
  8500. cntl |= CURSOR_MODE_128_ARGB_AX;
  8501. break;
  8502. case 256:
  8503. cntl |= CURSOR_MODE_256_ARGB_AX;
  8504. break;
  8505. default:
  8506. MISSING_CASE(plane_state->base.crtc_w);
  8507. return;
  8508. }
  8509. cntl |= pipe << 28; /* Connect to correct pipe */
  8510. if (HAS_DDI(dev))
  8511. cntl |= CURSOR_PIPE_CSC_ENABLE;
  8512. if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
  8513. cntl |= CURSOR_ROTATE_180;
  8514. }
  8515. if (intel_crtc->cursor_cntl != cntl) {
  8516. I915_WRITE(CURCNTR(pipe), cntl);
  8517. POSTING_READ(CURCNTR(pipe));
  8518. intel_crtc->cursor_cntl = cntl;
  8519. }
  8520. /* and commit changes on next vblank */
  8521. I915_WRITE(CURBASE(pipe), base);
  8522. POSTING_READ(CURBASE(pipe));
  8523. intel_crtc->cursor_base = base;
  8524. }
  8525. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  8526. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  8527. const struct intel_plane_state *plane_state)
  8528. {
  8529. struct drm_device *dev = crtc->dev;
  8530. struct drm_i915_private *dev_priv = dev->dev_private;
  8531. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8532. int pipe = intel_crtc->pipe;
  8533. u32 base = intel_crtc->cursor_addr;
  8534. u32 pos = 0;
  8535. if (plane_state) {
  8536. int x = plane_state->base.crtc_x;
  8537. int y = plane_state->base.crtc_y;
  8538. if (x < 0) {
  8539. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  8540. x = -x;
  8541. }
  8542. pos |= x << CURSOR_X_SHIFT;
  8543. if (y < 0) {
  8544. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  8545. y = -y;
  8546. }
  8547. pos |= y << CURSOR_Y_SHIFT;
  8548. /* ILK+ do this automagically */
  8549. if (HAS_GMCH_DISPLAY(dev) &&
  8550. plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
  8551. base += (plane_state->base.crtc_h *
  8552. plane_state->base.crtc_w - 1) * 4;
  8553. }
  8554. }
  8555. I915_WRITE(CURPOS(pipe), pos);
  8556. if (IS_845G(dev) || IS_I865G(dev))
  8557. i845_update_cursor(crtc, base, plane_state);
  8558. else
  8559. i9xx_update_cursor(crtc, base, plane_state);
  8560. }
  8561. static bool cursor_size_ok(struct drm_device *dev,
  8562. uint32_t width, uint32_t height)
  8563. {
  8564. if (width == 0 || height == 0)
  8565. return false;
  8566. /*
  8567. * 845g/865g are special in that they are only limited by
  8568. * the width of their cursors, the height is arbitrary up to
  8569. * the precision of the register. Everything else requires
  8570. * square cursors, limited to a few power-of-two sizes.
  8571. */
  8572. if (IS_845G(dev) || IS_I865G(dev)) {
  8573. if ((width & 63) != 0)
  8574. return false;
  8575. if (width > (IS_845G(dev) ? 64 : 512))
  8576. return false;
  8577. if (height > 1023)
  8578. return false;
  8579. } else {
  8580. switch (width | height) {
  8581. case 256:
  8582. case 128:
  8583. if (IS_GEN2(dev))
  8584. return false;
  8585. case 64:
  8586. break;
  8587. default:
  8588. return false;
  8589. }
  8590. }
  8591. return true;
  8592. }
  8593. /* VESA 640x480x72Hz mode to set on the pipe */
  8594. static struct drm_display_mode load_detect_mode = {
  8595. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  8596. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  8597. };
  8598. struct drm_framebuffer *
  8599. __intel_framebuffer_create(struct drm_device *dev,
  8600. struct drm_mode_fb_cmd2 *mode_cmd,
  8601. struct drm_i915_gem_object *obj)
  8602. {
  8603. struct intel_framebuffer *intel_fb;
  8604. int ret;
  8605. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  8606. if (!intel_fb)
  8607. return ERR_PTR(-ENOMEM);
  8608. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  8609. if (ret)
  8610. goto err;
  8611. return &intel_fb->base;
  8612. err:
  8613. kfree(intel_fb);
  8614. return ERR_PTR(ret);
  8615. }
  8616. static struct drm_framebuffer *
  8617. intel_framebuffer_create(struct drm_device *dev,
  8618. struct drm_mode_fb_cmd2 *mode_cmd,
  8619. struct drm_i915_gem_object *obj)
  8620. {
  8621. struct drm_framebuffer *fb;
  8622. int ret;
  8623. ret = i915_mutex_lock_interruptible(dev);
  8624. if (ret)
  8625. return ERR_PTR(ret);
  8626. fb = __intel_framebuffer_create(dev, mode_cmd, obj);
  8627. mutex_unlock(&dev->struct_mutex);
  8628. return fb;
  8629. }
  8630. static u32
  8631. intel_framebuffer_pitch_for_width(int width, int bpp)
  8632. {
  8633. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  8634. return ALIGN(pitch, 64);
  8635. }
  8636. static u32
  8637. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  8638. {
  8639. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  8640. return PAGE_ALIGN(pitch * mode->vdisplay);
  8641. }
  8642. static struct drm_framebuffer *
  8643. intel_framebuffer_create_for_mode(struct drm_device *dev,
  8644. struct drm_display_mode *mode,
  8645. int depth, int bpp)
  8646. {
  8647. struct drm_framebuffer *fb;
  8648. struct drm_i915_gem_object *obj;
  8649. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  8650. obj = i915_gem_object_create(dev,
  8651. intel_framebuffer_size_for_mode(mode, bpp));
  8652. if (IS_ERR(obj))
  8653. return ERR_CAST(obj);
  8654. mode_cmd.width = mode->hdisplay;
  8655. mode_cmd.height = mode->vdisplay;
  8656. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  8657. bpp);
  8658. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  8659. fb = intel_framebuffer_create(dev, &mode_cmd, obj);
  8660. if (IS_ERR(fb))
  8661. drm_gem_object_unreference_unlocked(&obj->base);
  8662. return fb;
  8663. }
  8664. static struct drm_framebuffer *
  8665. mode_fits_in_fbdev(struct drm_device *dev,
  8666. struct drm_display_mode *mode)
  8667. {
  8668. #ifdef CONFIG_DRM_FBDEV_EMULATION
  8669. struct drm_i915_private *dev_priv = dev->dev_private;
  8670. struct drm_i915_gem_object *obj;
  8671. struct drm_framebuffer *fb;
  8672. if (!dev_priv->fbdev)
  8673. return NULL;
  8674. if (!dev_priv->fbdev->fb)
  8675. return NULL;
  8676. obj = dev_priv->fbdev->fb->obj;
  8677. BUG_ON(!obj);
  8678. fb = &dev_priv->fbdev->fb->base;
  8679. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  8680. fb->bits_per_pixel))
  8681. return NULL;
  8682. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  8683. return NULL;
  8684. drm_framebuffer_reference(fb);
  8685. return fb;
  8686. #else
  8687. return NULL;
  8688. #endif
  8689. }
  8690. static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
  8691. struct drm_crtc *crtc,
  8692. struct drm_display_mode *mode,
  8693. struct drm_framebuffer *fb,
  8694. int x, int y)
  8695. {
  8696. struct drm_plane_state *plane_state;
  8697. int hdisplay, vdisplay;
  8698. int ret;
  8699. plane_state = drm_atomic_get_plane_state(state, crtc->primary);
  8700. if (IS_ERR(plane_state))
  8701. return PTR_ERR(plane_state);
  8702. if (mode)
  8703. drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
  8704. else
  8705. hdisplay = vdisplay = 0;
  8706. ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
  8707. if (ret)
  8708. return ret;
  8709. drm_atomic_set_fb_for_plane(plane_state, fb);
  8710. plane_state->crtc_x = 0;
  8711. plane_state->crtc_y = 0;
  8712. plane_state->crtc_w = hdisplay;
  8713. plane_state->crtc_h = vdisplay;
  8714. plane_state->src_x = x << 16;
  8715. plane_state->src_y = y << 16;
  8716. plane_state->src_w = hdisplay << 16;
  8717. plane_state->src_h = vdisplay << 16;
  8718. return 0;
  8719. }
  8720. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  8721. struct drm_display_mode *mode,
  8722. struct intel_load_detect_pipe *old,
  8723. struct drm_modeset_acquire_ctx *ctx)
  8724. {
  8725. struct intel_crtc *intel_crtc;
  8726. struct intel_encoder *intel_encoder =
  8727. intel_attached_encoder(connector);
  8728. struct drm_crtc *possible_crtc;
  8729. struct drm_encoder *encoder = &intel_encoder->base;
  8730. struct drm_crtc *crtc = NULL;
  8731. struct drm_device *dev = encoder->dev;
  8732. struct drm_framebuffer *fb;
  8733. struct drm_mode_config *config = &dev->mode_config;
  8734. struct drm_atomic_state *state = NULL, *restore_state = NULL;
  8735. struct drm_connector_state *connector_state;
  8736. struct intel_crtc_state *crtc_state;
  8737. int ret, i = -1;
  8738. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  8739. connector->base.id, connector->name,
  8740. encoder->base.id, encoder->name);
  8741. old->restore_state = NULL;
  8742. retry:
  8743. ret = drm_modeset_lock(&config->connection_mutex, ctx);
  8744. if (ret)
  8745. goto fail;
  8746. /*
  8747. * Algorithm gets a little messy:
  8748. *
  8749. * - if the connector already has an assigned crtc, use it (but make
  8750. * sure it's on first)
  8751. *
  8752. * - try to find the first unused crtc that can drive this connector,
  8753. * and use that if we find one
  8754. */
  8755. /* See if we already have a CRTC for this connector */
  8756. if (connector->state->crtc) {
  8757. crtc = connector->state->crtc;
  8758. ret = drm_modeset_lock(&crtc->mutex, ctx);
  8759. if (ret)
  8760. goto fail;
  8761. /* Make sure the crtc and connector are running */
  8762. goto found;
  8763. }
  8764. /* Find an unused one (if possible) */
  8765. for_each_crtc(dev, possible_crtc) {
  8766. i++;
  8767. if (!(encoder->possible_crtcs & (1 << i)))
  8768. continue;
  8769. ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
  8770. if (ret)
  8771. goto fail;
  8772. if (possible_crtc->state->enable) {
  8773. drm_modeset_unlock(&possible_crtc->mutex);
  8774. continue;
  8775. }
  8776. crtc = possible_crtc;
  8777. break;
  8778. }
  8779. /*
  8780. * If we didn't find an unused CRTC, don't use any.
  8781. */
  8782. if (!crtc) {
  8783. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  8784. goto fail;
  8785. }
  8786. found:
  8787. intel_crtc = to_intel_crtc(crtc);
  8788. ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
  8789. if (ret)
  8790. goto fail;
  8791. state = drm_atomic_state_alloc(dev);
  8792. restore_state = drm_atomic_state_alloc(dev);
  8793. if (!state || !restore_state) {
  8794. ret = -ENOMEM;
  8795. goto fail;
  8796. }
  8797. state->acquire_ctx = ctx;
  8798. restore_state->acquire_ctx = ctx;
  8799. connector_state = drm_atomic_get_connector_state(state, connector);
  8800. if (IS_ERR(connector_state)) {
  8801. ret = PTR_ERR(connector_state);
  8802. goto fail;
  8803. }
  8804. ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
  8805. if (ret)
  8806. goto fail;
  8807. crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
  8808. if (IS_ERR(crtc_state)) {
  8809. ret = PTR_ERR(crtc_state);
  8810. goto fail;
  8811. }
  8812. crtc_state->base.active = crtc_state->base.enable = true;
  8813. if (!mode)
  8814. mode = &load_detect_mode;
  8815. /* We need a framebuffer large enough to accommodate all accesses
  8816. * that the plane may generate whilst we perform load detection.
  8817. * We can not rely on the fbcon either being present (we get called
  8818. * during its initialisation to detect all boot displays, or it may
  8819. * not even exist) or that it is large enough to satisfy the
  8820. * requested mode.
  8821. */
  8822. fb = mode_fits_in_fbdev(dev, mode);
  8823. if (fb == NULL) {
  8824. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  8825. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  8826. } else
  8827. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  8828. if (IS_ERR(fb)) {
  8829. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  8830. goto fail;
  8831. }
  8832. ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
  8833. if (ret)
  8834. goto fail;
  8835. drm_framebuffer_unreference(fb);
  8836. ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
  8837. if (ret)
  8838. goto fail;
  8839. ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
  8840. if (!ret)
  8841. ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
  8842. if (!ret)
  8843. ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
  8844. if (ret) {
  8845. DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
  8846. goto fail;
  8847. }
  8848. ret = drm_atomic_commit(state);
  8849. if (ret) {
  8850. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  8851. goto fail;
  8852. }
  8853. old->restore_state = restore_state;
  8854. /* let the connector get through one full cycle before testing */
  8855. intel_wait_for_vblank(dev, intel_crtc->pipe);
  8856. return true;
  8857. fail:
  8858. drm_atomic_state_free(state);
  8859. drm_atomic_state_free(restore_state);
  8860. restore_state = state = NULL;
  8861. if (ret == -EDEADLK) {
  8862. drm_modeset_backoff(ctx);
  8863. goto retry;
  8864. }
  8865. return false;
  8866. }
  8867. void intel_release_load_detect_pipe(struct drm_connector *connector,
  8868. struct intel_load_detect_pipe *old,
  8869. struct drm_modeset_acquire_ctx *ctx)
  8870. {
  8871. struct intel_encoder *intel_encoder =
  8872. intel_attached_encoder(connector);
  8873. struct drm_encoder *encoder = &intel_encoder->base;
  8874. struct drm_atomic_state *state = old->restore_state;
  8875. int ret;
  8876. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  8877. connector->base.id, connector->name,
  8878. encoder->base.id, encoder->name);
  8879. if (!state)
  8880. return;
  8881. ret = drm_atomic_commit(state);
  8882. if (ret) {
  8883. DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
  8884. drm_atomic_state_free(state);
  8885. }
  8886. }
  8887. static int i9xx_pll_refclk(struct drm_device *dev,
  8888. const struct intel_crtc_state *pipe_config)
  8889. {
  8890. struct drm_i915_private *dev_priv = dev->dev_private;
  8891. u32 dpll = pipe_config->dpll_hw_state.dpll;
  8892. if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
  8893. return dev_priv->vbt.lvds_ssc_freq;
  8894. else if (HAS_PCH_SPLIT(dev))
  8895. return 120000;
  8896. else if (!IS_GEN2(dev))
  8897. return 96000;
  8898. else
  8899. return 48000;
  8900. }
  8901. /* Returns the clock of the currently programmed mode of the given pipe. */
  8902. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  8903. struct intel_crtc_state *pipe_config)
  8904. {
  8905. struct drm_device *dev = crtc->base.dev;
  8906. struct drm_i915_private *dev_priv = dev->dev_private;
  8907. int pipe = pipe_config->cpu_transcoder;
  8908. u32 dpll = pipe_config->dpll_hw_state.dpll;
  8909. u32 fp;
  8910. struct dpll clock;
  8911. int port_clock;
  8912. int refclk = i9xx_pll_refclk(dev, pipe_config);
  8913. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  8914. fp = pipe_config->dpll_hw_state.fp0;
  8915. else
  8916. fp = pipe_config->dpll_hw_state.fp1;
  8917. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  8918. if (IS_PINEVIEW(dev)) {
  8919. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  8920. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  8921. } else {
  8922. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  8923. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  8924. }
  8925. if (!IS_GEN2(dev)) {
  8926. if (IS_PINEVIEW(dev))
  8927. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  8928. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  8929. else
  8930. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  8931. DPLL_FPA01_P1_POST_DIV_SHIFT);
  8932. switch (dpll & DPLL_MODE_MASK) {
  8933. case DPLLB_MODE_DAC_SERIAL:
  8934. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  8935. 5 : 10;
  8936. break;
  8937. case DPLLB_MODE_LVDS:
  8938. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  8939. 7 : 14;
  8940. break;
  8941. default:
  8942. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  8943. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  8944. return;
  8945. }
  8946. if (IS_PINEVIEW(dev))
  8947. port_clock = pnv_calc_dpll_params(refclk, &clock);
  8948. else
  8949. port_clock = i9xx_calc_dpll_params(refclk, &clock);
  8950. } else {
  8951. u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
  8952. bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
  8953. if (is_lvds) {
  8954. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  8955. DPLL_FPA01_P1_POST_DIV_SHIFT);
  8956. if (lvds & LVDS_CLKB_POWER_UP)
  8957. clock.p2 = 7;
  8958. else
  8959. clock.p2 = 14;
  8960. } else {
  8961. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  8962. clock.p1 = 2;
  8963. else {
  8964. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  8965. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  8966. }
  8967. if (dpll & PLL_P2_DIVIDE_BY_4)
  8968. clock.p2 = 4;
  8969. else
  8970. clock.p2 = 2;
  8971. }
  8972. port_clock = i9xx_calc_dpll_params(refclk, &clock);
  8973. }
  8974. /*
  8975. * This value includes pixel_multiplier. We will use
  8976. * port_clock to compute adjusted_mode.crtc_clock in the
  8977. * encoder's get_config() function.
  8978. */
  8979. pipe_config->port_clock = port_clock;
  8980. }
  8981. int intel_dotclock_calculate(int link_freq,
  8982. const struct intel_link_m_n *m_n)
  8983. {
  8984. /*
  8985. * The calculation for the data clock is:
  8986. * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
  8987. * But we want to avoid losing precison if possible, so:
  8988. * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
  8989. *
  8990. * and the link clock is simpler:
  8991. * link_clock = (m * link_clock) / n
  8992. */
  8993. if (!m_n->link_n)
  8994. return 0;
  8995. return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
  8996. }
  8997. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  8998. struct intel_crtc_state *pipe_config)
  8999. {
  9000. struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  9001. /* read out port_clock from the DPLL */
  9002. i9xx_crtc_clock_get(crtc, pipe_config);
  9003. /*
  9004. * In case there is an active pipe without active ports,
  9005. * we may need some idea for the dotclock anyway.
  9006. * Calculate one based on the FDI configuration.
  9007. */
  9008. pipe_config->base.adjusted_mode.crtc_clock =
  9009. intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
  9010. &pipe_config->fdi_m_n);
  9011. }
  9012. /** Returns the currently programmed mode of the given pipe. */
  9013. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  9014. struct drm_crtc *crtc)
  9015. {
  9016. struct drm_i915_private *dev_priv = dev->dev_private;
  9017. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9018. enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  9019. struct drm_display_mode *mode;
  9020. struct intel_crtc_state *pipe_config;
  9021. int htot = I915_READ(HTOTAL(cpu_transcoder));
  9022. int hsync = I915_READ(HSYNC(cpu_transcoder));
  9023. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  9024. int vsync = I915_READ(VSYNC(cpu_transcoder));
  9025. enum pipe pipe = intel_crtc->pipe;
  9026. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  9027. if (!mode)
  9028. return NULL;
  9029. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  9030. if (!pipe_config) {
  9031. kfree(mode);
  9032. return NULL;
  9033. }
  9034. /*
  9035. * Construct a pipe_config sufficient for getting the clock info
  9036. * back out of crtc_clock_get.
  9037. *
  9038. * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  9039. * to use a real value here instead.
  9040. */
  9041. pipe_config->cpu_transcoder = (enum transcoder) pipe;
  9042. pipe_config->pixel_multiplier = 1;
  9043. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
  9044. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
  9045. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
  9046. i9xx_crtc_clock_get(intel_crtc, pipe_config);
  9047. mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
  9048. mode->hdisplay = (htot & 0xffff) + 1;
  9049. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  9050. mode->hsync_start = (hsync & 0xffff) + 1;
  9051. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  9052. mode->vdisplay = (vtot & 0xffff) + 1;
  9053. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  9054. mode->vsync_start = (vsync & 0xffff) + 1;
  9055. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  9056. drm_mode_set_name(mode);
  9057. kfree(pipe_config);
  9058. return mode;
  9059. }
  9060. void intel_mark_busy(struct drm_i915_private *dev_priv)
  9061. {
  9062. if (dev_priv->mm.busy)
  9063. return;
  9064. intel_runtime_pm_get(dev_priv);
  9065. i915_update_gfx_val(dev_priv);
  9066. if (INTEL_GEN(dev_priv) >= 6)
  9067. gen6_rps_busy(dev_priv);
  9068. dev_priv->mm.busy = true;
  9069. }
  9070. void intel_mark_idle(struct drm_i915_private *dev_priv)
  9071. {
  9072. if (!dev_priv->mm.busy)
  9073. return;
  9074. dev_priv->mm.busy = false;
  9075. if (INTEL_GEN(dev_priv) >= 6)
  9076. gen6_rps_idle(dev_priv);
  9077. intel_runtime_pm_put(dev_priv);
  9078. }
  9079. static void intel_crtc_destroy(struct drm_crtc *crtc)
  9080. {
  9081. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9082. struct drm_device *dev = crtc->dev;
  9083. struct intel_unpin_work *work;
  9084. spin_lock_irq(&dev->event_lock);
  9085. work = intel_crtc->unpin_work;
  9086. intel_crtc->unpin_work = NULL;
  9087. spin_unlock_irq(&dev->event_lock);
  9088. if (work) {
  9089. cancel_work_sync(&work->work);
  9090. kfree(work);
  9091. }
  9092. drm_crtc_cleanup(crtc);
  9093. kfree(intel_crtc);
  9094. }
  9095. static void intel_unpin_work_fn(struct work_struct *__work)
  9096. {
  9097. struct intel_unpin_work *work =
  9098. container_of(__work, struct intel_unpin_work, work);
  9099. struct intel_crtc *crtc = to_intel_crtc(work->crtc);
  9100. struct drm_device *dev = crtc->base.dev;
  9101. struct drm_plane *primary = crtc->base.primary;
  9102. mutex_lock(&dev->struct_mutex);
  9103. intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
  9104. drm_gem_object_unreference(&work->pending_flip_obj->base);
  9105. if (work->flip_queued_req)
  9106. i915_gem_request_assign(&work->flip_queued_req, NULL);
  9107. mutex_unlock(&dev->struct_mutex);
  9108. intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
  9109. intel_fbc_post_update(crtc);
  9110. drm_framebuffer_unreference(work->old_fb);
  9111. BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
  9112. atomic_dec(&crtc->unpin_work_count);
  9113. kfree(work);
  9114. }
  9115. static void do_intel_finish_page_flip(struct drm_i915_private *dev_priv,
  9116. struct drm_crtc *crtc)
  9117. {
  9118. struct drm_device *dev = dev_priv->dev;
  9119. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9120. struct intel_unpin_work *work;
  9121. unsigned long flags;
  9122. /* Ignore early vblank irqs */
  9123. if (intel_crtc == NULL)
  9124. return;
  9125. /*
  9126. * This is called both by irq handlers and the reset code (to complete
  9127. * lost pageflips) so needs the full irqsave spinlocks.
  9128. */
  9129. spin_lock_irqsave(&dev->event_lock, flags);
  9130. work = intel_crtc->unpin_work;
  9131. /* Ensure we don't miss a work->pending update ... */
  9132. smp_rmb();
  9133. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  9134. spin_unlock_irqrestore(&dev->event_lock, flags);
  9135. return;
  9136. }
  9137. page_flip_completed(intel_crtc);
  9138. spin_unlock_irqrestore(&dev->event_lock, flags);
  9139. }
  9140. void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe)
  9141. {
  9142. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  9143. do_intel_finish_page_flip(dev_priv, crtc);
  9144. }
  9145. void intel_finish_page_flip_plane(struct drm_i915_private *dev_priv, int plane)
  9146. {
  9147. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  9148. do_intel_finish_page_flip(dev_priv, crtc);
  9149. }
  9150. /* Is 'a' after or equal to 'b'? */
  9151. static bool g4x_flip_count_after_eq(u32 a, u32 b)
  9152. {
  9153. return !((a - b) & 0x80000000);
  9154. }
  9155. static bool page_flip_finished(struct intel_crtc *crtc)
  9156. {
  9157. struct drm_device *dev = crtc->base.dev;
  9158. struct drm_i915_private *dev_priv = dev->dev_private;
  9159. unsigned reset_counter;
  9160. reset_counter = i915_reset_counter(&dev_priv->gpu_error);
  9161. if (crtc->reset_counter != reset_counter)
  9162. return true;
  9163. /*
  9164. * The relevant registers doen't exist on pre-ctg.
  9165. * As the flip done interrupt doesn't trigger for mmio
  9166. * flips on gmch platforms, a flip count check isn't
  9167. * really needed there. But since ctg has the registers,
  9168. * include it in the check anyway.
  9169. */
  9170. if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
  9171. return true;
  9172. /*
  9173. * BDW signals flip done immediately if the plane
  9174. * is disabled, even if the plane enable is already
  9175. * armed to occur at the next vblank :(
  9176. */
  9177. /*
  9178. * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
  9179. * used the same base address. In that case the mmio flip might
  9180. * have completed, but the CS hasn't even executed the flip yet.
  9181. *
  9182. * A flip count check isn't enough as the CS might have updated
  9183. * the base address just after start of vblank, but before we
  9184. * managed to process the interrupt. This means we'd complete the
  9185. * CS flip too soon.
  9186. *
  9187. * Combining both checks should get us a good enough result. It may
  9188. * still happen that the CS flip has been executed, but has not
  9189. * yet actually completed. But in case the base address is the same
  9190. * anyway, we don't really care.
  9191. */
  9192. return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
  9193. crtc->unpin_work->gtt_offset &&
  9194. g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
  9195. crtc->unpin_work->flip_count);
  9196. }
  9197. void intel_prepare_page_flip(struct drm_i915_private *dev_priv, int plane)
  9198. {
  9199. struct drm_device *dev = dev_priv->dev;
  9200. struct intel_crtc *intel_crtc =
  9201. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  9202. unsigned long flags;
  9203. /*
  9204. * This is called both by irq handlers and the reset code (to complete
  9205. * lost pageflips) so needs the full irqsave spinlocks.
  9206. *
  9207. * NB: An MMIO update of the plane base pointer will also
  9208. * generate a page-flip completion irq, i.e. every modeset
  9209. * is also accompanied by a spurious intel_prepare_page_flip().
  9210. */
  9211. spin_lock_irqsave(&dev->event_lock, flags);
  9212. if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
  9213. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  9214. spin_unlock_irqrestore(&dev->event_lock, flags);
  9215. }
  9216. static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
  9217. {
  9218. /* Ensure that the work item is consistent when activating it ... */
  9219. smp_wmb();
  9220. atomic_set(&work->pending, INTEL_FLIP_PENDING);
  9221. /* and that it is marked active as soon as the irq could fire. */
  9222. smp_wmb();
  9223. }
  9224. static int intel_gen2_queue_flip(struct drm_device *dev,
  9225. struct drm_crtc *crtc,
  9226. struct drm_framebuffer *fb,
  9227. struct drm_i915_gem_object *obj,
  9228. struct drm_i915_gem_request *req,
  9229. uint32_t flags)
  9230. {
  9231. struct intel_engine_cs *engine = req->engine;
  9232. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9233. u32 flip_mask;
  9234. int ret;
  9235. ret = intel_ring_begin(req, 6);
  9236. if (ret)
  9237. return ret;
  9238. /* Can't queue multiple flips, so wait for the previous
  9239. * one to finish before executing the next.
  9240. */
  9241. if (intel_crtc->plane)
  9242. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  9243. else
  9244. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  9245. intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
  9246. intel_ring_emit(engine, MI_NOOP);
  9247. intel_ring_emit(engine, MI_DISPLAY_FLIP |
  9248. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  9249. intel_ring_emit(engine, fb->pitches[0]);
  9250. intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
  9251. intel_ring_emit(engine, 0); /* aux display base address, unused */
  9252. intel_mark_page_flip_active(intel_crtc->unpin_work);
  9253. return 0;
  9254. }
  9255. static int intel_gen3_queue_flip(struct drm_device *dev,
  9256. struct drm_crtc *crtc,
  9257. struct drm_framebuffer *fb,
  9258. struct drm_i915_gem_object *obj,
  9259. struct drm_i915_gem_request *req,
  9260. uint32_t flags)
  9261. {
  9262. struct intel_engine_cs *engine = req->engine;
  9263. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9264. u32 flip_mask;
  9265. int ret;
  9266. ret = intel_ring_begin(req, 6);
  9267. if (ret)
  9268. return ret;
  9269. if (intel_crtc->plane)
  9270. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  9271. else
  9272. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  9273. intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
  9274. intel_ring_emit(engine, MI_NOOP);
  9275. intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
  9276. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  9277. intel_ring_emit(engine, fb->pitches[0]);
  9278. intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
  9279. intel_ring_emit(engine, MI_NOOP);
  9280. intel_mark_page_flip_active(intel_crtc->unpin_work);
  9281. return 0;
  9282. }
  9283. static int intel_gen4_queue_flip(struct drm_device *dev,
  9284. struct drm_crtc *crtc,
  9285. struct drm_framebuffer *fb,
  9286. struct drm_i915_gem_object *obj,
  9287. struct drm_i915_gem_request *req,
  9288. uint32_t flags)
  9289. {
  9290. struct intel_engine_cs *engine = req->engine;
  9291. struct drm_i915_private *dev_priv = dev->dev_private;
  9292. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9293. uint32_t pf, pipesrc;
  9294. int ret;
  9295. ret = intel_ring_begin(req, 4);
  9296. if (ret)
  9297. return ret;
  9298. /* i965+ uses the linear or tiled offsets from the
  9299. * Display Registers (which do not change across a page-flip)
  9300. * so we need only reprogram the base address.
  9301. */
  9302. intel_ring_emit(engine, MI_DISPLAY_FLIP |
  9303. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  9304. intel_ring_emit(engine, fb->pitches[0]);
  9305. intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
  9306. obj->tiling_mode);
  9307. /* XXX Enabling the panel-fitter across page-flip is so far
  9308. * untested on non-native modes, so ignore it for now.
  9309. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  9310. */
  9311. pf = 0;
  9312. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  9313. intel_ring_emit(engine, pf | pipesrc);
  9314. intel_mark_page_flip_active(intel_crtc->unpin_work);
  9315. return 0;
  9316. }
  9317. static int intel_gen6_queue_flip(struct drm_device *dev,
  9318. struct drm_crtc *crtc,
  9319. struct drm_framebuffer *fb,
  9320. struct drm_i915_gem_object *obj,
  9321. struct drm_i915_gem_request *req,
  9322. uint32_t flags)
  9323. {
  9324. struct intel_engine_cs *engine = req->engine;
  9325. struct drm_i915_private *dev_priv = dev->dev_private;
  9326. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9327. uint32_t pf, pipesrc;
  9328. int ret;
  9329. ret = intel_ring_begin(req, 4);
  9330. if (ret)
  9331. return ret;
  9332. intel_ring_emit(engine, MI_DISPLAY_FLIP |
  9333. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  9334. intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
  9335. intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
  9336. /* Contrary to the suggestions in the documentation,
  9337. * "Enable Panel Fitter" does not seem to be required when page
  9338. * flipping with a non-native mode, and worse causes a normal
  9339. * modeset to fail.
  9340. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  9341. */
  9342. pf = 0;
  9343. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  9344. intel_ring_emit(engine, pf | pipesrc);
  9345. intel_mark_page_flip_active(intel_crtc->unpin_work);
  9346. return 0;
  9347. }
  9348. static int intel_gen7_queue_flip(struct drm_device *dev,
  9349. struct drm_crtc *crtc,
  9350. struct drm_framebuffer *fb,
  9351. struct drm_i915_gem_object *obj,
  9352. struct drm_i915_gem_request *req,
  9353. uint32_t flags)
  9354. {
  9355. struct intel_engine_cs *engine = req->engine;
  9356. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9357. uint32_t plane_bit = 0;
  9358. int len, ret;
  9359. switch (intel_crtc->plane) {
  9360. case PLANE_A:
  9361. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  9362. break;
  9363. case PLANE_B:
  9364. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  9365. break;
  9366. case PLANE_C:
  9367. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  9368. break;
  9369. default:
  9370. WARN_ONCE(1, "unknown plane in flip command\n");
  9371. return -ENODEV;
  9372. }
  9373. len = 4;
  9374. if (engine->id == RCS) {
  9375. len += 6;
  9376. /*
  9377. * On Gen 8, SRM is now taking an extra dword to accommodate
  9378. * 48bits addresses, and we need a NOOP for the batch size to
  9379. * stay even.
  9380. */
  9381. if (IS_GEN8(dev))
  9382. len += 2;
  9383. }
  9384. /*
  9385. * BSpec MI_DISPLAY_FLIP for IVB:
  9386. * "The full packet must be contained within the same cache line."
  9387. *
  9388. * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
  9389. * cacheline, if we ever start emitting more commands before
  9390. * the MI_DISPLAY_FLIP we may need to first emit everything else,
  9391. * then do the cacheline alignment, and finally emit the
  9392. * MI_DISPLAY_FLIP.
  9393. */
  9394. ret = intel_ring_cacheline_align(req);
  9395. if (ret)
  9396. return ret;
  9397. ret = intel_ring_begin(req, len);
  9398. if (ret)
  9399. return ret;
  9400. /* Unmask the flip-done completion message. Note that the bspec says that
  9401. * we should do this for both the BCS and RCS, and that we must not unmask
  9402. * more than one flip event at any time (or ensure that one flip message
  9403. * can be sent by waiting for flip-done prior to queueing new flips).
  9404. * Experimentation says that BCS works despite DERRMR masking all
  9405. * flip-done completion events and that unmasking all planes at once
  9406. * for the RCS also doesn't appear to drop events. Setting the DERRMR
  9407. * to zero does lead to lockups within MI_DISPLAY_FLIP.
  9408. */
  9409. if (engine->id == RCS) {
  9410. intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
  9411. intel_ring_emit_reg(engine, DERRMR);
  9412. intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  9413. DERRMR_PIPEB_PRI_FLIP_DONE |
  9414. DERRMR_PIPEC_PRI_FLIP_DONE));
  9415. if (IS_GEN8(dev))
  9416. intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
  9417. MI_SRM_LRM_GLOBAL_GTT);
  9418. else
  9419. intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
  9420. MI_SRM_LRM_GLOBAL_GTT);
  9421. intel_ring_emit_reg(engine, DERRMR);
  9422. intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
  9423. if (IS_GEN8(dev)) {
  9424. intel_ring_emit(engine, 0);
  9425. intel_ring_emit(engine, MI_NOOP);
  9426. }
  9427. }
  9428. intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
  9429. intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
  9430. intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
  9431. intel_ring_emit(engine, (MI_NOOP));
  9432. intel_mark_page_flip_active(intel_crtc->unpin_work);
  9433. return 0;
  9434. }
  9435. static bool use_mmio_flip(struct intel_engine_cs *engine,
  9436. struct drm_i915_gem_object *obj)
  9437. {
  9438. /*
  9439. * This is not being used for older platforms, because
  9440. * non-availability of flip done interrupt forces us to use
  9441. * CS flips. Older platforms derive flip done using some clever
  9442. * tricks involving the flip_pending status bits and vblank irqs.
  9443. * So using MMIO flips there would disrupt this mechanism.
  9444. */
  9445. if (engine == NULL)
  9446. return true;
  9447. if (INTEL_GEN(engine->i915) < 5)
  9448. return false;
  9449. if (i915.use_mmio_flip < 0)
  9450. return false;
  9451. else if (i915.use_mmio_flip > 0)
  9452. return true;
  9453. else if (i915.enable_execlists)
  9454. return true;
  9455. else if (obj->base.dma_buf &&
  9456. !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
  9457. false))
  9458. return true;
  9459. else
  9460. return engine != i915_gem_request_get_engine(obj->last_write_req);
  9461. }
  9462. static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
  9463. unsigned int rotation,
  9464. struct intel_unpin_work *work)
  9465. {
  9466. struct drm_device *dev = intel_crtc->base.dev;
  9467. struct drm_i915_private *dev_priv = dev->dev_private;
  9468. struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
  9469. const enum pipe pipe = intel_crtc->pipe;
  9470. u32 ctl, stride, tile_height;
  9471. ctl = I915_READ(PLANE_CTL(pipe, 0));
  9472. ctl &= ~PLANE_CTL_TILED_MASK;
  9473. switch (fb->modifier[0]) {
  9474. case DRM_FORMAT_MOD_NONE:
  9475. break;
  9476. case I915_FORMAT_MOD_X_TILED:
  9477. ctl |= PLANE_CTL_TILED_X;
  9478. break;
  9479. case I915_FORMAT_MOD_Y_TILED:
  9480. ctl |= PLANE_CTL_TILED_Y;
  9481. break;
  9482. case I915_FORMAT_MOD_Yf_TILED:
  9483. ctl |= PLANE_CTL_TILED_YF;
  9484. break;
  9485. default:
  9486. MISSING_CASE(fb->modifier[0]);
  9487. }
  9488. /*
  9489. * The stride is either expressed as a multiple of 64 bytes chunks for
  9490. * linear buffers or in number of tiles for tiled buffers.
  9491. */
  9492. if (intel_rotation_90_or_270(rotation)) {
  9493. /* stride = Surface height in tiles */
  9494. tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
  9495. stride = DIV_ROUND_UP(fb->height, tile_height);
  9496. } else {
  9497. stride = fb->pitches[0] /
  9498. intel_fb_stride_alignment(dev_priv, fb->modifier[0],
  9499. fb->pixel_format);
  9500. }
  9501. /*
  9502. * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
  9503. * PLANE_SURF updates, the update is then guaranteed to be atomic.
  9504. */
  9505. I915_WRITE(PLANE_CTL(pipe, 0), ctl);
  9506. I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
  9507. I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
  9508. POSTING_READ(PLANE_SURF(pipe, 0));
  9509. }
  9510. static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
  9511. struct intel_unpin_work *work)
  9512. {
  9513. struct drm_device *dev = intel_crtc->base.dev;
  9514. struct drm_i915_private *dev_priv = dev->dev_private;
  9515. struct intel_framebuffer *intel_fb =
  9516. to_intel_framebuffer(intel_crtc->base.primary->fb);
  9517. struct drm_i915_gem_object *obj = intel_fb->obj;
  9518. i915_reg_t reg = DSPCNTR(intel_crtc->plane);
  9519. u32 dspcntr;
  9520. dspcntr = I915_READ(reg);
  9521. if (obj->tiling_mode != I915_TILING_NONE)
  9522. dspcntr |= DISPPLANE_TILED;
  9523. else
  9524. dspcntr &= ~DISPPLANE_TILED;
  9525. I915_WRITE(reg, dspcntr);
  9526. I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
  9527. POSTING_READ(DSPSURF(intel_crtc->plane));
  9528. }
  9529. /*
  9530. * XXX: This is the temporary way to update the plane registers until we get
  9531. * around to using the usual plane update functions for MMIO flips
  9532. */
  9533. static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
  9534. {
  9535. struct intel_crtc *crtc = mmio_flip->crtc;
  9536. struct intel_unpin_work *work;
  9537. spin_lock_irq(&crtc->base.dev->event_lock);
  9538. work = crtc->unpin_work;
  9539. spin_unlock_irq(&crtc->base.dev->event_lock);
  9540. if (work == NULL)
  9541. return;
  9542. intel_mark_page_flip_active(work);
  9543. intel_pipe_update_start(crtc);
  9544. if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
  9545. skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
  9546. else
  9547. /* use_mmio_flip() retricts MMIO flips to ilk+ */
  9548. ilk_do_mmio_flip(crtc, work);
  9549. intel_pipe_update_end(crtc);
  9550. }
  9551. static void intel_mmio_flip_work_func(struct work_struct *work)
  9552. {
  9553. struct intel_mmio_flip *mmio_flip =
  9554. container_of(work, struct intel_mmio_flip, work);
  9555. struct intel_framebuffer *intel_fb =
  9556. to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
  9557. struct drm_i915_gem_object *obj = intel_fb->obj;
  9558. if (mmio_flip->req) {
  9559. WARN_ON(__i915_wait_request(mmio_flip->req,
  9560. false, NULL,
  9561. &mmio_flip->i915->rps.mmioflips));
  9562. i915_gem_request_unreference(mmio_flip->req);
  9563. }
  9564. /* For framebuffer backed by dmabuf, wait for fence */
  9565. if (obj->base.dma_buf)
  9566. WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
  9567. false, false,
  9568. MAX_SCHEDULE_TIMEOUT) < 0);
  9569. intel_do_mmio_flip(mmio_flip);
  9570. kfree(mmio_flip);
  9571. }
  9572. static int intel_queue_mmio_flip(struct drm_device *dev,
  9573. struct drm_crtc *crtc,
  9574. struct drm_i915_gem_object *obj)
  9575. {
  9576. struct intel_mmio_flip *mmio_flip;
  9577. mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
  9578. if (mmio_flip == NULL)
  9579. return -ENOMEM;
  9580. mmio_flip->i915 = to_i915(dev);
  9581. mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
  9582. mmio_flip->crtc = to_intel_crtc(crtc);
  9583. mmio_flip->rotation = crtc->primary->state->rotation;
  9584. INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
  9585. schedule_work(&mmio_flip->work);
  9586. return 0;
  9587. }
  9588. static int intel_default_queue_flip(struct drm_device *dev,
  9589. struct drm_crtc *crtc,
  9590. struct drm_framebuffer *fb,
  9591. struct drm_i915_gem_object *obj,
  9592. struct drm_i915_gem_request *req,
  9593. uint32_t flags)
  9594. {
  9595. return -ENODEV;
  9596. }
  9597. static bool __intel_pageflip_stall_check(struct drm_device *dev,
  9598. struct drm_crtc *crtc)
  9599. {
  9600. struct drm_i915_private *dev_priv = dev->dev_private;
  9601. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9602. struct intel_unpin_work *work = intel_crtc->unpin_work;
  9603. u32 addr;
  9604. if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
  9605. return true;
  9606. if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
  9607. return false;
  9608. if (!work->enable_stall_check)
  9609. return false;
  9610. if (work->flip_ready_vblank == 0) {
  9611. if (work->flip_queued_req &&
  9612. !i915_gem_request_completed(work->flip_queued_req, true))
  9613. return false;
  9614. work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
  9615. }
  9616. if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
  9617. return false;
  9618. /* Potential stall - if we see that the flip has happened,
  9619. * assume a missed interrupt. */
  9620. if (INTEL_INFO(dev)->gen >= 4)
  9621. addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
  9622. else
  9623. addr = I915_READ(DSPADDR(intel_crtc->plane));
  9624. /* There is a potential issue here with a false positive after a flip
  9625. * to the same address. We could address this by checking for a
  9626. * non-incrementing frame counter.
  9627. */
  9628. return addr == work->gtt_offset;
  9629. }
  9630. void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
  9631. {
  9632. struct drm_device *dev = dev_priv->dev;
  9633. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  9634. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9635. struct intel_unpin_work *work;
  9636. WARN_ON(!in_interrupt());
  9637. if (crtc == NULL)
  9638. return;
  9639. spin_lock(&dev->event_lock);
  9640. work = intel_crtc->unpin_work;
  9641. if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
  9642. WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
  9643. work->flip_queued_vblank, drm_vblank_count(dev, pipe));
  9644. page_flip_completed(intel_crtc);
  9645. work = NULL;
  9646. }
  9647. if (work != NULL &&
  9648. drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
  9649. intel_queue_rps_boost_for_request(work->flip_queued_req);
  9650. spin_unlock(&dev->event_lock);
  9651. }
  9652. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  9653. struct drm_framebuffer *fb,
  9654. struct drm_pending_vblank_event *event,
  9655. uint32_t page_flip_flags)
  9656. {
  9657. struct drm_device *dev = crtc->dev;
  9658. struct drm_i915_private *dev_priv = dev->dev_private;
  9659. struct drm_framebuffer *old_fb = crtc->primary->fb;
  9660. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  9661. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9662. struct drm_plane *primary = crtc->primary;
  9663. enum pipe pipe = intel_crtc->pipe;
  9664. struct intel_unpin_work *work;
  9665. struct intel_engine_cs *engine;
  9666. bool mmio_flip;
  9667. struct drm_i915_gem_request *request = NULL;
  9668. int ret;
  9669. /*
  9670. * drm_mode_page_flip_ioctl() should already catch this, but double
  9671. * check to be safe. In the future we may enable pageflipping from
  9672. * a disabled primary plane.
  9673. */
  9674. if (WARN_ON(intel_fb_obj(old_fb) == NULL))
  9675. return -EBUSY;
  9676. /* Can't change pixel format via MI display flips. */
  9677. if (fb->pixel_format != crtc->primary->fb->pixel_format)
  9678. return -EINVAL;
  9679. /*
  9680. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  9681. * Note that pitch changes could also affect these register.
  9682. */
  9683. if (INTEL_INFO(dev)->gen > 3 &&
  9684. (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
  9685. fb->pitches[0] != crtc->primary->fb->pitches[0]))
  9686. return -EINVAL;
  9687. if (i915_terminally_wedged(&dev_priv->gpu_error))
  9688. goto out_hang;
  9689. work = kzalloc(sizeof(*work), GFP_KERNEL);
  9690. if (work == NULL)
  9691. return -ENOMEM;
  9692. work->event = event;
  9693. work->crtc = crtc;
  9694. work->old_fb = old_fb;
  9695. INIT_WORK(&work->work, intel_unpin_work_fn);
  9696. ret = drm_crtc_vblank_get(crtc);
  9697. if (ret)
  9698. goto free_work;
  9699. /* We borrow the event spin lock for protecting unpin_work */
  9700. spin_lock_irq(&dev->event_lock);
  9701. if (intel_crtc->unpin_work) {
  9702. /* Before declaring the flip queue wedged, check if
  9703. * the hardware completed the operation behind our backs.
  9704. */
  9705. if (__intel_pageflip_stall_check(dev, crtc)) {
  9706. DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
  9707. page_flip_completed(intel_crtc);
  9708. } else {
  9709. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  9710. spin_unlock_irq(&dev->event_lock);
  9711. drm_crtc_vblank_put(crtc);
  9712. kfree(work);
  9713. return -EBUSY;
  9714. }
  9715. }
  9716. intel_crtc->unpin_work = work;
  9717. spin_unlock_irq(&dev->event_lock);
  9718. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  9719. flush_workqueue(dev_priv->wq);
  9720. /* Reference the objects for the scheduled work. */
  9721. drm_framebuffer_reference(work->old_fb);
  9722. drm_gem_object_reference(&obj->base);
  9723. crtc->primary->fb = fb;
  9724. update_state_fb(crtc->primary);
  9725. intel_fbc_pre_update(intel_crtc);
  9726. work->pending_flip_obj = obj;
  9727. ret = i915_mutex_lock_interruptible(dev);
  9728. if (ret)
  9729. goto cleanup;
  9730. intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
  9731. if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) {
  9732. ret = -EIO;
  9733. goto cleanup;
  9734. }
  9735. atomic_inc(&intel_crtc->unpin_work_count);
  9736. if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
  9737. work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
  9738. if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  9739. engine = &dev_priv->engine[BCS];
  9740. if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
  9741. /* vlv: DISPLAY_FLIP fails to change tiling */
  9742. engine = NULL;
  9743. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  9744. engine = &dev_priv->engine[BCS];
  9745. } else if (INTEL_INFO(dev)->gen >= 7) {
  9746. engine = i915_gem_request_get_engine(obj->last_write_req);
  9747. if (engine == NULL || engine->id != RCS)
  9748. engine = &dev_priv->engine[BCS];
  9749. } else {
  9750. engine = &dev_priv->engine[RCS];
  9751. }
  9752. mmio_flip = use_mmio_flip(engine, obj);
  9753. /* When using CS flips, we want to emit semaphores between rings.
  9754. * However, when using mmio flips we will create a task to do the
  9755. * synchronisation, so all we want here is to pin the framebuffer
  9756. * into the display plane and skip any waits.
  9757. */
  9758. if (!mmio_flip) {
  9759. ret = i915_gem_object_sync(obj, engine, &request);
  9760. if (ret)
  9761. goto cleanup_pending;
  9762. }
  9763. ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
  9764. if (ret)
  9765. goto cleanup_pending;
  9766. work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
  9767. obj, 0);
  9768. work->gtt_offset += intel_crtc->dspaddr_offset;
  9769. if (mmio_flip) {
  9770. ret = intel_queue_mmio_flip(dev, crtc, obj);
  9771. if (ret)
  9772. goto cleanup_unpin;
  9773. i915_gem_request_assign(&work->flip_queued_req,
  9774. obj->last_write_req);
  9775. } else {
  9776. if (!request) {
  9777. request = i915_gem_request_alloc(engine, NULL);
  9778. if (IS_ERR(request)) {
  9779. ret = PTR_ERR(request);
  9780. goto cleanup_unpin;
  9781. }
  9782. }
  9783. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
  9784. page_flip_flags);
  9785. if (ret)
  9786. goto cleanup_unpin;
  9787. i915_gem_request_assign(&work->flip_queued_req, request);
  9788. }
  9789. if (request)
  9790. i915_add_request_no_flush(request);
  9791. work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
  9792. work->enable_stall_check = true;
  9793. i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
  9794. to_intel_plane(primary)->frontbuffer_bit);
  9795. mutex_unlock(&dev->struct_mutex);
  9796. intel_frontbuffer_flip_prepare(dev,
  9797. to_intel_plane(primary)->frontbuffer_bit);
  9798. trace_i915_flip_request(intel_crtc->plane, obj);
  9799. return 0;
  9800. cleanup_unpin:
  9801. intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
  9802. cleanup_pending:
  9803. if (!IS_ERR_OR_NULL(request))
  9804. i915_add_request_no_flush(request);
  9805. atomic_dec(&intel_crtc->unpin_work_count);
  9806. mutex_unlock(&dev->struct_mutex);
  9807. cleanup:
  9808. crtc->primary->fb = old_fb;
  9809. update_state_fb(crtc->primary);
  9810. drm_gem_object_unreference_unlocked(&obj->base);
  9811. drm_framebuffer_unreference(work->old_fb);
  9812. spin_lock_irq(&dev->event_lock);
  9813. intel_crtc->unpin_work = NULL;
  9814. spin_unlock_irq(&dev->event_lock);
  9815. drm_crtc_vblank_put(crtc);
  9816. free_work:
  9817. kfree(work);
  9818. if (ret == -EIO) {
  9819. struct drm_atomic_state *state;
  9820. struct drm_plane_state *plane_state;
  9821. out_hang:
  9822. state = drm_atomic_state_alloc(dev);
  9823. if (!state)
  9824. return -ENOMEM;
  9825. state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
  9826. retry:
  9827. plane_state = drm_atomic_get_plane_state(state, primary);
  9828. ret = PTR_ERR_OR_ZERO(plane_state);
  9829. if (!ret) {
  9830. drm_atomic_set_fb_for_plane(plane_state, fb);
  9831. ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
  9832. if (!ret)
  9833. ret = drm_atomic_commit(state);
  9834. }
  9835. if (ret == -EDEADLK) {
  9836. drm_modeset_backoff(state->acquire_ctx);
  9837. drm_atomic_state_clear(state);
  9838. goto retry;
  9839. }
  9840. if (ret)
  9841. drm_atomic_state_free(state);
  9842. if (ret == 0 && event) {
  9843. spin_lock_irq(&dev->event_lock);
  9844. drm_crtc_send_vblank_event(crtc, event);
  9845. spin_unlock_irq(&dev->event_lock);
  9846. }
  9847. }
  9848. return ret;
  9849. }
  9850. /**
  9851. * intel_wm_need_update - Check whether watermarks need updating
  9852. * @plane: drm plane
  9853. * @state: new plane state
  9854. *
  9855. * Check current plane state versus the new one to determine whether
  9856. * watermarks need to be recalculated.
  9857. *
  9858. * Returns true or false.
  9859. */
  9860. static bool intel_wm_need_update(struct drm_plane *plane,
  9861. struct drm_plane_state *state)
  9862. {
  9863. struct intel_plane_state *new = to_intel_plane_state(state);
  9864. struct intel_plane_state *cur = to_intel_plane_state(plane->state);
  9865. /* Update watermarks on tiling or size changes. */
  9866. if (new->visible != cur->visible)
  9867. return true;
  9868. if (!cur->base.fb || !new->base.fb)
  9869. return false;
  9870. if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
  9871. cur->base.rotation != new->base.rotation ||
  9872. drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
  9873. drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
  9874. drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
  9875. drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
  9876. return true;
  9877. return false;
  9878. }
  9879. static bool needs_scaling(struct intel_plane_state *state)
  9880. {
  9881. int src_w = drm_rect_width(&state->src) >> 16;
  9882. int src_h = drm_rect_height(&state->src) >> 16;
  9883. int dst_w = drm_rect_width(&state->dst);
  9884. int dst_h = drm_rect_height(&state->dst);
  9885. return (src_w != dst_w || src_h != dst_h);
  9886. }
  9887. int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
  9888. struct drm_plane_state *plane_state)
  9889. {
  9890. struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
  9891. struct drm_crtc *crtc = crtc_state->crtc;
  9892. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9893. struct drm_plane *plane = plane_state->plane;
  9894. struct drm_device *dev = crtc->dev;
  9895. struct drm_i915_private *dev_priv = to_i915(dev);
  9896. struct intel_plane_state *old_plane_state =
  9897. to_intel_plane_state(plane->state);
  9898. int idx = intel_crtc->base.base.id, ret;
  9899. bool mode_changed = needs_modeset(crtc_state);
  9900. bool was_crtc_enabled = crtc->state->active;
  9901. bool is_crtc_enabled = crtc_state->active;
  9902. bool turn_off, turn_on, visible, was_visible;
  9903. struct drm_framebuffer *fb = plane_state->fb;
  9904. if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
  9905. plane->type != DRM_PLANE_TYPE_CURSOR) {
  9906. ret = skl_update_scaler_plane(
  9907. to_intel_crtc_state(crtc_state),
  9908. to_intel_plane_state(plane_state));
  9909. if (ret)
  9910. return ret;
  9911. }
  9912. was_visible = old_plane_state->visible;
  9913. visible = to_intel_plane_state(plane_state)->visible;
  9914. if (!was_crtc_enabled && WARN_ON(was_visible))
  9915. was_visible = false;
  9916. /*
  9917. * Visibility is calculated as if the crtc was on, but
  9918. * after scaler setup everything depends on it being off
  9919. * when the crtc isn't active.
  9920. *
  9921. * FIXME this is wrong for watermarks. Watermarks should also
  9922. * be computed as if the pipe would be active. Perhaps move
  9923. * per-plane wm computation to the .check_plane() hook, and
  9924. * only combine the results from all planes in the current place?
  9925. */
  9926. if (!is_crtc_enabled)
  9927. to_intel_plane_state(plane_state)->visible = visible = false;
  9928. if (!was_visible && !visible)
  9929. return 0;
  9930. if (fb != old_plane_state->base.fb)
  9931. pipe_config->fb_changed = true;
  9932. turn_off = was_visible && (!visible || mode_changed);
  9933. turn_on = visible && (!was_visible || mode_changed);
  9934. DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
  9935. plane->base.id, fb ? fb->base.id : -1);
  9936. DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
  9937. plane->base.id, was_visible, visible,
  9938. turn_off, turn_on, mode_changed);
  9939. if (turn_on) {
  9940. pipe_config->update_wm_pre = true;
  9941. /* must disable cxsr around plane enable/disable */
  9942. if (plane->type != DRM_PLANE_TYPE_CURSOR)
  9943. pipe_config->disable_cxsr = true;
  9944. } else if (turn_off) {
  9945. pipe_config->update_wm_post = true;
  9946. /* must disable cxsr around plane enable/disable */
  9947. if (plane->type != DRM_PLANE_TYPE_CURSOR)
  9948. pipe_config->disable_cxsr = true;
  9949. } else if (intel_wm_need_update(plane, plane_state)) {
  9950. /* FIXME bollocks */
  9951. pipe_config->update_wm_pre = true;
  9952. pipe_config->update_wm_post = true;
  9953. }
  9954. /* Pre-gen9 platforms need two-step watermark updates */
  9955. if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
  9956. INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
  9957. to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
  9958. if (visible || was_visible)
  9959. pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
  9960. /*
  9961. * WaCxSRDisabledForSpriteScaling:ivb
  9962. *
  9963. * cstate->update_wm was already set above, so this flag will
  9964. * take effect when we commit and program watermarks.
  9965. */
  9966. if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
  9967. needs_scaling(to_intel_plane_state(plane_state)) &&
  9968. !needs_scaling(old_plane_state))
  9969. pipe_config->disable_lp_wm = true;
  9970. return 0;
  9971. }
  9972. static bool encoders_cloneable(const struct intel_encoder *a,
  9973. const struct intel_encoder *b)
  9974. {
  9975. /* masks could be asymmetric, so check both ways */
  9976. return a == b || (a->cloneable & (1 << b->type) &&
  9977. b->cloneable & (1 << a->type));
  9978. }
  9979. static bool check_single_encoder_cloning(struct drm_atomic_state *state,
  9980. struct intel_crtc *crtc,
  9981. struct intel_encoder *encoder)
  9982. {
  9983. struct intel_encoder *source_encoder;
  9984. struct drm_connector *connector;
  9985. struct drm_connector_state *connector_state;
  9986. int i;
  9987. for_each_connector_in_state(state, connector, connector_state, i) {
  9988. if (connector_state->crtc != &crtc->base)
  9989. continue;
  9990. source_encoder =
  9991. to_intel_encoder(connector_state->best_encoder);
  9992. if (!encoders_cloneable(encoder, source_encoder))
  9993. return false;
  9994. }
  9995. return true;
  9996. }
  9997. static bool check_encoder_cloning(struct drm_atomic_state *state,
  9998. struct intel_crtc *crtc)
  9999. {
  10000. struct intel_encoder *encoder;
  10001. struct drm_connector *connector;
  10002. struct drm_connector_state *connector_state;
  10003. int i;
  10004. for_each_connector_in_state(state, connector, connector_state, i) {
  10005. if (connector_state->crtc != &crtc->base)
  10006. continue;
  10007. encoder = to_intel_encoder(connector_state->best_encoder);
  10008. if (!check_single_encoder_cloning(state, crtc, encoder))
  10009. return false;
  10010. }
  10011. return true;
  10012. }
  10013. static int intel_crtc_atomic_check(struct drm_crtc *crtc,
  10014. struct drm_crtc_state *crtc_state)
  10015. {
  10016. struct drm_device *dev = crtc->dev;
  10017. struct drm_i915_private *dev_priv = dev->dev_private;
  10018. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10019. struct intel_crtc_state *pipe_config =
  10020. to_intel_crtc_state(crtc_state);
  10021. struct drm_atomic_state *state = crtc_state->state;
  10022. int ret;
  10023. bool mode_changed = needs_modeset(crtc_state);
  10024. if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
  10025. DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  10026. return -EINVAL;
  10027. }
  10028. if (mode_changed && !crtc_state->active)
  10029. pipe_config->update_wm_post = true;
  10030. if (mode_changed && crtc_state->enable &&
  10031. dev_priv->display.crtc_compute_clock &&
  10032. !WARN_ON(pipe_config->shared_dpll)) {
  10033. ret = dev_priv->display.crtc_compute_clock(intel_crtc,
  10034. pipe_config);
  10035. if (ret)
  10036. return ret;
  10037. }
  10038. if (crtc_state->color_mgmt_changed) {
  10039. ret = intel_color_check(crtc, crtc_state);
  10040. if (ret)
  10041. return ret;
  10042. }
  10043. ret = 0;
  10044. if (dev_priv->display.compute_pipe_wm) {
  10045. ret = dev_priv->display.compute_pipe_wm(pipe_config);
  10046. if (ret) {
  10047. DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
  10048. return ret;
  10049. }
  10050. }
  10051. if (dev_priv->display.compute_intermediate_wm &&
  10052. !to_intel_atomic_state(state)->skip_intermediate_wm) {
  10053. if (WARN_ON(!dev_priv->display.compute_pipe_wm))
  10054. return 0;
  10055. /*
  10056. * Calculate 'intermediate' watermarks that satisfy both the
  10057. * old state and the new state. We can program these
  10058. * immediately.
  10059. */
  10060. ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
  10061. intel_crtc,
  10062. pipe_config);
  10063. if (ret) {
  10064. DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
  10065. return ret;
  10066. }
  10067. }
  10068. if (INTEL_INFO(dev)->gen >= 9) {
  10069. if (mode_changed)
  10070. ret = skl_update_scaler_crtc(pipe_config);
  10071. if (!ret)
  10072. ret = intel_atomic_setup_scalers(dev, intel_crtc,
  10073. pipe_config);
  10074. }
  10075. return ret;
  10076. }
  10077. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  10078. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  10079. .atomic_begin = intel_begin_crtc_commit,
  10080. .atomic_flush = intel_finish_crtc_commit,
  10081. .atomic_check = intel_crtc_atomic_check,
  10082. };
  10083. static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
  10084. {
  10085. struct intel_connector *connector;
  10086. for_each_intel_connector(dev, connector) {
  10087. if (connector->base.encoder) {
  10088. connector->base.state->best_encoder =
  10089. connector->base.encoder;
  10090. connector->base.state->crtc =
  10091. connector->base.encoder->crtc;
  10092. } else {
  10093. connector->base.state->best_encoder = NULL;
  10094. connector->base.state->crtc = NULL;
  10095. }
  10096. }
  10097. }
  10098. static void
  10099. connected_sink_compute_bpp(struct intel_connector *connector,
  10100. struct intel_crtc_state *pipe_config)
  10101. {
  10102. int bpp = pipe_config->pipe_bpp;
  10103. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  10104. connector->base.base.id,
  10105. connector->base.name);
  10106. /* Don't use an invalid EDID bpc value */
  10107. if (connector->base.display_info.bpc &&
  10108. connector->base.display_info.bpc * 3 < bpp) {
  10109. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  10110. bpp, connector->base.display_info.bpc*3);
  10111. pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  10112. }
  10113. /* Clamp bpp to default limit on screens without EDID 1.4 */
  10114. if (connector->base.display_info.bpc == 0) {
  10115. int type = connector->base.connector_type;
  10116. int clamp_bpp = 24;
  10117. /* Fall back to 18 bpp when DP sink capability is unknown. */
  10118. if (type == DRM_MODE_CONNECTOR_DisplayPort ||
  10119. type == DRM_MODE_CONNECTOR_eDP)
  10120. clamp_bpp = 18;
  10121. if (bpp > clamp_bpp) {
  10122. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
  10123. bpp, clamp_bpp);
  10124. pipe_config->pipe_bpp = clamp_bpp;
  10125. }
  10126. }
  10127. }
  10128. static int
  10129. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  10130. struct intel_crtc_state *pipe_config)
  10131. {
  10132. struct drm_device *dev = crtc->base.dev;
  10133. struct drm_atomic_state *state;
  10134. struct drm_connector *connector;
  10135. struct drm_connector_state *connector_state;
  10136. int bpp, i;
  10137. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
  10138. bpp = 10*3;
  10139. else if (INTEL_INFO(dev)->gen >= 5)
  10140. bpp = 12*3;
  10141. else
  10142. bpp = 8*3;
  10143. pipe_config->pipe_bpp = bpp;
  10144. state = pipe_config->base.state;
  10145. /* Clamp display bpp to EDID value */
  10146. for_each_connector_in_state(state, connector, connector_state, i) {
  10147. if (connector_state->crtc != &crtc->base)
  10148. continue;
  10149. connected_sink_compute_bpp(to_intel_connector(connector),
  10150. pipe_config);
  10151. }
  10152. return bpp;
  10153. }
  10154. static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
  10155. {
  10156. DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
  10157. "type: 0x%x flags: 0x%x\n",
  10158. mode->crtc_clock,
  10159. mode->crtc_hdisplay, mode->crtc_hsync_start,
  10160. mode->crtc_hsync_end, mode->crtc_htotal,
  10161. mode->crtc_vdisplay, mode->crtc_vsync_start,
  10162. mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
  10163. }
  10164. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  10165. struct intel_crtc_state *pipe_config,
  10166. const char *context)
  10167. {
  10168. struct drm_device *dev = crtc->base.dev;
  10169. struct drm_plane *plane;
  10170. struct intel_plane *intel_plane;
  10171. struct intel_plane_state *state;
  10172. struct drm_framebuffer *fb;
  10173. DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
  10174. context, pipe_config, pipe_name(crtc->pipe));
  10175. DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
  10176. DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  10177. pipe_config->pipe_bpp, pipe_config->dither);
  10178. DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  10179. pipe_config->has_pch_encoder,
  10180. pipe_config->fdi_lanes,
  10181. pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  10182. pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  10183. pipe_config->fdi_m_n.tu);
  10184. DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  10185. pipe_config->has_dp_encoder,
  10186. pipe_config->lane_count,
  10187. pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
  10188. pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
  10189. pipe_config->dp_m_n.tu);
  10190. DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
  10191. pipe_config->has_dp_encoder,
  10192. pipe_config->lane_count,
  10193. pipe_config->dp_m2_n2.gmch_m,
  10194. pipe_config->dp_m2_n2.gmch_n,
  10195. pipe_config->dp_m2_n2.link_m,
  10196. pipe_config->dp_m2_n2.link_n,
  10197. pipe_config->dp_m2_n2.tu);
  10198. DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
  10199. pipe_config->has_audio,
  10200. pipe_config->has_infoframe);
  10201. DRM_DEBUG_KMS("requested mode:\n");
  10202. drm_mode_debug_printmodeline(&pipe_config->base.mode);
  10203. DRM_DEBUG_KMS("adjusted mode:\n");
  10204. drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
  10205. intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
  10206. DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
  10207. DRM_DEBUG_KMS("pipe src size: %dx%d\n",
  10208. pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  10209. DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
  10210. crtc->num_scalers,
  10211. pipe_config->scaler_state.scaler_users,
  10212. pipe_config->scaler_state.scaler_id);
  10213. DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  10214. pipe_config->gmch_pfit.control,
  10215. pipe_config->gmch_pfit.pgm_ratios,
  10216. pipe_config->gmch_pfit.lvds_border_bits);
  10217. DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  10218. pipe_config->pch_pfit.pos,
  10219. pipe_config->pch_pfit.size,
  10220. pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  10221. DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  10222. DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  10223. if (IS_BROXTON(dev)) {
  10224. DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
  10225. "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
  10226. "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
  10227. pipe_config->ddi_pll_sel,
  10228. pipe_config->dpll_hw_state.ebb0,
  10229. pipe_config->dpll_hw_state.ebb4,
  10230. pipe_config->dpll_hw_state.pll0,
  10231. pipe_config->dpll_hw_state.pll1,
  10232. pipe_config->dpll_hw_state.pll2,
  10233. pipe_config->dpll_hw_state.pll3,
  10234. pipe_config->dpll_hw_state.pll6,
  10235. pipe_config->dpll_hw_state.pll8,
  10236. pipe_config->dpll_hw_state.pll9,
  10237. pipe_config->dpll_hw_state.pll10,
  10238. pipe_config->dpll_hw_state.pcsdw12);
  10239. } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
  10240. DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
  10241. "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
  10242. pipe_config->ddi_pll_sel,
  10243. pipe_config->dpll_hw_state.ctrl1,
  10244. pipe_config->dpll_hw_state.cfgcr1,
  10245. pipe_config->dpll_hw_state.cfgcr2);
  10246. } else if (HAS_DDI(dev)) {
  10247. DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
  10248. pipe_config->ddi_pll_sel,
  10249. pipe_config->dpll_hw_state.wrpll,
  10250. pipe_config->dpll_hw_state.spll);
  10251. } else {
  10252. DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
  10253. "fp0: 0x%x, fp1: 0x%x\n",
  10254. pipe_config->dpll_hw_state.dpll,
  10255. pipe_config->dpll_hw_state.dpll_md,
  10256. pipe_config->dpll_hw_state.fp0,
  10257. pipe_config->dpll_hw_state.fp1);
  10258. }
  10259. DRM_DEBUG_KMS("planes on this crtc\n");
  10260. list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  10261. intel_plane = to_intel_plane(plane);
  10262. if (intel_plane->pipe != crtc->pipe)
  10263. continue;
  10264. state = to_intel_plane_state(plane->state);
  10265. fb = state->base.fb;
  10266. if (!fb) {
  10267. DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
  10268. "disabled, scaler_id = %d\n",
  10269. plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
  10270. plane->base.id, intel_plane->pipe,
  10271. (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
  10272. drm_plane_index(plane), state->scaler_id);
  10273. continue;
  10274. }
  10275. DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
  10276. plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
  10277. plane->base.id, intel_plane->pipe,
  10278. crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
  10279. drm_plane_index(plane));
  10280. DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
  10281. fb->base.id, fb->width, fb->height, fb->pixel_format);
  10282. DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
  10283. state->scaler_id,
  10284. state->src.x1 >> 16, state->src.y1 >> 16,
  10285. drm_rect_width(&state->src) >> 16,
  10286. drm_rect_height(&state->src) >> 16,
  10287. state->dst.x1, state->dst.y1,
  10288. drm_rect_width(&state->dst), drm_rect_height(&state->dst));
  10289. }
  10290. }
  10291. static bool check_digital_port_conflicts(struct drm_atomic_state *state)
  10292. {
  10293. struct drm_device *dev = state->dev;
  10294. struct drm_connector *connector;
  10295. unsigned int used_ports = 0;
  10296. /*
  10297. * Walk the connector list instead of the encoder
  10298. * list to detect the problem on ddi platforms
  10299. * where there's just one encoder per digital port.
  10300. */
  10301. drm_for_each_connector(connector, dev) {
  10302. struct drm_connector_state *connector_state;
  10303. struct intel_encoder *encoder;
  10304. connector_state = drm_atomic_get_existing_connector_state(state, connector);
  10305. if (!connector_state)
  10306. connector_state = connector->state;
  10307. if (!connector_state->best_encoder)
  10308. continue;
  10309. encoder = to_intel_encoder(connector_state->best_encoder);
  10310. WARN_ON(!connector_state->crtc);
  10311. switch (encoder->type) {
  10312. unsigned int port_mask;
  10313. case INTEL_OUTPUT_UNKNOWN:
  10314. if (WARN_ON(!HAS_DDI(dev)))
  10315. break;
  10316. case INTEL_OUTPUT_DISPLAYPORT:
  10317. case INTEL_OUTPUT_HDMI:
  10318. case INTEL_OUTPUT_EDP:
  10319. port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
  10320. /* the same port mustn't appear more than once */
  10321. if (used_ports & port_mask)
  10322. return false;
  10323. used_ports |= port_mask;
  10324. default:
  10325. break;
  10326. }
  10327. }
  10328. return true;
  10329. }
  10330. static void
  10331. clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
  10332. {
  10333. struct drm_crtc_state tmp_state;
  10334. struct intel_crtc_scaler_state scaler_state;
  10335. struct intel_dpll_hw_state dpll_hw_state;
  10336. struct intel_shared_dpll *shared_dpll;
  10337. uint32_t ddi_pll_sel;
  10338. bool force_thru;
  10339. /* FIXME: before the switch to atomic started, a new pipe_config was
  10340. * kzalloc'd. Code that depends on any field being zero should be
  10341. * fixed, so that the crtc_state can be safely duplicated. For now,
  10342. * only fields that are know to not cause problems are preserved. */
  10343. tmp_state = crtc_state->base;
  10344. scaler_state = crtc_state->scaler_state;
  10345. shared_dpll = crtc_state->shared_dpll;
  10346. dpll_hw_state = crtc_state->dpll_hw_state;
  10347. ddi_pll_sel = crtc_state->ddi_pll_sel;
  10348. force_thru = crtc_state->pch_pfit.force_thru;
  10349. memset(crtc_state, 0, sizeof *crtc_state);
  10350. crtc_state->base = tmp_state;
  10351. crtc_state->scaler_state = scaler_state;
  10352. crtc_state->shared_dpll = shared_dpll;
  10353. crtc_state->dpll_hw_state = dpll_hw_state;
  10354. crtc_state->ddi_pll_sel = ddi_pll_sel;
  10355. crtc_state->pch_pfit.force_thru = force_thru;
  10356. }
  10357. static int
  10358. intel_modeset_pipe_config(struct drm_crtc *crtc,
  10359. struct intel_crtc_state *pipe_config)
  10360. {
  10361. struct drm_atomic_state *state = pipe_config->base.state;
  10362. struct intel_encoder *encoder;
  10363. struct drm_connector *connector;
  10364. struct drm_connector_state *connector_state;
  10365. int base_bpp, ret = -EINVAL;
  10366. int i;
  10367. bool retry = true;
  10368. clear_intel_crtc_state(pipe_config);
  10369. pipe_config->cpu_transcoder =
  10370. (enum transcoder) to_intel_crtc(crtc)->pipe;
  10371. /*
  10372. * Sanitize sync polarity flags based on requested ones. If neither
  10373. * positive or negative polarity is requested, treat this as meaning
  10374. * negative polarity.
  10375. */
  10376. if (!(pipe_config->base.adjusted_mode.flags &
  10377. (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  10378. pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  10379. if (!(pipe_config->base.adjusted_mode.flags &
  10380. (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  10381. pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  10382. base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  10383. pipe_config);
  10384. if (base_bpp < 0)
  10385. goto fail;
  10386. /*
  10387. * Determine the real pipe dimensions. Note that stereo modes can
  10388. * increase the actual pipe size due to the frame doubling and
  10389. * insertion of additional space for blanks between the frame. This
  10390. * is stored in the crtc timings. We use the requested mode to do this
  10391. * computation to clearly distinguish it from the adjusted mode, which
  10392. * can be changed by the connectors in the below retry loop.
  10393. */
  10394. drm_crtc_get_hv_timing(&pipe_config->base.mode,
  10395. &pipe_config->pipe_src_w,
  10396. &pipe_config->pipe_src_h);
  10397. encoder_retry:
  10398. /* Ensure the port clock defaults are reset when retrying. */
  10399. pipe_config->port_clock = 0;
  10400. pipe_config->pixel_multiplier = 1;
  10401. /* Fill in default crtc timings, allow encoders to overwrite them. */
  10402. drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
  10403. CRTC_STEREO_DOUBLE);
  10404. /* Pass our mode to the connectors and the CRTC to give them a chance to
  10405. * adjust it according to limitations or connector properties, and also
  10406. * a chance to reject the mode entirely.
  10407. */
  10408. for_each_connector_in_state(state, connector, connector_state, i) {
  10409. if (connector_state->crtc != crtc)
  10410. continue;
  10411. encoder = to_intel_encoder(connector_state->best_encoder);
  10412. if (!(encoder->compute_config(encoder, pipe_config))) {
  10413. DRM_DEBUG_KMS("Encoder config failure\n");
  10414. goto fail;
  10415. }
  10416. }
  10417. /* Set default port clock if not overwritten by the encoder. Needs to be
  10418. * done afterwards in case the encoder adjusts the mode. */
  10419. if (!pipe_config->port_clock)
  10420. pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
  10421. * pipe_config->pixel_multiplier;
  10422. ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  10423. if (ret < 0) {
  10424. DRM_DEBUG_KMS("CRTC fixup failed\n");
  10425. goto fail;
  10426. }
  10427. if (ret == RETRY) {
  10428. if (WARN(!retry, "loop in pipe configuration computation\n")) {
  10429. ret = -EINVAL;
  10430. goto fail;
  10431. }
  10432. DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  10433. retry = false;
  10434. goto encoder_retry;
  10435. }
  10436. /* Dithering seems to not pass-through bits correctly when it should, so
  10437. * only enable it on 6bpc panels. */
  10438. pipe_config->dither = pipe_config->pipe_bpp == 6*3;
  10439. DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
  10440. base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  10441. fail:
  10442. return ret;
  10443. }
  10444. static void
  10445. intel_modeset_update_crtc_state(struct drm_atomic_state *state)
  10446. {
  10447. struct drm_crtc *crtc;
  10448. struct drm_crtc_state *crtc_state;
  10449. int i;
  10450. /* Double check state. */
  10451. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  10452. to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
  10453. /* Update hwmode for vblank functions */
  10454. if (crtc->state->active)
  10455. crtc->hwmode = crtc->state->adjusted_mode;
  10456. else
  10457. crtc->hwmode.crtc_clock = 0;
  10458. /*
  10459. * Update legacy state to satisfy fbc code. This can
  10460. * be removed when fbc uses the atomic state.
  10461. */
  10462. if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
  10463. struct drm_plane_state *plane_state = crtc->primary->state;
  10464. crtc->primary->fb = plane_state->fb;
  10465. crtc->x = plane_state->src_x >> 16;
  10466. crtc->y = plane_state->src_y >> 16;
  10467. }
  10468. }
  10469. }
  10470. static bool intel_fuzzy_clock_check(int clock1, int clock2)
  10471. {
  10472. int diff;
  10473. if (clock1 == clock2)
  10474. return true;
  10475. if (!clock1 || !clock2)
  10476. return false;
  10477. diff = abs(clock1 - clock2);
  10478. if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  10479. return true;
  10480. return false;
  10481. }
  10482. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  10483. list_for_each_entry((intel_crtc), \
  10484. &(dev)->mode_config.crtc_list, \
  10485. base.head) \
  10486. for_each_if (mask & (1 <<(intel_crtc)->pipe))
  10487. static bool
  10488. intel_compare_m_n(unsigned int m, unsigned int n,
  10489. unsigned int m2, unsigned int n2,
  10490. bool exact)
  10491. {
  10492. if (m == m2 && n == n2)
  10493. return true;
  10494. if (exact || !m || !n || !m2 || !n2)
  10495. return false;
  10496. BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
  10497. if (n > n2) {
  10498. while (n > n2) {
  10499. m2 <<= 1;
  10500. n2 <<= 1;
  10501. }
  10502. } else if (n < n2) {
  10503. while (n < n2) {
  10504. m <<= 1;
  10505. n <<= 1;
  10506. }
  10507. }
  10508. if (n != n2)
  10509. return false;
  10510. return intel_fuzzy_clock_check(m, m2);
  10511. }
  10512. static bool
  10513. intel_compare_link_m_n(const struct intel_link_m_n *m_n,
  10514. struct intel_link_m_n *m2_n2,
  10515. bool adjust)
  10516. {
  10517. if (m_n->tu == m2_n2->tu &&
  10518. intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
  10519. m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
  10520. intel_compare_m_n(m_n->link_m, m_n->link_n,
  10521. m2_n2->link_m, m2_n2->link_n, !adjust)) {
  10522. if (adjust)
  10523. *m2_n2 = *m_n;
  10524. return true;
  10525. }
  10526. return false;
  10527. }
  10528. static bool
  10529. intel_pipe_config_compare(struct drm_device *dev,
  10530. struct intel_crtc_state *current_config,
  10531. struct intel_crtc_state *pipe_config,
  10532. bool adjust)
  10533. {
  10534. bool ret = true;
  10535. #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
  10536. do { \
  10537. if (!adjust) \
  10538. DRM_ERROR(fmt, ##__VA_ARGS__); \
  10539. else \
  10540. DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
  10541. } while (0)
  10542. #define PIPE_CONF_CHECK_X(name) \
  10543. if (current_config->name != pipe_config->name) { \
  10544. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10545. "(expected 0x%08x, found 0x%08x)\n", \
  10546. current_config->name, \
  10547. pipe_config->name); \
  10548. ret = false; \
  10549. }
  10550. #define PIPE_CONF_CHECK_I(name) \
  10551. if (current_config->name != pipe_config->name) { \
  10552. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10553. "(expected %i, found %i)\n", \
  10554. current_config->name, \
  10555. pipe_config->name); \
  10556. ret = false; \
  10557. }
  10558. #define PIPE_CONF_CHECK_P(name) \
  10559. if (current_config->name != pipe_config->name) { \
  10560. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10561. "(expected %p, found %p)\n", \
  10562. current_config->name, \
  10563. pipe_config->name); \
  10564. ret = false; \
  10565. }
  10566. #define PIPE_CONF_CHECK_M_N(name) \
  10567. if (!intel_compare_link_m_n(&current_config->name, \
  10568. &pipe_config->name,\
  10569. adjust)) { \
  10570. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10571. "(expected tu %i gmch %i/%i link %i/%i, " \
  10572. "found tu %i, gmch %i/%i link %i/%i)\n", \
  10573. current_config->name.tu, \
  10574. current_config->name.gmch_m, \
  10575. current_config->name.gmch_n, \
  10576. current_config->name.link_m, \
  10577. current_config->name.link_n, \
  10578. pipe_config->name.tu, \
  10579. pipe_config->name.gmch_m, \
  10580. pipe_config->name.gmch_n, \
  10581. pipe_config->name.link_m, \
  10582. pipe_config->name.link_n); \
  10583. ret = false; \
  10584. }
  10585. /* This is required for BDW+ where there is only one set of registers for
  10586. * switching between high and low RR.
  10587. * This macro can be used whenever a comparison has to be made between one
  10588. * hw state and multiple sw state variables.
  10589. */
  10590. #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
  10591. if (!intel_compare_link_m_n(&current_config->name, \
  10592. &pipe_config->name, adjust) && \
  10593. !intel_compare_link_m_n(&current_config->alt_name, \
  10594. &pipe_config->name, adjust)) { \
  10595. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10596. "(expected tu %i gmch %i/%i link %i/%i, " \
  10597. "or tu %i gmch %i/%i link %i/%i, " \
  10598. "found tu %i, gmch %i/%i link %i/%i)\n", \
  10599. current_config->name.tu, \
  10600. current_config->name.gmch_m, \
  10601. current_config->name.gmch_n, \
  10602. current_config->name.link_m, \
  10603. current_config->name.link_n, \
  10604. current_config->alt_name.tu, \
  10605. current_config->alt_name.gmch_m, \
  10606. current_config->alt_name.gmch_n, \
  10607. current_config->alt_name.link_m, \
  10608. current_config->alt_name.link_n, \
  10609. pipe_config->name.tu, \
  10610. pipe_config->name.gmch_m, \
  10611. pipe_config->name.gmch_n, \
  10612. pipe_config->name.link_m, \
  10613. pipe_config->name.link_n); \
  10614. ret = false; \
  10615. }
  10616. #define PIPE_CONF_CHECK_FLAGS(name, mask) \
  10617. if ((current_config->name ^ pipe_config->name) & (mask)) { \
  10618. INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
  10619. "(expected %i, found %i)\n", \
  10620. current_config->name & (mask), \
  10621. pipe_config->name & (mask)); \
  10622. ret = false; \
  10623. }
  10624. #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
  10625. if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
  10626. INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  10627. "(expected %i, found %i)\n", \
  10628. current_config->name, \
  10629. pipe_config->name); \
  10630. ret = false; \
  10631. }
  10632. #define PIPE_CONF_QUIRK(quirk) \
  10633. ((current_config->quirks | pipe_config->quirks) & (quirk))
  10634. PIPE_CONF_CHECK_I(cpu_transcoder);
  10635. PIPE_CONF_CHECK_I(has_pch_encoder);
  10636. PIPE_CONF_CHECK_I(fdi_lanes);
  10637. PIPE_CONF_CHECK_M_N(fdi_m_n);
  10638. PIPE_CONF_CHECK_I(has_dp_encoder);
  10639. PIPE_CONF_CHECK_I(lane_count);
  10640. if (INTEL_INFO(dev)->gen < 8) {
  10641. PIPE_CONF_CHECK_M_N(dp_m_n);
  10642. if (current_config->has_drrs)
  10643. PIPE_CONF_CHECK_M_N(dp_m2_n2);
  10644. } else
  10645. PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
  10646. PIPE_CONF_CHECK_I(has_dsi_encoder);
  10647. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
  10648. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
  10649. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
  10650. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
  10651. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
  10652. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
  10653. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
  10654. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
  10655. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
  10656. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
  10657. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
  10658. PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
  10659. PIPE_CONF_CHECK_I(pixel_multiplier);
  10660. PIPE_CONF_CHECK_I(has_hdmi_sink);
  10661. if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
  10662. IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
  10663. PIPE_CONF_CHECK_I(limited_color_range);
  10664. PIPE_CONF_CHECK_I(has_infoframe);
  10665. PIPE_CONF_CHECK_I(has_audio);
  10666. PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  10667. DRM_MODE_FLAG_INTERLACE);
  10668. if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  10669. PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  10670. DRM_MODE_FLAG_PHSYNC);
  10671. PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  10672. DRM_MODE_FLAG_NHSYNC);
  10673. PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  10674. DRM_MODE_FLAG_PVSYNC);
  10675. PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  10676. DRM_MODE_FLAG_NVSYNC);
  10677. }
  10678. PIPE_CONF_CHECK_X(gmch_pfit.control);
  10679. /* pfit ratios are autocomputed by the hw on gen4+ */
  10680. if (INTEL_INFO(dev)->gen < 4)
  10681. PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
  10682. PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
  10683. if (!adjust) {
  10684. PIPE_CONF_CHECK_I(pipe_src_w);
  10685. PIPE_CONF_CHECK_I(pipe_src_h);
  10686. PIPE_CONF_CHECK_I(pch_pfit.enabled);
  10687. if (current_config->pch_pfit.enabled) {
  10688. PIPE_CONF_CHECK_X(pch_pfit.pos);
  10689. PIPE_CONF_CHECK_X(pch_pfit.size);
  10690. }
  10691. PIPE_CONF_CHECK_I(scaler_state.scaler_id);
  10692. }
  10693. /* BDW+ don't expose a synchronous way to read the state */
  10694. if (IS_HASWELL(dev))
  10695. PIPE_CONF_CHECK_I(ips_enabled);
  10696. PIPE_CONF_CHECK_I(double_wide);
  10697. PIPE_CONF_CHECK_X(ddi_pll_sel);
  10698. PIPE_CONF_CHECK_P(shared_dpll);
  10699. PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  10700. PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  10701. PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  10702. PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  10703. PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
  10704. PIPE_CONF_CHECK_X(dpll_hw_state.spll);
  10705. PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
  10706. PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
  10707. PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
  10708. PIPE_CONF_CHECK_X(dsi_pll.ctrl);
  10709. PIPE_CONF_CHECK_X(dsi_pll.div);
  10710. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  10711. PIPE_CONF_CHECK_I(pipe_bpp);
  10712. PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
  10713. PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
  10714. #undef PIPE_CONF_CHECK_X
  10715. #undef PIPE_CONF_CHECK_I
  10716. #undef PIPE_CONF_CHECK_P
  10717. #undef PIPE_CONF_CHECK_FLAGS
  10718. #undef PIPE_CONF_CHECK_CLOCK_FUZZY
  10719. #undef PIPE_CONF_QUIRK
  10720. #undef INTEL_ERR_OR_DBG_KMS
  10721. return ret;
  10722. }
  10723. static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
  10724. const struct intel_crtc_state *pipe_config)
  10725. {
  10726. if (pipe_config->has_pch_encoder) {
  10727. int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
  10728. &pipe_config->fdi_m_n);
  10729. int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
  10730. /*
  10731. * FDI already provided one idea for the dotclock.
  10732. * Yell if the encoder disagrees.
  10733. */
  10734. WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
  10735. "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
  10736. fdi_dotclock, dotclock);
  10737. }
  10738. }
  10739. static void verify_wm_state(struct drm_crtc *crtc,
  10740. struct drm_crtc_state *new_state)
  10741. {
  10742. struct drm_device *dev = crtc->dev;
  10743. struct drm_i915_private *dev_priv = dev->dev_private;
  10744. struct skl_ddb_allocation hw_ddb, *sw_ddb;
  10745. struct skl_ddb_entry *hw_entry, *sw_entry;
  10746. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10747. const enum pipe pipe = intel_crtc->pipe;
  10748. int plane;
  10749. if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
  10750. return;
  10751. skl_ddb_get_hw_state(dev_priv, &hw_ddb);
  10752. sw_ddb = &dev_priv->wm.skl_hw.ddb;
  10753. /* planes */
  10754. for_each_plane(dev_priv, pipe, plane) {
  10755. hw_entry = &hw_ddb.plane[pipe][plane];
  10756. sw_entry = &sw_ddb->plane[pipe][plane];
  10757. if (skl_ddb_entry_equal(hw_entry, sw_entry))
  10758. continue;
  10759. DRM_ERROR("mismatch in DDB state pipe %c plane %d "
  10760. "(expected (%u,%u), found (%u,%u))\n",
  10761. pipe_name(pipe), plane + 1,
  10762. sw_entry->start, sw_entry->end,
  10763. hw_entry->start, hw_entry->end);
  10764. }
  10765. /* cursor */
  10766. hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
  10767. sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
  10768. if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
  10769. DRM_ERROR("mismatch in DDB state pipe %c cursor "
  10770. "(expected (%u,%u), found (%u,%u))\n",
  10771. pipe_name(pipe),
  10772. sw_entry->start, sw_entry->end,
  10773. hw_entry->start, hw_entry->end);
  10774. }
  10775. }
  10776. static void
  10777. verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
  10778. {
  10779. struct drm_connector *connector;
  10780. drm_for_each_connector(connector, dev) {
  10781. struct drm_encoder *encoder = connector->encoder;
  10782. struct drm_connector_state *state = connector->state;
  10783. if (state->crtc != crtc)
  10784. continue;
  10785. intel_connector_verify_state(to_intel_connector(connector));
  10786. I915_STATE_WARN(state->best_encoder != encoder,
  10787. "connector's atomic encoder doesn't match legacy encoder\n");
  10788. }
  10789. }
  10790. static void
  10791. verify_encoder_state(struct drm_device *dev)
  10792. {
  10793. struct intel_encoder *encoder;
  10794. struct intel_connector *connector;
  10795. for_each_intel_encoder(dev, encoder) {
  10796. bool enabled = false;
  10797. enum pipe pipe;
  10798. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  10799. encoder->base.base.id,
  10800. encoder->base.name);
  10801. for_each_intel_connector(dev, connector) {
  10802. if (connector->base.state->best_encoder != &encoder->base)
  10803. continue;
  10804. enabled = true;
  10805. I915_STATE_WARN(connector->base.state->crtc !=
  10806. encoder->base.crtc,
  10807. "connector's crtc doesn't match encoder crtc\n");
  10808. }
  10809. I915_STATE_WARN(!!encoder->base.crtc != enabled,
  10810. "encoder's enabled state mismatch "
  10811. "(expected %i, found %i)\n",
  10812. !!encoder->base.crtc, enabled);
  10813. if (!encoder->base.crtc) {
  10814. bool active;
  10815. active = encoder->get_hw_state(encoder, &pipe);
  10816. I915_STATE_WARN(active,
  10817. "encoder detached but still enabled on pipe %c.\n",
  10818. pipe_name(pipe));
  10819. }
  10820. }
  10821. }
  10822. static void
  10823. verify_crtc_state(struct drm_crtc *crtc,
  10824. struct drm_crtc_state *old_crtc_state,
  10825. struct drm_crtc_state *new_crtc_state)
  10826. {
  10827. struct drm_device *dev = crtc->dev;
  10828. struct drm_i915_private *dev_priv = dev->dev_private;
  10829. struct intel_encoder *encoder;
  10830. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10831. struct intel_crtc_state *pipe_config, *sw_config;
  10832. struct drm_atomic_state *old_state;
  10833. bool active;
  10834. old_state = old_crtc_state->state;
  10835. __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
  10836. pipe_config = to_intel_crtc_state(old_crtc_state);
  10837. memset(pipe_config, 0, sizeof(*pipe_config));
  10838. pipe_config->base.crtc = crtc;
  10839. pipe_config->base.state = old_state;
  10840. DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
  10841. active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
  10842. /* hw state is inconsistent with the pipe quirk */
  10843. if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  10844. (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  10845. active = new_crtc_state->active;
  10846. I915_STATE_WARN(new_crtc_state->active != active,
  10847. "crtc active state doesn't match with hw state "
  10848. "(expected %i, found %i)\n", new_crtc_state->active, active);
  10849. I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
  10850. "transitional active state does not match atomic hw state "
  10851. "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
  10852. for_each_encoder_on_crtc(dev, crtc, encoder) {
  10853. enum pipe pipe;
  10854. active = encoder->get_hw_state(encoder, &pipe);
  10855. I915_STATE_WARN(active != new_crtc_state->active,
  10856. "[ENCODER:%i] active %i with crtc active %i\n",
  10857. encoder->base.base.id, active, new_crtc_state->active);
  10858. I915_STATE_WARN(active && intel_crtc->pipe != pipe,
  10859. "Encoder connected to wrong pipe %c\n",
  10860. pipe_name(pipe));
  10861. if (active)
  10862. encoder->get_config(encoder, pipe_config);
  10863. }
  10864. if (!new_crtc_state->active)
  10865. return;
  10866. intel_pipe_config_sanity_check(dev_priv, pipe_config);
  10867. sw_config = to_intel_crtc_state(crtc->state);
  10868. if (!intel_pipe_config_compare(dev, sw_config,
  10869. pipe_config, false)) {
  10870. I915_STATE_WARN(1, "pipe state doesn't match!\n");
  10871. intel_dump_pipe_config(intel_crtc, pipe_config,
  10872. "[hw state]");
  10873. intel_dump_pipe_config(intel_crtc, sw_config,
  10874. "[sw state]");
  10875. }
  10876. }
  10877. static void
  10878. verify_single_dpll_state(struct drm_i915_private *dev_priv,
  10879. struct intel_shared_dpll *pll,
  10880. struct drm_crtc *crtc,
  10881. struct drm_crtc_state *new_state)
  10882. {
  10883. struct intel_dpll_hw_state dpll_hw_state;
  10884. unsigned crtc_mask;
  10885. bool active;
  10886. memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  10887. DRM_DEBUG_KMS("%s\n", pll->name);
  10888. active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
  10889. if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
  10890. I915_STATE_WARN(!pll->on && pll->active_mask,
  10891. "pll in active use but not on in sw tracking\n");
  10892. I915_STATE_WARN(pll->on && !pll->active_mask,
  10893. "pll is on but not used by any active crtc\n");
  10894. I915_STATE_WARN(pll->on != active,
  10895. "pll on state mismatch (expected %i, found %i)\n",
  10896. pll->on, active);
  10897. }
  10898. if (!crtc) {
  10899. I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
  10900. "more active pll users than references: %x vs %x\n",
  10901. pll->active_mask, pll->config.crtc_mask);
  10902. return;
  10903. }
  10904. crtc_mask = 1 << drm_crtc_index(crtc);
  10905. if (new_state->active)
  10906. I915_STATE_WARN(!(pll->active_mask & crtc_mask),
  10907. "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
  10908. pipe_name(drm_crtc_index(crtc)), pll->active_mask);
  10909. else
  10910. I915_STATE_WARN(pll->active_mask & crtc_mask,
  10911. "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
  10912. pipe_name(drm_crtc_index(crtc)), pll->active_mask);
  10913. I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
  10914. "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
  10915. crtc_mask, pll->config.crtc_mask);
  10916. I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
  10917. &dpll_hw_state,
  10918. sizeof(dpll_hw_state)),
  10919. "pll hw state mismatch\n");
  10920. }
  10921. static void
  10922. verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
  10923. struct drm_crtc_state *old_crtc_state,
  10924. struct drm_crtc_state *new_crtc_state)
  10925. {
  10926. struct drm_i915_private *dev_priv = dev->dev_private;
  10927. struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
  10928. struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
  10929. if (new_state->shared_dpll)
  10930. verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
  10931. if (old_state->shared_dpll &&
  10932. old_state->shared_dpll != new_state->shared_dpll) {
  10933. unsigned crtc_mask = 1 << drm_crtc_index(crtc);
  10934. struct intel_shared_dpll *pll = old_state->shared_dpll;
  10935. I915_STATE_WARN(pll->active_mask & crtc_mask,
  10936. "pll active mismatch (didn't expect pipe %c in active mask)\n",
  10937. pipe_name(drm_crtc_index(crtc)));
  10938. I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
  10939. "pll enabled crtcs mismatch (found %x in enabled mask)\n",
  10940. pipe_name(drm_crtc_index(crtc)));
  10941. }
  10942. }
  10943. static void
  10944. intel_modeset_verify_crtc(struct drm_crtc *crtc,
  10945. struct drm_crtc_state *old_state,
  10946. struct drm_crtc_state *new_state)
  10947. {
  10948. if (!needs_modeset(new_state) &&
  10949. !to_intel_crtc_state(new_state)->update_pipe)
  10950. return;
  10951. verify_wm_state(crtc, new_state);
  10952. verify_connector_state(crtc->dev, crtc);
  10953. verify_crtc_state(crtc, old_state, new_state);
  10954. verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
  10955. }
  10956. static void
  10957. verify_disabled_dpll_state(struct drm_device *dev)
  10958. {
  10959. struct drm_i915_private *dev_priv = dev->dev_private;
  10960. int i;
  10961. for (i = 0; i < dev_priv->num_shared_dpll; i++)
  10962. verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
  10963. }
  10964. static void
  10965. intel_modeset_verify_disabled(struct drm_device *dev)
  10966. {
  10967. verify_encoder_state(dev);
  10968. verify_connector_state(dev, NULL);
  10969. verify_disabled_dpll_state(dev);
  10970. }
  10971. static void update_scanline_offset(struct intel_crtc *crtc)
  10972. {
  10973. struct drm_device *dev = crtc->base.dev;
  10974. /*
  10975. * The scanline counter increments at the leading edge of hsync.
  10976. *
  10977. * On most platforms it starts counting from vtotal-1 on the
  10978. * first active line. That means the scanline counter value is
  10979. * always one less than what we would expect. Ie. just after
  10980. * start of vblank, which also occurs at start of hsync (on the
  10981. * last active line), the scanline counter will read vblank_start-1.
  10982. *
  10983. * On gen2 the scanline counter starts counting from 1 instead
  10984. * of vtotal-1, so we have to subtract one (or rather add vtotal-1
  10985. * to keep the value positive), instead of adding one.
  10986. *
  10987. * On HSW+ the behaviour of the scanline counter depends on the output
  10988. * type. For DP ports it behaves like most other platforms, but on HDMI
  10989. * there's an extra 1 line difference. So we need to add two instead of
  10990. * one to the value.
  10991. */
  10992. if (IS_GEN2(dev)) {
  10993. const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  10994. int vtotal;
  10995. vtotal = adjusted_mode->crtc_vtotal;
  10996. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  10997. vtotal /= 2;
  10998. crtc->scanline_offset = vtotal - 1;
  10999. } else if (HAS_DDI(dev) &&
  11000. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
  11001. crtc->scanline_offset = 2;
  11002. } else
  11003. crtc->scanline_offset = 1;
  11004. }
  11005. static void intel_modeset_clear_plls(struct drm_atomic_state *state)
  11006. {
  11007. struct drm_device *dev = state->dev;
  11008. struct drm_i915_private *dev_priv = to_i915(dev);
  11009. struct intel_shared_dpll_config *shared_dpll = NULL;
  11010. struct drm_crtc *crtc;
  11011. struct drm_crtc_state *crtc_state;
  11012. int i;
  11013. if (!dev_priv->display.crtc_compute_clock)
  11014. return;
  11015. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  11016. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11017. struct intel_shared_dpll *old_dpll =
  11018. to_intel_crtc_state(crtc->state)->shared_dpll;
  11019. if (!needs_modeset(crtc_state))
  11020. continue;
  11021. to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
  11022. if (!old_dpll)
  11023. continue;
  11024. if (!shared_dpll)
  11025. shared_dpll = intel_atomic_get_shared_dpll_state(state);
  11026. intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
  11027. }
  11028. }
  11029. /*
  11030. * This implements the workaround described in the "notes" section of the mode
  11031. * set sequence documentation. When going from no pipes or single pipe to
  11032. * multiple pipes, and planes are enabled after the pipe, we need to wait at
  11033. * least 2 vblanks on the first pipe before enabling planes on the second pipe.
  11034. */
  11035. static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
  11036. {
  11037. struct drm_crtc_state *crtc_state;
  11038. struct intel_crtc *intel_crtc;
  11039. struct drm_crtc *crtc;
  11040. struct intel_crtc_state *first_crtc_state = NULL;
  11041. struct intel_crtc_state *other_crtc_state = NULL;
  11042. enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
  11043. int i;
  11044. /* look at all crtc's that are going to be enabled in during modeset */
  11045. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  11046. intel_crtc = to_intel_crtc(crtc);
  11047. if (!crtc_state->active || !needs_modeset(crtc_state))
  11048. continue;
  11049. if (first_crtc_state) {
  11050. other_crtc_state = to_intel_crtc_state(crtc_state);
  11051. break;
  11052. } else {
  11053. first_crtc_state = to_intel_crtc_state(crtc_state);
  11054. first_pipe = intel_crtc->pipe;
  11055. }
  11056. }
  11057. /* No workaround needed? */
  11058. if (!first_crtc_state)
  11059. return 0;
  11060. /* w/a possibly needed, check how many crtc's are already enabled. */
  11061. for_each_intel_crtc(state->dev, intel_crtc) {
  11062. struct intel_crtc_state *pipe_config;
  11063. pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
  11064. if (IS_ERR(pipe_config))
  11065. return PTR_ERR(pipe_config);
  11066. pipe_config->hsw_workaround_pipe = INVALID_PIPE;
  11067. if (!pipe_config->base.active ||
  11068. needs_modeset(&pipe_config->base))
  11069. continue;
  11070. /* 2 or more enabled crtcs means no need for w/a */
  11071. if (enabled_pipe != INVALID_PIPE)
  11072. return 0;
  11073. enabled_pipe = intel_crtc->pipe;
  11074. }
  11075. if (enabled_pipe != INVALID_PIPE)
  11076. first_crtc_state->hsw_workaround_pipe = enabled_pipe;
  11077. else if (other_crtc_state)
  11078. other_crtc_state->hsw_workaround_pipe = first_pipe;
  11079. return 0;
  11080. }
  11081. static int intel_modeset_all_pipes(struct drm_atomic_state *state)
  11082. {
  11083. struct drm_crtc *crtc;
  11084. struct drm_crtc_state *crtc_state;
  11085. int ret = 0;
  11086. /* add all active pipes to the state */
  11087. for_each_crtc(state->dev, crtc) {
  11088. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  11089. if (IS_ERR(crtc_state))
  11090. return PTR_ERR(crtc_state);
  11091. if (!crtc_state->active || needs_modeset(crtc_state))
  11092. continue;
  11093. crtc_state->mode_changed = true;
  11094. ret = drm_atomic_add_affected_connectors(state, crtc);
  11095. if (ret)
  11096. break;
  11097. ret = drm_atomic_add_affected_planes(state, crtc);
  11098. if (ret)
  11099. break;
  11100. }
  11101. return ret;
  11102. }
  11103. static int intel_modeset_checks(struct drm_atomic_state *state)
  11104. {
  11105. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  11106. struct drm_i915_private *dev_priv = state->dev->dev_private;
  11107. struct drm_crtc *crtc;
  11108. struct drm_crtc_state *crtc_state;
  11109. int ret = 0, i;
  11110. if (!check_digital_port_conflicts(state)) {
  11111. DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
  11112. return -EINVAL;
  11113. }
  11114. intel_state->modeset = true;
  11115. intel_state->active_crtcs = dev_priv->active_crtcs;
  11116. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  11117. if (crtc_state->active)
  11118. intel_state->active_crtcs |= 1 << i;
  11119. else
  11120. intel_state->active_crtcs &= ~(1 << i);
  11121. if (crtc_state->active != crtc->state->active)
  11122. intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
  11123. }
  11124. /*
  11125. * See if the config requires any additional preparation, e.g.
  11126. * to adjust global state with pipes off. We need to do this
  11127. * here so we can get the modeset_pipe updated config for the new
  11128. * mode set on this crtc. For other crtcs we need to use the
  11129. * adjusted_mode bits in the crtc directly.
  11130. */
  11131. if (dev_priv->display.modeset_calc_cdclk) {
  11132. ret = dev_priv->display.modeset_calc_cdclk(state);
  11133. if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
  11134. ret = intel_modeset_all_pipes(state);
  11135. if (ret < 0)
  11136. return ret;
  11137. DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
  11138. intel_state->cdclk, intel_state->dev_cdclk);
  11139. } else
  11140. to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
  11141. intel_modeset_clear_plls(state);
  11142. if (IS_HASWELL(dev_priv))
  11143. return haswell_mode_set_planes_workaround(state);
  11144. return 0;
  11145. }
  11146. /*
  11147. * Handle calculation of various watermark data at the end of the atomic check
  11148. * phase. The code here should be run after the per-crtc and per-plane 'check'
  11149. * handlers to ensure that all derived state has been updated.
  11150. */
  11151. static void calc_watermark_data(struct drm_atomic_state *state)
  11152. {
  11153. struct drm_device *dev = state->dev;
  11154. struct drm_i915_private *dev_priv = to_i915(dev);
  11155. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  11156. struct drm_crtc *crtc;
  11157. struct drm_crtc_state *cstate;
  11158. struct drm_plane *plane;
  11159. struct drm_plane_state *pstate;
  11160. /*
  11161. * Calculate watermark configuration details now that derived
  11162. * plane/crtc state is all properly updated.
  11163. */
  11164. drm_for_each_crtc(crtc, dev) {
  11165. cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
  11166. crtc->state;
  11167. if (cstate->active)
  11168. intel_state->wm_config.num_pipes_active++;
  11169. }
  11170. drm_for_each_legacy_plane(plane, dev) {
  11171. pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
  11172. plane->state;
  11173. if (!to_intel_plane_state(pstate)->visible)
  11174. continue;
  11175. intel_state->wm_config.sprites_enabled = true;
  11176. if (pstate->crtc_w != pstate->src_w >> 16 ||
  11177. pstate->crtc_h != pstate->src_h >> 16)
  11178. intel_state->wm_config.sprites_scaled = true;
  11179. }
  11180. /* Is there platform-specific watermark information to calculate? */
  11181. if (dev_priv->display.compute_global_watermarks)
  11182. dev_priv->display.compute_global_watermarks(state);
  11183. }
  11184. /**
  11185. * intel_atomic_check - validate state object
  11186. * @dev: drm device
  11187. * @state: state to validate
  11188. */
  11189. static int intel_atomic_check(struct drm_device *dev,
  11190. struct drm_atomic_state *state)
  11191. {
  11192. struct drm_i915_private *dev_priv = to_i915(dev);
  11193. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  11194. struct drm_crtc *crtc;
  11195. struct drm_crtc_state *crtc_state;
  11196. int ret, i;
  11197. bool any_ms = false;
  11198. ret = drm_atomic_helper_check_modeset(dev, state);
  11199. if (ret)
  11200. return ret;
  11201. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  11202. struct intel_crtc_state *pipe_config =
  11203. to_intel_crtc_state(crtc_state);
  11204. /* Catch I915_MODE_FLAG_INHERITED */
  11205. if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
  11206. crtc_state->mode_changed = true;
  11207. if (!crtc_state->enable) {
  11208. if (needs_modeset(crtc_state))
  11209. any_ms = true;
  11210. continue;
  11211. }
  11212. if (!needs_modeset(crtc_state))
  11213. continue;
  11214. /* FIXME: For only active_changed we shouldn't need to do any
  11215. * state recomputation at all. */
  11216. ret = drm_atomic_add_affected_connectors(state, crtc);
  11217. if (ret)
  11218. return ret;
  11219. ret = intel_modeset_pipe_config(crtc, pipe_config);
  11220. if (ret) {
  11221. intel_dump_pipe_config(to_intel_crtc(crtc),
  11222. pipe_config, "[failed]");
  11223. return ret;
  11224. }
  11225. if (i915.fastboot &&
  11226. intel_pipe_config_compare(dev,
  11227. to_intel_crtc_state(crtc->state),
  11228. pipe_config, true)) {
  11229. crtc_state->mode_changed = false;
  11230. to_intel_crtc_state(crtc_state)->update_pipe = true;
  11231. }
  11232. if (needs_modeset(crtc_state)) {
  11233. any_ms = true;
  11234. ret = drm_atomic_add_affected_planes(state, crtc);
  11235. if (ret)
  11236. return ret;
  11237. }
  11238. intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  11239. needs_modeset(crtc_state) ?
  11240. "[modeset]" : "[fastset]");
  11241. }
  11242. if (any_ms) {
  11243. ret = intel_modeset_checks(state);
  11244. if (ret)
  11245. return ret;
  11246. } else
  11247. intel_state->cdclk = dev_priv->cdclk_freq;
  11248. ret = drm_atomic_helper_check_planes(dev, state);
  11249. if (ret)
  11250. return ret;
  11251. intel_fbc_choose_crtc(dev_priv, state);
  11252. calc_watermark_data(state);
  11253. return 0;
  11254. }
  11255. static int intel_atomic_prepare_commit(struct drm_device *dev,
  11256. struct drm_atomic_state *state,
  11257. bool async)
  11258. {
  11259. struct drm_i915_private *dev_priv = dev->dev_private;
  11260. struct drm_plane_state *plane_state;
  11261. struct drm_crtc_state *crtc_state;
  11262. struct drm_plane *plane;
  11263. struct drm_crtc *crtc;
  11264. int i, ret;
  11265. if (async) {
  11266. DRM_DEBUG_KMS("i915 does not yet support async commit\n");
  11267. return -EINVAL;
  11268. }
  11269. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  11270. if (state->legacy_cursor_update)
  11271. continue;
  11272. ret = intel_crtc_wait_for_pending_flips(crtc);
  11273. if (ret)
  11274. return ret;
  11275. if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
  11276. flush_workqueue(dev_priv->wq);
  11277. }
  11278. ret = mutex_lock_interruptible(&dev->struct_mutex);
  11279. if (ret)
  11280. return ret;
  11281. ret = drm_atomic_helper_prepare_planes(dev, state);
  11282. mutex_unlock(&dev->struct_mutex);
  11283. if (!ret && !async) {
  11284. for_each_plane_in_state(state, plane, plane_state, i) {
  11285. struct intel_plane_state *intel_plane_state =
  11286. to_intel_plane_state(plane_state);
  11287. if (!intel_plane_state->wait_req)
  11288. continue;
  11289. ret = __i915_wait_request(intel_plane_state->wait_req,
  11290. true, NULL, NULL);
  11291. if (ret) {
  11292. /* Any hang should be swallowed by the wait */
  11293. WARN_ON(ret == -EIO);
  11294. mutex_lock(&dev->struct_mutex);
  11295. drm_atomic_helper_cleanup_planes(dev, state);
  11296. mutex_unlock(&dev->struct_mutex);
  11297. break;
  11298. }
  11299. }
  11300. }
  11301. return ret;
  11302. }
  11303. static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
  11304. struct drm_i915_private *dev_priv,
  11305. unsigned crtc_mask)
  11306. {
  11307. unsigned last_vblank_count[I915_MAX_PIPES];
  11308. enum pipe pipe;
  11309. int ret;
  11310. if (!crtc_mask)
  11311. return;
  11312. for_each_pipe(dev_priv, pipe) {
  11313. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  11314. if (!((1 << pipe) & crtc_mask))
  11315. continue;
  11316. ret = drm_crtc_vblank_get(crtc);
  11317. if (WARN_ON(ret != 0)) {
  11318. crtc_mask &= ~(1 << pipe);
  11319. continue;
  11320. }
  11321. last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
  11322. }
  11323. for_each_pipe(dev_priv, pipe) {
  11324. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  11325. long lret;
  11326. if (!((1 << pipe) & crtc_mask))
  11327. continue;
  11328. lret = wait_event_timeout(dev->vblank[pipe].queue,
  11329. last_vblank_count[pipe] !=
  11330. drm_crtc_vblank_count(crtc),
  11331. msecs_to_jiffies(50));
  11332. WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
  11333. drm_crtc_vblank_put(crtc);
  11334. }
  11335. }
  11336. static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
  11337. {
  11338. /* fb updated, need to unpin old fb */
  11339. if (crtc_state->fb_changed)
  11340. return true;
  11341. /* wm changes, need vblank before final wm's */
  11342. if (crtc_state->update_wm_post)
  11343. return true;
  11344. /*
  11345. * cxsr is re-enabled after vblank.
  11346. * This is already handled by crtc_state->update_wm_post,
  11347. * but added for clarity.
  11348. */
  11349. if (crtc_state->disable_cxsr)
  11350. return true;
  11351. return false;
  11352. }
  11353. /**
  11354. * intel_atomic_commit - commit validated state object
  11355. * @dev: DRM device
  11356. * @state: the top-level driver state object
  11357. * @async: asynchronous commit
  11358. *
  11359. * This function commits a top-level state object that has been validated
  11360. * with drm_atomic_helper_check().
  11361. *
  11362. * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
  11363. * we can only handle plane-related operations and do not yet support
  11364. * asynchronous commit.
  11365. *
  11366. * RETURNS
  11367. * Zero for success or -errno.
  11368. */
  11369. static int intel_atomic_commit(struct drm_device *dev,
  11370. struct drm_atomic_state *state,
  11371. bool async)
  11372. {
  11373. struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
  11374. struct drm_i915_private *dev_priv = dev->dev_private;
  11375. struct drm_crtc_state *old_crtc_state;
  11376. struct drm_crtc *crtc;
  11377. struct intel_crtc_state *intel_cstate;
  11378. int ret = 0, i;
  11379. bool hw_check = intel_state->modeset;
  11380. unsigned long put_domains[I915_MAX_PIPES] = {};
  11381. unsigned crtc_vblank_mask = 0;
  11382. ret = intel_atomic_prepare_commit(dev, state, async);
  11383. if (ret) {
  11384. DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
  11385. return ret;
  11386. }
  11387. drm_atomic_helper_swap_state(dev, state);
  11388. dev_priv->wm.config = intel_state->wm_config;
  11389. dev_priv->wm.distrust_bios_wm = false;
  11390. dev_priv->wm.skl_results.ddb = intel_state->ddb;
  11391. intel_shared_dpll_commit(state);
  11392. if (intel_state->modeset) {
  11393. memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
  11394. sizeof(intel_state->min_pixclk));
  11395. dev_priv->active_crtcs = intel_state->active_crtcs;
  11396. dev_priv->atomic_cdclk_freq = intel_state->cdclk;
  11397. intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
  11398. }
  11399. for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
  11400. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11401. if (needs_modeset(crtc->state) ||
  11402. to_intel_crtc_state(crtc->state)->update_pipe) {
  11403. hw_check = true;
  11404. put_domains[to_intel_crtc(crtc)->pipe] =
  11405. modeset_get_crtc_power_domains(crtc,
  11406. to_intel_crtc_state(crtc->state));
  11407. }
  11408. if (!needs_modeset(crtc->state))
  11409. continue;
  11410. intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
  11411. if (old_crtc_state->active) {
  11412. intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
  11413. dev_priv->display.crtc_disable(crtc);
  11414. intel_crtc->active = false;
  11415. intel_fbc_disable(intel_crtc);
  11416. intel_disable_shared_dpll(intel_crtc);
  11417. /*
  11418. * Underruns don't always raise
  11419. * interrupts, so check manually.
  11420. */
  11421. intel_check_cpu_fifo_underruns(dev_priv);
  11422. intel_check_pch_fifo_underruns(dev_priv);
  11423. if (!crtc->state->active)
  11424. intel_update_watermarks(crtc);
  11425. }
  11426. }
  11427. /* Only after disabling all output pipelines that will be changed can we
  11428. * update the the output configuration. */
  11429. intel_modeset_update_crtc_state(state);
  11430. if (intel_state->modeset) {
  11431. drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
  11432. if (dev_priv->display.modeset_commit_cdclk &&
  11433. intel_state->dev_cdclk != dev_priv->cdclk_freq)
  11434. dev_priv->display.modeset_commit_cdclk(state);
  11435. intel_modeset_verify_disabled(dev);
  11436. }
  11437. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  11438. for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
  11439. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11440. bool modeset = needs_modeset(crtc->state);
  11441. struct intel_crtc_state *pipe_config =
  11442. to_intel_crtc_state(crtc->state);
  11443. bool update_pipe = !modeset && pipe_config->update_pipe;
  11444. if (modeset && crtc->state->active) {
  11445. update_scanline_offset(to_intel_crtc(crtc));
  11446. dev_priv->display.crtc_enable(crtc);
  11447. }
  11448. if (!modeset)
  11449. intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
  11450. if (crtc->state->active &&
  11451. drm_atomic_get_existing_plane_state(state, crtc->primary))
  11452. intel_fbc_enable(intel_crtc);
  11453. if (crtc->state->active &&
  11454. (crtc->state->planes_changed || update_pipe))
  11455. drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
  11456. if (pipe_config->base.active && needs_vblank_wait(pipe_config))
  11457. crtc_vblank_mask |= 1 << i;
  11458. }
  11459. /* FIXME: add subpixel order */
  11460. if (!state->legacy_cursor_update)
  11461. intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
  11462. /*
  11463. * Now that the vblank has passed, we can go ahead and program the
  11464. * optimal watermarks on platforms that need two-step watermark
  11465. * programming.
  11466. *
  11467. * TODO: Move this (and other cleanup) to an async worker eventually.
  11468. */
  11469. for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
  11470. intel_cstate = to_intel_crtc_state(crtc->state);
  11471. if (dev_priv->display.optimize_watermarks)
  11472. dev_priv->display.optimize_watermarks(intel_cstate);
  11473. }
  11474. for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
  11475. intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
  11476. if (put_domains[i])
  11477. modeset_put_power_domains(dev_priv, put_domains[i]);
  11478. intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
  11479. }
  11480. if (intel_state->modeset)
  11481. intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
  11482. mutex_lock(&dev->struct_mutex);
  11483. drm_atomic_helper_cleanup_planes(dev, state);
  11484. mutex_unlock(&dev->struct_mutex);
  11485. drm_atomic_state_free(state);
  11486. /* As one of the primary mmio accessors, KMS has a high likelihood
  11487. * of triggering bugs in unclaimed access. After we finish
  11488. * modesetting, see if an error has been flagged, and if so
  11489. * enable debugging for the next modeset - and hope we catch
  11490. * the culprit.
  11491. *
  11492. * XXX note that we assume display power is on at this point.
  11493. * This might hold true now but we need to add pm helper to check
  11494. * unclaimed only when the hardware is on, as atomic commits
  11495. * can happen also when the device is completely off.
  11496. */
  11497. intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
  11498. return 0;
  11499. }
  11500. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  11501. {
  11502. struct drm_device *dev = crtc->dev;
  11503. struct drm_atomic_state *state;
  11504. struct drm_crtc_state *crtc_state;
  11505. int ret;
  11506. state = drm_atomic_state_alloc(dev);
  11507. if (!state) {
  11508. DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
  11509. crtc->base.id);
  11510. return;
  11511. }
  11512. state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
  11513. retry:
  11514. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  11515. ret = PTR_ERR_OR_ZERO(crtc_state);
  11516. if (!ret) {
  11517. if (!crtc_state->active)
  11518. goto out;
  11519. crtc_state->mode_changed = true;
  11520. ret = drm_atomic_commit(state);
  11521. }
  11522. if (ret == -EDEADLK) {
  11523. drm_atomic_state_clear(state);
  11524. drm_modeset_backoff(state->acquire_ctx);
  11525. goto retry;
  11526. }
  11527. if (ret)
  11528. out:
  11529. drm_atomic_state_free(state);
  11530. }
  11531. #undef for_each_intel_crtc_masked
  11532. static const struct drm_crtc_funcs intel_crtc_funcs = {
  11533. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  11534. .set_config = drm_atomic_helper_set_config,
  11535. .set_property = drm_atomic_helper_crtc_set_property,
  11536. .destroy = intel_crtc_destroy,
  11537. .page_flip = intel_crtc_page_flip,
  11538. .atomic_duplicate_state = intel_crtc_duplicate_state,
  11539. .atomic_destroy_state = intel_crtc_destroy_state,
  11540. };
  11541. /**
  11542. * intel_prepare_plane_fb - Prepare fb for usage on plane
  11543. * @plane: drm plane to prepare for
  11544. * @fb: framebuffer to prepare for presentation
  11545. *
  11546. * Prepares a framebuffer for usage on a display plane. Generally this
  11547. * involves pinning the underlying object and updating the frontbuffer tracking
  11548. * bits. Some older platforms need special physical address handling for
  11549. * cursor planes.
  11550. *
  11551. * Must be called with struct_mutex held.
  11552. *
  11553. * Returns 0 on success, negative error code on failure.
  11554. */
  11555. int
  11556. intel_prepare_plane_fb(struct drm_plane *plane,
  11557. const struct drm_plane_state *new_state)
  11558. {
  11559. struct drm_device *dev = plane->dev;
  11560. struct drm_framebuffer *fb = new_state->fb;
  11561. struct intel_plane *intel_plane = to_intel_plane(plane);
  11562. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  11563. struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
  11564. int ret = 0;
  11565. if (!obj && !old_obj)
  11566. return 0;
  11567. if (old_obj) {
  11568. struct drm_crtc_state *crtc_state =
  11569. drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
  11570. /* Big Hammer, we also need to ensure that any pending
  11571. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  11572. * current scanout is retired before unpinning the old
  11573. * framebuffer. Note that we rely on userspace rendering
  11574. * into the buffer attached to the pipe they are waiting
  11575. * on. If not, userspace generates a GPU hang with IPEHR
  11576. * point to the MI_WAIT_FOR_EVENT.
  11577. *
  11578. * This should only fail upon a hung GPU, in which case we
  11579. * can safely continue.
  11580. */
  11581. if (needs_modeset(crtc_state))
  11582. ret = i915_gem_object_wait_rendering(old_obj, true);
  11583. if (ret) {
  11584. /* GPU hangs should have been swallowed by the wait */
  11585. WARN_ON(ret == -EIO);
  11586. return ret;
  11587. }
  11588. }
  11589. /* For framebuffer backed by dmabuf, wait for fence */
  11590. if (obj && obj->base.dma_buf) {
  11591. long lret;
  11592. lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
  11593. false, true,
  11594. MAX_SCHEDULE_TIMEOUT);
  11595. if (lret == -ERESTARTSYS)
  11596. return lret;
  11597. WARN(lret < 0, "waiting returns %li\n", lret);
  11598. }
  11599. if (!obj) {
  11600. ret = 0;
  11601. } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
  11602. INTEL_INFO(dev)->cursor_needs_physical) {
  11603. int align = IS_I830(dev) ? 16 * 1024 : 256;
  11604. ret = i915_gem_object_attach_phys(obj, align);
  11605. if (ret)
  11606. DRM_DEBUG_KMS("failed to attach phys object\n");
  11607. } else {
  11608. ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
  11609. }
  11610. if (ret == 0) {
  11611. if (obj) {
  11612. struct intel_plane_state *plane_state =
  11613. to_intel_plane_state(new_state);
  11614. i915_gem_request_assign(&plane_state->wait_req,
  11615. obj->last_write_req);
  11616. }
  11617. i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
  11618. }
  11619. return ret;
  11620. }
  11621. /**
  11622. * intel_cleanup_plane_fb - Cleans up an fb after plane use
  11623. * @plane: drm plane to clean up for
  11624. * @fb: old framebuffer that was on plane
  11625. *
  11626. * Cleans up a framebuffer that has just been removed from a plane.
  11627. *
  11628. * Must be called with struct_mutex held.
  11629. */
  11630. void
  11631. intel_cleanup_plane_fb(struct drm_plane *plane,
  11632. const struct drm_plane_state *old_state)
  11633. {
  11634. struct drm_device *dev = plane->dev;
  11635. struct intel_plane *intel_plane = to_intel_plane(plane);
  11636. struct intel_plane_state *old_intel_state;
  11637. struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
  11638. struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
  11639. old_intel_state = to_intel_plane_state(old_state);
  11640. if (!obj && !old_obj)
  11641. return;
  11642. if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
  11643. !INTEL_INFO(dev)->cursor_needs_physical))
  11644. intel_unpin_fb_obj(old_state->fb, old_state->rotation);
  11645. /* prepare_fb aborted? */
  11646. if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
  11647. (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
  11648. i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
  11649. i915_gem_request_assign(&old_intel_state->wait_req, NULL);
  11650. }
  11651. int
  11652. skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
  11653. {
  11654. int max_scale;
  11655. struct drm_device *dev;
  11656. struct drm_i915_private *dev_priv;
  11657. int crtc_clock, cdclk;
  11658. if (!intel_crtc || !crtc_state->base.enable)
  11659. return DRM_PLANE_HELPER_NO_SCALING;
  11660. dev = intel_crtc->base.dev;
  11661. dev_priv = dev->dev_private;
  11662. crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
  11663. cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
  11664. if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
  11665. return DRM_PLANE_HELPER_NO_SCALING;
  11666. /*
  11667. * skl max scale is lower of:
  11668. * close to 3 but not 3, -1 is for that purpose
  11669. * or
  11670. * cdclk/crtc_clock
  11671. */
  11672. max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
  11673. return max_scale;
  11674. }
  11675. static int
  11676. intel_check_primary_plane(struct drm_plane *plane,
  11677. struct intel_crtc_state *crtc_state,
  11678. struct intel_plane_state *state)
  11679. {
  11680. struct drm_crtc *crtc = state->base.crtc;
  11681. struct drm_framebuffer *fb = state->base.fb;
  11682. int min_scale = DRM_PLANE_HELPER_NO_SCALING;
  11683. int max_scale = DRM_PLANE_HELPER_NO_SCALING;
  11684. bool can_position = false;
  11685. if (INTEL_INFO(plane->dev)->gen >= 9) {
  11686. /* use scaler when colorkey is not required */
  11687. if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
  11688. min_scale = 1;
  11689. max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
  11690. }
  11691. can_position = true;
  11692. }
  11693. return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
  11694. &state->dst, &state->clip,
  11695. min_scale, max_scale,
  11696. can_position, true,
  11697. &state->visible);
  11698. }
  11699. static void intel_begin_crtc_commit(struct drm_crtc *crtc,
  11700. struct drm_crtc_state *old_crtc_state)
  11701. {
  11702. struct drm_device *dev = crtc->dev;
  11703. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11704. struct intel_crtc_state *old_intel_state =
  11705. to_intel_crtc_state(old_crtc_state);
  11706. bool modeset = needs_modeset(crtc->state);
  11707. /* Perform vblank evasion around commit operation */
  11708. intel_pipe_update_start(intel_crtc);
  11709. if (modeset)
  11710. return;
  11711. if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
  11712. intel_color_set_csc(crtc->state);
  11713. intel_color_load_luts(crtc->state);
  11714. }
  11715. if (to_intel_crtc_state(crtc->state)->update_pipe)
  11716. intel_update_pipe_config(intel_crtc, old_intel_state);
  11717. else if (INTEL_INFO(dev)->gen >= 9)
  11718. skl_detach_scalers(intel_crtc);
  11719. }
  11720. static void intel_finish_crtc_commit(struct drm_crtc *crtc,
  11721. struct drm_crtc_state *old_crtc_state)
  11722. {
  11723. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11724. intel_pipe_update_end(intel_crtc);
  11725. }
  11726. /**
  11727. * intel_plane_destroy - destroy a plane
  11728. * @plane: plane to destroy
  11729. *
  11730. * Common destruction function for all types of planes (primary, cursor,
  11731. * sprite).
  11732. */
  11733. void intel_plane_destroy(struct drm_plane *plane)
  11734. {
  11735. struct intel_plane *intel_plane = to_intel_plane(plane);
  11736. drm_plane_cleanup(plane);
  11737. kfree(intel_plane);
  11738. }
  11739. const struct drm_plane_funcs intel_plane_funcs = {
  11740. .update_plane = drm_atomic_helper_update_plane,
  11741. .disable_plane = drm_atomic_helper_disable_plane,
  11742. .destroy = intel_plane_destroy,
  11743. .set_property = drm_atomic_helper_plane_set_property,
  11744. .atomic_get_property = intel_plane_atomic_get_property,
  11745. .atomic_set_property = intel_plane_atomic_set_property,
  11746. .atomic_duplicate_state = intel_plane_duplicate_state,
  11747. .atomic_destroy_state = intel_plane_destroy_state,
  11748. };
  11749. static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
  11750. int pipe)
  11751. {
  11752. struct intel_plane *primary = NULL;
  11753. struct intel_plane_state *state = NULL;
  11754. const uint32_t *intel_primary_formats;
  11755. unsigned int num_formats;
  11756. int ret;
  11757. primary = kzalloc(sizeof(*primary), GFP_KERNEL);
  11758. if (!primary)
  11759. goto fail;
  11760. state = intel_create_plane_state(&primary->base);
  11761. if (!state)
  11762. goto fail;
  11763. primary->base.state = &state->base;
  11764. primary->can_scale = false;
  11765. primary->max_downscale = 1;
  11766. if (INTEL_INFO(dev)->gen >= 9) {
  11767. primary->can_scale = true;
  11768. state->scaler_id = -1;
  11769. }
  11770. primary->pipe = pipe;
  11771. primary->plane = pipe;
  11772. primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
  11773. primary->check_plane = intel_check_primary_plane;
  11774. if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
  11775. primary->plane = !pipe;
  11776. if (INTEL_INFO(dev)->gen >= 9) {
  11777. intel_primary_formats = skl_primary_formats;
  11778. num_formats = ARRAY_SIZE(skl_primary_formats);
  11779. primary->update_plane = skylake_update_primary_plane;
  11780. primary->disable_plane = skylake_disable_primary_plane;
  11781. } else if (HAS_PCH_SPLIT(dev)) {
  11782. intel_primary_formats = i965_primary_formats;
  11783. num_formats = ARRAY_SIZE(i965_primary_formats);
  11784. primary->update_plane = ironlake_update_primary_plane;
  11785. primary->disable_plane = i9xx_disable_primary_plane;
  11786. } else if (INTEL_INFO(dev)->gen >= 4) {
  11787. intel_primary_formats = i965_primary_formats;
  11788. num_formats = ARRAY_SIZE(i965_primary_formats);
  11789. primary->update_plane = i9xx_update_primary_plane;
  11790. primary->disable_plane = i9xx_disable_primary_plane;
  11791. } else {
  11792. intel_primary_formats = i8xx_primary_formats;
  11793. num_formats = ARRAY_SIZE(i8xx_primary_formats);
  11794. primary->update_plane = i9xx_update_primary_plane;
  11795. primary->disable_plane = i9xx_disable_primary_plane;
  11796. }
  11797. ret = drm_universal_plane_init(dev, &primary->base, 0,
  11798. &intel_plane_funcs,
  11799. intel_primary_formats, num_formats,
  11800. DRM_PLANE_TYPE_PRIMARY, NULL);
  11801. if (ret)
  11802. goto fail;
  11803. if (INTEL_INFO(dev)->gen >= 4)
  11804. intel_create_rotation_property(dev, primary);
  11805. drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
  11806. return &primary->base;
  11807. fail:
  11808. kfree(state);
  11809. kfree(primary);
  11810. return NULL;
  11811. }
  11812. void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
  11813. {
  11814. if (!dev->mode_config.rotation_property) {
  11815. unsigned long flags = BIT(DRM_ROTATE_0) |
  11816. BIT(DRM_ROTATE_180);
  11817. if (INTEL_INFO(dev)->gen >= 9)
  11818. flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
  11819. dev->mode_config.rotation_property =
  11820. drm_mode_create_rotation_property(dev, flags);
  11821. }
  11822. if (dev->mode_config.rotation_property)
  11823. drm_object_attach_property(&plane->base.base,
  11824. dev->mode_config.rotation_property,
  11825. plane->base.state->rotation);
  11826. }
  11827. static int
  11828. intel_check_cursor_plane(struct drm_plane *plane,
  11829. struct intel_crtc_state *crtc_state,
  11830. struct intel_plane_state *state)
  11831. {
  11832. struct drm_crtc *crtc = crtc_state->base.crtc;
  11833. struct drm_framebuffer *fb = state->base.fb;
  11834. struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  11835. enum pipe pipe = to_intel_plane(plane)->pipe;
  11836. unsigned stride;
  11837. int ret;
  11838. ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
  11839. &state->dst, &state->clip,
  11840. DRM_PLANE_HELPER_NO_SCALING,
  11841. DRM_PLANE_HELPER_NO_SCALING,
  11842. true, true, &state->visible);
  11843. if (ret)
  11844. return ret;
  11845. /* if we want to turn off the cursor ignore width and height */
  11846. if (!obj)
  11847. return 0;
  11848. /* Check for which cursor types we support */
  11849. if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
  11850. DRM_DEBUG("Cursor dimension %dx%d not supported\n",
  11851. state->base.crtc_w, state->base.crtc_h);
  11852. return -EINVAL;
  11853. }
  11854. stride = roundup_pow_of_two(state->base.crtc_w) * 4;
  11855. if (obj->base.size < stride * state->base.crtc_h) {
  11856. DRM_DEBUG_KMS("buffer is too small\n");
  11857. return -ENOMEM;
  11858. }
  11859. if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
  11860. DRM_DEBUG_KMS("cursor cannot be tiled\n");
  11861. return -EINVAL;
  11862. }
  11863. /*
  11864. * There's something wrong with the cursor on CHV pipe C.
  11865. * If it straddles the left edge of the screen then
  11866. * moving it away from the edge or disabling it often
  11867. * results in a pipe underrun, and often that can lead to
  11868. * dead pipe (constant underrun reported, and it scans
  11869. * out just a solid color). To recover from that, the
  11870. * display power well must be turned off and on again.
  11871. * Refuse the put the cursor into that compromised position.
  11872. */
  11873. if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
  11874. state->visible && state->base.crtc_x < 0) {
  11875. DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
  11876. return -EINVAL;
  11877. }
  11878. return 0;
  11879. }
  11880. static void
  11881. intel_disable_cursor_plane(struct drm_plane *plane,
  11882. struct drm_crtc *crtc)
  11883. {
  11884. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11885. intel_crtc->cursor_addr = 0;
  11886. intel_crtc_update_cursor(crtc, NULL);
  11887. }
  11888. static void
  11889. intel_update_cursor_plane(struct drm_plane *plane,
  11890. const struct intel_crtc_state *crtc_state,
  11891. const struct intel_plane_state *state)
  11892. {
  11893. struct drm_crtc *crtc = crtc_state->base.crtc;
  11894. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11895. struct drm_device *dev = plane->dev;
  11896. struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
  11897. uint32_t addr;
  11898. if (!obj)
  11899. addr = 0;
  11900. else if (!INTEL_INFO(dev)->cursor_needs_physical)
  11901. addr = i915_gem_obj_ggtt_offset(obj);
  11902. else
  11903. addr = obj->phys_handle->busaddr;
  11904. intel_crtc->cursor_addr = addr;
  11905. intel_crtc_update_cursor(crtc, state);
  11906. }
  11907. static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
  11908. int pipe)
  11909. {
  11910. struct intel_plane *cursor = NULL;
  11911. struct intel_plane_state *state = NULL;
  11912. int ret;
  11913. cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
  11914. if (!cursor)
  11915. goto fail;
  11916. state = intel_create_plane_state(&cursor->base);
  11917. if (!state)
  11918. goto fail;
  11919. cursor->base.state = &state->base;
  11920. cursor->can_scale = false;
  11921. cursor->max_downscale = 1;
  11922. cursor->pipe = pipe;
  11923. cursor->plane = pipe;
  11924. cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
  11925. cursor->check_plane = intel_check_cursor_plane;
  11926. cursor->update_plane = intel_update_cursor_plane;
  11927. cursor->disable_plane = intel_disable_cursor_plane;
  11928. ret = drm_universal_plane_init(dev, &cursor->base, 0,
  11929. &intel_plane_funcs,
  11930. intel_cursor_formats,
  11931. ARRAY_SIZE(intel_cursor_formats),
  11932. DRM_PLANE_TYPE_CURSOR, NULL);
  11933. if (ret)
  11934. goto fail;
  11935. if (INTEL_INFO(dev)->gen >= 4) {
  11936. if (!dev->mode_config.rotation_property)
  11937. dev->mode_config.rotation_property =
  11938. drm_mode_create_rotation_property(dev,
  11939. BIT(DRM_ROTATE_0) |
  11940. BIT(DRM_ROTATE_180));
  11941. if (dev->mode_config.rotation_property)
  11942. drm_object_attach_property(&cursor->base.base,
  11943. dev->mode_config.rotation_property,
  11944. state->base.rotation);
  11945. }
  11946. if (INTEL_INFO(dev)->gen >=9)
  11947. state->scaler_id = -1;
  11948. drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
  11949. return &cursor->base;
  11950. fail:
  11951. kfree(state);
  11952. kfree(cursor);
  11953. return NULL;
  11954. }
  11955. static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
  11956. struct intel_crtc_state *crtc_state)
  11957. {
  11958. int i;
  11959. struct intel_scaler *intel_scaler;
  11960. struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
  11961. for (i = 0; i < intel_crtc->num_scalers; i++) {
  11962. intel_scaler = &scaler_state->scalers[i];
  11963. intel_scaler->in_use = 0;
  11964. intel_scaler->mode = PS_SCALER_MODE_DYN;
  11965. }
  11966. scaler_state->scaler_id = -1;
  11967. }
  11968. static void intel_crtc_init(struct drm_device *dev, int pipe)
  11969. {
  11970. struct drm_i915_private *dev_priv = dev->dev_private;
  11971. struct intel_crtc *intel_crtc;
  11972. struct intel_crtc_state *crtc_state = NULL;
  11973. struct drm_plane *primary = NULL;
  11974. struct drm_plane *cursor = NULL;
  11975. int ret;
  11976. intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
  11977. if (intel_crtc == NULL)
  11978. return;
  11979. crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
  11980. if (!crtc_state)
  11981. goto fail;
  11982. intel_crtc->config = crtc_state;
  11983. intel_crtc->base.state = &crtc_state->base;
  11984. crtc_state->base.crtc = &intel_crtc->base;
  11985. /* initialize shared scalers */
  11986. if (INTEL_INFO(dev)->gen >= 9) {
  11987. if (pipe == PIPE_C)
  11988. intel_crtc->num_scalers = 1;
  11989. else
  11990. intel_crtc->num_scalers = SKL_NUM_SCALERS;
  11991. skl_init_scalers(dev, intel_crtc, crtc_state);
  11992. }
  11993. primary = intel_primary_plane_create(dev, pipe);
  11994. if (!primary)
  11995. goto fail;
  11996. cursor = intel_cursor_plane_create(dev, pipe);
  11997. if (!cursor)
  11998. goto fail;
  11999. ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
  12000. cursor, &intel_crtc_funcs, NULL);
  12001. if (ret)
  12002. goto fail;
  12003. /*
  12004. * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
  12005. * is hooked to pipe B. Hence we want plane A feeding pipe B.
  12006. */
  12007. intel_crtc->pipe = pipe;
  12008. intel_crtc->plane = pipe;
  12009. if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
  12010. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  12011. intel_crtc->plane = !pipe;
  12012. }
  12013. intel_crtc->cursor_base = ~0;
  12014. intel_crtc->cursor_cntl = ~0;
  12015. intel_crtc->cursor_size = ~0;
  12016. intel_crtc->wm.cxsr_allowed = true;
  12017. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  12018. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  12019. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  12020. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  12021. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  12022. intel_color_init(&intel_crtc->base);
  12023. WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
  12024. return;
  12025. fail:
  12026. if (primary)
  12027. drm_plane_cleanup(primary);
  12028. if (cursor)
  12029. drm_plane_cleanup(cursor);
  12030. kfree(crtc_state);
  12031. kfree(intel_crtc);
  12032. }
  12033. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
  12034. {
  12035. struct drm_encoder *encoder = connector->base.encoder;
  12036. struct drm_device *dev = connector->base.dev;
  12037. WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  12038. if (!encoder || WARN_ON(!encoder->crtc))
  12039. return INVALID_PIPE;
  12040. return to_intel_crtc(encoder->crtc)->pipe;
  12041. }
  12042. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  12043. struct drm_file *file)
  12044. {
  12045. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  12046. struct drm_crtc *drmmode_crtc;
  12047. struct intel_crtc *crtc;
  12048. drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
  12049. if (!drmmode_crtc) {
  12050. DRM_ERROR("no such CRTC id\n");
  12051. return -ENOENT;
  12052. }
  12053. crtc = to_intel_crtc(drmmode_crtc);
  12054. pipe_from_crtc_id->pipe = crtc->pipe;
  12055. return 0;
  12056. }
  12057. static int intel_encoder_clones(struct intel_encoder *encoder)
  12058. {
  12059. struct drm_device *dev = encoder->base.dev;
  12060. struct intel_encoder *source_encoder;
  12061. int index_mask = 0;
  12062. int entry = 0;
  12063. for_each_intel_encoder(dev, source_encoder) {
  12064. if (encoders_cloneable(encoder, source_encoder))
  12065. index_mask |= (1 << entry);
  12066. entry++;
  12067. }
  12068. return index_mask;
  12069. }
  12070. static bool has_edp_a(struct drm_device *dev)
  12071. {
  12072. struct drm_i915_private *dev_priv = dev->dev_private;
  12073. if (!IS_MOBILE(dev))
  12074. return false;
  12075. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  12076. return false;
  12077. if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
  12078. return false;
  12079. return true;
  12080. }
  12081. static bool intel_crt_present(struct drm_device *dev)
  12082. {
  12083. struct drm_i915_private *dev_priv = dev->dev_private;
  12084. if (INTEL_INFO(dev)->gen >= 9)
  12085. return false;
  12086. if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
  12087. return false;
  12088. if (IS_CHERRYVIEW(dev))
  12089. return false;
  12090. if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
  12091. return false;
  12092. /* DDI E can't be used if DDI A requires 4 lanes */
  12093. if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
  12094. return false;
  12095. if (!dev_priv->vbt.int_crt_support)
  12096. return false;
  12097. return true;
  12098. }
  12099. static void intel_setup_outputs(struct drm_device *dev)
  12100. {
  12101. struct drm_i915_private *dev_priv = dev->dev_private;
  12102. struct intel_encoder *encoder;
  12103. bool dpd_is_edp = false;
  12104. intel_lvds_init(dev);
  12105. if (intel_crt_present(dev))
  12106. intel_crt_init(dev);
  12107. if (IS_BROXTON(dev)) {
  12108. /*
  12109. * FIXME: Broxton doesn't support port detection via the
  12110. * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
  12111. * detect the ports.
  12112. */
  12113. intel_ddi_init(dev, PORT_A);
  12114. intel_ddi_init(dev, PORT_B);
  12115. intel_ddi_init(dev, PORT_C);
  12116. intel_dsi_init(dev);
  12117. } else if (HAS_DDI(dev)) {
  12118. int found;
  12119. /*
  12120. * Haswell uses DDI functions to detect digital outputs.
  12121. * On SKL pre-D0 the strap isn't connected, so we assume
  12122. * it's there.
  12123. */
  12124. found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
  12125. /* WaIgnoreDDIAStrap: skl */
  12126. if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
  12127. intel_ddi_init(dev, PORT_A);
  12128. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  12129. * register */
  12130. found = I915_READ(SFUSE_STRAP);
  12131. if (found & SFUSE_STRAP_DDIB_DETECTED)
  12132. intel_ddi_init(dev, PORT_B);
  12133. if (found & SFUSE_STRAP_DDIC_DETECTED)
  12134. intel_ddi_init(dev, PORT_C);
  12135. if (found & SFUSE_STRAP_DDID_DETECTED)
  12136. intel_ddi_init(dev, PORT_D);
  12137. /*
  12138. * On SKL we don't have a way to detect DDI-E so we rely on VBT.
  12139. */
  12140. if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
  12141. (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
  12142. dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
  12143. dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
  12144. intel_ddi_init(dev, PORT_E);
  12145. } else if (HAS_PCH_SPLIT(dev)) {
  12146. int found;
  12147. dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
  12148. if (has_edp_a(dev))
  12149. intel_dp_init(dev, DP_A, PORT_A);
  12150. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  12151. /* PCH SDVOB multiplex with HDMIB */
  12152. found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
  12153. if (!found)
  12154. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  12155. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  12156. intel_dp_init(dev, PCH_DP_B, PORT_B);
  12157. }
  12158. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  12159. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  12160. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  12161. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  12162. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  12163. intel_dp_init(dev, PCH_DP_C, PORT_C);
  12164. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  12165. intel_dp_init(dev, PCH_DP_D, PORT_D);
  12166. } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  12167. /*
  12168. * The DP_DETECTED bit is the latched state of the DDC
  12169. * SDA pin at boot. However since eDP doesn't require DDC
  12170. * (no way to plug in a DP->HDMI dongle) the DDC pins for
  12171. * eDP ports may have been muxed to an alternate function.
  12172. * Thus we can't rely on the DP_DETECTED bit alone to detect
  12173. * eDP ports. Consult the VBT as well as DP_DETECTED to
  12174. * detect eDP ports.
  12175. */
  12176. if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
  12177. !intel_dp_is_edp(dev, PORT_B))
  12178. intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
  12179. if (I915_READ(VLV_DP_B) & DP_DETECTED ||
  12180. intel_dp_is_edp(dev, PORT_B))
  12181. intel_dp_init(dev, VLV_DP_B, PORT_B);
  12182. if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
  12183. !intel_dp_is_edp(dev, PORT_C))
  12184. intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
  12185. if (I915_READ(VLV_DP_C) & DP_DETECTED ||
  12186. intel_dp_is_edp(dev, PORT_C))
  12187. intel_dp_init(dev, VLV_DP_C, PORT_C);
  12188. if (IS_CHERRYVIEW(dev)) {
  12189. /* eDP not supported on port D, so don't check VBT */
  12190. if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
  12191. intel_hdmi_init(dev, CHV_HDMID, PORT_D);
  12192. if (I915_READ(CHV_DP_D) & DP_DETECTED)
  12193. intel_dp_init(dev, CHV_DP_D, PORT_D);
  12194. }
  12195. intel_dsi_init(dev);
  12196. } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
  12197. bool found = false;
  12198. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  12199. DRM_DEBUG_KMS("probing SDVOB\n");
  12200. found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
  12201. if (!found && IS_G4X(dev)) {
  12202. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  12203. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  12204. }
  12205. if (!found && IS_G4X(dev))
  12206. intel_dp_init(dev, DP_B, PORT_B);
  12207. }
  12208. /* Before G4X SDVOC doesn't have its own detect register */
  12209. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  12210. DRM_DEBUG_KMS("probing SDVOC\n");
  12211. found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
  12212. }
  12213. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  12214. if (IS_G4X(dev)) {
  12215. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  12216. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  12217. }
  12218. if (IS_G4X(dev))
  12219. intel_dp_init(dev, DP_C, PORT_C);
  12220. }
  12221. if (IS_G4X(dev) &&
  12222. (I915_READ(DP_D) & DP_DETECTED))
  12223. intel_dp_init(dev, DP_D, PORT_D);
  12224. } else if (IS_GEN2(dev))
  12225. intel_dvo_init(dev);
  12226. if (SUPPORTS_TV(dev))
  12227. intel_tv_init(dev);
  12228. intel_psr_init(dev);
  12229. for_each_intel_encoder(dev, encoder) {
  12230. encoder->base.possible_crtcs = encoder->crtc_mask;
  12231. encoder->base.possible_clones =
  12232. intel_encoder_clones(encoder);
  12233. }
  12234. intel_init_pch_refclk(dev);
  12235. drm_helper_move_panel_connectors_to_head(dev);
  12236. }
  12237. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  12238. {
  12239. struct drm_device *dev = fb->dev;
  12240. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  12241. drm_framebuffer_cleanup(fb);
  12242. mutex_lock(&dev->struct_mutex);
  12243. WARN_ON(!intel_fb->obj->framebuffer_references--);
  12244. drm_gem_object_unreference(&intel_fb->obj->base);
  12245. mutex_unlock(&dev->struct_mutex);
  12246. kfree(intel_fb);
  12247. }
  12248. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  12249. struct drm_file *file,
  12250. unsigned int *handle)
  12251. {
  12252. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  12253. struct drm_i915_gem_object *obj = intel_fb->obj;
  12254. if (obj->userptr.mm) {
  12255. DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
  12256. return -EINVAL;
  12257. }
  12258. return drm_gem_handle_create(file, &obj->base, handle);
  12259. }
  12260. static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
  12261. struct drm_file *file,
  12262. unsigned flags, unsigned color,
  12263. struct drm_clip_rect *clips,
  12264. unsigned num_clips)
  12265. {
  12266. struct drm_device *dev = fb->dev;
  12267. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  12268. struct drm_i915_gem_object *obj = intel_fb->obj;
  12269. mutex_lock(&dev->struct_mutex);
  12270. intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
  12271. mutex_unlock(&dev->struct_mutex);
  12272. return 0;
  12273. }
  12274. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  12275. .destroy = intel_user_framebuffer_destroy,
  12276. .create_handle = intel_user_framebuffer_create_handle,
  12277. .dirty = intel_user_framebuffer_dirty,
  12278. };
  12279. static
  12280. u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
  12281. uint32_t pixel_format)
  12282. {
  12283. u32 gen = INTEL_INFO(dev)->gen;
  12284. if (gen >= 9) {
  12285. int cpp = drm_format_plane_cpp(pixel_format, 0);
  12286. /* "The stride in bytes must not exceed the of the size of 8K
  12287. * pixels and 32K bytes."
  12288. */
  12289. return min(8192 * cpp, 32768);
  12290. } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
  12291. return 32*1024;
  12292. } else if (gen >= 4) {
  12293. if (fb_modifier == I915_FORMAT_MOD_X_TILED)
  12294. return 16*1024;
  12295. else
  12296. return 32*1024;
  12297. } else if (gen >= 3) {
  12298. if (fb_modifier == I915_FORMAT_MOD_X_TILED)
  12299. return 8*1024;
  12300. else
  12301. return 16*1024;
  12302. } else {
  12303. /* XXX DSPC is limited to 4k tiled */
  12304. return 8*1024;
  12305. }
  12306. }
  12307. static int intel_framebuffer_init(struct drm_device *dev,
  12308. struct intel_framebuffer *intel_fb,
  12309. struct drm_mode_fb_cmd2 *mode_cmd,
  12310. struct drm_i915_gem_object *obj)
  12311. {
  12312. struct drm_i915_private *dev_priv = to_i915(dev);
  12313. unsigned int aligned_height;
  12314. int ret;
  12315. u32 pitch_limit, stride_alignment;
  12316. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  12317. if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
  12318. /* Enforce that fb modifier and tiling mode match, but only for
  12319. * X-tiled. This is needed for FBC. */
  12320. if (!!(obj->tiling_mode == I915_TILING_X) !=
  12321. !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
  12322. DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
  12323. return -EINVAL;
  12324. }
  12325. } else {
  12326. if (obj->tiling_mode == I915_TILING_X)
  12327. mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
  12328. else if (obj->tiling_mode == I915_TILING_Y) {
  12329. DRM_DEBUG("No Y tiling for legacy addfb\n");
  12330. return -EINVAL;
  12331. }
  12332. }
  12333. /* Passed in modifier sanity checking. */
  12334. switch (mode_cmd->modifier[0]) {
  12335. case I915_FORMAT_MOD_Y_TILED:
  12336. case I915_FORMAT_MOD_Yf_TILED:
  12337. if (INTEL_INFO(dev)->gen < 9) {
  12338. DRM_DEBUG("Unsupported tiling 0x%llx!\n",
  12339. mode_cmd->modifier[0]);
  12340. return -EINVAL;
  12341. }
  12342. case DRM_FORMAT_MOD_NONE:
  12343. case I915_FORMAT_MOD_X_TILED:
  12344. break;
  12345. default:
  12346. DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
  12347. mode_cmd->modifier[0]);
  12348. return -EINVAL;
  12349. }
  12350. stride_alignment = intel_fb_stride_alignment(dev_priv,
  12351. mode_cmd->modifier[0],
  12352. mode_cmd->pixel_format);
  12353. if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
  12354. DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
  12355. mode_cmd->pitches[0], stride_alignment);
  12356. return -EINVAL;
  12357. }
  12358. pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
  12359. mode_cmd->pixel_format);
  12360. if (mode_cmd->pitches[0] > pitch_limit) {
  12361. DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
  12362. mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
  12363. "tiled" : "linear",
  12364. mode_cmd->pitches[0], pitch_limit);
  12365. return -EINVAL;
  12366. }
  12367. if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
  12368. mode_cmd->pitches[0] != obj->stride) {
  12369. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  12370. mode_cmd->pitches[0], obj->stride);
  12371. return -EINVAL;
  12372. }
  12373. /* Reject formats not supported by any plane early. */
  12374. switch (mode_cmd->pixel_format) {
  12375. case DRM_FORMAT_C8:
  12376. case DRM_FORMAT_RGB565:
  12377. case DRM_FORMAT_XRGB8888:
  12378. case DRM_FORMAT_ARGB8888:
  12379. break;
  12380. case DRM_FORMAT_XRGB1555:
  12381. if (INTEL_INFO(dev)->gen > 3) {
  12382. DRM_DEBUG("unsupported pixel format: %s\n",
  12383. drm_get_format_name(mode_cmd->pixel_format));
  12384. return -EINVAL;
  12385. }
  12386. break;
  12387. case DRM_FORMAT_ABGR8888:
  12388. if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
  12389. INTEL_INFO(dev)->gen < 9) {
  12390. DRM_DEBUG("unsupported pixel format: %s\n",
  12391. drm_get_format_name(mode_cmd->pixel_format));
  12392. return -EINVAL;
  12393. }
  12394. break;
  12395. case DRM_FORMAT_XBGR8888:
  12396. case DRM_FORMAT_XRGB2101010:
  12397. case DRM_FORMAT_XBGR2101010:
  12398. if (INTEL_INFO(dev)->gen < 4) {
  12399. DRM_DEBUG("unsupported pixel format: %s\n",
  12400. drm_get_format_name(mode_cmd->pixel_format));
  12401. return -EINVAL;
  12402. }
  12403. break;
  12404. case DRM_FORMAT_ABGR2101010:
  12405. if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
  12406. DRM_DEBUG("unsupported pixel format: %s\n",
  12407. drm_get_format_name(mode_cmd->pixel_format));
  12408. return -EINVAL;
  12409. }
  12410. break;
  12411. case DRM_FORMAT_YUYV:
  12412. case DRM_FORMAT_UYVY:
  12413. case DRM_FORMAT_YVYU:
  12414. case DRM_FORMAT_VYUY:
  12415. if (INTEL_INFO(dev)->gen < 5) {
  12416. DRM_DEBUG("unsupported pixel format: %s\n",
  12417. drm_get_format_name(mode_cmd->pixel_format));
  12418. return -EINVAL;
  12419. }
  12420. break;
  12421. default:
  12422. DRM_DEBUG("unsupported pixel format: %s\n",
  12423. drm_get_format_name(mode_cmd->pixel_format));
  12424. return -EINVAL;
  12425. }
  12426. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  12427. if (mode_cmd->offsets[0] != 0)
  12428. return -EINVAL;
  12429. aligned_height = intel_fb_align_height(dev, mode_cmd->height,
  12430. mode_cmd->pixel_format,
  12431. mode_cmd->modifier[0]);
  12432. /* FIXME drm helper for size checks (especially planar formats)? */
  12433. if (obj->base.size < aligned_height * mode_cmd->pitches[0])
  12434. return -EINVAL;
  12435. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  12436. intel_fb->obj = obj;
  12437. intel_fill_fb_info(dev_priv, &intel_fb->base);
  12438. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  12439. if (ret) {
  12440. DRM_ERROR("framebuffer init failed %d\n", ret);
  12441. return ret;
  12442. }
  12443. intel_fb->obj->framebuffer_references++;
  12444. return 0;
  12445. }
  12446. static struct drm_framebuffer *
  12447. intel_user_framebuffer_create(struct drm_device *dev,
  12448. struct drm_file *filp,
  12449. const struct drm_mode_fb_cmd2 *user_mode_cmd)
  12450. {
  12451. struct drm_framebuffer *fb;
  12452. struct drm_i915_gem_object *obj;
  12453. struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
  12454. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  12455. mode_cmd.handles[0]));
  12456. if (&obj->base == NULL)
  12457. return ERR_PTR(-ENOENT);
  12458. fb = intel_framebuffer_create(dev, &mode_cmd, obj);
  12459. if (IS_ERR(fb))
  12460. drm_gem_object_unreference_unlocked(&obj->base);
  12461. return fb;
  12462. }
  12463. #ifndef CONFIG_DRM_FBDEV_EMULATION
  12464. static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
  12465. {
  12466. }
  12467. #endif
  12468. static const struct drm_mode_config_funcs intel_mode_funcs = {
  12469. .fb_create = intel_user_framebuffer_create,
  12470. .output_poll_changed = intel_fbdev_output_poll_changed,
  12471. .atomic_check = intel_atomic_check,
  12472. .atomic_commit = intel_atomic_commit,
  12473. .atomic_state_alloc = intel_atomic_state_alloc,
  12474. .atomic_state_clear = intel_atomic_state_clear,
  12475. };
  12476. /**
  12477. * intel_init_display_hooks - initialize the display modesetting hooks
  12478. * @dev_priv: device private
  12479. */
  12480. void intel_init_display_hooks(struct drm_i915_private *dev_priv)
  12481. {
  12482. if (INTEL_INFO(dev_priv)->gen >= 9) {
  12483. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  12484. dev_priv->display.get_initial_plane_config =
  12485. skylake_get_initial_plane_config;
  12486. dev_priv->display.crtc_compute_clock =
  12487. haswell_crtc_compute_clock;
  12488. dev_priv->display.crtc_enable = haswell_crtc_enable;
  12489. dev_priv->display.crtc_disable = haswell_crtc_disable;
  12490. } else if (HAS_DDI(dev_priv)) {
  12491. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  12492. dev_priv->display.get_initial_plane_config =
  12493. ironlake_get_initial_plane_config;
  12494. dev_priv->display.crtc_compute_clock =
  12495. haswell_crtc_compute_clock;
  12496. dev_priv->display.crtc_enable = haswell_crtc_enable;
  12497. dev_priv->display.crtc_disable = haswell_crtc_disable;
  12498. } else if (HAS_PCH_SPLIT(dev_priv)) {
  12499. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  12500. dev_priv->display.get_initial_plane_config =
  12501. ironlake_get_initial_plane_config;
  12502. dev_priv->display.crtc_compute_clock =
  12503. ironlake_crtc_compute_clock;
  12504. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  12505. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  12506. } else if (IS_CHERRYVIEW(dev_priv)) {
  12507. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12508. dev_priv->display.get_initial_plane_config =
  12509. i9xx_get_initial_plane_config;
  12510. dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
  12511. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  12512. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12513. } else if (IS_VALLEYVIEW(dev_priv)) {
  12514. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12515. dev_priv->display.get_initial_plane_config =
  12516. i9xx_get_initial_plane_config;
  12517. dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
  12518. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  12519. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12520. } else if (IS_G4X(dev_priv)) {
  12521. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12522. dev_priv->display.get_initial_plane_config =
  12523. i9xx_get_initial_plane_config;
  12524. dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
  12525. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  12526. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12527. } else if (IS_PINEVIEW(dev_priv)) {
  12528. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12529. dev_priv->display.get_initial_plane_config =
  12530. i9xx_get_initial_plane_config;
  12531. dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
  12532. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  12533. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12534. } else if (!IS_GEN2(dev_priv)) {
  12535. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12536. dev_priv->display.get_initial_plane_config =
  12537. i9xx_get_initial_plane_config;
  12538. dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
  12539. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  12540. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12541. } else {
  12542. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  12543. dev_priv->display.get_initial_plane_config =
  12544. i9xx_get_initial_plane_config;
  12545. dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
  12546. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  12547. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  12548. }
  12549. /* Returns the core display clock speed */
  12550. if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
  12551. dev_priv->display.get_display_clock_speed =
  12552. skylake_get_display_clock_speed;
  12553. else if (IS_BROXTON(dev_priv))
  12554. dev_priv->display.get_display_clock_speed =
  12555. broxton_get_display_clock_speed;
  12556. else if (IS_BROADWELL(dev_priv))
  12557. dev_priv->display.get_display_clock_speed =
  12558. broadwell_get_display_clock_speed;
  12559. else if (IS_HASWELL(dev_priv))
  12560. dev_priv->display.get_display_clock_speed =
  12561. haswell_get_display_clock_speed;
  12562. else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
  12563. dev_priv->display.get_display_clock_speed =
  12564. valleyview_get_display_clock_speed;
  12565. else if (IS_GEN5(dev_priv))
  12566. dev_priv->display.get_display_clock_speed =
  12567. ilk_get_display_clock_speed;
  12568. else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
  12569. IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
  12570. dev_priv->display.get_display_clock_speed =
  12571. i945_get_display_clock_speed;
  12572. else if (IS_GM45(dev_priv))
  12573. dev_priv->display.get_display_clock_speed =
  12574. gm45_get_display_clock_speed;
  12575. else if (IS_CRESTLINE(dev_priv))
  12576. dev_priv->display.get_display_clock_speed =
  12577. i965gm_get_display_clock_speed;
  12578. else if (IS_PINEVIEW(dev_priv))
  12579. dev_priv->display.get_display_clock_speed =
  12580. pnv_get_display_clock_speed;
  12581. else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
  12582. dev_priv->display.get_display_clock_speed =
  12583. g33_get_display_clock_speed;
  12584. else if (IS_I915G(dev_priv))
  12585. dev_priv->display.get_display_clock_speed =
  12586. i915_get_display_clock_speed;
  12587. else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
  12588. dev_priv->display.get_display_clock_speed =
  12589. i9xx_misc_get_display_clock_speed;
  12590. else if (IS_I915GM(dev_priv))
  12591. dev_priv->display.get_display_clock_speed =
  12592. i915gm_get_display_clock_speed;
  12593. else if (IS_I865G(dev_priv))
  12594. dev_priv->display.get_display_clock_speed =
  12595. i865_get_display_clock_speed;
  12596. else if (IS_I85X(dev_priv))
  12597. dev_priv->display.get_display_clock_speed =
  12598. i85x_get_display_clock_speed;
  12599. else { /* 830 */
  12600. WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
  12601. dev_priv->display.get_display_clock_speed =
  12602. i830_get_display_clock_speed;
  12603. }
  12604. if (IS_GEN5(dev_priv)) {
  12605. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  12606. } else if (IS_GEN6(dev_priv)) {
  12607. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  12608. } else if (IS_IVYBRIDGE(dev_priv)) {
  12609. /* FIXME: detect B0+ stepping and use auto training */
  12610. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  12611. } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
  12612. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  12613. if (IS_BROADWELL(dev_priv)) {
  12614. dev_priv->display.modeset_commit_cdclk =
  12615. broadwell_modeset_commit_cdclk;
  12616. dev_priv->display.modeset_calc_cdclk =
  12617. broadwell_modeset_calc_cdclk;
  12618. }
  12619. } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
  12620. dev_priv->display.modeset_commit_cdclk =
  12621. valleyview_modeset_commit_cdclk;
  12622. dev_priv->display.modeset_calc_cdclk =
  12623. valleyview_modeset_calc_cdclk;
  12624. } else if (IS_BROXTON(dev_priv)) {
  12625. dev_priv->display.modeset_commit_cdclk =
  12626. broxton_modeset_commit_cdclk;
  12627. dev_priv->display.modeset_calc_cdclk =
  12628. broxton_modeset_calc_cdclk;
  12629. }
  12630. switch (INTEL_INFO(dev_priv)->gen) {
  12631. case 2:
  12632. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  12633. break;
  12634. case 3:
  12635. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  12636. break;
  12637. case 4:
  12638. case 5:
  12639. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  12640. break;
  12641. case 6:
  12642. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  12643. break;
  12644. case 7:
  12645. case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
  12646. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  12647. break;
  12648. case 9:
  12649. /* Drop through - unsupported since execlist only. */
  12650. default:
  12651. /* Default just returns -ENODEV to indicate unsupported */
  12652. dev_priv->display.queue_flip = intel_default_queue_flip;
  12653. }
  12654. }
  12655. /*
  12656. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  12657. * resume, or other times. This quirk makes sure that's the case for
  12658. * affected systems.
  12659. */
  12660. static void quirk_pipea_force(struct drm_device *dev)
  12661. {
  12662. struct drm_i915_private *dev_priv = dev->dev_private;
  12663. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  12664. DRM_INFO("applying pipe a force quirk\n");
  12665. }
  12666. static void quirk_pipeb_force(struct drm_device *dev)
  12667. {
  12668. struct drm_i915_private *dev_priv = dev->dev_private;
  12669. dev_priv->quirks |= QUIRK_PIPEB_FORCE;
  12670. DRM_INFO("applying pipe b force quirk\n");
  12671. }
  12672. /*
  12673. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  12674. */
  12675. static void quirk_ssc_force_disable(struct drm_device *dev)
  12676. {
  12677. struct drm_i915_private *dev_priv = dev->dev_private;
  12678. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  12679. DRM_INFO("applying lvds SSC disable quirk\n");
  12680. }
  12681. /*
  12682. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  12683. * brightness value
  12684. */
  12685. static void quirk_invert_brightness(struct drm_device *dev)
  12686. {
  12687. struct drm_i915_private *dev_priv = dev->dev_private;
  12688. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  12689. DRM_INFO("applying inverted panel brightness quirk\n");
  12690. }
  12691. /* Some VBT's incorrectly indicate no backlight is present */
  12692. static void quirk_backlight_present(struct drm_device *dev)
  12693. {
  12694. struct drm_i915_private *dev_priv = dev->dev_private;
  12695. dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
  12696. DRM_INFO("applying backlight present quirk\n");
  12697. }
  12698. struct intel_quirk {
  12699. int device;
  12700. int subsystem_vendor;
  12701. int subsystem_device;
  12702. void (*hook)(struct drm_device *dev);
  12703. };
  12704. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  12705. struct intel_dmi_quirk {
  12706. void (*hook)(struct drm_device *dev);
  12707. const struct dmi_system_id (*dmi_id_list)[];
  12708. };
  12709. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  12710. {
  12711. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  12712. return 1;
  12713. }
  12714. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  12715. {
  12716. .dmi_id_list = &(const struct dmi_system_id[]) {
  12717. {
  12718. .callback = intel_dmi_reverse_brightness,
  12719. .ident = "NCR Corporation",
  12720. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  12721. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  12722. },
  12723. },
  12724. { } /* terminating entry */
  12725. },
  12726. .hook = quirk_invert_brightness,
  12727. },
  12728. };
  12729. static struct intel_quirk intel_quirks[] = {
  12730. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  12731. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  12732. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  12733. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  12734. /* 830 needs to leave pipe A & dpll A up */
  12735. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  12736. /* 830 needs to leave pipe B & dpll B up */
  12737. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
  12738. /* Lenovo U160 cannot use SSC on LVDS */
  12739. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  12740. /* Sony Vaio Y cannot use SSC on LVDS */
  12741. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  12742. /* Acer Aspire 5734Z must invert backlight brightness */
  12743. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  12744. /* Acer/eMachines G725 */
  12745. { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  12746. /* Acer/eMachines e725 */
  12747. { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  12748. /* Acer/Packard Bell NCL20 */
  12749. { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  12750. /* Acer Aspire 4736Z */
  12751. { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  12752. /* Acer Aspire 5336 */
  12753. { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
  12754. /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
  12755. { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
  12756. /* Acer C720 Chromebook (Core i3 4005U) */
  12757. { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
  12758. /* Apple Macbook 2,1 (Core 2 T7400) */
  12759. { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
  12760. /* Apple Macbook 4,1 */
  12761. { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
  12762. /* Toshiba CB35 Chromebook (Celeron 2955U) */
  12763. { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
  12764. /* HP Chromebook 14 (Celeron 2955U) */
  12765. { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
  12766. /* Dell Chromebook 11 */
  12767. { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
  12768. /* Dell Chromebook 11 (2015 version) */
  12769. { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
  12770. };
  12771. static void intel_init_quirks(struct drm_device *dev)
  12772. {
  12773. struct pci_dev *d = dev->pdev;
  12774. int i;
  12775. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  12776. struct intel_quirk *q = &intel_quirks[i];
  12777. if (d->device == q->device &&
  12778. (d->subsystem_vendor == q->subsystem_vendor ||
  12779. q->subsystem_vendor == PCI_ANY_ID) &&
  12780. (d->subsystem_device == q->subsystem_device ||
  12781. q->subsystem_device == PCI_ANY_ID))
  12782. q->hook(dev);
  12783. }
  12784. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  12785. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  12786. intel_dmi_quirks[i].hook(dev);
  12787. }
  12788. }
  12789. /* Disable the VGA plane that we never use */
  12790. static void i915_disable_vga(struct drm_device *dev)
  12791. {
  12792. struct drm_i915_private *dev_priv = dev->dev_private;
  12793. u8 sr1;
  12794. i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
  12795. /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
  12796. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  12797. outb(SR01, VGA_SR_INDEX);
  12798. sr1 = inb(VGA_SR_DATA);
  12799. outb(sr1 | 1<<5, VGA_SR_DATA);
  12800. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  12801. udelay(300);
  12802. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  12803. POSTING_READ(vga_reg);
  12804. }
  12805. void intel_modeset_init_hw(struct drm_device *dev)
  12806. {
  12807. struct drm_i915_private *dev_priv = dev->dev_private;
  12808. intel_update_cdclk(dev);
  12809. dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
  12810. intel_init_clock_gating(dev);
  12811. intel_enable_gt_powersave(dev_priv);
  12812. }
  12813. /*
  12814. * Calculate what we think the watermarks should be for the state we've read
  12815. * out of the hardware and then immediately program those watermarks so that
  12816. * we ensure the hardware settings match our internal state.
  12817. *
  12818. * We can calculate what we think WM's should be by creating a duplicate of the
  12819. * current state (which was constructed during hardware readout) and running it
  12820. * through the atomic check code to calculate new watermark values in the
  12821. * state object.
  12822. */
  12823. static void sanitize_watermarks(struct drm_device *dev)
  12824. {
  12825. struct drm_i915_private *dev_priv = to_i915(dev);
  12826. struct drm_atomic_state *state;
  12827. struct drm_crtc *crtc;
  12828. struct drm_crtc_state *cstate;
  12829. struct drm_modeset_acquire_ctx ctx;
  12830. int ret;
  12831. int i;
  12832. /* Only supported on platforms that use atomic watermark design */
  12833. if (!dev_priv->display.optimize_watermarks)
  12834. return;
  12835. /*
  12836. * We need to hold connection_mutex before calling duplicate_state so
  12837. * that the connector loop is protected.
  12838. */
  12839. drm_modeset_acquire_init(&ctx, 0);
  12840. retry:
  12841. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  12842. if (ret == -EDEADLK) {
  12843. drm_modeset_backoff(&ctx);
  12844. goto retry;
  12845. } else if (WARN_ON(ret)) {
  12846. goto fail;
  12847. }
  12848. state = drm_atomic_helper_duplicate_state(dev, &ctx);
  12849. if (WARN_ON(IS_ERR(state)))
  12850. goto fail;
  12851. /*
  12852. * Hardware readout is the only time we don't want to calculate
  12853. * intermediate watermarks (since we don't trust the current
  12854. * watermarks).
  12855. */
  12856. to_intel_atomic_state(state)->skip_intermediate_wm = true;
  12857. ret = intel_atomic_check(dev, state);
  12858. if (ret) {
  12859. /*
  12860. * If we fail here, it means that the hardware appears to be
  12861. * programmed in a way that shouldn't be possible, given our
  12862. * understanding of watermark requirements. This might mean a
  12863. * mistake in the hardware readout code or a mistake in the
  12864. * watermark calculations for a given platform. Raise a WARN
  12865. * so that this is noticeable.
  12866. *
  12867. * If this actually happens, we'll have to just leave the
  12868. * BIOS-programmed watermarks untouched and hope for the best.
  12869. */
  12870. WARN(true, "Could not determine valid watermarks for inherited state\n");
  12871. goto fail;
  12872. }
  12873. /* Write calculated watermark values back */
  12874. to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
  12875. for_each_crtc_in_state(state, crtc, cstate, i) {
  12876. struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
  12877. cs->wm.need_postvbl_update = true;
  12878. dev_priv->display.optimize_watermarks(cs);
  12879. }
  12880. drm_atomic_state_free(state);
  12881. fail:
  12882. drm_modeset_drop_locks(&ctx);
  12883. drm_modeset_acquire_fini(&ctx);
  12884. }
  12885. void intel_modeset_init(struct drm_device *dev)
  12886. {
  12887. struct drm_i915_private *dev_priv = to_i915(dev);
  12888. struct i915_ggtt *ggtt = &dev_priv->ggtt;
  12889. int sprite, ret;
  12890. enum pipe pipe;
  12891. struct intel_crtc *crtc;
  12892. drm_mode_config_init(dev);
  12893. dev->mode_config.min_width = 0;
  12894. dev->mode_config.min_height = 0;
  12895. dev->mode_config.preferred_depth = 24;
  12896. dev->mode_config.prefer_shadow = 1;
  12897. dev->mode_config.allow_fb_modifiers = true;
  12898. dev->mode_config.funcs = &intel_mode_funcs;
  12899. intel_init_quirks(dev);
  12900. intel_init_pm(dev);
  12901. if (INTEL_INFO(dev)->num_pipes == 0)
  12902. return;
  12903. /*
  12904. * There may be no VBT; and if the BIOS enabled SSC we can
  12905. * just keep using it to avoid unnecessary flicker. Whereas if the
  12906. * BIOS isn't using it, don't assume it will work even if the VBT
  12907. * indicates as much.
  12908. */
  12909. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  12910. bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
  12911. DREF_SSC1_ENABLE);
  12912. if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
  12913. DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
  12914. bios_lvds_use_ssc ? "en" : "dis",
  12915. dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
  12916. dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
  12917. }
  12918. }
  12919. if (IS_GEN2(dev)) {
  12920. dev->mode_config.max_width = 2048;
  12921. dev->mode_config.max_height = 2048;
  12922. } else if (IS_GEN3(dev)) {
  12923. dev->mode_config.max_width = 4096;
  12924. dev->mode_config.max_height = 4096;
  12925. } else {
  12926. dev->mode_config.max_width = 8192;
  12927. dev->mode_config.max_height = 8192;
  12928. }
  12929. if (IS_845G(dev) || IS_I865G(dev)) {
  12930. dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
  12931. dev->mode_config.cursor_height = 1023;
  12932. } else if (IS_GEN2(dev)) {
  12933. dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
  12934. dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
  12935. } else {
  12936. dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
  12937. dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
  12938. }
  12939. dev->mode_config.fb_base = ggtt->mappable_base;
  12940. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  12941. INTEL_INFO(dev)->num_pipes,
  12942. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  12943. for_each_pipe(dev_priv, pipe) {
  12944. intel_crtc_init(dev, pipe);
  12945. for_each_sprite(dev_priv, pipe, sprite) {
  12946. ret = intel_plane_init(dev, pipe, sprite);
  12947. if (ret)
  12948. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  12949. pipe_name(pipe), sprite_name(pipe, sprite), ret);
  12950. }
  12951. }
  12952. intel_update_czclk(dev_priv);
  12953. intel_update_cdclk(dev);
  12954. intel_shared_dpll_init(dev);
  12955. /* Just disable it once at startup */
  12956. i915_disable_vga(dev);
  12957. intel_setup_outputs(dev);
  12958. drm_modeset_lock_all(dev);
  12959. intel_modeset_setup_hw_state(dev);
  12960. drm_modeset_unlock_all(dev);
  12961. for_each_intel_crtc(dev, crtc) {
  12962. struct intel_initial_plane_config plane_config = {};
  12963. if (!crtc->active)
  12964. continue;
  12965. /*
  12966. * Note that reserving the BIOS fb up front prevents us
  12967. * from stuffing other stolen allocations like the ring
  12968. * on top. This prevents some ugliness at boot time, and
  12969. * can even allow for smooth boot transitions if the BIOS
  12970. * fb is large enough for the active pipe configuration.
  12971. */
  12972. dev_priv->display.get_initial_plane_config(crtc,
  12973. &plane_config);
  12974. /*
  12975. * If the fb is shared between multiple heads, we'll
  12976. * just get the first one.
  12977. */
  12978. intel_find_initial_plane_obj(crtc, &plane_config);
  12979. }
  12980. /*
  12981. * Make sure hardware watermarks really match the state we read out.
  12982. * Note that we need to do this after reconstructing the BIOS fb's
  12983. * since the watermark calculation done here will use pstate->fb.
  12984. */
  12985. sanitize_watermarks(dev);
  12986. }
  12987. static void intel_enable_pipe_a(struct drm_device *dev)
  12988. {
  12989. struct intel_connector *connector;
  12990. struct drm_connector *crt = NULL;
  12991. struct intel_load_detect_pipe load_detect_temp;
  12992. struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
  12993. /* We can't just switch on the pipe A, we need to set things up with a
  12994. * proper mode and output configuration. As a gross hack, enable pipe A
  12995. * by enabling the load detect pipe once. */
  12996. for_each_intel_connector(dev, connector) {
  12997. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  12998. crt = &connector->base;
  12999. break;
  13000. }
  13001. }
  13002. if (!crt)
  13003. return;
  13004. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
  13005. intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
  13006. }
  13007. static bool
  13008. intel_check_plane_mapping(struct intel_crtc *crtc)
  13009. {
  13010. struct drm_device *dev = crtc->base.dev;
  13011. struct drm_i915_private *dev_priv = dev->dev_private;
  13012. u32 val;
  13013. if (INTEL_INFO(dev)->num_pipes == 1)
  13014. return true;
  13015. val = I915_READ(DSPCNTR(!crtc->plane));
  13016. if ((val & DISPLAY_PLANE_ENABLE) &&
  13017. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  13018. return false;
  13019. return true;
  13020. }
  13021. static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
  13022. {
  13023. struct drm_device *dev = crtc->base.dev;
  13024. struct intel_encoder *encoder;
  13025. for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  13026. return true;
  13027. return false;
  13028. }
  13029. static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
  13030. {
  13031. struct drm_device *dev = encoder->base.dev;
  13032. struct intel_connector *connector;
  13033. for_each_connector_on_encoder(dev, &encoder->base, connector)
  13034. return true;
  13035. return false;
  13036. }
  13037. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  13038. {
  13039. struct drm_device *dev = crtc->base.dev;
  13040. struct drm_i915_private *dev_priv = dev->dev_private;
  13041. enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  13042. /* Clear any frame start delays used for debugging left by the BIOS */
  13043. if (!transcoder_is_dsi(cpu_transcoder)) {
  13044. i915_reg_t reg = PIPECONF(cpu_transcoder);
  13045. I915_WRITE(reg,
  13046. I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  13047. }
  13048. /* restore vblank interrupts to correct state */
  13049. drm_crtc_vblank_reset(&crtc->base);
  13050. if (crtc->active) {
  13051. struct intel_plane *plane;
  13052. drm_crtc_vblank_on(&crtc->base);
  13053. /* Disable everything but the primary plane */
  13054. for_each_intel_plane_on_crtc(dev, crtc, plane) {
  13055. if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
  13056. continue;
  13057. plane->disable_plane(&plane->base, &crtc->base);
  13058. }
  13059. }
  13060. /* We need to sanitize the plane -> pipe mapping first because this will
  13061. * disable the crtc (and hence change the state) if it is wrong. Note
  13062. * that gen4+ has a fixed plane -> pipe mapping. */
  13063. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  13064. bool plane;
  13065. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  13066. crtc->base.base.id);
  13067. /* Pipe has the wrong plane attached and the plane is active.
  13068. * Temporarily change the plane mapping and disable everything
  13069. * ... */
  13070. plane = crtc->plane;
  13071. to_intel_plane_state(crtc->base.primary->state)->visible = true;
  13072. crtc->plane = !plane;
  13073. intel_crtc_disable_noatomic(&crtc->base);
  13074. crtc->plane = plane;
  13075. }
  13076. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  13077. crtc->pipe == PIPE_A && !crtc->active) {
  13078. /* BIOS forgot to enable pipe A, this mostly happens after
  13079. * resume. Force-enable the pipe to fix this, the update_dpms
  13080. * call below we restore the pipe to the right state, but leave
  13081. * the required bits on. */
  13082. intel_enable_pipe_a(dev);
  13083. }
  13084. /* Adjust the state of the output pipe according to whether we
  13085. * have active connectors/encoders. */
  13086. if (crtc->active && !intel_crtc_has_encoders(crtc))
  13087. intel_crtc_disable_noatomic(&crtc->base);
  13088. if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
  13089. /*
  13090. * We start out with underrun reporting disabled to avoid races.
  13091. * For correct bookkeeping mark this on active crtcs.
  13092. *
  13093. * Also on gmch platforms we dont have any hardware bits to
  13094. * disable the underrun reporting. Which means we need to start
  13095. * out with underrun reporting disabled also on inactive pipes,
  13096. * since otherwise we'll complain about the garbage we read when
  13097. * e.g. coming up after runtime pm.
  13098. *
  13099. * No protection against concurrent access is required - at
  13100. * worst a fifo underrun happens which also sets this to false.
  13101. */
  13102. crtc->cpu_fifo_underrun_disabled = true;
  13103. crtc->pch_fifo_underrun_disabled = true;
  13104. }
  13105. }
  13106. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  13107. {
  13108. struct intel_connector *connector;
  13109. struct drm_device *dev = encoder->base.dev;
  13110. /* We need to check both for a crtc link (meaning that the
  13111. * encoder is active and trying to read from a pipe) and the
  13112. * pipe itself being active. */
  13113. bool has_active_crtc = encoder->base.crtc &&
  13114. to_intel_crtc(encoder->base.crtc)->active;
  13115. if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
  13116. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  13117. encoder->base.base.id,
  13118. encoder->base.name);
  13119. /* Connector is active, but has no active pipe. This is
  13120. * fallout from our resume register restoring. Disable
  13121. * the encoder manually again. */
  13122. if (encoder->base.crtc) {
  13123. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  13124. encoder->base.base.id,
  13125. encoder->base.name);
  13126. encoder->disable(encoder);
  13127. if (encoder->post_disable)
  13128. encoder->post_disable(encoder);
  13129. }
  13130. encoder->base.crtc = NULL;
  13131. /* Inconsistent output/port/pipe state happens presumably due to
  13132. * a bug in one of the get_hw_state functions. Or someplace else
  13133. * in our code, like the register restore mess on resume. Clamp
  13134. * things to off as a safer default. */
  13135. for_each_intel_connector(dev, connector) {
  13136. if (connector->encoder != encoder)
  13137. continue;
  13138. connector->base.dpms = DRM_MODE_DPMS_OFF;
  13139. connector->base.encoder = NULL;
  13140. }
  13141. }
  13142. /* Enabled encoders without active connectors will be fixed in
  13143. * the crtc fixup. */
  13144. }
  13145. void i915_redisable_vga_power_on(struct drm_device *dev)
  13146. {
  13147. struct drm_i915_private *dev_priv = dev->dev_private;
  13148. i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
  13149. if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
  13150. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  13151. i915_disable_vga(dev);
  13152. }
  13153. }
  13154. void i915_redisable_vga(struct drm_device *dev)
  13155. {
  13156. struct drm_i915_private *dev_priv = dev->dev_private;
  13157. /* This function can be called both from intel_modeset_setup_hw_state or
  13158. * at a very early point in our resume sequence, where the power well
  13159. * structures are not yet restored. Since this function is at a very
  13160. * paranoid "someone might have enabled VGA while we were not looking"
  13161. * level, just check if the power well is enabled instead of trying to
  13162. * follow the "don't touch the power well if we don't need it" policy
  13163. * the rest of the driver uses. */
  13164. if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
  13165. return;
  13166. i915_redisable_vga_power_on(dev);
  13167. intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
  13168. }
  13169. static bool primary_get_hw_state(struct intel_plane *plane)
  13170. {
  13171. struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
  13172. return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
  13173. }
  13174. /* FIXME read out full plane state for all planes */
  13175. static void readout_plane_state(struct intel_crtc *crtc)
  13176. {
  13177. struct drm_plane *primary = crtc->base.primary;
  13178. struct intel_plane_state *plane_state =
  13179. to_intel_plane_state(primary->state);
  13180. plane_state->visible = crtc->active &&
  13181. primary_get_hw_state(to_intel_plane(primary));
  13182. if (plane_state->visible)
  13183. crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
  13184. }
  13185. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  13186. {
  13187. struct drm_i915_private *dev_priv = dev->dev_private;
  13188. enum pipe pipe;
  13189. struct intel_crtc *crtc;
  13190. struct intel_encoder *encoder;
  13191. struct intel_connector *connector;
  13192. int i;
  13193. dev_priv->active_crtcs = 0;
  13194. for_each_intel_crtc(dev, crtc) {
  13195. struct intel_crtc_state *crtc_state = crtc->config;
  13196. int pixclk = 0;
  13197. __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
  13198. memset(crtc_state, 0, sizeof(*crtc_state));
  13199. crtc_state->base.crtc = &crtc->base;
  13200. crtc_state->base.active = crtc_state->base.enable =
  13201. dev_priv->display.get_pipe_config(crtc, crtc_state);
  13202. crtc->base.enabled = crtc_state->base.enable;
  13203. crtc->active = crtc_state->base.active;
  13204. if (crtc_state->base.active) {
  13205. dev_priv->active_crtcs |= 1 << crtc->pipe;
  13206. if (IS_BROADWELL(dev_priv)) {
  13207. pixclk = ilk_pipe_pixel_rate(crtc_state);
  13208. /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
  13209. if (crtc_state->ips_enabled)
  13210. pixclk = DIV_ROUND_UP(pixclk * 100, 95);
  13211. } else if (IS_VALLEYVIEW(dev_priv) ||
  13212. IS_CHERRYVIEW(dev_priv) ||
  13213. IS_BROXTON(dev_priv))
  13214. pixclk = crtc_state->base.adjusted_mode.crtc_clock;
  13215. else
  13216. WARN_ON(dev_priv->display.modeset_calc_cdclk);
  13217. }
  13218. dev_priv->min_pixclk[crtc->pipe] = pixclk;
  13219. readout_plane_state(crtc);
  13220. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  13221. crtc->base.base.id,
  13222. crtc->active ? "enabled" : "disabled");
  13223. }
  13224. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  13225. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  13226. pll->on = pll->funcs.get_hw_state(dev_priv, pll,
  13227. &pll->config.hw_state);
  13228. pll->config.crtc_mask = 0;
  13229. for_each_intel_crtc(dev, crtc) {
  13230. if (crtc->active && crtc->config->shared_dpll == pll)
  13231. pll->config.crtc_mask |= 1 << crtc->pipe;
  13232. }
  13233. pll->active_mask = pll->config.crtc_mask;
  13234. DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
  13235. pll->name, pll->config.crtc_mask, pll->on);
  13236. }
  13237. for_each_intel_encoder(dev, encoder) {
  13238. pipe = 0;
  13239. if (encoder->get_hw_state(encoder, &pipe)) {
  13240. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  13241. encoder->base.crtc = &crtc->base;
  13242. encoder->get_config(encoder, crtc->config);
  13243. } else {
  13244. encoder->base.crtc = NULL;
  13245. }
  13246. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
  13247. encoder->base.base.id,
  13248. encoder->base.name,
  13249. encoder->base.crtc ? "enabled" : "disabled",
  13250. pipe_name(pipe));
  13251. }
  13252. for_each_intel_connector(dev, connector) {
  13253. if (connector->get_hw_state(connector)) {
  13254. connector->base.dpms = DRM_MODE_DPMS_ON;
  13255. encoder = connector->encoder;
  13256. connector->base.encoder = &encoder->base;
  13257. if (encoder->base.crtc &&
  13258. encoder->base.crtc->state->active) {
  13259. /*
  13260. * This has to be done during hardware readout
  13261. * because anything calling .crtc_disable may
  13262. * rely on the connector_mask being accurate.
  13263. */
  13264. encoder->base.crtc->state->connector_mask |=
  13265. 1 << drm_connector_index(&connector->base);
  13266. encoder->base.crtc->state->encoder_mask |=
  13267. 1 << drm_encoder_index(&encoder->base);
  13268. }
  13269. } else {
  13270. connector->base.dpms = DRM_MODE_DPMS_OFF;
  13271. connector->base.encoder = NULL;
  13272. }
  13273. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  13274. connector->base.base.id,
  13275. connector->base.name,
  13276. connector->base.encoder ? "enabled" : "disabled");
  13277. }
  13278. for_each_intel_crtc(dev, crtc) {
  13279. crtc->base.hwmode = crtc->config->base.adjusted_mode;
  13280. memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
  13281. if (crtc->base.state->active) {
  13282. intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
  13283. intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
  13284. WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
  13285. /*
  13286. * The initial mode needs to be set in order to keep
  13287. * the atomic core happy. It wants a valid mode if the
  13288. * crtc's enabled, so we do the above call.
  13289. *
  13290. * At this point some state updated by the connectors
  13291. * in their ->detect() callback has not run yet, so
  13292. * no recalculation can be done yet.
  13293. *
  13294. * Even if we could do a recalculation and modeset
  13295. * right now it would cause a double modeset if
  13296. * fbdev or userspace chooses a different initial mode.
  13297. *
  13298. * If that happens, someone indicated they wanted a
  13299. * mode change, which means it's safe to do a full
  13300. * recalculation.
  13301. */
  13302. crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
  13303. drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
  13304. update_scanline_offset(crtc);
  13305. }
  13306. intel_pipe_config_sanity_check(dev_priv, crtc->config);
  13307. }
  13308. }
  13309. /* Scan out the current hw modeset state,
  13310. * and sanitizes it to the current state
  13311. */
  13312. static void
  13313. intel_modeset_setup_hw_state(struct drm_device *dev)
  13314. {
  13315. struct drm_i915_private *dev_priv = dev->dev_private;
  13316. enum pipe pipe;
  13317. struct intel_crtc *crtc;
  13318. struct intel_encoder *encoder;
  13319. int i;
  13320. intel_modeset_readout_hw_state(dev);
  13321. /* HW state is read out, now we need to sanitize this mess. */
  13322. for_each_intel_encoder(dev, encoder) {
  13323. intel_sanitize_encoder(encoder);
  13324. }
  13325. for_each_pipe(dev_priv, pipe) {
  13326. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  13327. intel_sanitize_crtc(crtc);
  13328. intel_dump_pipe_config(crtc, crtc->config,
  13329. "[setup_hw_state]");
  13330. }
  13331. intel_modeset_update_connector_atomic_state(dev);
  13332. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  13333. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  13334. if (!pll->on || pll->active_mask)
  13335. continue;
  13336. DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  13337. pll->funcs.disable(dev_priv, pll);
  13338. pll->on = false;
  13339. }
  13340. if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
  13341. vlv_wm_get_hw_state(dev);
  13342. else if (IS_GEN9(dev))
  13343. skl_wm_get_hw_state(dev);
  13344. else if (HAS_PCH_SPLIT(dev))
  13345. ilk_wm_get_hw_state(dev);
  13346. for_each_intel_crtc(dev, crtc) {
  13347. unsigned long put_domains;
  13348. put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
  13349. if (WARN_ON(put_domains))
  13350. modeset_put_power_domains(dev_priv, put_domains);
  13351. }
  13352. intel_display_set_init_power(dev_priv, false);
  13353. intel_fbc_init_pipe_state(dev_priv);
  13354. }
  13355. void intel_display_resume(struct drm_device *dev)
  13356. {
  13357. struct drm_i915_private *dev_priv = to_i915(dev);
  13358. struct drm_atomic_state *state = dev_priv->modeset_restore_state;
  13359. struct drm_modeset_acquire_ctx ctx;
  13360. int ret;
  13361. bool setup = false;
  13362. dev_priv->modeset_restore_state = NULL;
  13363. /*
  13364. * This is a cludge because with real atomic modeset mode_config.mutex
  13365. * won't be taken. Unfortunately some probed state like
  13366. * audio_codec_enable is still protected by mode_config.mutex, so lock
  13367. * it here for now.
  13368. */
  13369. mutex_lock(&dev->mode_config.mutex);
  13370. drm_modeset_acquire_init(&ctx, 0);
  13371. retry:
  13372. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  13373. if (ret == 0 && !setup) {
  13374. setup = true;
  13375. intel_modeset_setup_hw_state(dev);
  13376. i915_redisable_vga(dev);
  13377. }
  13378. if (ret == 0 && state) {
  13379. struct drm_crtc_state *crtc_state;
  13380. struct drm_crtc *crtc;
  13381. int i;
  13382. state->acquire_ctx = &ctx;
  13383. for_each_crtc_in_state(state, crtc, crtc_state, i) {
  13384. /*
  13385. * Force recalculation even if we restore
  13386. * current state. With fast modeset this may not result
  13387. * in a modeset when the state is compatible.
  13388. */
  13389. crtc_state->mode_changed = true;
  13390. }
  13391. ret = drm_atomic_commit(state);
  13392. }
  13393. if (ret == -EDEADLK) {
  13394. drm_modeset_backoff(&ctx);
  13395. goto retry;
  13396. }
  13397. drm_modeset_drop_locks(&ctx);
  13398. drm_modeset_acquire_fini(&ctx);
  13399. mutex_unlock(&dev->mode_config.mutex);
  13400. if (ret) {
  13401. DRM_ERROR("Restoring old state failed with %i\n", ret);
  13402. drm_atomic_state_free(state);
  13403. }
  13404. }
  13405. void intel_modeset_gem_init(struct drm_device *dev)
  13406. {
  13407. struct drm_i915_private *dev_priv = to_i915(dev);
  13408. struct drm_crtc *c;
  13409. struct drm_i915_gem_object *obj;
  13410. int ret;
  13411. intel_init_gt_powersave(dev_priv);
  13412. intel_modeset_init_hw(dev);
  13413. intel_setup_overlay(dev_priv);
  13414. /*
  13415. * Make sure any fbs we allocated at startup are properly
  13416. * pinned & fenced. When we do the allocation it's too early
  13417. * for this.
  13418. */
  13419. for_each_crtc(dev, c) {
  13420. obj = intel_fb_obj(c->primary->fb);
  13421. if (obj == NULL)
  13422. continue;
  13423. mutex_lock(&dev->struct_mutex);
  13424. ret = intel_pin_and_fence_fb_obj(c->primary->fb,
  13425. c->primary->state->rotation);
  13426. mutex_unlock(&dev->struct_mutex);
  13427. if (ret) {
  13428. DRM_ERROR("failed to pin boot fb on pipe %d\n",
  13429. to_intel_crtc(c)->pipe);
  13430. drm_framebuffer_unreference(c->primary->fb);
  13431. c->primary->fb = NULL;
  13432. c->primary->crtc = c->primary->state->crtc = NULL;
  13433. update_state_fb(c->primary);
  13434. c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
  13435. }
  13436. }
  13437. intel_backlight_register(dev);
  13438. }
  13439. void intel_connector_unregister(struct intel_connector *intel_connector)
  13440. {
  13441. struct drm_connector *connector = &intel_connector->base;
  13442. intel_panel_destroy_backlight(connector);
  13443. drm_connector_unregister(connector);
  13444. }
  13445. void intel_modeset_cleanup(struct drm_device *dev)
  13446. {
  13447. struct drm_i915_private *dev_priv = dev->dev_private;
  13448. struct intel_connector *connector;
  13449. intel_disable_gt_powersave(dev_priv);
  13450. intel_backlight_unregister(dev);
  13451. /*
  13452. * Interrupts and polling as the first thing to avoid creating havoc.
  13453. * Too much stuff here (turning of connectors, ...) would
  13454. * experience fancy races otherwise.
  13455. */
  13456. intel_irq_uninstall(dev_priv);
  13457. /*
  13458. * Due to the hpd irq storm handling the hotplug work can re-arm the
  13459. * poll handlers. Hence disable polling after hpd handling is shut down.
  13460. */
  13461. drm_kms_helper_poll_fini(dev);
  13462. intel_unregister_dsm_handler();
  13463. intel_fbc_global_disable(dev_priv);
  13464. /* flush any delayed tasks or pending work */
  13465. flush_scheduled_work();
  13466. /* destroy the backlight and sysfs files before encoders/connectors */
  13467. for_each_intel_connector(dev, connector)
  13468. connector->unregister(connector);
  13469. drm_mode_config_cleanup(dev);
  13470. intel_cleanup_overlay(dev_priv);
  13471. intel_cleanup_gt_powersave(dev_priv);
  13472. intel_teardown_gmbus(dev);
  13473. }
  13474. /*
  13475. * Return which encoder is currently attached for connector.
  13476. */
  13477. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  13478. {
  13479. return &intel_attached_encoder(connector)->base;
  13480. }
  13481. void intel_connector_attach_encoder(struct intel_connector *connector,
  13482. struct intel_encoder *encoder)
  13483. {
  13484. connector->encoder = encoder;
  13485. drm_mode_connector_attach_encoder(&connector->base,
  13486. &encoder->base);
  13487. }
  13488. /*
  13489. * set vga decode state - true == enable VGA decode
  13490. */
  13491. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  13492. {
  13493. struct drm_i915_private *dev_priv = dev->dev_private;
  13494. unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
  13495. u16 gmch_ctrl;
  13496. if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
  13497. DRM_ERROR("failed to read control word\n");
  13498. return -EIO;
  13499. }
  13500. if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
  13501. return 0;
  13502. if (state)
  13503. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  13504. else
  13505. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  13506. if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
  13507. DRM_ERROR("failed to write control word\n");
  13508. return -EIO;
  13509. }
  13510. return 0;
  13511. }
  13512. struct intel_display_error_state {
  13513. u32 power_well_driver;
  13514. int num_transcoders;
  13515. struct intel_cursor_error_state {
  13516. u32 control;
  13517. u32 position;
  13518. u32 base;
  13519. u32 size;
  13520. } cursor[I915_MAX_PIPES];
  13521. struct intel_pipe_error_state {
  13522. bool power_domain_on;
  13523. u32 source;
  13524. u32 stat;
  13525. } pipe[I915_MAX_PIPES];
  13526. struct intel_plane_error_state {
  13527. u32 control;
  13528. u32 stride;
  13529. u32 size;
  13530. u32 pos;
  13531. u32 addr;
  13532. u32 surface;
  13533. u32 tile_offset;
  13534. } plane[I915_MAX_PIPES];
  13535. struct intel_transcoder_error_state {
  13536. bool power_domain_on;
  13537. enum transcoder cpu_transcoder;
  13538. u32 conf;
  13539. u32 htotal;
  13540. u32 hblank;
  13541. u32 hsync;
  13542. u32 vtotal;
  13543. u32 vblank;
  13544. u32 vsync;
  13545. } transcoder[4];
  13546. };
  13547. struct intel_display_error_state *
  13548. intel_display_capture_error_state(struct drm_i915_private *dev_priv)
  13549. {
  13550. struct intel_display_error_state *error;
  13551. int transcoders[] = {
  13552. TRANSCODER_A,
  13553. TRANSCODER_B,
  13554. TRANSCODER_C,
  13555. TRANSCODER_EDP,
  13556. };
  13557. int i;
  13558. if (INTEL_INFO(dev_priv)->num_pipes == 0)
  13559. return NULL;
  13560. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  13561. if (error == NULL)
  13562. return NULL;
  13563. if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  13564. error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  13565. for_each_pipe(dev_priv, i) {
  13566. error->pipe[i].power_domain_on =
  13567. __intel_display_power_is_enabled(dev_priv,
  13568. POWER_DOMAIN_PIPE(i));
  13569. if (!error->pipe[i].power_domain_on)
  13570. continue;
  13571. error->cursor[i].control = I915_READ(CURCNTR(i));
  13572. error->cursor[i].position = I915_READ(CURPOS(i));
  13573. error->cursor[i].base = I915_READ(CURBASE(i));
  13574. error->plane[i].control = I915_READ(DSPCNTR(i));
  13575. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  13576. if (INTEL_GEN(dev_priv) <= 3) {
  13577. error->plane[i].size = I915_READ(DSPSIZE(i));
  13578. error->plane[i].pos = I915_READ(DSPPOS(i));
  13579. }
  13580. if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
  13581. error->plane[i].addr = I915_READ(DSPADDR(i));
  13582. if (INTEL_GEN(dev_priv) >= 4) {
  13583. error->plane[i].surface = I915_READ(DSPSURF(i));
  13584. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  13585. }
  13586. error->pipe[i].source = I915_READ(PIPESRC(i));
  13587. if (HAS_GMCH_DISPLAY(dev_priv))
  13588. error->pipe[i].stat = I915_READ(PIPESTAT(i));
  13589. }
  13590. /* Note: this does not include DSI transcoders. */
  13591. error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
  13592. if (HAS_DDI(dev_priv))
  13593. error->num_transcoders++; /* Account for eDP. */
  13594. for (i = 0; i < error->num_transcoders; i++) {
  13595. enum transcoder cpu_transcoder = transcoders[i];
  13596. error->transcoder[i].power_domain_on =
  13597. __intel_display_power_is_enabled(dev_priv,
  13598. POWER_DOMAIN_TRANSCODER(cpu_transcoder));
  13599. if (!error->transcoder[i].power_domain_on)
  13600. continue;
  13601. error->transcoder[i].cpu_transcoder = cpu_transcoder;
  13602. error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  13603. error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  13604. error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  13605. error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  13606. error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  13607. error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  13608. error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  13609. }
  13610. return error;
  13611. }
  13612. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  13613. void
  13614. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  13615. struct drm_device *dev,
  13616. struct intel_display_error_state *error)
  13617. {
  13618. struct drm_i915_private *dev_priv = dev->dev_private;
  13619. int i;
  13620. if (!error)
  13621. return;
  13622. err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  13623. if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  13624. err_printf(m, "PWR_WELL_CTL2: %08x\n",
  13625. error->power_well_driver);
  13626. for_each_pipe(dev_priv, i) {
  13627. err_printf(m, "Pipe [%d]:\n", i);
  13628. err_printf(m, " Power: %s\n",
  13629. onoff(error->pipe[i].power_domain_on));
  13630. err_printf(m, " SRC: %08x\n", error->pipe[i].source);
  13631. err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
  13632. err_printf(m, "Plane [%d]:\n", i);
  13633. err_printf(m, " CNTR: %08x\n", error->plane[i].control);
  13634. err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  13635. if (INTEL_INFO(dev)->gen <= 3) {
  13636. err_printf(m, " SIZE: %08x\n", error->plane[i].size);
  13637. err_printf(m, " POS: %08x\n", error->plane[i].pos);
  13638. }
  13639. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  13640. err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  13641. if (INTEL_INFO(dev)->gen >= 4) {
  13642. err_printf(m, " SURF: %08x\n", error->plane[i].surface);
  13643. err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  13644. }
  13645. err_printf(m, "Cursor [%d]:\n", i);
  13646. err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  13647. err_printf(m, " POS: %08x\n", error->cursor[i].position);
  13648. err_printf(m, " BASE: %08x\n", error->cursor[i].base);
  13649. }
  13650. for (i = 0; i < error->num_transcoders; i++) {
  13651. err_printf(m, "CPU transcoder: %s\n",
  13652. transcoder_name(error->transcoder[i].cpu_transcoder));
  13653. err_printf(m, " Power: %s\n",
  13654. onoff(error->transcoder[i].power_domain_on));
  13655. err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
  13656. err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
  13657. err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
  13658. err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
  13659. err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
  13660. err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
  13661. err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
  13662. }
  13663. }