drm.c 32 KB

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  1. /*
  2. * Copyright (C) 2012 Avionic Design GmbH
  3. * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/bitops.h>
  10. #include <linux/host1x.h>
  11. #include <linux/idr.h>
  12. #include <linux/iommu.h>
  13. #include <drm/drm_atomic.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include "drm.h"
  16. #include "gem.h"
  17. #define DRIVER_NAME "tegra"
  18. #define DRIVER_DESC "NVIDIA Tegra graphics"
  19. #define DRIVER_DATE "20120330"
  20. #define DRIVER_MAJOR 0
  21. #define DRIVER_MINOR 0
  22. #define DRIVER_PATCHLEVEL 0
  23. #define CARVEOUT_SZ SZ_64M
  24. #define CDMA_GATHER_FETCHES_MAX_NB 16383
  25. struct tegra_drm_file {
  26. struct idr contexts;
  27. struct mutex lock;
  28. };
  29. static void tegra_atomic_schedule(struct tegra_drm *tegra,
  30. struct drm_atomic_state *state)
  31. {
  32. tegra->commit.state = state;
  33. schedule_work(&tegra->commit.work);
  34. }
  35. static void tegra_atomic_complete(struct tegra_drm *tegra,
  36. struct drm_atomic_state *state)
  37. {
  38. struct drm_device *drm = tegra->drm;
  39. /*
  40. * Everything below can be run asynchronously without the need to grab
  41. * any modeset locks at all under one condition: It must be guaranteed
  42. * that the asynchronous work has either been cancelled (if the driver
  43. * supports it, which at least requires that the framebuffers get
  44. * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
  45. * before the new state gets committed on the software side with
  46. * drm_atomic_helper_swap_state().
  47. *
  48. * This scheme allows new atomic state updates to be prepared and
  49. * checked in parallel to the asynchronous completion of the previous
  50. * update. Which is important since compositors need to figure out the
  51. * composition of the next frame right after having submitted the
  52. * current layout.
  53. */
  54. drm_atomic_helper_commit_modeset_disables(drm, state);
  55. drm_atomic_helper_commit_modeset_enables(drm, state);
  56. drm_atomic_helper_commit_planes(drm, state,
  57. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  58. drm_atomic_helper_wait_for_vblanks(drm, state);
  59. drm_atomic_helper_cleanup_planes(drm, state);
  60. drm_atomic_state_put(state);
  61. }
  62. static void tegra_atomic_work(struct work_struct *work)
  63. {
  64. struct tegra_drm *tegra = container_of(work, struct tegra_drm,
  65. commit.work);
  66. tegra_atomic_complete(tegra, tegra->commit.state);
  67. }
  68. static int tegra_atomic_commit(struct drm_device *drm,
  69. struct drm_atomic_state *state, bool nonblock)
  70. {
  71. struct tegra_drm *tegra = drm->dev_private;
  72. int err;
  73. err = drm_atomic_helper_prepare_planes(drm, state);
  74. if (err)
  75. return err;
  76. /* serialize outstanding nonblocking commits */
  77. mutex_lock(&tegra->commit.lock);
  78. flush_work(&tegra->commit.work);
  79. /*
  80. * This is the point of no return - everything below never fails except
  81. * when the hw goes bonghits. Which means we can commit the new state on
  82. * the software side now.
  83. */
  84. err = drm_atomic_helper_swap_state(state, true);
  85. if (err) {
  86. mutex_unlock(&tegra->commit.lock);
  87. drm_atomic_helper_cleanup_planes(drm, state);
  88. return err;
  89. }
  90. drm_atomic_state_get(state);
  91. if (nonblock)
  92. tegra_atomic_schedule(tegra, state);
  93. else
  94. tegra_atomic_complete(tegra, state);
  95. mutex_unlock(&tegra->commit.lock);
  96. return 0;
  97. }
  98. static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
  99. .fb_create = tegra_fb_create,
  100. #ifdef CONFIG_DRM_FBDEV_EMULATION
  101. .output_poll_changed = tegra_fb_output_poll_changed,
  102. #endif
  103. .atomic_check = drm_atomic_helper_check,
  104. .atomic_commit = tegra_atomic_commit,
  105. };
  106. static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
  107. {
  108. struct host1x_device *device = to_host1x_device(drm->dev);
  109. struct tegra_drm *tegra;
  110. int err;
  111. tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
  112. if (!tegra)
  113. return -ENOMEM;
  114. if (iommu_present(&platform_bus_type)) {
  115. u64 carveout_start, carveout_end, gem_start, gem_end;
  116. struct iommu_domain_geometry *geometry;
  117. unsigned long order;
  118. tegra->domain = iommu_domain_alloc(&platform_bus_type);
  119. if (!tegra->domain) {
  120. err = -ENOMEM;
  121. goto free;
  122. }
  123. geometry = &tegra->domain->geometry;
  124. gem_start = geometry->aperture_start;
  125. gem_end = geometry->aperture_end - CARVEOUT_SZ;
  126. carveout_start = gem_end + 1;
  127. carveout_end = geometry->aperture_end;
  128. order = __ffs(tegra->domain->pgsize_bitmap);
  129. init_iova_domain(&tegra->carveout.domain, 1UL << order,
  130. carveout_start >> order);
  131. tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
  132. tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
  133. drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
  134. mutex_init(&tegra->mm_lock);
  135. DRM_DEBUG("IOMMU apertures:\n");
  136. DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
  137. DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
  138. carveout_end);
  139. }
  140. mutex_init(&tegra->clients_lock);
  141. INIT_LIST_HEAD(&tegra->clients);
  142. mutex_init(&tegra->commit.lock);
  143. INIT_WORK(&tegra->commit.work, tegra_atomic_work);
  144. drm->dev_private = tegra;
  145. tegra->drm = drm;
  146. drm_mode_config_init(drm);
  147. drm->mode_config.min_width = 0;
  148. drm->mode_config.min_height = 0;
  149. drm->mode_config.max_width = 4096;
  150. drm->mode_config.max_height = 4096;
  151. drm->mode_config.allow_fb_modifiers = true;
  152. drm->mode_config.funcs = &tegra_drm_mode_funcs;
  153. err = tegra_drm_fb_prepare(drm);
  154. if (err < 0)
  155. goto config;
  156. drm_kms_helper_poll_init(drm);
  157. err = host1x_device_init(device);
  158. if (err < 0)
  159. goto fbdev;
  160. /*
  161. * We don't use the drm_irq_install() helpers provided by the DRM
  162. * core, so we need to set this manually in order to allow the
  163. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  164. */
  165. drm->irq_enabled = true;
  166. /* syncpoints are used for full 32-bit hardware VBLANK counters */
  167. drm->max_vblank_count = 0xffffffff;
  168. err = drm_vblank_init(drm, drm->mode_config.num_crtc);
  169. if (err < 0)
  170. goto device;
  171. drm_mode_config_reset(drm);
  172. err = tegra_drm_fb_init(drm);
  173. if (err < 0)
  174. goto device;
  175. return 0;
  176. device:
  177. host1x_device_exit(device);
  178. fbdev:
  179. drm_kms_helper_poll_fini(drm);
  180. tegra_drm_fb_free(drm);
  181. config:
  182. drm_mode_config_cleanup(drm);
  183. if (tegra->domain) {
  184. iommu_domain_free(tegra->domain);
  185. drm_mm_takedown(&tegra->mm);
  186. mutex_destroy(&tegra->mm_lock);
  187. put_iova_domain(&tegra->carveout.domain);
  188. }
  189. free:
  190. kfree(tegra);
  191. return err;
  192. }
  193. static void tegra_drm_unload(struct drm_device *drm)
  194. {
  195. struct host1x_device *device = to_host1x_device(drm->dev);
  196. struct tegra_drm *tegra = drm->dev_private;
  197. int err;
  198. drm_kms_helper_poll_fini(drm);
  199. tegra_drm_fb_exit(drm);
  200. drm_mode_config_cleanup(drm);
  201. err = host1x_device_exit(device);
  202. if (err < 0)
  203. return;
  204. if (tegra->domain) {
  205. iommu_domain_free(tegra->domain);
  206. drm_mm_takedown(&tegra->mm);
  207. mutex_destroy(&tegra->mm_lock);
  208. put_iova_domain(&tegra->carveout.domain);
  209. }
  210. kfree(tegra);
  211. }
  212. static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
  213. {
  214. struct tegra_drm_file *fpriv;
  215. fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
  216. if (!fpriv)
  217. return -ENOMEM;
  218. idr_init(&fpriv->contexts);
  219. mutex_init(&fpriv->lock);
  220. filp->driver_priv = fpriv;
  221. return 0;
  222. }
  223. static void tegra_drm_context_free(struct tegra_drm_context *context)
  224. {
  225. context->client->ops->close_channel(context);
  226. kfree(context);
  227. }
  228. static void tegra_drm_lastclose(struct drm_device *drm)
  229. {
  230. #ifdef CONFIG_DRM_FBDEV_EMULATION
  231. struct tegra_drm *tegra = drm->dev_private;
  232. tegra_fbdev_restore_mode(tegra->fbdev);
  233. #endif
  234. }
  235. static struct host1x_bo *
  236. host1x_bo_lookup(struct drm_file *file, u32 handle)
  237. {
  238. struct drm_gem_object *gem;
  239. struct tegra_bo *bo;
  240. gem = drm_gem_object_lookup(file, handle);
  241. if (!gem)
  242. return NULL;
  243. bo = to_tegra_bo(gem);
  244. return &bo->base;
  245. }
  246. static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
  247. struct drm_tegra_reloc __user *src,
  248. struct drm_device *drm,
  249. struct drm_file *file)
  250. {
  251. u32 cmdbuf, target;
  252. int err;
  253. err = get_user(cmdbuf, &src->cmdbuf.handle);
  254. if (err < 0)
  255. return err;
  256. err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
  257. if (err < 0)
  258. return err;
  259. err = get_user(target, &src->target.handle);
  260. if (err < 0)
  261. return err;
  262. err = get_user(dest->target.offset, &src->target.offset);
  263. if (err < 0)
  264. return err;
  265. err = get_user(dest->shift, &src->shift);
  266. if (err < 0)
  267. return err;
  268. dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
  269. if (!dest->cmdbuf.bo)
  270. return -ENOENT;
  271. dest->target.bo = host1x_bo_lookup(file, target);
  272. if (!dest->target.bo)
  273. return -ENOENT;
  274. return 0;
  275. }
  276. static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
  277. struct drm_tegra_waitchk __user *src,
  278. struct drm_file *file)
  279. {
  280. u32 cmdbuf;
  281. int err;
  282. err = get_user(cmdbuf, &src->handle);
  283. if (err < 0)
  284. return err;
  285. err = get_user(dest->offset, &src->offset);
  286. if (err < 0)
  287. return err;
  288. err = get_user(dest->syncpt_id, &src->syncpt);
  289. if (err < 0)
  290. return err;
  291. err = get_user(dest->thresh, &src->thresh);
  292. if (err < 0)
  293. return err;
  294. dest->bo = host1x_bo_lookup(file, cmdbuf);
  295. if (!dest->bo)
  296. return -ENOENT;
  297. return 0;
  298. }
  299. int tegra_drm_submit(struct tegra_drm_context *context,
  300. struct drm_tegra_submit *args, struct drm_device *drm,
  301. struct drm_file *file)
  302. {
  303. unsigned int num_cmdbufs = args->num_cmdbufs;
  304. unsigned int num_relocs = args->num_relocs;
  305. unsigned int num_waitchks = args->num_waitchks;
  306. struct drm_tegra_cmdbuf __user *cmdbufs =
  307. (void __user *)(uintptr_t)args->cmdbufs;
  308. struct drm_tegra_reloc __user *relocs =
  309. (void __user *)(uintptr_t)args->relocs;
  310. struct drm_tegra_waitchk __user *waitchks =
  311. (void __user *)(uintptr_t)args->waitchks;
  312. struct drm_tegra_syncpt syncpt;
  313. struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
  314. struct drm_gem_object **refs;
  315. struct host1x_syncpt *sp;
  316. struct host1x_job *job;
  317. unsigned int num_refs;
  318. int err;
  319. /* We don't yet support other than one syncpt_incr struct per submit */
  320. if (args->num_syncpts != 1)
  321. return -EINVAL;
  322. /* We don't yet support waitchks */
  323. if (args->num_waitchks != 0)
  324. return -EINVAL;
  325. job = host1x_job_alloc(context->channel, args->num_cmdbufs,
  326. args->num_relocs, args->num_waitchks);
  327. if (!job)
  328. return -ENOMEM;
  329. job->num_relocs = args->num_relocs;
  330. job->num_waitchk = args->num_waitchks;
  331. job->client = (u32)args->context;
  332. job->class = context->client->base.class;
  333. job->serialize = true;
  334. /*
  335. * Track referenced BOs so that they can be unreferenced after the
  336. * submission is complete.
  337. */
  338. num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks;
  339. refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
  340. if (!refs) {
  341. err = -ENOMEM;
  342. goto put;
  343. }
  344. /* reuse as an iterator later */
  345. num_refs = 0;
  346. while (num_cmdbufs) {
  347. struct drm_tegra_cmdbuf cmdbuf;
  348. struct host1x_bo *bo;
  349. struct tegra_bo *obj;
  350. u64 offset;
  351. if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
  352. err = -EFAULT;
  353. goto fail;
  354. }
  355. /*
  356. * The maximum number of CDMA gather fetches is 16383, a higher
  357. * value means the words count is malformed.
  358. */
  359. if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
  360. err = -EINVAL;
  361. goto fail;
  362. }
  363. bo = host1x_bo_lookup(file, cmdbuf.handle);
  364. if (!bo) {
  365. err = -ENOENT;
  366. goto fail;
  367. }
  368. offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
  369. obj = host1x_to_tegra_bo(bo);
  370. refs[num_refs++] = &obj->gem;
  371. /*
  372. * Gather buffer base address must be 4-bytes aligned,
  373. * unaligned offset is malformed and cause commands stream
  374. * corruption on the buffer address relocation.
  375. */
  376. if (offset & 3 || offset >= obj->gem.size) {
  377. err = -EINVAL;
  378. goto fail;
  379. }
  380. host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
  381. num_cmdbufs--;
  382. cmdbufs++;
  383. }
  384. /* copy and resolve relocations from submit */
  385. while (num_relocs--) {
  386. struct host1x_reloc *reloc;
  387. struct tegra_bo *obj;
  388. err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
  389. &relocs[num_relocs], drm,
  390. file);
  391. if (err < 0)
  392. goto fail;
  393. reloc = &job->relocarray[num_relocs];
  394. obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
  395. refs[num_refs++] = &obj->gem;
  396. /*
  397. * The unaligned cmdbuf offset will cause an unaligned write
  398. * during of the relocations patching, corrupting the commands
  399. * stream.
  400. */
  401. if (reloc->cmdbuf.offset & 3 ||
  402. reloc->cmdbuf.offset >= obj->gem.size) {
  403. err = -EINVAL;
  404. goto fail;
  405. }
  406. obj = host1x_to_tegra_bo(reloc->target.bo);
  407. refs[num_refs++] = &obj->gem;
  408. if (reloc->target.offset >= obj->gem.size) {
  409. err = -EINVAL;
  410. goto fail;
  411. }
  412. }
  413. /* copy and resolve waitchks from submit */
  414. while (num_waitchks--) {
  415. struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
  416. struct tegra_bo *obj;
  417. err = host1x_waitchk_copy_from_user(wait,
  418. &waitchks[num_waitchks],
  419. file);
  420. if (err < 0)
  421. goto fail;
  422. obj = host1x_to_tegra_bo(wait->bo);
  423. refs[num_refs++] = &obj->gem;
  424. /*
  425. * The unaligned offset will cause an unaligned write during
  426. * of the waitchks patching, corrupting the commands stream.
  427. */
  428. if (wait->offset & 3 ||
  429. wait->offset >= obj->gem.size) {
  430. err = -EINVAL;
  431. goto fail;
  432. }
  433. }
  434. if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
  435. sizeof(syncpt))) {
  436. err = -EFAULT;
  437. goto fail;
  438. }
  439. /* check whether syncpoint ID is valid */
  440. sp = host1x_syncpt_get(host1x, syncpt.id);
  441. if (!sp) {
  442. err = -ENOENT;
  443. goto fail;
  444. }
  445. job->is_addr_reg = context->client->ops->is_addr_reg;
  446. job->is_valid_class = context->client->ops->is_valid_class;
  447. job->syncpt_incrs = syncpt.incrs;
  448. job->syncpt_id = syncpt.id;
  449. job->timeout = 10000;
  450. if (args->timeout && args->timeout < 10000)
  451. job->timeout = args->timeout;
  452. err = host1x_job_pin(job, context->client->base.dev);
  453. if (err)
  454. goto fail;
  455. err = host1x_job_submit(job);
  456. if (err) {
  457. host1x_job_unpin(job);
  458. goto fail;
  459. }
  460. args->fence = job->syncpt_end;
  461. fail:
  462. while (num_refs--)
  463. drm_gem_object_put_unlocked(refs[num_refs]);
  464. kfree(refs);
  465. put:
  466. host1x_job_put(job);
  467. return err;
  468. }
  469. #ifdef CONFIG_DRM_TEGRA_STAGING
  470. static int tegra_gem_create(struct drm_device *drm, void *data,
  471. struct drm_file *file)
  472. {
  473. struct drm_tegra_gem_create *args = data;
  474. struct tegra_bo *bo;
  475. bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
  476. &args->handle);
  477. if (IS_ERR(bo))
  478. return PTR_ERR(bo);
  479. return 0;
  480. }
  481. static int tegra_gem_mmap(struct drm_device *drm, void *data,
  482. struct drm_file *file)
  483. {
  484. struct drm_tegra_gem_mmap *args = data;
  485. struct drm_gem_object *gem;
  486. struct tegra_bo *bo;
  487. gem = drm_gem_object_lookup(file, args->handle);
  488. if (!gem)
  489. return -EINVAL;
  490. bo = to_tegra_bo(gem);
  491. args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
  492. drm_gem_object_put_unlocked(gem);
  493. return 0;
  494. }
  495. static int tegra_syncpt_read(struct drm_device *drm, void *data,
  496. struct drm_file *file)
  497. {
  498. struct host1x *host = dev_get_drvdata(drm->dev->parent);
  499. struct drm_tegra_syncpt_read *args = data;
  500. struct host1x_syncpt *sp;
  501. sp = host1x_syncpt_get(host, args->id);
  502. if (!sp)
  503. return -EINVAL;
  504. args->value = host1x_syncpt_read_min(sp);
  505. return 0;
  506. }
  507. static int tegra_syncpt_incr(struct drm_device *drm, void *data,
  508. struct drm_file *file)
  509. {
  510. struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
  511. struct drm_tegra_syncpt_incr *args = data;
  512. struct host1x_syncpt *sp;
  513. sp = host1x_syncpt_get(host1x, args->id);
  514. if (!sp)
  515. return -EINVAL;
  516. return host1x_syncpt_incr(sp);
  517. }
  518. static int tegra_syncpt_wait(struct drm_device *drm, void *data,
  519. struct drm_file *file)
  520. {
  521. struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
  522. struct drm_tegra_syncpt_wait *args = data;
  523. struct host1x_syncpt *sp;
  524. sp = host1x_syncpt_get(host1x, args->id);
  525. if (!sp)
  526. return -EINVAL;
  527. return host1x_syncpt_wait(sp, args->thresh, args->timeout,
  528. &args->value);
  529. }
  530. static int tegra_client_open(struct tegra_drm_file *fpriv,
  531. struct tegra_drm_client *client,
  532. struct tegra_drm_context *context)
  533. {
  534. int err;
  535. err = client->ops->open_channel(client, context);
  536. if (err < 0)
  537. return err;
  538. err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
  539. if (err < 0) {
  540. client->ops->close_channel(context);
  541. return err;
  542. }
  543. context->client = client;
  544. context->id = err;
  545. return 0;
  546. }
  547. static int tegra_open_channel(struct drm_device *drm, void *data,
  548. struct drm_file *file)
  549. {
  550. struct tegra_drm_file *fpriv = file->driver_priv;
  551. struct tegra_drm *tegra = drm->dev_private;
  552. struct drm_tegra_open_channel *args = data;
  553. struct tegra_drm_context *context;
  554. struct tegra_drm_client *client;
  555. int err = -ENODEV;
  556. context = kzalloc(sizeof(*context), GFP_KERNEL);
  557. if (!context)
  558. return -ENOMEM;
  559. mutex_lock(&fpriv->lock);
  560. list_for_each_entry(client, &tegra->clients, list)
  561. if (client->base.class == args->client) {
  562. err = tegra_client_open(fpriv, client, context);
  563. if (err < 0)
  564. break;
  565. args->context = context->id;
  566. break;
  567. }
  568. if (err < 0)
  569. kfree(context);
  570. mutex_unlock(&fpriv->lock);
  571. return err;
  572. }
  573. static int tegra_close_channel(struct drm_device *drm, void *data,
  574. struct drm_file *file)
  575. {
  576. struct tegra_drm_file *fpriv = file->driver_priv;
  577. struct drm_tegra_close_channel *args = data;
  578. struct tegra_drm_context *context;
  579. int err = 0;
  580. mutex_lock(&fpriv->lock);
  581. context = idr_find(&fpriv->contexts, args->context);
  582. if (!context) {
  583. err = -EINVAL;
  584. goto unlock;
  585. }
  586. idr_remove(&fpriv->contexts, context->id);
  587. tegra_drm_context_free(context);
  588. unlock:
  589. mutex_unlock(&fpriv->lock);
  590. return err;
  591. }
  592. static int tegra_get_syncpt(struct drm_device *drm, void *data,
  593. struct drm_file *file)
  594. {
  595. struct tegra_drm_file *fpriv = file->driver_priv;
  596. struct drm_tegra_get_syncpt *args = data;
  597. struct tegra_drm_context *context;
  598. struct host1x_syncpt *syncpt;
  599. int err = 0;
  600. mutex_lock(&fpriv->lock);
  601. context = idr_find(&fpriv->contexts, args->context);
  602. if (!context) {
  603. err = -ENODEV;
  604. goto unlock;
  605. }
  606. if (args->index >= context->client->base.num_syncpts) {
  607. err = -EINVAL;
  608. goto unlock;
  609. }
  610. syncpt = context->client->base.syncpts[args->index];
  611. args->id = host1x_syncpt_id(syncpt);
  612. unlock:
  613. mutex_unlock(&fpriv->lock);
  614. return err;
  615. }
  616. static int tegra_submit(struct drm_device *drm, void *data,
  617. struct drm_file *file)
  618. {
  619. struct tegra_drm_file *fpriv = file->driver_priv;
  620. struct drm_tegra_submit *args = data;
  621. struct tegra_drm_context *context;
  622. int err;
  623. mutex_lock(&fpriv->lock);
  624. context = idr_find(&fpriv->contexts, args->context);
  625. if (!context) {
  626. err = -ENODEV;
  627. goto unlock;
  628. }
  629. err = context->client->ops->submit(context, args, drm, file);
  630. unlock:
  631. mutex_unlock(&fpriv->lock);
  632. return err;
  633. }
  634. static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
  635. struct drm_file *file)
  636. {
  637. struct tegra_drm_file *fpriv = file->driver_priv;
  638. struct drm_tegra_get_syncpt_base *args = data;
  639. struct tegra_drm_context *context;
  640. struct host1x_syncpt_base *base;
  641. struct host1x_syncpt *syncpt;
  642. int err = 0;
  643. mutex_lock(&fpriv->lock);
  644. context = idr_find(&fpriv->contexts, args->context);
  645. if (!context) {
  646. err = -ENODEV;
  647. goto unlock;
  648. }
  649. if (args->syncpt >= context->client->base.num_syncpts) {
  650. err = -EINVAL;
  651. goto unlock;
  652. }
  653. syncpt = context->client->base.syncpts[args->syncpt];
  654. base = host1x_syncpt_get_base(syncpt);
  655. if (!base) {
  656. err = -ENXIO;
  657. goto unlock;
  658. }
  659. args->id = host1x_syncpt_base_id(base);
  660. unlock:
  661. mutex_unlock(&fpriv->lock);
  662. return err;
  663. }
  664. static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
  665. struct drm_file *file)
  666. {
  667. struct drm_tegra_gem_set_tiling *args = data;
  668. enum tegra_bo_tiling_mode mode;
  669. struct drm_gem_object *gem;
  670. unsigned long value = 0;
  671. struct tegra_bo *bo;
  672. switch (args->mode) {
  673. case DRM_TEGRA_GEM_TILING_MODE_PITCH:
  674. mode = TEGRA_BO_TILING_MODE_PITCH;
  675. if (args->value != 0)
  676. return -EINVAL;
  677. break;
  678. case DRM_TEGRA_GEM_TILING_MODE_TILED:
  679. mode = TEGRA_BO_TILING_MODE_TILED;
  680. if (args->value != 0)
  681. return -EINVAL;
  682. break;
  683. case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
  684. mode = TEGRA_BO_TILING_MODE_BLOCK;
  685. if (args->value > 5)
  686. return -EINVAL;
  687. value = args->value;
  688. break;
  689. default:
  690. return -EINVAL;
  691. }
  692. gem = drm_gem_object_lookup(file, args->handle);
  693. if (!gem)
  694. return -ENOENT;
  695. bo = to_tegra_bo(gem);
  696. bo->tiling.mode = mode;
  697. bo->tiling.value = value;
  698. drm_gem_object_put_unlocked(gem);
  699. return 0;
  700. }
  701. static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
  702. struct drm_file *file)
  703. {
  704. struct drm_tegra_gem_get_tiling *args = data;
  705. struct drm_gem_object *gem;
  706. struct tegra_bo *bo;
  707. int err = 0;
  708. gem = drm_gem_object_lookup(file, args->handle);
  709. if (!gem)
  710. return -ENOENT;
  711. bo = to_tegra_bo(gem);
  712. switch (bo->tiling.mode) {
  713. case TEGRA_BO_TILING_MODE_PITCH:
  714. args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
  715. args->value = 0;
  716. break;
  717. case TEGRA_BO_TILING_MODE_TILED:
  718. args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
  719. args->value = 0;
  720. break;
  721. case TEGRA_BO_TILING_MODE_BLOCK:
  722. args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
  723. args->value = bo->tiling.value;
  724. break;
  725. default:
  726. err = -EINVAL;
  727. break;
  728. }
  729. drm_gem_object_put_unlocked(gem);
  730. return err;
  731. }
  732. static int tegra_gem_set_flags(struct drm_device *drm, void *data,
  733. struct drm_file *file)
  734. {
  735. struct drm_tegra_gem_set_flags *args = data;
  736. struct drm_gem_object *gem;
  737. struct tegra_bo *bo;
  738. if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
  739. return -EINVAL;
  740. gem = drm_gem_object_lookup(file, args->handle);
  741. if (!gem)
  742. return -ENOENT;
  743. bo = to_tegra_bo(gem);
  744. bo->flags = 0;
  745. if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
  746. bo->flags |= TEGRA_BO_BOTTOM_UP;
  747. drm_gem_object_put_unlocked(gem);
  748. return 0;
  749. }
  750. static int tegra_gem_get_flags(struct drm_device *drm, void *data,
  751. struct drm_file *file)
  752. {
  753. struct drm_tegra_gem_get_flags *args = data;
  754. struct drm_gem_object *gem;
  755. struct tegra_bo *bo;
  756. gem = drm_gem_object_lookup(file, args->handle);
  757. if (!gem)
  758. return -ENOENT;
  759. bo = to_tegra_bo(gem);
  760. args->flags = 0;
  761. if (bo->flags & TEGRA_BO_BOTTOM_UP)
  762. args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
  763. drm_gem_object_put_unlocked(gem);
  764. return 0;
  765. }
  766. #endif
  767. static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
  768. #ifdef CONFIG_DRM_TEGRA_STAGING
  769. DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
  770. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  771. DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
  772. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  773. DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
  774. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  775. DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
  776. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  777. DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
  778. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  779. DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
  780. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  781. DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
  782. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  783. DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
  784. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  785. DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
  786. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  787. DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
  788. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  789. DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
  790. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  791. DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
  792. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  793. DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
  794. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  795. DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
  796. DRM_UNLOCKED | DRM_RENDER_ALLOW),
  797. #endif
  798. };
  799. static const struct file_operations tegra_drm_fops = {
  800. .owner = THIS_MODULE,
  801. .open = drm_open,
  802. .release = drm_release,
  803. .unlocked_ioctl = drm_ioctl,
  804. .mmap = tegra_drm_mmap,
  805. .poll = drm_poll,
  806. .read = drm_read,
  807. .compat_ioctl = drm_compat_ioctl,
  808. .llseek = noop_llseek,
  809. };
  810. static int tegra_drm_context_cleanup(int id, void *p, void *data)
  811. {
  812. struct tegra_drm_context *context = p;
  813. tegra_drm_context_free(context);
  814. return 0;
  815. }
  816. static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
  817. {
  818. struct tegra_drm_file *fpriv = file->driver_priv;
  819. mutex_lock(&fpriv->lock);
  820. idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
  821. mutex_unlock(&fpriv->lock);
  822. idr_destroy(&fpriv->contexts);
  823. mutex_destroy(&fpriv->lock);
  824. kfree(fpriv);
  825. }
  826. #ifdef CONFIG_DEBUG_FS
  827. static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
  828. {
  829. struct drm_info_node *node = (struct drm_info_node *)s->private;
  830. struct drm_device *drm = node->minor->dev;
  831. struct drm_framebuffer *fb;
  832. mutex_lock(&drm->mode_config.fb_lock);
  833. list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
  834. seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
  835. fb->base.id, fb->width, fb->height,
  836. fb->format->depth,
  837. fb->format->cpp[0] * 8,
  838. drm_framebuffer_read_refcount(fb));
  839. }
  840. mutex_unlock(&drm->mode_config.fb_lock);
  841. return 0;
  842. }
  843. static int tegra_debugfs_iova(struct seq_file *s, void *data)
  844. {
  845. struct drm_info_node *node = (struct drm_info_node *)s->private;
  846. struct drm_device *drm = node->minor->dev;
  847. struct tegra_drm *tegra = drm->dev_private;
  848. struct drm_printer p = drm_seq_file_printer(s);
  849. if (tegra->domain) {
  850. mutex_lock(&tegra->mm_lock);
  851. drm_mm_print(&tegra->mm, &p);
  852. mutex_unlock(&tegra->mm_lock);
  853. }
  854. return 0;
  855. }
  856. static struct drm_info_list tegra_debugfs_list[] = {
  857. { "framebuffers", tegra_debugfs_framebuffers, 0 },
  858. { "iova", tegra_debugfs_iova, 0 },
  859. };
  860. static int tegra_debugfs_init(struct drm_minor *minor)
  861. {
  862. return drm_debugfs_create_files(tegra_debugfs_list,
  863. ARRAY_SIZE(tegra_debugfs_list),
  864. minor->debugfs_root, minor);
  865. }
  866. #endif
  867. static struct drm_driver tegra_drm_driver = {
  868. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  869. DRIVER_ATOMIC | DRIVER_RENDER,
  870. .load = tegra_drm_load,
  871. .unload = tegra_drm_unload,
  872. .open = tegra_drm_open,
  873. .postclose = tegra_drm_postclose,
  874. .lastclose = tegra_drm_lastclose,
  875. #if defined(CONFIG_DEBUG_FS)
  876. .debugfs_init = tegra_debugfs_init,
  877. #endif
  878. .gem_free_object_unlocked = tegra_bo_free_object,
  879. .gem_vm_ops = &tegra_bo_vm_ops,
  880. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  881. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  882. .gem_prime_export = tegra_gem_prime_export,
  883. .gem_prime_import = tegra_gem_prime_import,
  884. .dumb_create = tegra_bo_dumb_create,
  885. .ioctls = tegra_drm_ioctls,
  886. .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
  887. .fops = &tegra_drm_fops,
  888. .name = DRIVER_NAME,
  889. .desc = DRIVER_DESC,
  890. .date = DRIVER_DATE,
  891. .major = DRIVER_MAJOR,
  892. .minor = DRIVER_MINOR,
  893. .patchlevel = DRIVER_PATCHLEVEL,
  894. };
  895. int tegra_drm_register_client(struct tegra_drm *tegra,
  896. struct tegra_drm_client *client)
  897. {
  898. mutex_lock(&tegra->clients_lock);
  899. list_add_tail(&client->list, &tegra->clients);
  900. mutex_unlock(&tegra->clients_lock);
  901. return 0;
  902. }
  903. int tegra_drm_unregister_client(struct tegra_drm *tegra,
  904. struct tegra_drm_client *client)
  905. {
  906. mutex_lock(&tegra->clients_lock);
  907. list_del_init(&client->list);
  908. mutex_unlock(&tegra->clients_lock);
  909. return 0;
  910. }
  911. void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
  912. dma_addr_t *dma)
  913. {
  914. struct iova *alloc;
  915. void *virt;
  916. gfp_t gfp;
  917. int err;
  918. if (tegra->domain)
  919. size = iova_align(&tegra->carveout.domain, size);
  920. else
  921. size = PAGE_ALIGN(size);
  922. gfp = GFP_KERNEL | __GFP_ZERO;
  923. if (!tegra->domain) {
  924. /*
  925. * Many units only support 32-bit addresses, even on 64-bit
  926. * SoCs. If there is no IOMMU to translate into a 32-bit IO
  927. * virtual address space, force allocations to be in the
  928. * lower 32-bit range.
  929. */
  930. gfp |= GFP_DMA;
  931. }
  932. virt = (void *)__get_free_pages(gfp, get_order(size));
  933. if (!virt)
  934. return ERR_PTR(-ENOMEM);
  935. if (!tegra->domain) {
  936. /*
  937. * If IOMMU is disabled, devices address physical memory
  938. * directly.
  939. */
  940. *dma = virt_to_phys(virt);
  941. return virt;
  942. }
  943. alloc = alloc_iova(&tegra->carveout.domain,
  944. size >> tegra->carveout.shift,
  945. tegra->carveout.limit, true);
  946. if (!alloc) {
  947. err = -EBUSY;
  948. goto free_pages;
  949. }
  950. *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
  951. err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
  952. size, IOMMU_READ | IOMMU_WRITE);
  953. if (err < 0)
  954. goto free_iova;
  955. return virt;
  956. free_iova:
  957. __free_iova(&tegra->carveout.domain, alloc);
  958. free_pages:
  959. free_pages((unsigned long)virt, get_order(size));
  960. return ERR_PTR(err);
  961. }
  962. void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
  963. dma_addr_t dma)
  964. {
  965. if (tegra->domain)
  966. size = iova_align(&tegra->carveout.domain, size);
  967. else
  968. size = PAGE_ALIGN(size);
  969. if (tegra->domain) {
  970. iommu_unmap(tegra->domain, dma, size);
  971. free_iova(&tegra->carveout.domain,
  972. iova_pfn(&tegra->carveout.domain, dma));
  973. }
  974. free_pages((unsigned long)virt, get_order(size));
  975. }
  976. static int host1x_drm_probe(struct host1x_device *dev)
  977. {
  978. struct drm_driver *driver = &tegra_drm_driver;
  979. struct drm_device *drm;
  980. int err;
  981. drm = drm_dev_alloc(driver, &dev->dev);
  982. if (IS_ERR(drm))
  983. return PTR_ERR(drm);
  984. dev_set_drvdata(&dev->dev, drm);
  985. err = drm_dev_register(drm, 0);
  986. if (err < 0)
  987. goto unref;
  988. return 0;
  989. unref:
  990. drm_dev_unref(drm);
  991. return err;
  992. }
  993. static int host1x_drm_remove(struct host1x_device *dev)
  994. {
  995. struct drm_device *drm = dev_get_drvdata(&dev->dev);
  996. drm_dev_unregister(drm);
  997. drm_dev_unref(drm);
  998. return 0;
  999. }
  1000. #ifdef CONFIG_PM_SLEEP
  1001. static int host1x_drm_suspend(struct device *dev)
  1002. {
  1003. struct drm_device *drm = dev_get_drvdata(dev);
  1004. struct tegra_drm *tegra = drm->dev_private;
  1005. drm_kms_helper_poll_disable(drm);
  1006. tegra_drm_fb_suspend(drm);
  1007. tegra->state = drm_atomic_helper_suspend(drm);
  1008. if (IS_ERR(tegra->state)) {
  1009. tegra_drm_fb_resume(drm);
  1010. drm_kms_helper_poll_enable(drm);
  1011. return PTR_ERR(tegra->state);
  1012. }
  1013. return 0;
  1014. }
  1015. static int host1x_drm_resume(struct device *dev)
  1016. {
  1017. struct drm_device *drm = dev_get_drvdata(dev);
  1018. struct tegra_drm *tegra = drm->dev_private;
  1019. drm_atomic_helper_resume(drm, tegra->state);
  1020. tegra_drm_fb_resume(drm);
  1021. drm_kms_helper_poll_enable(drm);
  1022. return 0;
  1023. }
  1024. #endif
  1025. static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
  1026. host1x_drm_resume);
  1027. static const struct of_device_id host1x_drm_subdevs[] = {
  1028. { .compatible = "nvidia,tegra20-dc", },
  1029. { .compatible = "nvidia,tegra20-hdmi", },
  1030. { .compatible = "nvidia,tegra20-gr2d", },
  1031. { .compatible = "nvidia,tegra20-gr3d", },
  1032. { .compatible = "nvidia,tegra30-dc", },
  1033. { .compatible = "nvidia,tegra30-hdmi", },
  1034. { .compatible = "nvidia,tegra30-gr2d", },
  1035. { .compatible = "nvidia,tegra30-gr3d", },
  1036. { .compatible = "nvidia,tegra114-dsi", },
  1037. { .compatible = "nvidia,tegra114-hdmi", },
  1038. { .compatible = "nvidia,tegra114-gr3d", },
  1039. { .compatible = "nvidia,tegra124-dc", },
  1040. { .compatible = "nvidia,tegra124-sor", },
  1041. { .compatible = "nvidia,tegra124-hdmi", },
  1042. { .compatible = "nvidia,tegra124-dsi", },
  1043. { .compatible = "nvidia,tegra124-vic", },
  1044. { .compatible = "nvidia,tegra132-dsi", },
  1045. { .compatible = "nvidia,tegra210-dc", },
  1046. { .compatible = "nvidia,tegra210-dsi", },
  1047. { .compatible = "nvidia,tegra210-sor", },
  1048. { .compatible = "nvidia,tegra210-sor1", },
  1049. { .compatible = "nvidia,tegra210-vic", },
  1050. { /* sentinel */ }
  1051. };
  1052. static struct host1x_driver host1x_drm_driver = {
  1053. .driver = {
  1054. .name = "drm",
  1055. .pm = &host1x_drm_pm_ops,
  1056. },
  1057. .probe = host1x_drm_probe,
  1058. .remove = host1x_drm_remove,
  1059. .subdevs = host1x_drm_subdevs,
  1060. };
  1061. static struct platform_driver * const drivers[] = {
  1062. &tegra_dc_driver,
  1063. &tegra_hdmi_driver,
  1064. &tegra_dsi_driver,
  1065. &tegra_dpaux_driver,
  1066. &tegra_sor_driver,
  1067. &tegra_gr2d_driver,
  1068. &tegra_gr3d_driver,
  1069. &tegra_vic_driver,
  1070. };
  1071. static int __init host1x_drm_init(void)
  1072. {
  1073. int err;
  1074. err = host1x_driver_register(&host1x_drm_driver);
  1075. if (err < 0)
  1076. return err;
  1077. err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  1078. if (err < 0)
  1079. goto unregister_host1x;
  1080. return 0;
  1081. unregister_host1x:
  1082. host1x_driver_unregister(&host1x_drm_driver);
  1083. return err;
  1084. }
  1085. module_init(host1x_drm_init);
  1086. static void __exit host1x_drm_exit(void)
  1087. {
  1088. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  1089. host1x_driver_unregister(&host1x_drm_driver);
  1090. }
  1091. module_exit(host1x_drm_exit);
  1092. MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
  1093. MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
  1094. MODULE_LICENSE("GPL v2");