platform.c 13 KB

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  1. /*
  2. * platform.c - DesignWare HS OTG Controller platform driver
  3. *
  4. * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/slab.h>
  39. #include <linux/clk.h>
  40. #include <linux/device.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/of_device.h>
  43. #include <linux/mutex.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/phy/phy.h>
  46. #include <linux/platform_data/s3c-hsotg.h>
  47. #include <linux/usb/of.h>
  48. #include "core.h"
  49. #include "hcd.h"
  50. #include "debug.h"
  51. static const char dwc2_driver_name[] = "dwc2";
  52. static const struct dwc2_core_params params_bcm2835 = {
  53. .otg_cap = 0, /* HNP/SRP capable */
  54. .otg_ver = 0, /* 1.3 */
  55. .dma_enable = 1,
  56. .dma_desc_enable = 0,
  57. .speed = 0, /* High Speed */
  58. .enable_dynamic_fifo = 1,
  59. .en_multiple_tx_fifo = 1,
  60. .host_rx_fifo_size = 774, /* 774 DWORDs */
  61. .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
  62. .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
  63. .max_transfer_size = 65535,
  64. .max_packet_count = 511,
  65. .host_channels = 8,
  66. .phy_type = 1, /* UTMI */
  67. .phy_utmi_width = 8, /* 8 bits */
  68. .phy_ulpi_ddr = 0, /* Single */
  69. .phy_ulpi_ext_vbus = 0,
  70. .i2c_enable = 0,
  71. .ulpi_fs_ls = 0,
  72. .host_support_fs_ls_low_power = 0,
  73. .host_ls_low_power_phy_clk = 0, /* 48 MHz */
  74. .ts_dline = 0,
  75. .reload_ctl = 0,
  76. .ahbcfg = 0x10,
  77. .uframe_sched = 0,
  78. .external_id_pin_ctl = -1,
  79. .hibernation = -1,
  80. };
  81. static const struct dwc2_core_params params_rk3066 = {
  82. .otg_cap = 2, /* non-HNP/non-SRP */
  83. .otg_ver = -1,
  84. .dma_enable = -1,
  85. .dma_desc_enable = 0,
  86. .speed = -1,
  87. .enable_dynamic_fifo = 1,
  88. .en_multiple_tx_fifo = -1,
  89. .host_rx_fifo_size = 520, /* 520 DWORDs */
  90. .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
  91. .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
  92. .max_transfer_size = 65535,
  93. .max_packet_count = -1,
  94. .host_channels = -1,
  95. .phy_type = -1,
  96. .phy_utmi_width = -1,
  97. .phy_ulpi_ddr = -1,
  98. .phy_ulpi_ext_vbus = -1,
  99. .i2c_enable = -1,
  100. .ulpi_fs_ls = -1,
  101. .host_support_fs_ls_low_power = -1,
  102. .host_ls_low_power_phy_clk = -1,
  103. .ts_dline = -1,
  104. .reload_ctl = -1,
  105. .ahbcfg = 0x7, /* INCR16 */
  106. .uframe_sched = -1,
  107. .external_id_pin_ctl = -1,
  108. .hibernation = -1,
  109. };
  110. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  111. {
  112. struct platform_device *pdev = to_platform_device(hsotg->dev);
  113. int ret;
  114. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  115. hsotg->supplies);
  116. if (ret)
  117. return ret;
  118. ret = clk_prepare_enable(hsotg->clk);
  119. if (ret)
  120. return ret;
  121. if (hsotg->uphy)
  122. ret = usb_phy_init(hsotg->uphy);
  123. else if (hsotg->plat && hsotg->plat->phy_init)
  124. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  125. else {
  126. ret = phy_power_on(hsotg->phy);
  127. if (ret == 0)
  128. ret = phy_init(hsotg->phy);
  129. }
  130. return ret;
  131. }
  132. /**
  133. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  134. * @hsotg: The driver state
  135. *
  136. * A wrapper for platform code responsible for controlling
  137. * low-level USB platform resources (phy, clock, regulators)
  138. */
  139. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  140. {
  141. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  142. if (ret == 0)
  143. hsotg->ll_hw_enabled = true;
  144. return ret;
  145. }
  146. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  147. {
  148. struct platform_device *pdev = to_platform_device(hsotg->dev);
  149. int ret = 0;
  150. if (hsotg->uphy)
  151. usb_phy_shutdown(hsotg->uphy);
  152. else if (hsotg->plat && hsotg->plat->phy_exit)
  153. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  154. else {
  155. ret = phy_exit(hsotg->phy);
  156. if (ret == 0)
  157. ret = phy_power_off(hsotg->phy);
  158. }
  159. if (ret)
  160. return ret;
  161. clk_disable_unprepare(hsotg->clk);
  162. ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
  163. hsotg->supplies);
  164. return ret;
  165. }
  166. /**
  167. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  168. * @hsotg: The driver state
  169. *
  170. * A wrapper for platform code responsible for controlling
  171. * low-level USB platform resources (phy, clock, regulators)
  172. */
  173. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  174. {
  175. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  176. if (ret == 0)
  177. hsotg->ll_hw_enabled = false;
  178. return ret;
  179. }
  180. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  181. {
  182. int i, ret;
  183. /* Set default UTMI width */
  184. hsotg->phyif = GUSBCFG_PHYIF16;
  185. /*
  186. * Attempt to find a generic PHY, then look for an old style
  187. * USB PHY and then fall back to pdata
  188. */
  189. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  190. if (IS_ERR(hsotg->phy)) {
  191. hsotg->phy = NULL;
  192. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  193. if (IS_ERR(hsotg->uphy))
  194. hsotg->uphy = NULL;
  195. else
  196. hsotg->plat = dev_get_platdata(hsotg->dev);
  197. }
  198. if (hsotg->phy) {
  199. /*
  200. * If using the generic PHY framework, check if the PHY bus
  201. * width is 8-bit and set the phyif appropriately.
  202. */
  203. if (phy_get_bus_width(hsotg->phy) == 8)
  204. hsotg->phyif = GUSBCFG_PHYIF8;
  205. }
  206. if (!hsotg->phy && !hsotg->uphy && !hsotg->plat) {
  207. dev_err(hsotg->dev, "no platform data or transceiver defined\n");
  208. return -EPROBE_DEFER;
  209. }
  210. /* Clock */
  211. hsotg->clk = devm_clk_get(hsotg->dev, "otg");
  212. if (IS_ERR(hsotg->clk)) {
  213. hsotg->clk = NULL;
  214. dev_dbg(hsotg->dev, "cannot get otg clock\n");
  215. }
  216. /* Regulators */
  217. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  218. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  219. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  220. hsotg->supplies);
  221. if (ret) {
  222. dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
  223. return ret;
  224. }
  225. return 0;
  226. }
  227. /**
  228. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  229. * DWC_otg driver
  230. *
  231. * @dev: Platform device
  232. *
  233. * This routine is called, for example, when the rmmod command is executed. The
  234. * device may or may not be electrically present. If it is present, the driver
  235. * stops device processing. Any resources used on behalf of this device are
  236. * freed.
  237. */
  238. static int dwc2_driver_remove(struct platform_device *dev)
  239. {
  240. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  241. dwc2_debugfs_exit(hsotg);
  242. if (hsotg->hcd_enabled)
  243. dwc2_hcd_remove(hsotg);
  244. if (hsotg->gadget_enabled)
  245. dwc2_hsotg_remove(hsotg);
  246. if (hsotg->ll_hw_enabled)
  247. dwc2_lowlevel_hw_disable(hsotg);
  248. return 0;
  249. }
  250. static const struct of_device_id dwc2_of_match_table[] = {
  251. { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
  252. { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
  253. { .compatible = "snps,dwc2", .data = NULL },
  254. { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
  255. {},
  256. };
  257. MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
  258. /**
  259. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  260. * driver
  261. *
  262. * @dev: Platform device
  263. *
  264. * This routine creates the driver components required to control the device
  265. * (core, HCD, and PCD) and initializes the device. The driver components are
  266. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  267. * in the device private data. This allows the driver to access the dwc2_hsotg
  268. * structure on subsequent calls to driver methods for this device.
  269. */
  270. static int dwc2_driver_probe(struct platform_device *dev)
  271. {
  272. const struct of_device_id *match;
  273. const struct dwc2_core_params *params;
  274. struct dwc2_core_params defparams;
  275. struct dwc2_hsotg *hsotg;
  276. struct resource *res;
  277. int retval;
  278. int irq;
  279. match = of_match_device(dwc2_of_match_table, &dev->dev);
  280. if (match && match->data) {
  281. params = match->data;
  282. } else {
  283. /* Default all params to autodetect */
  284. dwc2_set_all_params(&defparams, -1);
  285. params = &defparams;
  286. /*
  287. * Disable descriptor dma mode by default as the HW can support
  288. * it, but does not support it for SPLIT transactions.
  289. */
  290. defparams.dma_desc_enable = 0;
  291. }
  292. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  293. if (!hsotg)
  294. return -ENOMEM;
  295. hsotg->dev = &dev->dev;
  296. /*
  297. * Use reasonable defaults so platforms don't have to provide these.
  298. */
  299. if (!dev->dev.dma_mask)
  300. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  301. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  302. if (retval)
  303. return retval;
  304. irq = platform_get_irq(dev, 0);
  305. if (irq < 0) {
  306. dev_err(&dev->dev, "missing IRQ resource\n");
  307. return irq;
  308. }
  309. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  310. irq);
  311. retval = devm_request_irq(hsotg->dev, irq,
  312. dwc2_handle_common_intr, IRQF_SHARED,
  313. dev_name(hsotg->dev), hsotg);
  314. if (retval)
  315. return retval;
  316. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  317. hsotg->regs = devm_ioremap_resource(&dev->dev, res);
  318. if (IS_ERR(hsotg->regs))
  319. return PTR_ERR(hsotg->regs);
  320. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  321. (unsigned long)res->start, hsotg->regs);
  322. hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
  323. if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
  324. hsotg->dr_mode != USB_DR_MODE_HOST) {
  325. hsotg->dr_mode = USB_DR_MODE_HOST;
  326. dev_warn(hsotg->dev,
  327. "Configuration mismatch. Forcing host mode\n");
  328. } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
  329. hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  330. hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
  331. dev_warn(hsotg->dev,
  332. "Configuration mismatch. Forcing peripheral mode\n");
  333. }
  334. retval = dwc2_lowlevel_hw_init(hsotg);
  335. if (retval)
  336. return retval;
  337. spin_lock_init(&hsotg->lock);
  338. hsotg->core_params = devm_kzalloc(&dev->dev,
  339. sizeof(*hsotg->core_params), GFP_KERNEL);
  340. if (!hsotg->core_params)
  341. return -ENOMEM;
  342. dwc2_set_all_params(hsotg->core_params, -1);
  343. retval = dwc2_lowlevel_hw_enable(hsotg);
  344. if (retval)
  345. return retval;
  346. /* Detect config values from hardware */
  347. retval = dwc2_get_hwparams(hsotg);
  348. if (retval)
  349. goto error;
  350. /* Validate parameter values */
  351. dwc2_set_parameters(hsotg, params);
  352. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  353. retval = dwc2_gadget_init(hsotg, irq);
  354. if (retval)
  355. goto error;
  356. hsotg->gadget_enabled = 1;
  357. }
  358. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  359. retval = dwc2_hcd_init(hsotg, irq);
  360. if (retval) {
  361. if (hsotg->gadget_enabled)
  362. dwc2_hsotg_remove(hsotg);
  363. goto error;
  364. }
  365. hsotg->hcd_enabled = 1;
  366. }
  367. platform_set_drvdata(dev, hsotg);
  368. dwc2_debugfs_init(hsotg);
  369. /* Gadget code manages lowlevel hw on its own */
  370. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  371. dwc2_lowlevel_hw_disable(hsotg);
  372. return 0;
  373. error:
  374. dwc2_lowlevel_hw_disable(hsotg);
  375. return retval;
  376. }
  377. static int __maybe_unused dwc2_suspend(struct device *dev)
  378. {
  379. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  380. int ret = 0;
  381. if (dwc2_is_device_mode(dwc2))
  382. dwc2_hsotg_suspend(dwc2);
  383. if (dwc2->ll_hw_enabled)
  384. ret = __dwc2_lowlevel_hw_disable(dwc2);
  385. return ret;
  386. }
  387. static int __maybe_unused dwc2_resume(struct device *dev)
  388. {
  389. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  390. int ret = 0;
  391. if (dwc2->ll_hw_enabled) {
  392. ret = __dwc2_lowlevel_hw_enable(dwc2);
  393. if (ret)
  394. return ret;
  395. }
  396. if (dwc2_is_device_mode(dwc2))
  397. ret = dwc2_hsotg_resume(dwc2);
  398. return ret;
  399. }
  400. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  401. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  402. };
  403. static struct platform_driver dwc2_platform_driver = {
  404. .driver = {
  405. .name = dwc2_driver_name,
  406. .of_match_table = dwc2_of_match_table,
  407. .pm = &dwc2_dev_pm_ops,
  408. },
  409. .probe = dwc2_driver_probe,
  410. .remove = dwc2_driver_remove,
  411. };
  412. module_platform_driver(dwc2_platform_driver);
  413. MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
  414. MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
  415. MODULE_LICENSE("Dual BSD/GPL");