omap_hwmod_2430_data.c 17 KB

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  1. /*
  2. * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
  3. *
  4. * Copyright (C) 2009-2011 Nokia Corporation
  5. * Copyright (C) 2012 Texas Instruments, Inc.
  6. * Paul Walmsley
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * XXX handle crossbar/shared link difference for L3?
  13. * XXX these should be marked initdata for multi-OMAP kernels
  14. */
  15. #include <linux/i2c-omap.h>
  16. #include <linux/platform_data/asoc-ti-mcbsp.h>
  17. #include <linux/platform_data/hsmmc-omap.h>
  18. #include <linux/platform_data/spi-omap2-mcspi.h>
  19. #include <linux/omap-dma.h>
  20. #include <plat/dmtimer.h>
  21. #include "omap_hwmod.h"
  22. #include "l3_2xxx.h"
  23. #include "soc.h"
  24. #include "omap_hwmod_common_data.h"
  25. #include "prm-regbits-24xx.h"
  26. #include "cm-regbits-24xx.h"
  27. #include "i2c.h"
  28. #include "wd_timer.h"
  29. /*
  30. * OMAP2430 hardware module integration data
  31. *
  32. * All of the data in this section should be autogeneratable from the
  33. * TI hardware database or other technical documentation. Data that
  34. * is driver-specific or driver-kernel integration-specific belongs
  35. * elsewhere.
  36. */
  37. /*
  38. * IP blocks
  39. */
  40. /* IVA2 (IVA2) */
  41. static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
  42. { .name = "logic", .rst_shift = 0 },
  43. { .name = "mmu", .rst_shift = 1 },
  44. };
  45. static struct omap_hwmod omap2430_iva_hwmod = {
  46. .name = "iva",
  47. .class = &iva_hwmod_class,
  48. .clkdm_name = "dsp_clkdm",
  49. .rst_lines = omap2430_iva_resets,
  50. .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
  51. .main_clk = "dsp_fck",
  52. };
  53. /* I2C common */
  54. static struct omap_hwmod_class_sysconfig i2c_sysc = {
  55. .rev_offs = 0x00,
  56. .sysc_offs = 0x20,
  57. .syss_offs = 0x10,
  58. .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  59. SYSS_HAS_RESET_STATUS),
  60. .sysc_fields = &omap_hwmod_sysc_type1,
  61. };
  62. static struct omap_hwmod_class i2c_class = {
  63. .name = "i2c",
  64. .sysc = &i2c_sysc,
  65. .rev = OMAP_I2C_IP_VERSION_1,
  66. .reset = &omap_i2c_reset,
  67. };
  68. static struct omap_i2c_dev_attr i2c_dev_attr = {
  69. .fifo_depth = 8, /* bytes */
  70. .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
  71. OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
  72. };
  73. /* I2C1 */
  74. static struct omap_hwmod omap2430_i2c1_hwmod = {
  75. .name = "i2c1",
  76. .flags = HWMOD_16BIT_REG,
  77. .main_clk = "i2chs1_fck",
  78. .prcm = {
  79. .omap2 = {
  80. /*
  81. * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
  82. * I2CHS IP's do not follow the usual pattern.
  83. * prcm_reg_id alone cannot be used to program
  84. * the iclk and fclk. Needs to be handled using
  85. * additional flags when clk handling is moved
  86. * to hwmod framework.
  87. */
  88. .module_offs = CORE_MOD,
  89. .idlest_reg_id = 1,
  90. .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
  91. },
  92. },
  93. .class = &i2c_class,
  94. .dev_attr = &i2c_dev_attr,
  95. };
  96. /* I2C2 */
  97. static struct omap_hwmod omap2430_i2c2_hwmod = {
  98. .name = "i2c2",
  99. .flags = HWMOD_16BIT_REG,
  100. .main_clk = "i2chs2_fck",
  101. .prcm = {
  102. .omap2 = {
  103. .module_offs = CORE_MOD,
  104. .idlest_reg_id = 1,
  105. .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
  106. },
  107. },
  108. .class = &i2c_class,
  109. .dev_attr = &i2c_dev_attr,
  110. };
  111. /* gpio5 */
  112. static struct omap_hwmod omap2430_gpio5_hwmod = {
  113. .name = "gpio5",
  114. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  115. .main_clk = "gpio5_fck",
  116. .prcm = {
  117. .omap2 = {
  118. .module_offs = CORE_MOD,
  119. .idlest_reg_id = 2,
  120. .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
  121. },
  122. },
  123. .class = &omap2xxx_gpio_hwmod_class,
  124. };
  125. /* dma attributes */
  126. static struct omap_dma_dev_attr dma_dev_attr = {
  127. .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
  128. IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
  129. .lch_count = 32,
  130. };
  131. static struct omap_hwmod omap2430_dma_system_hwmod = {
  132. .name = "dma",
  133. .class = &omap2xxx_dma_hwmod_class,
  134. .main_clk = "core_l3_ck",
  135. .dev_attr = &dma_dev_attr,
  136. .flags = HWMOD_NO_IDLEST,
  137. };
  138. /* mailbox */
  139. static struct omap_hwmod omap2430_mailbox_hwmod = {
  140. .name = "mailbox",
  141. .class = &omap2xxx_mailbox_hwmod_class,
  142. .main_clk = "mailboxes_ick",
  143. .prcm = {
  144. .omap2 = {
  145. .module_offs = CORE_MOD,
  146. .idlest_reg_id = 1,
  147. .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
  148. },
  149. },
  150. };
  151. /* mcspi3 */
  152. static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
  153. .num_chipselect = 2,
  154. };
  155. static struct omap_hwmod omap2430_mcspi3_hwmod = {
  156. .name = "mcspi3",
  157. .main_clk = "mcspi3_fck",
  158. .prcm = {
  159. .omap2 = {
  160. .module_offs = CORE_MOD,
  161. .idlest_reg_id = 2,
  162. .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
  163. },
  164. },
  165. .class = &omap2xxx_mcspi_class,
  166. .dev_attr = &omap_mcspi3_dev_attr,
  167. };
  168. /* usbhsotg */
  169. static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
  170. .rev_offs = 0x0400,
  171. .sysc_offs = 0x0404,
  172. .syss_offs = 0x0408,
  173. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
  174. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  175. SYSC_HAS_AUTOIDLE),
  176. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  177. MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  178. .sysc_fields = &omap_hwmod_sysc_type1,
  179. };
  180. static struct omap_hwmod_class usbotg_class = {
  181. .name = "usbotg",
  182. .sysc = &omap2430_usbhsotg_sysc,
  183. };
  184. /* usb_otg_hs */
  185. static struct omap_hwmod omap2430_usbhsotg_hwmod = {
  186. .name = "usb_otg_hs",
  187. .main_clk = "usbhs_ick",
  188. .prcm = {
  189. .omap2 = {
  190. .module_offs = CORE_MOD,
  191. .idlest_reg_id = 1,
  192. .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
  193. },
  194. },
  195. .class = &usbotg_class,
  196. /*
  197. * Erratum ID: i479 idle_req / idle_ack mechanism potentially
  198. * broken when autoidle is enabled
  199. * workaround is to disable the autoidle bit at module level.
  200. */
  201. .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
  202. | HWMOD_SWSUP_MSTANDBY,
  203. };
  204. /*
  205. * 'mcbsp' class
  206. * multi channel buffered serial port controller
  207. */
  208. static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
  209. .rev_offs = 0x007C,
  210. .sysc_offs = 0x008C,
  211. .sysc_flags = (SYSC_HAS_SOFTRESET),
  212. .sysc_fields = &omap_hwmod_sysc_type1,
  213. };
  214. static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
  215. .name = "mcbsp",
  216. .sysc = &omap2430_mcbsp_sysc,
  217. .rev = MCBSP_CONFIG_TYPE2,
  218. };
  219. static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
  220. { .role = "pad_fck", .clk = "mcbsp_clks" },
  221. { .role = "prcm_fck", .clk = "func_96m_ck" },
  222. };
  223. /* mcbsp1 */
  224. static struct omap_hwmod omap2430_mcbsp1_hwmod = {
  225. .name = "mcbsp1",
  226. .class = &omap2430_mcbsp_hwmod_class,
  227. .main_clk = "mcbsp1_fck",
  228. .prcm = {
  229. .omap2 = {
  230. .module_offs = CORE_MOD,
  231. .idlest_reg_id = 1,
  232. .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
  233. },
  234. },
  235. .opt_clks = mcbsp_opt_clks,
  236. .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
  237. };
  238. /* mcbsp2 */
  239. static struct omap_hwmod omap2430_mcbsp2_hwmod = {
  240. .name = "mcbsp2",
  241. .class = &omap2430_mcbsp_hwmod_class,
  242. .main_clk = "mcbsp2_fck",
  243. .prcm = {
  244. .omap2 = {
  245. .module_offs = CORE_MOD,
  246. .idlest_reg_id = 1,
  247. .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
  248. },
  249. },
  250. .opt_clks = mcbsp_opt_clks,
  251. .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
  252. };
  253. /* mcbsp3 */
  254. static struct omap_hwmod omap2430_mcbsp3_hwmod = {
  255. .name = "mcbsp3",
  256. .class = &omap2430_mcbsp_hwmod_class,
  257. .main_clk = "mcbsp3_fck",
  258. .prcm = {
  259. .omap2 = {
  260. .module_offs = CORE_MOD,
  261. .idlest_reg_id = 2,
  262. .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
  263. },
  264. },
  265. .opt_clks = mcbsp_opt_clks,
  266. .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
  267. };
  268. /* mcbsp4 */
  269. static struct omap_hwmod omap2430_mcbsp4_hwmod = {
  270. .name = "mcbsp4",
  271. .class = &omap2430_mcbsp_hwmod_class,
  272. .main_clk = "mcbsp4_fck",
  273. .prcm = {
  274. .omap2 = {
  275. .module_offs = CORE_MOD,
  276. .idlest_reg_id = 2,
  277. .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
  278. },
  279. },
  280. .opt_clks = mcbsp_opt_clks,
  281. .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
  282. };
  283. /* mcbsp5 */
  284. static struct omap_hwmod omap2430_mcbsp5_hwmod = {
  285. .name = "mcbsp5",
  286. .class = &omap2430_mcbsp_hwmod_class,
  287. .main_clk = "mcbsp5_fck",
  288. .prcm = {
  289. .omap2 = {
  290. .module_offs = CORE_MOD,
  291. .idlest_reg_id = 2,
  292. .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
  293. },
  294. },
  295. .opt_clks = mcbsp_opt_clks,
  296. .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
  297. };
  298. /* MMC/SD/SDIO common */
  299. static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
  300. .rev_offs = 0x1fc,
  301. .sysc_offs = 0x10,
  302. .syss_offs = 0x14,
  303. .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  304. SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  305. SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  306. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  307. .sysc_fields = &omap_hwmod_sysc_type1,
  308. };
  309. static struct omap_hwmod_class omap2430_mmc_class = {
  310. .name = "mmc",
  311. .sysc = &omap2430_mmc_sysc,
  312. };
  313. /* MMC/SD/SDIO1 */
  314. static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
  315. { .role = "dbck", .clk = "mmchsdb1_fck" },
  316. };
  317. static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
  318. .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  319. };
  320. static struct omap_hwmod omap2430_mmc1_hwmod = {
  321. .name = "mmc1",
  322. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  323. .opt_clks = omap2430_mmc1_opt_clks,
  324. .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
  325. .main_clk = "mmchs1_fck",
  326. .prcm = {
  327. .omap2 = {
  328. .module_offs = CORE_MOD,
  329. .idlest_reg_id = 2,
  330. .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
  331. },
  332. },
  333. .dev_attr = &mmc1_dev_attr,
  334. .class = &omap2430_mmc_class,
  335. };
  336. /* MMC/SD/SDIO2 */
  337. static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
  338. { .role = "dbck", .clk = "mmchsdb2_fck" },
  339. };
  340. static struct omap_hwmod omap2430_mmc2_hwmod = {
  341. .name = "mmc2",
  342. .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
  343. .opt_clks = omap2430_mmc2_opt_clks,
  344. .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
  345. .main_clk = "mmchs2_fck",
  346. .prcm = {
  347. .omap2 = {
  348. .module_offs = CORE_MOD,
  349. .idlest_reg_id = 2,
  350. .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
  351. },
  352. },
  353. .class = &omap2430_mmc_class,
  354. };
  355. /* HDQ1W/1-wire */
  356. static struct omap_hwmod omap2430_hdq1w_hwmod = {
  357. .name = "hdq1w",
  358. .main_clk = "hdq_fck",
  359. .prcm = {
  360. .omap2 = {
  361. .module_offs = CORE_MOD,
  362. .idlest_reg_id = 1,
  363. .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
  364. },
  365. },
  366. .class = &omap2_hdq1w_class,
  367. };
  368. /*
  369. * interfaces
  370. */
  371. /* L3 -> L4_CORE interface */
  372. /* l3_core -> usbhsotg interface */
  373. static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
  374. .master = &omap2430_usbhsotg_hwmod,
  375. .slave = &omap2xxx_l3_main_hwmod,
  376. .clk = "core_l3_ck",
  377. .user = OCP_USER_MPU,
  378. };
  379. /* L4 CORE -> I2C1 interface */
  380. static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
  381. .master = &omap2xxx_l4_core_hwmod,
  382. .slave = &omap2430_i2c1_hwmod,
  383. .clk = "i2c1_ick",
  384. .user = OCP_USER_MPU | OCP_USER_SDMA,
  385. };
  386. /* L4 CORE -> I2C2 interface */
  387. static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
  388. .master = &omap2xxx_l4_core_hwmod,
  389. .slave = &omap2430_i2c2_hwmod,
  390. .clk = "i2c2_ick",
  391. .user = OCP_USER_MPU | OCP_USER_SDMA,
  392. };
  393. /* l4_core ->usbhsotg interface */
  394. static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
  395. .master = &omap2xxx_l4_core_hwmod,
  396. .slave = &omap2430_usbhsotg_hwmod,
  397. .clk = "usb_l4_ick",
  398. .user = OCP_USER_MPU,
  399. };
  400. /* L4 CORE -> MMC1 interface */
  401. static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
  402. .master = &omap2xxx_l4_core_hwmod,
  403. .slave = &omap2430_mmc1_hwmod,
  404. .clk = "mmchs1_ick",
  405. .user = OCP_USER_MPU | OCP_USER_SDMA,
  406. };
  407. /* L4 CORE -> MMC2 interface */
  408. static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
  409. .master = &omap2xxx_l4_core_hwmod,
  410. .slave = &omap2430_mmc2_hwmod,
  411. .clk = "mmchs2_ick",
  412. .user = OCP_USER_MPU | OCP_USER_SDMA,
  413. };
  414. /* l4 core -> mcspi3 interface */
  415. static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
  416. .master = &omap2xxx_l4_core_hwmod,
  417. .slave = &omap2430_mcspi3_hwmod,
  418. .clk = "mcspi3_ick",
  419. .user = OCP_USER_MPU | OCP_USER_SDMA,
  420. };
  421. /* IVA2 <- L3 interface */
  422. static struct omap_hwmod_ocp_if omap2430_l3__iva = {
  423. .master = &omap2xxx_l3_main_hwmod,
  424. .slave = &omap2430_iva_hwmod,
  425. .clk = "core_l3_ck",
  426. .user = OCP_USER_MPU | OCP_USER_SDMA,
  427. };
  428. /* l4_wkup -> timer1 */
  429. static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
  430. .master = &omap2xxx_l4_wkup_hwmod,
  431. .slave = &omap2xxx_timer1_hwmod,
  432. .clk = "gpt1_ick",
  433. .user = OCP_USER_MPU | OCP_USER_SDMA,
  434. };
  435. /* l4_wkup -> wd_timer2 */
  436. static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
  437. .master = &omap2xxx_l4_wkup_hwmod,
  438. .slave = &omap2xxx_wd_timer2_hwmod,
  439. .clk = "mpu_wdt_ick",
  440. .user = OCP_USER_MPU | OCP_USER_SDMA,
  441. };
  442. /* l4_wkup -> gpio1 */
  443. static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
  444. .master = &omap2xxx_l4_wkup_hwmod,
  445. .slave = &omap2xxx_gpio1_hwmod,
  446. .clk = "gpios_ick",
  447. .user = OCP_USER_MPU | OCP_USER_SDMA,
  448. };
  449. /* l4_wkup -> gpio2 */
  450. static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
  451. .master = &omap2xxx_l4_wkup_hwmod,
  452. .slave = &omap2xxx_gpio2_hwmod,
  453. .clk = "gpios_ick",
  454. .user = OCP_USER_MPU | OCP_USER_SDMA,
  455. };
  456. /* l4_wkup -> gpio3 */
  457. static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
  458. .master = &omap2xxx_l4_wkup_hwmod,
  459. .slave = &omap2xxx_gpio3_hwmod,
  460. .clk = "gpios_ick",
  461. .user = OCP_USER_MPU | OCP_USER_SDMA,
  462. };
  463. /* l4_wkup -> gpio4 */
  464. static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
  465. .master = &omap2xxx_l4_wkup_hwmod,
  466. .slave = &omap2xxx_gpio4_hwmod,
  467. .clk = "gpios_ick",
  468. .user = OCP_USER_MPU | OCP_USER_SDMA,
  469. };
  470. /* l4_core -> gpio5 */
  471. static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
  472. .master = &omap2xxx_l4_core_hwmod,
  473. .slave = &omap2430_gpio5_hwmod,
  474. .clk = "gpio5_ick",
  475. .user = OCP_USER_MPU | OCP_USER_SDMA,
  476. };
  477. /* dma_system -> L3 */
  478. static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
  479. .master = &omap2430_dma_system_hwmod,
  480. .slave = &omap2xxx_l3_main_hwmod,
  481. .clk = "core_l3_ck",
  482. .user = OCP_USER_MPU | OCP_USER_SDMA,
  483. };
  484. /* l4_core -> dma_system */
  485. static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
  486. .master = &omap2xxx_l4_core_hwmod,
  487. .slave = &omap2430_dma_system_hwmod,
  488. .clk = "sdma_ick",
  489. .user = OCP_USER_MPU | OCP_USER_SDMA,
  490. };
  491. /* l4_core -> mailbox */
  492. static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
  493. .master = &omap2xxx_l4_core_hwmod,
  494. .slave = &omap2430_mailbox_hwmod,
  495. .user = OCP_USER_MPU | OCP_USER_SDMA,
  496. };
  497. /* l4_core -> mcbsp1 */
  498. static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
  499. .master = &omap2xxx_l4_core_hwmod,
  500. .slave = &omap2430_mcbsp1_hwmod,
  501. .clk = "mcbsp1_ick",
  502. .user = OCP_USER_MPU | OCP_USER_SDMA,
  503. };
  504. /* l4_core -> mcbsp2 */
  505. static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
  506. .master = &omap2xxx_l4_core_hwmod,
  507. .slave = &omap2430_mcbsp2_hwmod,
  508. .clk = "mcbsp2_ick",
  509. .user = OCP_USER_MPU | OCP_USER_SDMA,
  510. };
  511. /* l4_core -> mcbsp3 */
  512. static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
  513. .master = &omap2xxx_l4_core_hwmod,
  514. .slave = &omap2430_mcbsp3_hwmod,
  515. .clk = "mcbsp3_ick",
  516. .user = OCP_USER_MPU | OCP_USER_SDMA,
  517. };
  518. /* l4_core -> mcbsp4 */
  519. static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
  520. .master = &omap2xxx_l4_core_hwmod,
  521. .slave = &omap2430_mcbsp4_hwmod,
  522. .clk = "mcbsp4_ick",
  523. .user = OCP_USER_MPU | OCP_USER_SDMA,
  524. };
  525. /* l4_core -> mcbsp5 */
  526. static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
  527. .master = &omap2xxx_l4_core_hwmod,
  528. .slave = &omap2430_mcbsp5_hwmod,
  529. .clk = "mcbsp5_ick",
  530. .user = OCP_USER_MPU | OCP_USER_SDMA,
  531. };
  532. /* l4_core -> hdq1w */
  533. static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
  534. .master = &omap2xxx_l4_core_hwmod,
  535. .slave = &omap2430_hdq1w_hwmod,
  536. .clk = "hdq_ick",
  537. .user = OCP_USER_MPU | OCP_USER_SDMA,
  538. .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
  539. };
  540. /* l4_wkup -> 32ksync_counter */
  541. static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
  542. .master = &omap2xxx_l4_wkup_hwmod,
  543. .slave = &omap2xxx_counter_32k_hwmod,
  544. .clk = "sync_32k_ick",
  545. .user = OCP_USER_MPU | OCP_USER_SDMA,
  546. };
  547. static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
  548. .master = &omap2xxx_l3_main_hwmod,
  549. .slave = &omap2xxx_gpmc_hwmod,
  550. .clk = "core_l3_ck",
  551. .user = OCP_USER_MPU | OCP_USER_SDMA,
  552. };
  553. static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
  554. &omap2xxx_l3_main__l4_core,
  555. &omap2xxx_mpu__l3_main,
  556. &omap2xxx_dss__l3,
  557. &omap2430_usbhsotg__l3,
  558. &omap2430_l4_core__i2c1,
  559. &omap2430_l4_core__i2c2,
  560. &omap2xxx_l4_core__l4_wkup,
  561. &omap2_l4_core__uart1,
  562. &omap2_l4_core__uart2,
  563. &omap2_l4_core__uart3,
  564. &omap2430_l4_core__usbhsotg,
  565. &omap2430_l4_core__mmc1,
  566. &omap2430_l4_core__mmc2,
  567. &omap2xxx_l4_core__mcspi1,
  568. &omap2xxx_l4_core__mcspi2,
  569. &omap2430_l4_core__mcspi3,
  570. &omap2430_l3__iva,
  571. &omap2430_l4_wkup__timer1,
  572. &omap2xxx_l4_core__timer2,
  573. &omap2xxx_l4_core__timer3,
  574. &omap2xxx_l4_core__timer4,
  575. &omap2xxx_l4_core__timer5,
  576. &omap2xxx_l4_core__timer6,
  577. &omap2xxx_l4_core__timer7,
  578. &omap2xxx_l4_core__timer8,
  579. &omap2xxx_l4_core__timer9,
  580. &omap2xxx_l4_core__timer10,
  581. &omap2xxx_l4_core__timer11,
  582. &omap2xxx_l4_core__timer12,
  583. &omap2430_l4_wkup__wd_timer2,
  584. &omap2xxx_l4_core__dss,
  585. &omap2xxx_l4_core__dss_dispc,
  586. &omap2xxx_l4_core__dss_rfbi,
  587. &omap2xxx_l4_core__dss_venc,
  588. &omap2430_l4_wkup__gpio1,
  589. &omap2430_l4_wkup__gpio2,
  590. &omap2430_l4_wkup__gpio3,
  591. &omap2430_l4_wkup__gpio4,
  592. &omap2430_l4_core__gpio5,
  593. &omap2430_dma_system__l3,
  594. &omap2430_l4_core__dma_system,
  595. &omap2430_l4_core__mailbox,
  596. &omap2430_l4_core__mcbsp1,
  597. &omap2430_l4_core__mcbsp2,
  598. &omap2430_l4_core__mcbsp3,
  599. &omap2430_l4_core__mcbsp4,
  600. &omap2430_l4_core__mcbsp5,
  601. &omap2430_l4_core__hdq1w,
  602. &omap2xxx_l4_core__rng,
  603. &omap2xxx_l4_core__sham,
  604. &omap2xxx_l4_core__aes,
  605. &omap2430_l4_wkup__counter_32k,
  606. &omap2430_l3__gpmc,
  607. NULL,
  608. };
  609. int __init omap2430_hwmod_init(void)
  610. {
  611. omap_hwmod_init();
  612. return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
  613. }