utils.c 42 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446
  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10. * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  37. * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
  38. * All rights reserved.
  39. *
  40. * Redistribution and use in source and binary forms, with or without
  41. * modification, are permitted provided that the following conditions
  42. * are met:
  43. *
  44. * * Redistributions of source code must retain the above copyright
  45. * notice, this list of conditions and the following disclaimer.
  46. * * Redistributions in binary form must reproduce the above copyright
  47. * notice, this list of conditions and the following disclaimer in
  48. * the documentation and/or other materials provided with the
  49. * distribution.
  50. * * Neither the name Intel Corporation nor the names of its
  51. * contributors may be used to endorse or promote products derived
  52. * from this software without specific prior written permission.
  53. *
  54. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65. *
  66. *****************************************************************************/
  67. #include <net/mac80211.h>
  68. #include "iwl-debug.h"
  69. #include "iwl-io.h"
  70. #include "iwl-prph.h"
  71. #include "iwl-csr.h"
  72. #include "mvm.h"
  73. #include "fw/api/rs.h"
  74. /*
  75. * Will return 0 even if the cmd failed when RFKILL is asserted unless
  76. * CMD_WANT_SKB is set in cmd->flags.
  77. */
  78. int iwl_mvm_send_cmd(struct iwl_mvm *mvm, struct iwl_host_cmd *cmd)
  79. {
  80. int ret;
  81. #if defined(CONFIG_IWLWIFI_DEBUGFS) && defined(CONFIG_PM_SLEEP)
  82. if (WARN_ON(mvm->d3_test_active))
  83. return -EIO;
  84. #endif
  85. /*
  86. * Synchronous commands from this op-mode must hold
  87. * the mutex, this ensures we don't try to send two
  88. * (or more) synchronous commands at a time.
  89. */
  90. if (!(cmd->flags & CMD_ASYNC)) {
  91. lockdep_assert_held(&mvm->mutex);
  92. if (!(cmd->flags & CMD_SEND_IN_IDLE))
  93. iwl_mvm_ref(mvm, IWL_MVM_REF_SENDING_CMD);
  94. }
  95. ret = iwl_trans_send_cmd(mvm->trans, cmd);
  96. if (!(cmd->flags & (CMD_ASYNC | CMD_SEND_IN_IDLE)))
  97. iwl_mvm_unref(mvm, IWL_MVM_REF_SENDING_CMD);
  98. /*
  99. * If the caller wants the SKB, then don't hide any problems, the
  100. * caller might access the response buffer which will be NULL if
  101. * the command failed.
  102. */
  103. if (cmd->flags & CMD_WANT_SKB)
  104. return ret;
  105. /* Silently ignore failures if RFKILL is asserted */
  106. if (!ret || ret == -ERFKILL)
  107. return 0;
  108. return ret;
  109. }
  110. int iwl_mvm_send_cmd_pdu(struct iwl_mvm *mvm, u32 id,
  111. u32 flags, u16 len, const void *data)
  112. {
  113. struct iwl_host_cmd cmd = {
  114. .id = id,
  115. .len = { len, },
  116. .data = { data, },
  117. .flags = flags,
  118. };
  119. return iwl_mvm_send_cmd(mvm, &cmd);
  120. }
  121. /*
  122. * We assume that the caller set the status to the success value
  123. */
  124. int iwl_mvm_send_cmd_status(struct iwl_mvm *mvm, struct iwl_host_cmd *cmd,
  125. u32 *status)
  126. {
  127. struct iwl_rx_packet *pkt;
  128. struct iwl_cmd_response *resp;
  129. int ret, resp_len;
  130. lockdep_assert_held(&mvm->mutex);
  131. #if defined(CONFIG_IWLWIFI_DEBUGFS) && defined(CONFIG_PM_SLEEP)
  132. if (WARN_ON(mvm->d3_test_active))
  133. return -EIO;
  134. #endif
  135. /*
  136. * Only synchronous commands can wait for status,
  137. * we use WANT_SKB so the caller can't.
  138. */
  139. if (WARN_ONCE(cmd->flags & (CMD_ASYNC | CMD_WANT_SKB),
  140. "cmd flags %x", cmd->flags))
  141. return -EINVAL;
  142. cmd->flags |= CMD_WANT_SKB;
  143. ret = iwl_trans_send_cmd(mvm->trans, cmd);
  144. if (ret == -ERFKILL) {
  145. /*
  146. * The command failed because of RFKILL, don't update
  147. * the status, leave it as success and return 0.
  148. */
  149. return 0;
  150. } else if (ret) {
  151. return ret;
  152. }
  153. pkt = cmd->resp_pkt;
  154. resp_len = iwl_rx_packet_payload_len(pkt);
  155. if (WARN_ON_ONCE(resp_len != sizeof(*resp))) {
  156. ret = -EIO;
  157. goto out_free_resp;
  158. }
  159. resp = (void *)pkt->data;
  160. *status = le32_to_cpu(resp->status);
  161. out_free_resp:
  162. iwl_free_resp(cmd);
  163. return ret;
  164. }
  165. /*
  166. * We assume that the caller set the status to the sucess value
  167. */
  168. int iwl_mvm_send_cmd_pdu_status(struct iwl_mvm *mvm, u32 id, u16 len,
  169. const void *data, u32 *status)
  170. {
  171. struct iwl_host_cmd cmd = {
  172. .id = id,
  173. .len = { len, },
  174. .data = { data, },
  175. };
  176. return iwl_mvm_send_cmd_status(mvm, &cmd, status);
  177. }
  178. #define IWL_DECLARE_RATE_INFO(r) \
  179. [IWL_RATE_##r##M_INDEX] = IWL_RATE_##r##M_PLCP
  180. /*
  181. * Translate from fw_rate_index (IWL_RATE_XXM_INDEX) to PLCP
  182. */
  183. static const u8 fw_rate_idx_to_plcp[IWL_RATE_COUNT] = {
  184. IWL_DECLARE_RATE_INFO(1),
  185. IWL_DECLARE_RATE_INFO(2),
  186. IWL_DECLARE_RATE_INFO(5),
  187. IWL_DECLARE_RATE_INFO(11),
  188. IWL_DECLARE_RATE_INFO(6),
  189. IWL_DECLARE_RATE_INFO(9),
  190. IWL_DECLARE_RATE_INFO(12),
  191. IWL_DECLARE_RATE_INFO(18),
  192. IWL_DECLARE_RATE_INFO(24),
  193. IWL_DECLARE_RATE_INFO(36),
  194. IWL_DECLARE_RATE_INFO(48),
  195. IWL_DECLARE_RATE_INFO(54),
  196. };
  197. int iwl_mvm_legacy_rate_to_mac80211_idx(u32 rate_n_flags,
  198. enum nl80211_band band)
  199. {
  200. int rate = rate_n_flags & RATE_LEGACY_RATE_MSK;
  201. int idx;
  202. int band_offset = 0;
  203. /* Legacy rate format, search for match in table */
  204. if (band == NL80211_BAND_5GHZ)
  205. band_offset = IWL_FIRST_OFDM_RATE;
  206. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  207. if (fw_rate_idx_to_plcp[idx] == rate)
  208. return idx - band_offset;
  209. return -1;
  210. }
  211. u8 iwl_mvm_mac80211_idx_to_hwrate(int rate_idx)
  212. {
  213. /* Get PLCP rate for tx_cmd->rate_n_flags */
  214. return fw_rate_idx_to_plcp[rate_idx];
  215. }
  216. void iwl_mvm_rx_fw_error(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb)
  217. {
  218. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  219. struct iwl_error_resp *err_resp = (void *)pkt->data;
  220. IWL_ERR(mvm, "FW Error notification: type 0x%08X cmd_id 0x%02X\n",
  221. le32_to_cpu(err_resp->error_type), err_resp->cmd_id);
  222. IWL_ERR(mvm, "FW Error notification: seq 0x%04X service 0x%08X\n",
  223. le16_to_cpu(err_resp->bad_cmd_seq_num),
  224. le32_to_cpu(err_resp->error_service));
  225. IWL_ERR(mvm, "FW Error notification: timestamp 0x%16llX\n",
  226. le64_to_cpu(err_resp->timestamp));
  227. }
  228. /*
  229. * Returns the first antenna as ANT_[ABC], as defined in iwl-config.h.
  230. * The parameter should also be a combination of ANT_[ABC].
  231. */
  232. u8 first_antenna(u8 mask)
  233. {
  234. BUILD_BUG_ON(ANT_A != BIT(0)); /* using ffs is wrong if not */
  235. if (WARN_ON_ONCE(!mask)) /* ffs will return 0 if mask is zeroed */
  236. return BIT(0);
  237. return BIT(ffs(mask) - 1);
  238. }
  239. /*
  240. * Toggles between TX antennas to send the probe request on.
  241. * Receives the bitmask of valid TX antennas and the *index* used
  242. * for the last TX, and returns the next valid *index* to use.
  243. * In order to set it in the tx_cmd, must do BIT(idx).
  244. */
  245. u8 iwl_mvm_next_antenna(struct iwl_mvm *mvm, u8 valid, u8 last_idx)
  246. {
  247. u8 ind = last_idx;
  248. int i;
  249. for (i = 0; i < MAX_RS_ANT_NUM; i++) {
  250. ind = (ind + 1) % MAX_RS_ANT_NUM;
  251. if (valid & BIT(ind))
  252. return ind;
  253. }
  254. WARN_ONCE(1, "Failed to toggle between antennas 0x%x", valid);
  255. return last_idx;
  256. }
  257. static const struct {
  258. const char *name;
  259. u8 num;
  260. } advanced_lookup[] = {
  261. { "NMI_INTERRUPT_WDG", 0x34 },
  262. { "SYSASSERT", 0x35 },
  263. { "UCODE_VERSION_MISMATCH", 0x37 },
  264. { "BAD_COMMAND", 0x38 },
  265. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  266. { "FATAL_ERROR", 0x3D },
  267. { "NMI_TRM_HW_ERR", 0x46 },
  268. { "NMI_INTERRUPT_TRM", 0x4C },
  269. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  270. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  271. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  272. { "NMI_INTERRUPT_HOST", 0x66 },
  273. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  274. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  275. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  276. { "ADVANCED_SYSASSERT", 0 },
  277. };
  278. static const char *desc_lookup(u32 num)
  279. {
  280. int i;
  281. for (i = 0; i < ARRAY_SIZE(advanced_lookup) - 1; i++)
  282. if (advanced_lookup[i].num == num)
  283. return advanced_lookup[i].name;
  284. /* No entry matches 'num', so it is the last: ADVANCED_SYSASSERT */
  285. return advanced_lookup[i].name;
  286. }
  287. /*
  288. * Note: This structure is read from the device with IO accesses,
  289. * and the reading already does the endian conversion. As it is
  290. * read with u32-sized accesses, any members with a different size
  291. * need to be ordered correctly though!
  292. */
  293. struct iwl_error_event_table_v1 {
  294. u32 valid; /* (nonzero) valid, (0) log is empty */
  295. u32 error_id; /* type of error */
  296. u32 pc; /* program counter */
  297. u32 blink1; /* branch link */
  298. u32 blink2; /* branch link */
  299. u32 ilink1; /* interrupt link */
  300. u32 ilink2; /* interrupt link */
  301. u32 data1; /* error-specific data */
  302. u32 data2; /* error-specific data */
  303. u32 data3; /* error-specific data */
  304. u32 bcon_time; /* beacon timer */
  305. u32 tsf_low; /* network timestamp function timer */
  306. u32 tsf_hi; /* network timestamp function timer */
  307. u32 gp1; /* GP1 timer register */
  308. u32 gp2; /* GP2 timer register */
  309. u32 gp3; /* GP3 timer register */
  310. u32 ucode_ver; /* uCode version */
  311. u32 hw_ver; /* HW Silicon version */
  312. u32 brd_ver; /* HW board version */
  313. u32 log_pc; /* log program counter */
  314. u32 frame_ptr; /* frame pointer */
  315. u32 stack_ptr; /* stack pointer */
  316. u32 hcmd; /* last host command header */
  317. u32 isr0; /* isr status register LMPM_NIC_ISR0:
  318. * rxtx_flag */
  319. u32 isr1; /* isr status register LMPM_NIC_ISR1:
  320. * host_flag */
  321. u32 isr2; /* isr status register LMPM_NIC_ISR2:
  322. * enc_flag */
  323. u32 isr3; /* isr status register LMPM_NIC_ISR3:
  324. * time_flag */
  325. u32 isr4; /* isr status register LMPM_NIC_ISR4:
  326. * wico interrupt */
  327. u32 isr_pref; /* isr status register LMPM_NIC_PREF_STAT */
  328. u32 wait_event; /* wait event() caller address */
  329. u32 l2p_control; /* L2pControlField */
  330. u32 l2p_duration; /* L2pDurationField */
  331. u32 l2p_mhvalid; /* L2pMhValidBits */
  332. u32 l2p_addr_match; /* L2pAddrMatchStat */
  333. u32 lmpm_pmg_sel; /* indicate which clocks are turned on
  334. * (LMPM_PMG_SEL) */
  335. u32 u_timestamp; /* indicate when the date and time of the
  336. * compilation */
  337. u32 flow_handler; /* FH read/write pointers, RX credit */
  338. } __packed /* LOG_ERROR_TABLE_API_S_VER_1 */;
  339. struct iwl_error_event_table {
  340. u32 valid; /* (nonzero) valid, (0) log is empty */
  341. u32 error_id; /* type of error */
  342. u32 trm_hw_status0; /* TRM HW status */
  343. u32 trm_hw_status1; /* TRM HW status */
  344. u32 blink2; /* branch link */
  345. u32 ilink1; /* interrupt link */
  346. u32 ilink2; /* interrupt link */
  347. u32 data1; /* error-specific data */
  348. u32 data2; /* error-specific data */
  349. u32 data3; /* error-specific data */
  350. u32 bcon_time; /* beacon timer */
  351. u32 tsf_low; /* network timestamp function timer */
  352. u32 tsf_hi; /* network timestamp function timer */
  353. u32 gp1; /* GP1 timer register */
  354. u32 gp2; /* GP2 timer register */
  355. u32 fw_rev_type; /* firmware revision type */
  356. u32 major; /* uCode version major */
  357. u32 minor; /* uCode version minor */
  358. u32 hw_ver; /* HW Silicon version */
  359. u32 brd_ver; /* HW board version */
  360. u32 log_pc; /* log program counter */
  361. u32 frame_ptr; /* frame pointer */
  362. u32 stack_ptr; /* stack pointer */
  363. u32 hcmd; /* last host command header */
  364. u32 isr0; /* isr status register LMPM_NIC_ISR0:
  365. * rxtx_flag */
  366. u32 isr1; /* isr status register LMPM_NIC_ISR1:
  367. * host_flag */
  368. u32 isr2; /* isr status register LMPM_NIC_ISR2:
  369. * enc_flag */
  370. u32 isr3; /* isr status register LMPM_NIC_ISR3:
  371. * time_flag */
  372. u32 isr4; /* isr status register LMPM_NIC_ISR4:
  373. * wico interrupt */
  374. u32 last_cmd_id; /* last HCMD id handled by the firmware */
  375. u32 wait_event; /* wait event() caller address */
  376. u32 l2p_control; /* L2pControlField */
  377. u32 l2p_duration; /* L2pDurationField */
  378. u32 l2p_mhvalid; /* L2pMhValidBits */
  379. u32 l2p_addr_match; /* L2pAddrMatchStat */
  380. u32 lmpm_pmg_sel; /* indicate which clocks are turned on
  381. * (LMPM_PMG_SEL) */
  382. u32 u_timestamp; /* indicate when the date and time of the
  383. * compilation */
  384. u32 flow_handler; /* FH read/write pointers, RX credit */
  385. } __packed /* LOG_ERROR_TABLE_API_S_VER_3 */;
  386. /*
  387. * UMAC error struct - relevant starting from family 8000 chip.
  388. * Note: This structure is read from the device with IO accesses,
  389. * and the reading already does the endian conversion. As it is
  390. * read with u32-sized accesses, any members with a different size
  391. * need to be ordered correctly though!
  392. */
  393. struct iwl_umac_error_event_table {
  394. u32 valid; /* (nonzero) valid, (0) log is empty */
  395. u32 error_id; /* type of error */
  396. u32 blink1; /* branch link */
  397. u32 blink2; /* branch link */
  398. u32 ilink1; /* interrupt link */
  399. u32 ilink2; /* interrupt link */
  400. u32 data1; /* error-specific data */
  401. u32 data2; /* error-specific data */
  402. u32 data3; /* error-specific data */
  403. u32 umac_major;
  404. u32 umac_minor;
  405. u32 frame_pointer; /* core register 27*/
  406. u32 stack_pointer; /* core register 28 */
  407. u32 cmd_header; /* latest host cmd sent to UMAC */
  408. u32 nic_isr_pref; /* ISR status register */
  409. } __packed;
  410. #define ERROR_START_OFFSET (1 * sizeof(u32))
  411. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  412. static void iwl_mvm_dump_umac_error_log(struct iwl_mvm *mvm)
  413. {
  414. struct iwl_trans *trans = mvm->trans;
  415. struct iwl_umac_error_event_table table;
  416. if (!mvm->support_umac_log)
  417. return;
  418. iwl_trans_read_mem_bytes(trans, mvm->umac_error_event_table, &table,
  419. sizeof(table));
  420. if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
  421. IWL_ERR(trans, "Start IWL Error Log Dump:\n");
  422. IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
  423. mvm->status, table.valid);
  424. }
  425. IWL_ERR(mvm, "0x%08X | %s\n", table.error_id,
  426. desc_lookup(table.error_id));
  427. IWL_ERR(mvm, "0x%08X | umac branchlink1\n", table.blink1);
  428. IWL_ERR(mvm, "0x%08X | umac branchlink2\n", table.blink2);
  429. IWL_ERR(mvm, "0x%08X | umac interruptlink1\n", table.ilink1);
  430. IWL_ERR(mvm, "0x%08X | umac interruptlink2\n", table.ilink2);
  431. IWL_ERR(mvm, "0x%08X | umac data1\n", table.data1);
  432. IWL_ERR(mvm, "0x%08X | umac data2\n", table.data2);
  433. IWL_ERR(mvm, "0x%08X | umac data3\n", table.data3);
  434. IWL_ERR(mvm, "0x%08X | umac major\n", table.umac_major);
  435. IWL_ERR(mvm, "0x%08X | umac minor\n", table.umac_minor);
  436. IWL_ERR(mvm, "0x%08X | frame pointer\n", table.frame_pointer);
  437. IWL_ERR(mvm, "0x%08X | stack pointer\n", table.stack_pointer);
  438. IWL_ERR(mvm, "0x%08X | last host cmd\n", table.cmd_header);
  439. IWL_ERR(mvm, "0x%08X | isr status reg\n", table.nic_isr_pref);
  440. }
  441. static void iwl_mvm_dump_lmac_error_log(struct iwl_mvm *mvm, u32 base)
  442. {
  443. struct iwl_trans *trans = mvm->trans;
  444. struct iwl_error_event_table table;
  445. u32 val;
  446. if (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT) {
  447. if (!base)
  448. base = mvm->fw->init_errlog_ptr;
  449. } else {
  450. if (!base)
  451. base = mvm->fw->inst_errlog_ptr;
  452. }
  453. if (base < 0x400000) {
  454. IWL_ERR(mvm,
  455. "Not valid error log pointer 0x%08X for %s uCode\n",
  456. base,
  457. (mvm->fwrt.cur_fw_img == IWL_UCODE_INIT)
  458. ? "Init" : "RT");
  459. return;
  460. }
  461. /* check if there is a HW error */
  462. val = iwl_trans_read_mem32(trans, base);
  463. if (((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50)) {
  464. int err;
  465. IWL_ERR(trans, "HW error, resetting before reading\n");
  466. /* reset the device */
  467. iwl_trans_sw_reset(trans);
  468. /* set INIT_DONE flag */
  469. iwl_set_bit(trans, CSR_GP_CNTRL,
  470. CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  471. /* and wait for clock stabilization */
  472. if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
  473. udelay(2);
  474. err = iwl_poll_bit(trans, CSR_GP_CNTRL,
  475. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  476. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  477. 25000);
  478. if (err < 0) {
  479. IWL_DEBUG_INFO(trans,
  480. "Failed to reset the card for the dump\n");
  481. return;
  482. }
  483. }
  484. iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
  485. if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
  486. IWL_ERR(trans, "Start IWL Error Log Dump:\n");
  487. IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
  488. mvm->status, table.valid);
  489. }
  490. /* Do not change this output - scripts rely on it */
  491. IWL_ERR(mvm, "Loaded firmware version: %s\n", mvm->fw->fw_version);
  492. trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
  493. table.data1, table.data2, table.data3,
  494. table.blink2, table.ilink1,
  495. table.ilink2, table.bcon_time, table.gp1,
  496. table.gp2, table.fw_rev_type, table.major,
  497. table.minor, table.hw_ver, table.brd_ver);
  498. IWL_ERR(mvm, "0x%08X | %-28s\n", table.error_id,
  499. desc_lookup(table.error_id));
  500. IWL_ERR(mvm, "0x%08X | trm_hw_status0\n", table.trm_hw_status0);
  501. IWL_ERR(mvm, "0x%08X | trm_hw_status1\n", table.trm_hw_status1);
  502. IWL_ERR(mvm, "0x%08X | branchlink2\n", table.blink2);
  503. IWL_ERR(mvm, "0x%08X | interruptlink1\n", table.ilink1);
  504. IWL_ERR(mvm, "0x%08X | interruptlink2\n", table.ilink2);
  505. IWL_ERR(mvm, "0x%08X | data1\n", table.data1);
  506. IWL_ERR(mvm, "0x%08X | data2\n", table.data2);
  507. IWL_ERR(mvm, "0x%08X | data3\n", table.data3);
  508. IWL_ERR(mvm, "0x%08X | beacon time\n", table.bcon_time);
  509. IWL_ERR(mvm, "0x%08X | tsf low\n", table.tsf_low);
  510. IWL_ERR(mvm, "0x%08X | tsf hi\n", table.tsf_hi);
  511. IWL_ERR(mvm, "0x%08X | time gp1\n", table.gp1);
  512. IWL_ERR(mvm, "0x%08X | time gp2\n", table.gp2);
  513. IWL_ERR(mvm, "0x%08X | uCode revision type\n", table.fw_rev_type);
  514. IWL_ERR(mvm, "0x%08X | uCode version major\n", table.major);
  515. IWL_ERR(mvm, "0x%08X | uCode version minor\n", table.minor);
  516. IWL_ERR(mvm, "0x%08X | hw version\n", table.hw_ver);
  517. IWL_ERR(mvm, "0x%08X | board version\n", table.brd_ver);
  518. IWL_ERR(mvm, "0x%08X | hcmd\n", table.hcmd);
  519. IWL_ERR(mvm, "0x%08X | isr0\n", table.isr0);
  520. IWL_ERR(mvm, "0x%08X | isr1\n", table.isr1);
  521. IWL_ERR(mvm, "0x%08X | isr2\n", table.isr2);
  522. IWL_ERR(mvm, "0x%08X | isr3\n", table.isr3);
  523. IWL_ERR(mvm, "0x%08X | isr4\n", table.isr4);
  524. IWL_ERR(mvm, "0x%08X | last cmd Id\n", table.last_cmd_id);
  525. IWL_ERR(mvm, "0x%08X | wait_event\n", table.wait_event);
  526. IWL_ERR(mvm, "0x%08X | l2p_control\n", table.l2p_control);
  527. IWL_ERR(mvm, "0x%08X | l2p_duration\n", table.l2p_duration);
  528. IWL_ERR(mvm, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
  529. IWL_ERR(mvm, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
  530. IWL_ERR(mvm, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
  531. IWL_ERR(mvm, "0x%08X | timestamp\n", table.u_timestamp);
  532. IWL_ERR(mvm, "0x%08X | flow_handler\n", table.flow_handler);
  533. }
  534. void iwl_mvm_dump_nic_error_log(struct iwl_mvm *mvm)
  535. {
  536. if (!test_bit(STATUS_DEVICE_ENABLED, &mvm->trans->status)) {
  537. IWL_ERR(mvm,
  538. "DEVICE_ENABLED bit is not set. Aborting dump.\n");
  539. return;
  540. }
  541. iwl_mvm_dump_lmac_error_log(mvm, mvm->error_event_table[0]);
  542. if (mvm->error_event_table[1])
  543. iwl_mvm_dump_lmac_error_log(mvm, mvm->error_event_table[1]);
  544. iwl_mvm_dump_umac_error_log(mvm);
  545. }
  546. int iwl_mvm_find_free_queue(struct iwl_mvm *mvm, u8 sta_id, u8 minq, u8 maxq)
  547. {
  548. int i;
  549. lockdep_assert_held(&mvm->queue_info_lock);
  550. /* This should not be hit with new TX path */
  551. if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
  552. return -ENOSPC;
  553. /* Start by looking for a free queue */
  554. for (i = minq; i <= maxq; i++)
  555. if (mvm->queue_info[i].hw_queue_refcount == 0 &&
  556. mvm->queue_info[i].status == IWL_MVM_QUEUE_FREE)
  557. return i;
  558. /*
  559. * If no free queue found - settle for an inactive one to reconfigure
  560. * Make sure that the inactive queue either already belongs to this STA,
  561. * or that if it belongs to another one - it isn't the reserved queue
  562. */
  563. for (i = minq; i <= maxq; i++)
  564. if (mvm->queue_info[i].status == IWL_MVM_QUEUE_INACTIVE &&
  565. (sta_id == mvm->queue_info[i].ra_sta_id ||
  566. !mvm->queue_info[i].reserved))
  567. return i;
  568. return -ENOSPC;
  569. }
  570. int iwl_mvm_reconfig_scd(struct iwl_mvm *mvm, int queue, int fifo, int sta_id,
  571. int tid, int frame_limit, u16 ssn)
  572. {
  573. struct iwl_scd_txq_cfg_cmd cmd = {
  574. .scd_queue = queue,
  575. .action = SCD_CFG_ENABLE_QUEUE,
  576. .window = frame_limit,
  577. .sta_id = sta_id,
  578. .ssn = cpu_to_le16(ssn),
  579. .tx_fifo = fifo,
  580. .aggregate = (queue >= IWL_MVM_DQA_MIN_DATA_QUEUE ||
  581. queue == IWL_MVM_DQA_BSS_CLIENT_QUEUE),
  582. .tid = tid,
  583. };
  584. int ret;
  585. if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
  586. return -EINVAL;
  587. spin_lock_bh(&mvm->queue_info_lock);
  588. if (WARN(mvm->queue_info[queue].hw_queue_refcount == 0,
  589. "Trying to reconfig unallocated queue %d\n", queue)) {
  590. spin_unlock_bh(&mvm->queue_info_lock);
  591. return -ENXIO;
  592. }
  593. spin_unlock_bh(&mvm->queue_info_lock);
  594. IWL_DEBUG_TX_QUEUES(mvm, "Reconfig SCD for TXQ #%d\n", queue);
  595. ret = iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, 0, sizeof(cmd), &cmd);
  596. WARN_ONCE(ret, "Failed to re-configure queue %d on FIFO %d, ret=%d\n",
  597. queue, fifo, ret);
  598. return ret;
  599. }
  600. static bool iwl_mvm_update_txq_mapping(struct iwl_mvm *mvm, int queue,
  601. int mac80211_queue, u8 sta_id, u8 tid)
  602. {
  603. bool enable_queue = true;
  604. spin_lock_bh(&mvm->queue_info_lock);
  605. /* Make sure this TID isn't already enabled */
  606. if (mvm->queue_info[queue].tid_bitmap & BIT(tid)) {
  607. spin_unlock_bh(&mvm->queue_info_lock);
  608. IWL_ERR(mvm, "Trying to enable TXQ %d with existing TID %d\n",
  609. queue, tid);
  610. return false;
  611. }
  612. /* Update mappings and refcounts */
  613. if (mvm->queue_info[queue].hw_queue_refcount > 0)
  614. enable_queue = false;
  615. if (mac80211_queue != IEEE80211_INVAL_HW_QUEUE) {
  616. WARN(mac80211_queue >=
  617. BITS_PER_BYTE * sizeof(mvm->hw_queue_to_mac80211[0]),
  618. "cannot track mac80211 queue %d (queue %d, sta %d, tid %d)\n",
  619. mac80211_queue, queue, sta_id, tid);
  620. mvm->hw_queue_to_mac80211[queue] |= BIT(mac80211_queue);
  621. }
  622. mvm->queue_info[queue].hw_queue_refcount++;
  623. mvm->queue_info[queue].tid_bitmap |= BIT(tid);
  624. mvm->queue_info[queue].ra_sta_id = sta_id;
  625. if (enable_queue) {
  626. if (tid != IWL_MAX_TID_COUNT)
  627. mvm->queue_info[queue].mac80211_ac =
  628. tid_to_mac80211_ac[tid];
  629. else
  630. mvm->queue_info[queue].mac80211_ac = IEEE80211_AC_VO;
  631. mvm->queue_info[queue].txq_tid = tid;
  632. }
  633. IWL_DEBUG_TX_QUEUES(mvm,
  634. "Enabling TXQ #%d refcount=%d (mac80211 map:0x%x)\n",
  635. queue, mvm->queue_info[queue].hw_queue_refcount,
  636. mvm->hw_queue_to_mac80211[queue]);
  637. spin_unlock_bh(&mvm->queue_info_lock);
  638. return enable_queue;
  639. }
  640. int iwl_mvm_tvqm_enable_txq(struct iwl_mvm *mvm, int mac80211_queue,
  641. u8 sta_id, u8 tid, unsigned int timeout)
  642. {
  643. struct iwl_tx_queue_cfg_cmd cmd = {
  644. .flags = cpu_to_le16(TX_QUEUE_CFG_ENABLE_QUEUE),
  645. .sta_id = sta_id,
  646. .tid = tid,
  647. };
  648. int queue;
  649. if (cmd.tid == IWL_MAX_TID_COUNT)
  650. cmd.tid = IWL_MGMT_TID;
  651. queue = iwl_trans_txq_alloc(mvm->trans, (void *)&cmd,
  652. SCD_QUEUE_CFG, timeout);
  653. if (queue < 0) {
  654. IWL_DEBUG_TX_QUEUES(mvm,
  655. "Failed allocating TXQ for sta %d tid %d, ret: %d\n",
  656. sta_id, tid, queue);
  657. return queue;
  658. }
  659. IWL_DEBUG_TX_QUEUES(mvm, "Enabling TXQ #%d for sta %d tid %d\n",
  660. queue, sta_id, tid);
  661. mvm->hw_queue_to_mac80211[queue] |= BIT(mac80211_queue);
  662. IWL_DEBUG_TX_QUEUES(mvm,
  663. "Enabling TXQ #%d (mac80211 map:0x%x)\n",
  664. queue, mvm->hw_queue_to_mac80211[queue]);
  665. return queue;
  666. }
  667. bool iwl_mvm_enable_txq(struct iwl_mvm *mvm, int queue, int mac80211_queue,
  668. u16 ssn, const struct iwl_trans_txq_scd_cfg *cfg,
  669. unsigned int wdg_timeout)
  670. {
  671. struct iwl_scd_txq_cfg_cmd cmd = {
  672. .scd_queue = queue,
  673. .action = SCD_CFG_ENABLE_QUEUE,
  674. .window = cfg->frame_limit,
  675. .sta_id = cfg->sta_id,
  676. .ssn = cpu_to_le16(ssn),
  677. .tx_fifo = cfg->fifo,
  678. .aggregate = cfg->aggregate,
  679. .tid = cfg->tid,
  680. };
  681. bool inc_ssn;
  682. if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
  683. return false;
  684. /* Send the enabling command if we need to */
  685. if (!iwl_mvm_update_txq_mapping(mvm, queue, mac80211_queue,
  686. cfg->sta_id, cfg->tid))
  687. return false;
  688. inc_ssn = iwl_trans_txq_enable_cfg(mvm->trans, queue, ssn,
  689. NULL, wdg_timeout);
  690. if (inc_ssn)
  691. le16_add_cpu(&cmd.ssn, 1);
  692. WARN(iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, 0, sizeof(cmd), &cmd),
  693. "Failed to configure queue %d on FIFO %d\n", queue, cfg->fifo);
  694. return inc_ssn;
  695. }
  696. int iwl_mvm_disable_txq(struct iwl_mvm *mvm, int queue, int mac80211_queue,
  697. u8 tid, u8 flags)
  698. {
  699. struct iwl_scd_txq_cfg_cmd cmd = {
  700. .scd_queue = queue,
  701. .action = SCD_CFG_DISABLE_QUEUE,
  702. };
  703. bool remove_mac_queue = true;
  704. int ret;
  705. if (iwl_mvm_has_new_tx_api(mvm)) {
  706. spin_lock_bh(&mvm->queue_info_lock);
  707. mvm->hw_queue_to_mac80211[queue] &= ~BIT(mac80211_queue);
  708. spin_unlock_bh(&mvm->queue_info_lock);
  709. iwl_trans_txq_free(mvm->trans, queue);
  710. return 0;
  711. }
  712. spin_lock_bh(&mvm->queue_info_lock);
  713. if (WARN_ON(mvm->queue_info[queue].hw_queue_refcount == 0)) {
  714. spin_unlock_bh(&mvm->queue_info_lock);
  715. return 0;
  716. }
  717. mvm->queue_info[queue].tid_bitmap &= ~BIT(tid);
  718. /*
  719. * If there is another TID with the same AC - don't remove the MAC queue
  720. * from the mapping
  721. */
  722. if (tid < IWL_MAX_TID_COUNT) {
  723. unsigned long tid_bitmap =
  724. mvm->queue_info[queue].tid_bitmap;
  725. int ac = tid_to_mac80211_ac[tid];
  726. int i;
  727. for_each_set_bit(i, &tid_bitmap, IWL_MAX_TID_COUNT) {
  728. if (tid_to_mac80211_ac[i] == ac)
  729. remove_mac_queue = false;
  730. }
  731. }
  732. if (remove_mac_queue)
  733. mvm->hw_queue_to_mac80211[queue] &=
  734. ~BIT(mac80211_queue);
  735. mvm->queue_info[queue].hw_queue_refcount--;
  736. cmd.action = mvm->queue_info[queue].hw_queue_refcount ?
  737. SCD_CFG_ENABLE_QUEUE : SCD_CFG_DISABLE_QUEUE;
  738. if (cmd.action == SCD_CFG_DISABLE_QUEUE)
  739. mvm->queue_info[queue].status = IWL_MVM_QUEUE_FREE;
  740. IWL_DEBUG_TX_QUEUES(mvm,
  741. "Disabling TXQ #%d refcount=%d (mac80211 map:0x%x)\n",
  742. queue,
  743. mvm->queue_info[queue].hw_queue_refcount,
  744. mvm->hw_queue_to_mac80211[queue]);
  745. /* If the queue is still enabled - nothing left to do in this func */
  746. if (cmd.action == SCD_CFG_ENABLE_QUEUE) {
  747. spin_unlock_bh(&mvm->queue_info_lock);
  748. return 0;
  749. }
  750. cmd.sta_id = mvm->queue_info[queue].ra_sta_id;
  751. cmd.tid = mvm->queue_info[queue].txq_tid;
  752. /* Make sure queue info is correct even though we overwrite it */
  753. WARN(mvm->queue_info[queue].hw_queue_refcount ||
  754. mvm->queue_info[queue].tid_bitmap ||
  755. mvm->hw_queue_to_mac80211[queue],
  756. "TXQ #%d info out-of-sync - refcount=%d, mac map=0x%x, tid=0x%x\n",
  757. queue, mvm->queue_info[queue].hw_queue_refcount,
  758. mvm->hw_queue_to_mac80211[queue],
  759. mvm->queue_info[queue].tid_bitmap);
  760. /* If we are here - the queue is freed and we can zero out these vals */
  761. mvm->queue_info[queue].hw_queue_refcount = 0;
  762. mvm->queue_info[queue].tid_bitmap = 0;
  763. mvm->hw_queue_to_mac80211[queue] = 0;
  764. /* Regardless if this is a reserved TXQ for a STA - mark it as false */
  765. mvm->queue_info[queue].reserved = false;
  766. spin_unlock_bh(&mvm->queue_info_lock);
  767. iwl_trans_txq_disable(mvm->trans, queue, false);
  768. ret = iwl_mvm_send_cmd_pdu(mvm, SCD_QUEUE_CFG, flags,
  769. sizeof(struct iwl_scd_txq_cfg_cmd), &cmd);
  770. if (ret)
  771. IWL_ERR(mvm, "Failed to disable queue %d (ret=%d)\n",
  772. queue, ret);
  773. return ret;
  774. }
  775. /**
  776. * iwl_mvm_send_lq_cmd() - Send link quality command
  777. * @init: This command is sent as part of station initialization right
  778. * after station has been added.
  779. *
  780. * The link quality command is sent as the last step of station creation.
  781. * This is the special case in which init is set and we call a callback in
  782. * this case to clear the state indicating that station creation is in
  783. * progress.
  784. */
  785. int iwl_mvm_send_lq_cmd(struct iwl_mvm *mvm, struct iwl_lq_cmd *lq, bool init)
  786. {
  787. struct iwl_host_cmd cmd = {
  788. .id = LQ_CMD,
  789. .len = { sizeof(struct iwl_lq_cmd), },
  790. .flags = init ? 0 : CMD_ASYNC,
  791. .data = { lq, },
  792. };
  793. if (WARN_ON(lq->sta_id == IWL_MVM_INVALID_STA ||
  794. iwl_mvm_has_tlc_offload(mvm)))
  795. return -EINVAL;
  796. return iwl_mvm_send_cmd(mvm, &cmd);
  797. }
  798. /**
  799. * iwl_mvm_update_smps - Get a request to change the SMPS mode
  800. * @req_type: The part of the driver who call for a change.
  801. * @smps_requests: The request to change the SMPS mode.
  802. *
  803. * Get a requst to change the SMPS mode,
  804. * and change it according to all other requests in the driver.
  805. */
  806. void iwl_mvm_update_smps(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
  807. enum iwl_mvm_smps_type_request req_type,
  808. enum ieee80211_smps_mode smps_request)
  809. {
  810. struct iwl_mvm_vif *mvmvif;
  811. enum ieee80211_smps_mode smps_mode;
  812. int i;
  813. lockdep_assert_held(&mvm->mutex);
  814. /* SMPS is irrelevant for NICs that don't have at least 2 RX antenna */
  815. if (num_of_ant(iwl_mvm_get_valid_rx_ant(mvm)) == 1)
  816. return;
  817. if (vif->type == NL80211_IFTYPE_AP)
  818. smps_mode = IEEE80211_SMPS_OFF;
  819. else
  820. smps_mode = IEEE80211_SMPS_AUTOMATIC;
  821. mvmvif = iwl_mvm_vif_from_mac80211(vif);
  822. mvmvif->smps_requests[req_type] = smps_request;
  823. for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
  824. if (mvmvif->smps_requests[i] == IEEE80211_SMPS_STATIC) {
  825. smps_mode = IEEE80211_SMPS_STATIC;
  826. break;
  827. }
  828. if (mvmvif->smps_requests[i] == IEEE80211_SMPS_DYNAMIC)
  829. smps_mode = IEEE80211_SMPS_DYNAMIC;
  830. }
  831. ieee80211_request_smps(vif, smps_mode);
  832. }
  833. int iwl_mvm_request_statistics(struct iwl_mvm *mvm, bool clear)
  834. {
  835. struct iwl_statistics_cmd scmd = {
  836. .flags = clear ? cpu_to_le32(IWL_STATISTICS_FLG_CLEAR) : 0,
  837. };
  838. struct iwl_host_cmd cmd = {
  839. .id = STATISTICS_CMD,
  840. .len[0] = sizeof(scmd),
  841. .data[0] = &scmd,
  842. .flags = CMD_WANT_SKB,
  843. };
  844. int ret;
  845. ret = iwl_mvm_send_cmd(mvm, &cmd);
  846. if (ret)
  847. return ret;
  848. iwl_mvm_handle_rx_statistics(mvm, cmd.resp_pkt);
  849. iwl_free_resp(&cmd);
  850. if (clear)
  851. iwl_mvm_accu_radio_stats(mvm);
  852. return 0;
  853. }
  854. void iwl_mvm_accu_radio_stats(struct iwl_mvm *mvm)
  855. {
  856. mvm->accu_radio_stats.rx_time += mvm->radio_stats.rx_time;
  857. mvm->accu_radio_stats.tx_time += mvm->radio_stats.tx_time;
  858. mvm->accu_radio_stats.on_time_rf += mvm->radio_stats.on_time_rf;
  859. mvm->accu_radio_stats.on_time_scan += mvm->radio_stats.on_time_scan;
  860. }
  861. static void iwl_mvm_diversity_iter(void *_data, u8 *mac,
  862. struct ieee80211_vif *vif)
  863. {
  864. struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
  865. bool *result = _data;
  866. int i;
  867. for (i = 0; i < NUM_IWL_MVM_SMPS_REQ; i++) {
  868. if (mvmvif->smps_requests[i] == IEEE80211_SMPS_STATIC ||
  869. mvmvif->smps_requests[i] == IEEE80211_SMPS_DYNAMIC)
  870. *result = false;
  871. }
  872. }
  873. bool iwl_mvm_rx_diversity_allowed(struct iwl_mvm *mvm)
  874. {
  875. bool result = true;
  876. lockdep_assert_held(&mvm->mutex);
  877. if (num_of_ant(iwl_mvm_get_valid_rx_ant(mvm)) == 1)
  878. return false;
  879. if (mvm->cfg->rx_with_siso_diversity)
  880. return false;
  881. ieee80211_iterate_active_interfaces_atomic(
  882. mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
  883. iwl_mvm_diversity_iter, &result);
  884. return result;
  885. }
  886. int iwl_mvm_update_low_latency(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
  887. bool prev)
  888. {
  889. struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif);
  890. int res;
  891. bool low_latency;
  892. lockdep_assert_held(&mvm->mutex);
  893. low_latency = iwl_mvm_vif_low_latency(mvmvif);
  894. if (low_latency == prev)
  895. return 0;
  896. if (fw_has_capa(&mvm->fw->ucode_capa,
  897. IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA)) {
  898. struct iwl_mac_low_latency_cmd cmd = {
  899. .mac_id = cpu_to_le32(mvmvif->id)
  900. };
  901. if (low_latency) {
  902. /* currently we don't care about the direction */
  903. cmd.low_latency_rx = 1;
  904. cmd.low_latency_tx = 1;
  905. }
  906. res = iwl_mvm_send_cmd_pdu(mvm,
  907. iwl_cmd_id(LOW_LATENCY_CMD,
  908. MAC_CONF_GROUP, 0),
  909. 0, sizeof(cmd), &cmd);
  910. if (res)
  911. IWL_ERR(mvm, "Failed to send low latency command\n");
  912. }
  913. res = iwl_mvm_update_quotas(mvm, false, NULL);
  914. if (res)
  915. return res;
  916. iwl_mvm_bt_coex_vif_change(mvm);
  917. return iwl_mvm_power_update_mac(mvm);
  918. }
  919. static void iwl_mvm_ll_iter(void *_data, u8 *mac, struct ieee80211_vif *vif)
  920. {
  921. bool *result = _data;
  922. if (iwl_mvm_vif_low_latency(iwl_mvm_vif_from_mac80211(vif)))
  923. *result = true;
  924. }
  925. bool iwl_mvm_low_latency(struct iwl_mvm *mvm)
  926. {
  927. bool result = false;
  928. ieee80211_iterate_active_interfaces_atomic(
  929. mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
  930. iwl_mvm_ll_iter, &result);
  931. return result;
  932. }
  933. struct iwl_bss_iter_data {
  934. struct ieee80211_vif *vif;
  935. bool error;
  936. };
  937. static void iwl_mvm_bss_iface_iterator(void *_data, u8 *mac,
  938. struct ieee80211_vif *vif)
  939. {
  940. struct iwl_bss_iter_data *data = _data;
  941. if (vif->type != NL80211_IFTYPE_STATION || vif->p2p)
  942. return;
  943. if (data->vif) {
  944. data->error = true;
  945. return;
  946. }
  947. data->vif = vif;
  948. }
  949. struct ieee80211_vif *iwl_mvm_get_bss_vif(struct iwl_mvm *mvm)
  950. {
  951. struct iwl_bss_iter_data bss_iter_data = {};
  952. ieee80211_iterate_active_interfaces_atomic(
  953. mvm->hw, IEEE80211_IFACE_ITER_NORMAL,
  954. iwl_mvm_bss_iface_iterator, &bss_iter_data);
  955. if (bss_iter_data.error) {
  956. IWL_ERR(mvm, "More than one managed interface active!\n");
  957. return ERR_PTR(-EINVAL);
  958. }
  959. return bss_iter_data.vif;
  960. }
  961. struct iwl_sta_iter_data {
  962. bool assoc;
  963. };
  964. static void iwl_mvm_sta_iface_iterator(void *_data, u8 *mac,
  965. struct ieee80211_vif *vif)
  966. {
  967. struct iwl_sta_iter_data *data = _data;
  968. if (vif->type != NL80211_IFTYPE_STATION)
  969. return;
  970. if (vif->bss_conf.assoc)
  971. data->assoc = true;
  972. }
  973. bool iwl_mvm_is_vif_assoc(struct iwl_mvm *mvm)
  974. {
  975. struct iwl_sta_iter_data data = {
  976. .assoc = false,
  977. };
  978. ieee80211_iterate_active_interfaces_atomic(mvm->hw,
  979. IEEE80211_IFACE_ITER_NORMAL,
  980. iwl_mvm_sta_iface_iterator,
  981. &data);
  982. return data.assoc;
  983. }
  984. unsigned int iwl_mvm_get_wd_timeout(struct iwl_mvm *mvm,
  985. struct ieee80211_vif *vif,
  986. bool tdls, bool cmd_q)
  987. {
  988. struct iwl_fw_dbg_trigger_tlv *trigger;
  989. struct iwl_fw_dbg_trigger_txq_timer *txq_timer;
  990. unsigned int default_timeout =
  991. cmd_q ? IWL_DEF_WD_TIMEOUT : mvm->cfg->base_params->wd_timeout;
  992. if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS)) {
  993. /*
  994. * We can't know when the station is asleep or awake, so we
  995. * must disable the queue hang detection.
  996. */
  997. if (fw_has_capa(&mvm->fw->ucode_capa,
  998. IWL_UCODE_TLV_CAPA_STA_PM_NOTIF) &&
  999. vif && vif->type == NL80211_IFTYPE_AP)
  1000. return IWL_WATCHDOG_DISABLED;
  1001. return iwlmvm_mod_params.tfd_q_hang_detect ?
  1002. default_timeout : IWL_WATCHDOG_DISABLED;
  1003. }
  1004. trigger = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_TXQ_TIMERS);
  1005. txq_timer = (void *)trigger->data;
  1006. if (tdls)
  1007. return le32_to_cpu(txq_timer->tdls);
  1008. if (cmd_q)
  1009. return le32_to_cpu(txq_timer->command_queue);
  1010. if (WARN_ON(!vif))
  1011. return default_timeout;
  1012. switch (ieee80211_vif_type_p2p(vif)) {
  1013. case NL80211_IFTYPE_ADHOC:
  1014. return le32_to_cpu(txq_timer->ibss);
  1015. case NL80211_IFTYPE_STATION:
  1016. return le32_to_cpu(txq_timer->bss);
  1017. case NL80211_IFTYPE_AP:
  1018. return le32_to_cpu(txq_timer->softap);
  1019. case NL80211_IFTYPE_P2P_CLIENT:
  1020. return le32_to_cpu(txq_timer->p2p_client);
  1021. case NL80211_IFTYPE_P2P_GO:
  1022. return le32_to_cpu(txq_timer->p2p_go);
  1023. case NL80211_IFTYPE_P2P_DEVICE:
  1024. return le32_to_cpu(txq_timer->p2p_device);
  1025. case NL80211_IFTYPE_MONITOR:
  1026. return default_timeout;
  1027. default:
  1028. WARN_ON(1);
  1029. return mvm->cfg->base_params->wd_timeout;
  1030. }
  1031. }
  1032. void iwl_mvm_connection_loss(struct iwl_mvm *mvm, struct ieee80211_vif *vif,
  1033. const char *errmsg)
  1034. {
  1035. struct iwl_fw_dbg_trigger_tlv *trig;
  1036. struct iwl_fw_dbg_trigger_mlme *trig_mlme;
  1037. if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_MLME))
  1038. goto out;
  1039. trig = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_MLME);
  1040. trig_mlme = (void *)trig->data;
  1041. if (!iwl_fw_dbg_trigger_check_stop(&mvm->fwrt,
  1042. ieee80211_vif_to_wdev(vif), trig))
  1043. goto out;
  1044. if (trig_mlme->stop_connection_loss &&
  1045. --trig_mlme->stop_connection_loss)
  1046. goto out;
  1047. iwl_fw_dbg_collect_trig(&mvm->fwrt, trig, "%s", errmsg);
  1048. out:
  1049. ieee80211_connection_loss(vif);
  1050. }
  1051. /*
  1052. * Remove inactive TIDs of a given queue.
  1053. * If all queue TIDs are inactive - mark the queue as inactive
  1054. * If only some the queue TIDs are inactive - unmap them from the queue
  1055. */
  1056. static void iwl_mvm_remove_inactive_tids(struct iwl_mvm *mvm,
  1057. struct iwl_mvm_sta *mvmsta, int queue,
  1058. unsigned long tid_bitmap)
  1059. {
  1060. int tid;
  1061. lockdep_assert_held(&mvmsta->lock);
  1062. lockdep_assert_held(&mvm->queue_info_lock);
  1063. if (WARN_ON(iwl_mvm_has_new_tx_api(mvm)))
  1064. return;
  1065. /* Go over all non-active TIDs, incl. IWL_MAX_TID_COUNT (for mgmt) */
  1066. for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
  1067. /* If some TFDs are still queued - don't mark TID as inactive */
  1068. if (iwl_mvm_tid_queued(mvm, &mvmsta->tid_data[tid]))
  1069. tid_bitmap &= ~BIT(tid);
  1070. /* Don't mark as inactive any TID that has an active BA */
  1071. if (mvmsta->tid_data[tid].state != IWL_AGG_OFF)
  1072. tid_bitmap &= ~BIT(tid);
  1073. }
  1074. /* If all TIDs in the queue are inactive - mark queue as inactive. */
  1075. if (tid_bitmap == mvm->queue_info[queue].tid_bitmap) {
  1076. mvm->queue_info[queue].status = IWL_MVM_QUEUE_INACTIVE;
  1077. for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1)
  1078. mvmsta->tid_data[tid].is_tid_active = false;
  1079. IWL_DEBUG_TX_QUEUES(mvm, "Queue %d marked as inactive\n",
  1080. queue);
  1081. return;
  1082. }
  1083. /*
  1084. * If we are here, this is a shared queue and not all TIDs timed-out.
  1085. * Remove the ones that did.
  1086. */
  1087. for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
  1088. int mac_queue = mvmsta->vif->hw_queue[tid_to_mac80211_ac[tid]];
  1089. mvmsta->tid_data[tid].txq_id = IWL_MVM_INVALID_QUEUE;
  1090. mvm->hw_queue_to_mac80211[queue] &= ~BIT(mac_queue);
  1091. mvm->queue_info[queue].hw_queue_refcount--;
  1092. mvm->queue_info[queue].tid_bitmap &= ~BIT(tid);
  1093. mvmsta->tid_data[tid].is_tid_active = false;
  1094. IWL_DEBUG_TX_QUEUES(mvm,
  1095. "Removing inactive TID %d from shared Q:%d\n",
  1096. tid, queue);
  1097. }
  1098. IWL_DEBUG_TX_QUEUES(mvm,
  1099. "TXQ #%d left with tid bitmap 0x%x\n", queue,
  1100. mvm->queue_info[queue].tid_bitmap);
  1101. /*
  1102. * There may be different TIDs with the same mac queues, so make
  1103. * sure all TIDs have existing corresponding mac queues enabled
  1104. */
  1105. tid_bitmap = mvm->queue_info[queue].tid_bitmap;
  1106. for_each_set_bit(tid, &tid_bitmap, IWL_MAX_TID_COUNT + 1) {
  1107. mvm->hw_queue_to_mac80211[queue] |=
  1108. BIT(mvmsta->vif->hw_queue[tid_to_mac80211_ac[tid]]);
  1109. }
  1110. /* If the queue is marked as shared - "unshare" it */
  1111. if (mvm->queue_info[queue].hw_queue_refcount == 1 &&
  1112. mvm->queue_info[queue].status == IWL_MVM_QUEUE_SHARED) {
  1113. mvm->queue_info[queue].status = IWL_MVM_QUEUE_RECONFIGURING;
  1114. IWL_DEBUG_TX_QUEUES(mvm, "Marking Q:%d for reconfig\n",
  1115. queue);
  1116. }
  1117. }
  1118. void iwl_mvm_inactivity_check(struct iwl_mvm *mvm)
  1119. {
  1120. unsigned long timeout_queues_map = 0;
  1121. unsigned long now = jiffies;
  1122. int i;
  1123. if (iwl_mvm_has_new_tx_api(mvm))
  1124. return;
  1125. spin_lock_bh(&mvm->queue_info_lock);
  1126. for (i = 0; i < IWL_MAX_HW_QUEUES; i++)
  1127. if (mvm->queue_info[i].hw_queue_refcount > 0)
  1128. timeout_queues_map |= BIT(i);
  1129. spin_unlock_bh(&mvm->queue_info_lock);
  1130. rcu_read_lock();
  1131. /*
  1132. * If a queue time outs - mark it as INACTIVE (don't remove right away
  1133. * if we don't have to.) This is an optimization in case traffic comes
  1134. * later, and we don't HAVE to use a currently-inactive queue
  1135. */
  1136. for_each_set_bit(i, &timeout_queues_map, IWL_MAX_HW_QUEUES) {
  1137. struct ieee80211_sta *sta;
  1138. struct iwl_mvm_sta *mvmsta;
  1139. u8 sta_id;
  1140. int tid;
  1141. unsigned long inactive_tid_bitmap = 0;
  1142. unsigned long queue_tid_bitmap;
  1143. spin_lock_bh(&mvm->queue_info_lock);
  1144. queue_tid_bitmap = mvm->queue_info[i].tid_bitmap;
  1145. /* If TXQ isn't in active use anyway - nothing to do here... */
  1146. if (mvm->queue_info[i].status != IWL_MVM_QUEUE_READY &&
  1147. mvm->queue_info[i].status != IWL_MVM_QUEUE_SHARED) {
  1148. spin_unlock_bh(&mvm->queue_info_lock);
  1149. continue;
  1150. }
  1151. /* Check to see if there are inactive TIDs on this queue */
  1152. for_each_set_bit(tid, &queue_tid_bitmap,
  1153. IWL_MAX_TID_COUNT + 1) {
  1154. if (time_after(mvm->queue_info[i].last_frame_time[tid] +
  1155. IWL_MVM_DQA_QUEUE_TIMEOUT, now))
  1156. continue;
  1157. inactive_tid_bitmap |= BIT(tid);
  1158. }
  1159. spin_unlock_bh(&mvm->queue_info_lock);
  1160. /* If all TIDs are active - finish check on this queue */
  1161. if (!inactive_tid_bitmap)
  1162. continue;
  1163. /*
  1164. * If we are here - the queue hadn't been served recently and is
  1165. * in use
  1166. */
  1167. sta_id = mvm->queue_info[i].ra_sta_id;
  1168. sta = rcu_dereference(mvm->fw_id_to_mac_id[sta_id]);
  1169. /*
  1170. * If the STA doesn't exist anymore, it isn't an error. It could
  1171. * be that it was removed since getting the queues, and in this
  1172. * case it should've inactivated its queues anyway.
  1173. */
  1174. if (IS_ERR_OR_NULL(sta))
  1175. continue;
  1176. mvmsta = iwl_mvm_sta_from_mac80211(sta);
  1177. spin_lock_bh(&mvmsta->lock);
  1178. spin_lock(&mvm->queue_info_lock);
  1179. iwl_mvm_remove_inactive_tids(mvm, mvmsta, i,
  1180. inactive_tid_bitmap);
  1181. spin_unlock(&mvm->queue_info_lock);
  1182. spin_unlock_bh(&mvmsta->lock);
  1183. }
  1184. rcu_read_unlock();
  1185. }
  1186. void iwl_mvm_event_frame_timeout_callback(struct iwl_mvm *mvm,
  1187. struct ieee80211_vif *vif,
  1188. const struct ieee80211_sta *sta,
  1189. u16 tid)
  1190. {
  1191. struct iwl_fw_dbg_trigger_tlv *trig;
  1192. struct iwl_fw_dbg_trigger_ba *ba_trig;
  1193. if (!iwl_fw_dbg_trigger_enabled(mvm->fw, FW_DBG_TRIGGER_BA))
  1194. return;
  1195. trig = iwl_fw_dbg_get_trigger(mvm->fw, FW_DBG_TRIGGER_BA);
  1196. ba_trig = (void *)trig->data;
  1197. if (!iwl_fw_dbg_trigger_check_stop(&mvm->fwrt,
  1198. ieee80211_vif_to_wdev(vif), trig))
  1199. return;
  1200. if (!(le16_to_cpu(ba_trig->frame_timeout) & BIT(tid)))
  1201. return;
  1202. iwl_fw_dbg_collect_trig(&mvm->fwrt, trig,
  1203. "Frame from %pM timed out, tid %d",
  1204. sta->addr, tid);
  1205. }
  1206. void iwl_mvm_get_sync_time(struct iwl_mvm *mvm, u32 *gp2, u64 *boottime)
  1207. {
  1208. bool ps_disabled;
  1209. lockdep_assert_held(&mvm->mutex);
  1210. /* Disable power save when reading GP2 */
  1211. ps_disabled = mvm->ps_disabled;
  1212. if (!ps_disabled) {
  1213. mvm->ps_disabled = true;
  1214. iwl_mvm_power_update_device(mvm);
  1215. }
  1216. *gp2 = iwl_read_prph(mvm->trans, DEVICE_SYSTEM_TIME_REG);
  1217. *boottime = ktime_get_boot_ns();
  1218. if (!ps_disabled) {
  1219. mvm->ps_disabled = ps_disabled;
  1220. iwl_mvm_power_update_device(mvm);
  1221. }
  1222. }