fw-dbg.c 25 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2015 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program;
  23. *
  24. * The full GNU General Public License is included in this distribution
  25. * in the file called COPYING.
  26. *
  27. * Contact Information:
  28. * Intel Linux Wireless <linuxwifi@intel.com>
  29. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30. *
  31. * BSD LICENSE
  32. *
  33. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  34. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  35. * Copyright(c) 2015 Intel Deutschland GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *
  64. *****************************************************************************/
  65. #include <linux/devcoredump.h>
  66. #include "fw-dbg.h"
  67. #include "iwl-io.h"
  68. #include "mvm.h"
  69. #include "iwl-prph.h"
  70. #include "iwl-csr.h"
  71. static ssize_t iwl_mvm_read_coredump(char *buffer, loff_t offset, size_t count,
  72. const void *data, size_t datalen)
  73. {
  74. const struct iwl_mvm_dump_ptrs *dump_ptrs = data;
  75. ssize_t bytes_read;
  76. ssize_t bytes_read_trans;
  77. if (offset < dump_ptrs->op_mode_len) {
  78. bytes_read = min_t(ssize_t, count,
  79. dump_ptrs->op_mode_len - offset);
  80. memcpy(buffer, (u8 *)dump_ptrs->op_mode_ptr + offset,
  81. bytes_read);
  82. offset += bytes_read;
  83. count -= bytes_read;
  84. if (count == 0)
  85. return bytes_read;
  86. } else {
  87. bytes_read = 0;
  88. }
  89. if (!dump_ptrs->trans_ptr)
  90. return bytes_read;
  91. offset -= dump_ptrs->op_mode_len;
  92. bytes_read_trans = min_t(ssize_t, count,
  93. dump_ptrs->trans_ptr->len - offset);
  94. memcpy(buffer + bytes_read,
  95. (u8 *)dump_ptrs->trans_ptr->data + offset,
  96. bytes_read_trans);
  97. return bytes_read + bytes_read_trans;
  98. }
  99. static void iwl_mvm_free_coredump(const void *data)
  100. {
  101. const struct iwl_mvm_dump_ptrs *fw_error_dump = data;
  102. vfree(fw_error_dump->op_mode_ptr);
  103. vfree(fw_error_dump->trans_ptr);
  104. kfree(fw_error_dump);
  105. }
  106. static void iwl_mvm_dump_fifos(struct iwl_mvm *mvm,
  107. struct iwl_fw_error_dump_data **dump_data)
  108. {
  109. struct iwl_fw_error_dump_fifo *fifo_hdr;
  110. u32 *fifo_data;
  111. u32 fifo_len;
  112. unsigned long flags;
  113. int i, j;
  114. if (!iwl_trans_grab_nic_access(mvm->trans, false, &flags))
  115. return;
  116. /* Pull RXF data from all RXFs */
  117. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) {
  118. /*
  119. * Keep aside the additional offset that might be needed for
  120. * next RXF
  121. */
  122. u32 offset_diff = RXF_DIFF_FROM_PREV * i;
  123. fifo_hdr = (void *)(*dump_data)->data;
  124. fifo_data = (void *)fifo_hdr->data;
  125. fifo_len = mvm->shared_mem_cfg.rxfifo_size[i];
  126. /* No need to try to read the data if the length is 0 */
  127. if (fifo_len == 0)
  128. continue;
  129. /* Add a TLV for the RXF */
  130. (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
  131. (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
  132. fifo_hdr->fifo_num = cpu_to_le32(i);
  133. fifo_hdr->available_bytes =
  134. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  135. RXF_RD_D_SPACE +
  136. offset_diff));
  137. fifo_hdr->wr_ptr =
  138. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  139. RXF_RD_WR_PTR +
  140. offset_diff));
  141. fifo_hdr->rd_ptr =
  142. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  143. RXF_RD_RD_PTR +
  144. offset_diff));
  145. fifo_hdr->fence_ptr =
  146. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  147. RXF_RD_FENCE_PTR +
  148. offset_diff));
  149. fifo_hdr->fence_mode =
  150. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  151. RXF_SET_FENCE_MODE +
  152. offset_diff));
  153. /* Lock fence */
  154. iwl_trans_write_prph(mvm->trans,
  155. RXF_SET_FENCE_MODE + offset_diff, 0x1);
  156. /* Set fence pointer to the same place like WR pointer */
  157. iwl_trans_write_prph(mvm->trans,
  158. RXF_LD_WR2FENCE + offset_diff, 0x1);
  159. /* Set fence offset */
  160. iwl_trans_write_prph(mvm->trans,
  161. RXF_LD_FENCE_OFFSET_ADDR + offset_diff,
  162. 0x0);
  163. /* Read FIFO */
  164. fifo_len /= sizeof(u32); /* Size in DWORDS */
  165. for (j = 0; j < fifo_len; j++)
  166. fifo_data[j] = iwl_trans_read_prph(mvm->trans,
  167. RXF_FIFO_RD_FENCE_INC +
  168. offset_diff);
  169. *dump_data = iwl_fw_error_next_data(*dump_data);
  170. }
  171. /* Pull TXF data from all TXFs */
  172. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) {
  173. /* Mark the number of TXF we're pulling now */
  174. iwl_trans_write_prph(mvm->trans, TXF_LARC_NUM, i);
  175. fifo_hdr = (void *)(*dump_data)->data;
  176. fifo_data = (void *)fifo_hdr->data;
  177. fifo_len = mvm->shared_mem_cfg.txfifo_size[i];
  178. /* No need to try to read the data if the length is 0 */
  179. if (fifo_len == 0)
  180. continue;
  181. /* Add a TLV for the FIFO */
  182. (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
  183. (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
  184. fifo_hdr->fifo_num = cpu_to_le32(i);
  185. fifo_hdr->available_bytes =
  186. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  187. TXF_FIFO_ITEM_CNT));
  188. fifo_hdr->wr_ptr =
  189. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  190. TXF_WR_PTR));
  191. fifo_hdr->rd_ptr =
  192. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  193. TXF_RD_PTR));
  194. fifo_hdr->fence_ptr =
  195. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  196. TXF_FENCE_PTR));
  197. fifo_hdr->fence_mode =
  198. cpu_to_le32(iwl_trans_read_prph(mvm->trans,
  199. TXF_LOCK_FENCE));
  200. /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
  201. iwl_trans_write_prph(mvm->trans, TXF_READ_MODIFY_ADDR,
  202. TXF_WR_PTR);
  203. /* Dummy-read to advance the read pointer to the head */
  204. iwl_trans_read_prph(mvm->trans, TXF_READ_MODIFY_DATA);
  205. /* Read FIFO */
  206. fifo_len /= sizeof(u32); /* Size in DWORDS */
  207. for (j = 0; j < fifo_len; j++)
  208. fifo_data[j] = iwl_trans_read_prph(mvm->trans,
  209. TXF_READ_MODIFY_DATA);
  210. *dump_data = iwl_fw_error_next_data(*dump_data);
  211. }
  212. iwl_trans_release_nic_access(mvm->trans, &flags);
  213. }
  214. void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm)
  215. {
  216. if (mvm->fw_dump_desc == &iwl_mvm_dump_desc_assert ||
  217. !mvm->fw_dump_desc)
  218. return;
  219. kfree(mvm->fw_dump_desc);
  220. mvm->fw_dump_desc = NULL;
  221. }
  222. #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */
  223. #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */
  224. static const struct {
  225. u32 start, end;
  226. } iwl_prph_dump_addr[] = {
  227. { .start = 0x00a00000, .end = 0x00a00000 },
  228. { .start = 0x00a0000c, .end = 0x00a00024 },
  229. { .start = 0x00a0002c, .end = 0x00a0003c },
  230. { .start = 0x00a00410, .end = 0x00a00418 },
  231. { .start = 0x00a00420, .end = 0x00a00420 },
  232. { .start = 0x00a00428, .end = 0x00a00428 },
  233. { .start = 0x00a00430, .end = 0x00a0043c },
  234. { .start = 0x00a00444, .end = 0x00a00444 },
  235. { .start = 0x00a004c0, .end = 0x00a004cc },
  236. { .start = 0x00a004d8, .end = 0x00a004d8 },
  237. { .start = 0x00a004e0, .end = 0x00a004f0 },
  238. { .start = 0x00a00840, .end = 0x00a00840 },
  239. { .start = 0x00a00850, .end = 0x00a00858 },
  240. { .start = 0x00a01004, .end = 0x00a01008 },
  241. { .start = 0x00a01010, .end = 0x00a01010 },
  242. { .start = 0x00a01018, .end = 0x00a01018 },
  243. { .start = 0x00a01024, .end = 0x00a01024 },
  244. { .start = 0x00a0102c, .end = 0x00a01034 },
  245. { .start = 0x00a0103c, .end = 0x00a01040 },
  246. { .start = 0x00a01048, .end = 0x00a01094 },
  247. { .start = 0x00a01c00, .end = 0x00a01c20 },
  248. { .start = 0x00a01c58, .end = 0x00a01c58 },
  249. { .start = 0x00a01c7c, .end = 0x00a01c7c },
  250. { .start = 0x00a01c28, .end = 0x00a01c54 },
  251. { .start = 0x00a01c5c, .end = 0x00a01c5c },
  252. { .start = 0x00a01c60, .end = 0x00a01cdc },
  253. { .start = 0x00a01ce0, .end = 0x00a01d0c },
  254. { .start = 0x00a01d18, .end = 0x00a01d20 },
  255. { .start = 0x00a01d2c, .end = 0x00a01d30 },
  256. { .start = 0x00a01d40, .end = 0x00a01d5c },
  257. { .start = 0x00a01d80, .end = 0x00a01d80 },
  258. { .start = 0x00a01d98, .end = 0x00a01d9c },
  259. { .start = 0x00a01da8, .end = 0x00a01da8 },
  260. { .start = 0x00a01db8, .end = 0x00a01df4 },
  261. { .start = 0x00a01dc0, .end = 0x00a01dfc },
  262. { .start = 0x00a01e00, .end = 0x00a01e2c },
  263. { .start = 0x00a01e40, .end = 0x00a01e60 },
  264. { .start = 0x00a01e68, .end = 0x00a01e6c },
  265. { .start = 0x00a01e74, .end = 0x00a01e74 },
  266. { .start = 0x00a01e84, .end = 0x00a01e90 },
  267. { .start = 0x00a01e9c, .end = 0x00a01ec4 },
  268. { .start = 0x00a01ed0, .end = 0x00a01ee0 },
  269. { .start = 0x00a01f00, .end = 0x00a01f1c },
  270. { .start = 0x00a01f44, .end = 0x00a01ffc },
  271. { .start = 0x00a02000, .end = 0x00a02048 },
  272. { .start = 0x00a02068, .end = 0x00a020f0 },
  273. { .start = 0x00a02100, .end = 0x00a02118 },
  274. { .start = 0x00a02140, .end = 0x00a0214c },
  275. { .start = 0x00a02168, .end = 0x00a0218c },
  276. { .start = 0x00a021c0, .end = 0x00a021c0 },
  277. { .start = 0x00a02400, .end = 0x00a02410 },
  278. { .start = 0x00a02418, .end = 0x00a02420 },
  279. { .start = 0x00a02428, .end = 0x00a0242c },
  280. { .start = 0x00a02434, .end = 0x00a02434 },
  281. { .start = 0x00a02440, .end = 0x00a02460 },
  282. { .start = 0x00a02468, .end = 0x00a024b0 },
  283. { .start = 0x00a024c8, .end = 0x00a024cc },
  284. { .start = 0x00a02500, .end = 0x00a02504 },
  285. { .start = 0x00a0250c, .end = 0x00a02510 },
  286. { .start = 0x00a02540, .end = 0x00a02554 },
  287. { .start = 0x00a02580, .end = 0x00a025f4 },
  288. { .start = 0x00a02600, .end = 0x00a0260c },
  289. { .start = 0x00a02648, .end = 0x00a02650 },
  290. { .start = 0x00a02680, .end = 0x00a02680 },
  291. { .start = 0x00a026c0, .end = 0x00a026d0 },
  292. { .start = 0x00a02700, .end = 0x00a0270c },
  293. { .start = 0x00a02804, .end = 0x00a02804 },
  294. { .start = 0x00a02818, .end = 0x00a0281c },
  295. { .start = 0x00a02c00, .end = 0x00a02db4 },
  296. { .start = 0x00a02df4, .end = 0x00a02fb0 },
  297. { .start = 0x00a03000, .end = 0x00a03014 },
  298. { .start = 0x00a0301c, .end = 0x00a0302c },
  299. { .start = 0x00a03034, .end = 0x00a03038 },
  300. { .start = 0x00a03040, .end = 0x00a03048 },
  301. { .start = 0x00a03060, .end = 0x00a03068 },
  302. { .start = 0x00a03070, .end = 0x00a03074 },
  303. { .start = 0x00a0307c, .end = 0x00a0307c },
  304. { .start = 0x00a03080, .end = 0x00a03084 },
  305. { .start = 0x00a0308c, .end = 0x00a03090 },
  306. { .start = 0x00a03098, .end = 0x00a03098 },
  307. { .start = 0x00a030a0, .end = 0x00a030a0 },
  308. { .start = 0x00a030a8, .end = 0x00a030b4 },
  309. { .start = 0x00a030bc, .end = 0x00a030bc },
  310. { .start = 0x00a030c0, .end = 0x00a0312c },
  311. { .start = 0x00a03c00, .end = 0x00a03c5c },
  312. { .start = 0x00a04400, .end = 0x00a04454 },
  313. { .start = 0x00a04460, .end = 0x00a04474 },
  314. { .start = 0x00a044c0, .end = 0x00a044ec },
  315. { .start = 0x00a04500, .end = 0x00a04504 },
  316. { .start = 0x00a04510, .end = 0x00a04538 },
  317. { .start = 0x00a04540, .end = 0x00a04548 },
  318. { .start = 0x00a04560, .end = 0x00a0457c },
  319. { .start = 0x00a04590, .end = 0x00a04598 },
  320. { .start = 0x00a045c0, .end = 0x00a045f4 },
  321. };
  322. static u32 iwl_dump_prph(struct iwl_trans *trans,
  323. struct iwl_fw_error_dump_data **data)
  324. {
  325. struct iwl_fw_error_dump_prph *prph;
  326. unsigned long flags;
  327. u32 prph_len = 0, i;
  328. if (!iwl_trans_grab_nic_access(trans, false, &flags))
  329. return 0;
  330. for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
  331. /* The range includes both boundaries */
  332. int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
  333. iwl_prph_dump_addr[i].start + 4;
  334. int reg;
  335. __le32 *val;
  336. prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
  337. (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
  338. (*data)->len = cpu_to_le32(sizeof(*prph) +
  339. num_bytes_in_chunk);
  340. prph = (void *)(*data)->data;
  341. prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
  342. val = (void *)prph->data;
  343. for (reg = iwl_prph_dump_addr[i].start;
  344. reg <= iwl_prph_dump_addr[i].end;
  345. reg += 4)
  346. *val++ = cpu_to_le32(iwl_read_prph_no_grab(trans,
  347. reg));
  348. *data = iwl_fw_error_next_data(*data);
  349. }
  350. iwl_trans_release_nic_access(trans, &flags);
  351. return prph_len;
  352. }
  353. void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
  354. {
  355. struct iwl_fw_error_dump_file *dump_file;
  356. struct iwl_fw_error_dump_data *dump_data;
  357. struct iwl_fw_error_dump_info *dump_info;
  358. struct iwl_fw_error_dump_mem *dump_mem;
  359. struct iwl_fw_error_dump_trigger_desc *dump_trig;
  360. struct iwl_mvm_dump_ptrs *fw_error_dump;
  361. u32 sram_len, sram_ofs;
  362. u32 file_len, fifo_data_len = 0;
  363. u32 smem_len = mvm->cfg->smem_len;
  364. u32 sram2_len = mvm->cfg->dccm2_len;
  365. bool monitor_dump_only = false;
  366. int i;
  367. lockdep_assert_held(&mvm->mutex);
  368. /* there's no point in fw dump if the bus is dead */
  369. if (test_bit(STATUS_TRANS_DEAD, &mvm->trans->status)) {
  370. IWL_ERR(mvm, "Skip fw error dump since bus is dead\n");
  371. return;
  372. }
  373. if (mvm->fw_dump_trig &&
  374. mvm->fw_dump_trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)
  375. monitor_dump_only = true;
  376. fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL);
  377. if (!fw_error_dump)
  378. return;
  379. /* SRAM - include stack CCM if driver knows the values for it */
  380. if (!mvm->cfg->dccm_offset || !mvm->cfg->dccm_len) {
  381. const struct fw_img *img;
  382. img = &mvm->fw->img[mvm->cur_ucode];
  383. sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
  384. sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
  385. } else {
  386. sram_ofs = mvm->cfg->dccm_offset;
  387. sram_len = mvm->cfg->dccm_len;
  388. }
  389. /* reading RXF/TXF sizes */
  390. if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
  391. struct iwl_mvm_shared_mem_cfg *mem_cfg = &mvm->shared_mem_cfg;
  392. fifo_data_len = 0;
  393. /* Count RXF size */
  394. for (i = 0; i < ARRAY_SIZE(mem_cfg->rxfifo_size); i++) {
  395. if (!mem_cfg->rxfifo_size[i])
  396. continue;
  397. /* Add header info */
  398. fifo_data_len += mem_cfg->rxfifo_size[i] +
  399. sizeof(*dump_data) +
  400. sizeof(struct iwl_fw_error_dump_fifo);
  401. }
  402. for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++) {
  403. if (!mem_cfg->txfifo_size[i])
  404. continue;
  405. /* Add header info */
  406. fifo_data_len += mem_cfg->txfifo_size[i] +
  407. sizeof(*dump_data) +
  408. sizeof(struct iwl_fw_error_dump_fifo);
  409. }
  410. }
  411. file_len = sizeof(*dump_file) +
  412. sizeof(*dump_data) * 2 +
  413. sram_len + sizeof(*dump_mem) +
  414. fifo_data_len +
  415. sizeof(*dump_info);
  416. /* Make room for the SMEM, if it exists */
  417. if (smem_len)
  418. file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len;
  419. /* Make room for the secondary SRAM, if it exists */
  420. if (sram2_len)
  421. file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len;
  422. /* Make room for fw's virtual image pages, if it exists */
  423. if (mvm->fw->img[mvm->cur_ucode].paging_mem_size)
  424. file_len += mvm->num_of_paging_blk *
  425. (sizeof(*dump_data) +
  426. sizeof(struct iwl_fw_error_dump_paging) +
  427. PAGING_BLOCK_SIZE);
  428. /* If we only want a monitor dump, reset the file length */
  429. if (monitor_dump_only) {
  430. file_len = sizeof(*dump_file) + sizeof(*dump_data) +
  431. sizeof(*dump_info);
  432. }
  433. /* Make room for PRPH registers */
  434. for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
  435. /* The range includes both boundaries */
  436. int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
  437. iwl_prph_dump_addr[i].start + 4;
  438. file_len += sizeof(*dump_data) +
  439. sizeof(struct iwl_fw_error_dump_prph) +
  440. num_bytes_in_chunk;
  441. }
  442. /*
  443. * In 8000 HW family B-step include the ICCM (which resides separately)
  444. */
  445. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
  446. CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP)
  447. file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
  448. IWL8260_ICCM_LEN;
  449. if (mvm->fw_dump_desc)
  450. file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
  451. mvm->fw_dump_desc->len;
  452. dump_file = vzalloc(file_len);
  453. if (!dump_file) {
  454. kfree(fw_error_dump);
  455. iwl_mvm_free_fw_dump_desc(mvm);
  456. return;
  457. }
  458. fw_error_dump->op_mode_ptr = dump_file;
  459. dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
  460. dump_data = (void *)dump_file->data;
  461. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
  462. dump_data->len = cpu_to_le32(sizeof(*dump_info));
  463. dump_info = (void *)dump_data->data;
  464. dump_info->device_family =
  465. mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000 ?
  466. cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) :
  467. cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8);
  468. dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(mvm->trans->hw_rev));
  469. memcpy(dump_info->fw_human_readable, mvm->fw->human_readable,
  470. sizeof(dump_info->fw_human_readable));
  471. strncpy(dump_info->dev_human_readable, mvm->cfg->name,
  472. sizeof(dump_info->dev_human_readable));
  473. strncpy(dump_info->bus_human_readable, mvm->dev->bus->name,
  474. sizeof(dump_info->bus_human_readable));
  475. dump_data = iwl_fw_error_next_data(dump_data);
  476. /* We only dump the FIFOs if the FW is in error state */
  477. if (test_bit(STATUS_FW_ERROR, &mvm->trans->status))
  478. iwl_mvm_dump_fifos(mvm, &dump_data);
  479. if (mvm->fw_dump_desc) {
  480. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
  481. dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
  482. mvm->fw_dump_desc->len);
  483. dump_trig = (void *)dump_data->data;
  484. memcpy(dump_trig, &mvm->fw_dump_desc->trig_desc,
  485. sizeof(*dump_trig) + mvm->fw_dump_desc->len);
  486. /* now we can free this copy */
  487. iwl_mvm_free_fw_dump_desc(mvm);
  488. dump_data = iwl_fw_error_next_data(dump_data);
  489. }
  490. /* In case we only want monitor dump, skip to dump trasport data */
  491. if (monitor_dump_only)
  492. goto dump_trans_data;
  493. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
  494. dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem));
  495. dump_mem = (void *)dump_data->data;
  496. dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
  497. dump_mem->offset = cpu_to_le32(sram_ofs);
  498. iwl_trans_read_mem_bytes(mvm->trans, sram_ofs, dump_mem->data,
  499. sram_len);
  500. if (smem_len) {
  501. dump_data = iwl_fw_error_next_data(dump_data);
  502. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
  503. dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem));
  504. dump_mem = (void *)dump_data->data;
  505. dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM);
  506. dump_mem->offset = cpu_to_le32(mvm->cfg->smem_offset);
  507. iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->smem_offset,
  508. dump_mem->data, smem_len);
  509. }
  510. if (sram2_len) {
  511. dump_data = iwl_fw_error_next_data(dump_data);
  512. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
  513. dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem));
  514. dump_mem = (void *)dump_data->data;
  515. dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
  516. dump_mem->offset = cpu_to_le32(mvm->cfg->dccm2_offset);
  517. iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->dccm2_offset,
  518. dump_mem->data, sram2_len);
  519. }
  520. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
  521. CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP) {
  522. dump_data = iwl_fw_error_next_data(dump_data);
  523. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
  524. dump_data->len = cpu_to_le32(IWL8260_ICCM_LEN +
  525. sizeof(*dump_mem));
  526. dump_mem = (void *)dump_data->data;
  527. dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
  528. dump_mem->offset = cpu_to_le32(IWL8260_ICCM_OFFSET);
  529. iwl_trans_read_mem_bytes(mvm->trans, IWL8260_ICCM_OFFSET,
  530. dump_mem->data, IWL8260_ICCM_LEN);
  531. }
  532. /* Dump fw's virtual image */
  533. if (mvm->fw->img[mvm->cur_ucode].paging_mem_size) {
  534. u32 i;
  535. for (i = 1; i < mvm->num_of_paging_blk + 1; i++) {
  536. struct iwl_fw_error_dump_paging *paging;
  537. struct page *pages =
  538. mvm->fw_paging_db[i].fw_paging_block;
  539. dump_data = iwl_fw_error_next_data(dump_data);
  540. dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
  541. dump_data->len = cpu_to_le32(sizeof(*paging) +
  542. PAGING_BLOCK_SIZE);
  543. paging = (void *)dump_data->data;
  544. paging->index = cpu_to_le32(i);
  545. memcpy(paging->data, page_address(pages),
  546. PAGING_BLOCK_SIZE);
  547. }
  548. }
  549. dump_data = iwl_fw_error_next_data(dump_data);
  550. iwl_dump_prph(mvm->trans, &dump_data);
  551. dump_trans_data:
  552. fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans,
  553. mvm->fw_dump_trig);
  554. fw_error_dump->op_mode_len = file_len;
  555. if (fw_error_dump->trans_ptr)
  556. file_len += fw_error_dump->trans_ptr->len;
  557. dump_file->file_len = cpu_to_le32(file_len);
  558. dev_coredumpm(mvm->trans->dev, THIS_MODULE, fw_error_dump, 0,
  559. GFP_KERNEL, iwl_mvm_read_coredump, iwl_mvm_free_coredump);
  560. mvm->fw_dump_trig = NULL;
  561. clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status);
  562. }
  563. struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert = {
  564. .trig_desc = {
  565. .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
  566. },
  567. };
  568. int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
  569. struct iwl_mvm_dump_desc *desc,
  570. struct iwl_fw_dbg_trigger_tlv *trigger)
  571. {
  572. unsigned int delay = 0;
  573. if (trigger)
  574. delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
  575. if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
  576. return -EBUSY;
  577. if (WARN_ON(mvm->fw_dump_desc))
  578. iwl_mvm_free_fw_dump_desc(mvm);
  579. IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
  580. le32_to_cpu(desc->trig_desc.type));
  581. mvm->fw_dump_desc = desc;
  582. mvm->fw_dump_trig = trigger;
  583. queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
  584. return 0;
  585. }
  586. int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
  587. const char *str, size_t len,
  588. struct iwl_fw_dbg_trigger_tlv *trigger)
  589. {
  590. struct iwl_mvm_dump_desc *desc;
  591. desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
  592. if (!desc)
  593. return -ENOMEM;
  594. desc->len = len;
  595. desc->trig_desc.type = cpu_to_le32(trig);
  596. memcpy(desc->trig_desc.data, str, len);
  597. return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
  598. }
  599. int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
  600. struct iwl_fw_dbg_trigger_tlv *trigger,
  601. const char *fmt, ...)
  602. {
  603. u16 occurrences = le16_to_cpu(trigger->occurrences);
  604. int ret, len = 0;
  605. char buf[64];
  606. if (!occurrences)
  607. return 0;
  608. if (fmt) {
  609. va_list ap;
  610. buf[sizeof(buf) - 1] = '\0';
  611. va_start(ap, fmt);
  612. vsnprintf(buf, sizeof(buf), fmt, ap);
  613. va_end(ap);
  614. /* check for truncation */
  615. if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
  616. buf[sizeof(buf) - 1] = '\0';
  617. len = strlen(buf) + 1;
  618. }
  619. ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
  620. trigger);
  621. if (ret)
  622. return ret;
  623. trigger->occurrences = cpu_to_le16(occurrences - 1);
  624. return 0;
  625. }
  626. static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
  627. {
  628. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
  629. iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
  630. else
  631. iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
  632. }
  633. int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
  634. {
  635. u8 *ptr;
  636. int ret;
  637. int i;
  638. if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
  639. "Invalid configuration %d\n", conf_id))
  640. return -EINVAL;
  641. /* EARLY START - firmware's configuration is hard coded */
  642. if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
  643. !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
  644. conf_id == FW_DBG_START_FROM_ALIVE) {
  645. iwl_mvm_restart_early_start(mvm);
  646. return 0;
  647. }
  648. if (!mvm->fw->dbg_conf_tlv[conf_id])
  649. return -EINVAL;
  650. if (mvm->fw_dbg_conf != FW_DBG_INVALID)
  651. IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
  652. mvm->fw_dbg_conf);
  653. /* Send all HCMDs for configuring the FW debug */
  654. ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
  655. for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
  656. struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
  657. ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
  658. le16_to_cpu(cmd->len), cmd->data);
  659. if (ret)
  660. return ret;
  661. ptr += sizeof(*cmd);
  662. ptr += le16_to_cpu(cmd->len);
  663. }
  664. mvm->fw_dbg_conf = conf_id;
  665. return ret;
  666. }