virtgpu_vq.c 26 KB

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  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Authors:
  6. * Dave Airlie <airlied@redhat.com>
  7. * Gerd Hoffmann <kraxel@redhat.com>
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a
  10. * copy of this software and associated documentation files (the "Software"),
  11. * to deal in the Software without restriction, including without limitation
  12. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13. * and/or sell copies of the Software, and to permit persons to whom the
  14. * Software is furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the next
  17. * paragraph) shall be included in all copies or substantial portions of the
  18. * Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  26. * OTHER DEALINGS IN THE SOFTWARE.
  27. */
  28. #include <drm/drmP.h>
  29. #include "virtgpu_drv.h"
  30. #include <linux/virtio.h>
  31. #include <linux/virtio_config.h>
  32. #include <linux/virtio_ring.h>
  33. #define MAX_INLINE_CMD_SIZE 96
  34. #define MAX_INLINE_RESP_SIZE 24
  35. #define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
  36. + MAX_INLINE_CMD_SIZE \
  37. + MAX_INLINE_RESP_SIZE)
  38. void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
  39. uint32_t *resid)
  40. {
  41. int handle;
  42. idr_preload(GFP_KERNEL);
  43. spin_lock(&vgdev->resource_idr_lock);
  44. handle = idr_alloc(&vgdev->resource_idr, NULL, 1, 0, GFP_NOWAIT);
  45. spin_unlock(&vgdev->resource_idr_lock);
  46. idr_preload_end();
  47. *resid = handle;
  48. }
  49. void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id)
  50. {
  51. spin_lock(&vgdev->resource_idr_lock);
  52. idr_remove(&vgdev->resource_idr, id);
  53. spin_unlock(&vgdev->resource_idr_lock);
  54. }
  55. void virtio_gpu_ctrl_ack(struct virtqueue *vq)
  56. {
  57. struct drm_device *dev = vq->vdev->priv;
  58. struct virtio_gpu_device *vgdev = dev->dev_private;
  59. schedule_work(&vgdev->ctrlq.dequeue_work);
  60. }
  61. void virtio_gpu_cursor_ack(struct virtqueue *vq)
  62. {
  63. struct drm_device *dev = vq->vdev->priv;
  64. struct virtio_gpu_device *vgdev = dev->dev_private;
  65. schedule_work(&vgdev->cursorq.dequeue_work);
  66. }
  67. int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
  68. {
  69. struct virtio_gpu_vbuffer *vbuf;
  70. int i, size, count = 16;
  71. void *ptr;
  72. INIT_LIST_HEAD(&vgdev->free_vbufs);
  73. spin_lock_init(&vgdev->free_vbufs_lock);
  74. count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
  75. count += virtqueue_get_vring_size(vgdev->cursorq.vq);
  76. size = count * VBUFFER_SIZE;
  77. DRM_INFO("virtio vbuffers: %d bufs, %zdB each, %dkB total.\n",
  78. count, VBUFFER_SIZE, size / 1024);
  79. vgdev->vbufs = kzalloc(size, GFP_KERNEL);
  80. if (!vgdev->vbufs)
  81. return -ENOMEM;
  82. for (i = 0, ptr = vgdev->vbufs;
  83. i < count;
  84. i++, ptr += VBUFFER_SIZE) {
  85. vbuf = ptr;
  86. list_add(&vbuf->list, &vgdev->free_vbufs);
  87. }
  88. return 0;
  89. }
  90. void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
  91. {
  92. struct virtio_gpu_vbuffer *vbuf;
  93. int i, count = 0;
  94. count += virtqueue_get_vring_size(vgdev->ctrlq.vq);
  95. count += virtqueue_get_vring_size(vgdev->cursorq.vq);
  96. spin_lock(&vgdev->free_vbufs_lock);
  97. for (i = 0; i < count; i++) {
  98. if (WARN_ON(list_empty(&vgdev->free_vbufs))) {
  99. spin_unlock(&vgdev->free_vbufs_lock);
  100. return;
  101. }
  102. vbuf = list_first_entry(&vgdev->free_vbufs,
  103. struct virtio_gpu_vbuffer, list);
  104. list_del(&vbuf->list);
  105. }
  106. spin_unlock(&vgdev->free_vbufs_lock);
  107. kfree(vgdev->vbufs);
  108. }
  109. static struct virtio_gpu_vbuffer*
  110. virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
  111. int size, int resp_size, void *resp_buf,
  112. virtio_gpu_resp_cb resp_cb)
  113. {
  114. struct virtio_gpu_vbuffer *vbuf;
  115. spin_lock(&vgdev->free_vbufs_lock);
  116. BUG_ON(list_empty(&vgdev->free_vbufs));
  117. vbuf = list_first_entry(&vgdev->free_vbufs,
  118. struct virtio_gpu_vbuffer, list);
  119. list_del(&vbuf->list);
  120. spin_unlock(&vgdev->free_vbufs_lock);
  121. memset(vbuf, 0, VBUFFER_SIZE);
  122. BUG_ON(size > MAX_INLINE_CMD_SIZE);
  123. vbuf->buf = (void *)vbuf + sizeof(*vbuf);
  124. vbuf->size = size;
  125. vbuf->resp_cb = resp_cb;
  126. vbuf->resp_size = resp_size;
  127. if (resp_size <= MAX_INLINE_RESP_SIZE)
  128. vbuf->resp_buf = (void *)vbuf->buf + size;
  129. else
  130. vbuf->resp_buf = resp_buf;
  131. BUG_ON(!vbuf->resp_buf);
  132. return vbuf;
  133. }
  134. static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
  135. struct virtio_gpu_vbuffer **vbuffer_p,
  136. int size)
  137. {
  138. struct virtio_gpu_vbuffer *vbuf;
  139. vbuf = virtio_gpu_get_vbuf(vgdev, size,
  140. sizeof(struct virtio_gpu_ctrl_hdr),
  141. NULL, NULL);
  142. if (IS_ERR(vbuf)) {
  143. *vbuffer_p = NULL;
  144. return ERR_CAST(vbuf);
  145. }
  146. *vbuffer_p = vbuf;
  147. return vbuf->buf;
  148. }
  149. static struct virtio_gpu_update_cursor*
  150. virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
  151. struct virtio_gpu_vbuffer **vbuffer_p)
  152. {
  153. struct virtio_gpu_vbuffer *vbuf;
  154. vbuf = virtio_gpu_get_vbuf
  155. (vgdev, sizeof(struct virtio_gpu_update_cursor),
  156. 0, NULL, NULL);
  157. if (IS_ERR(vbuf)) {
  158. *vbuffer_p = NULL;
  159. return ERR_CAST(vbuf);
  160. }
  161. *vbuffer_p = vbuf;
  162. return (struct virtio_gpu_update_cursor *)vbuf->buf;
  163. }
  164. static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
  165. virtio_gpu_resp_cb cb,
  166. struct virtio_gpu_vbuffer **vbuffer_p,
  167. int cmd_size, int resp_size,
  168. void *resp_buf)
  169. {
  170. struct virtio_gpu_vbuffer *vbuf;
  171. vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
  172. resp_size, resp_buf, cb);
  173. if (IS_ERR(vbuf)) {
  174. *vbuffer_p = NULL;
  175. return ERR_CAST(vbuf);
  176. }
  177. *vbuffer_p = vbuf;
  178. return (struct virtio_gpu_command *)vbuf->buf;
  179. }
  180. static void free_vbuf(struct virtio_gpu_device *vgdev,
  181. struct virtio_gpu_vbuffer *vbuf)
  182. {
  183. if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
  184. kfree(vbuf->resp_buf);
  185. kfree(vbuf->data_buf);
  186. spin_lock(&vgdev->free_vbufs_lock);
  187. list_add(&vbuf->list, &vgdev->free_vbufs);
  188. spin_unlock(&vgdev->free_vbufs_lock);
  189. }
  190. static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
  191. {
  192. struct virtio_gpu_vbuffer *vbuf;
  193. unsigned int len;
  194. int freed = 0;
  195. while ((vbuf = virtqueue_get_buf(vq, &len))) {
  196. list_add_tail(&vbuf->list, reclaim_list);
  197. freed++;
  198. }
  199. if (freed == 0)
  200. DRM_DEBUG("Huh? zero vbufs reclaimed");
  201. }
  202. void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
  203. {
  204. struct virtio_gpu_device *vgdev =
  205. container_of(work, struct virtio_gpu_device,
  206. ctrlq.dequeue_work);
  207. struct list_head reclaim_list;
  208. struct virtio_gpu_vbuffer *entry, *tmp;
  209. struct virtio_gpu_ctrl_hdr *resp;
  210. u64 fence_id = 0;
  211. INIT_LIST_HEAD(&reclaim_list);
  212. spin_lock(&vgdev->ctrlq.qlock);
  213. do {
  214. virtqueue_disable_cb(vgdev->ctrlq.vq);
  215. reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
  216. } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
  217. spin_unlock(&vgdev->ctrlq.qlock);
  218. list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
  219. resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
  220. if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA))
  221. DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
  222. if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
  223. u64 f = le64_to_cpu(resp->fence_id);
  224. if (fence_id > f) {
  225. DRM_ERROR("%s: Oops: fence %llx -> %llx\n",
  226. __func__, fence_id, f);
  227. } else {
  228. fence_id = f;
  229. }
  230. }
  231. if (entry->resp_cb)
  232. entry->resp_cb(vgdev, entry);
  233. list_del(&entry->list);
  234. free_vbuf(vgdev, entry);
  235. }
  236. wake_up(&vgdev->ctrlq.ack_queue);
  237. if (fence_id)
  238. virtio_gpu_fence_event_process(vgdev, fence_id);
  239. }
  240. void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
  241. {
  242. struct virtio_gpu_device *vgdev =
  243. container_of(work, struct virtio_gpu_device,
  244. cursorq.dequeue_work);
  245. struct list_head reclaim_list;
  246. struct virtio_gpu_vbuffer *entry, *tmp;
  247. INIT_LIST_HEAD(&reclaim_list);
  248. spin_lock(&vgdev->cursorq.qlock);
  249. do {
  250. virtqueue_disable_cb(vgdev->cursorq.vq);
  251. reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
  252. } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
  253. spin_unlock(&vgdev->cursorq.qlock);
  254. list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
  255. list_del(&entry->list);
  256. free_vbuf(vgdev, entry);
  257. }
  258. wake_up(&vgdev->cursorq.ack_queue);
  259. }
  260. static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev,
  261. struct virtio_gpu_vbuffer *vbuf)
  262. __releases(&vgdev->ctrlq.qlock)
  263. __acquires(&vgdev->ctrlq.qlock)
  264. {
  265. struct virtqueue *vq = vgdev->ctrlq.vq;
  266. struct scatterlist *sgs[3], vcmd, vout, vresp;
  267. int outcnt = 0, incnt = 0;
  268. int ret;
  269. if (!vgdev->vqs_ready)
  270. return -ENODEV;
  271. sg_init_one(&vcmd, vbuf->buf, vbuf->size);
  272. sgs[outcnt+incnt] = &vcmd;
  273. outcnt++;
  274. if (vbuf->data_size) {
  275. sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
  276. sgs[outcnt + incnt] = &vout;
  277. outcnt++;
  278. }
  279. if (vbuf->resp_size) {
  280. sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
  281. sgs[outcnt + incnt] = &vresp;
  282. incnt++;
  283. }
  284. retry:
  285. ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
  286. if (ret == -ENOSPC) {
  287. spin_unlock(&vgdev->ctrlq.qlock);
  288. wait_event(vgdev->ctrlq.ack_queue, vq->num_free);
  289. spin_lock(&vgdev->ctrlq.qlock);
  290. goto retry;
  291. } else {
  292. virtqueue_kick(vq);
  293. }
  294. if (!ret)
  295. ret = vq->num_free;
  296. return ret;
  297. }
  298. static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
  299. struct virtio_gpu_vbuffer *vbuf)
  300. {
  301. int rc;
  302. spin_lock(&vgdev->ctrlq.qlock);
  303. rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
  304. spin_unlock(&vgdev->ctrlq.qlock);
  305. return rc;
  306. }
  307. static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
  308. struct virtio_gpu_vbuffer *vbuf,
  309. struct virtio_gpu_ctrl_hdr *hdr,
  310. struct virtio_gpu_fence **fence)
  311. {
  312. struct virtqueue *vq = vgdev->ctrlq.vq;
  313. int rc;
  314. again:
  315. spin_lock(&vgdev->ctrlq.qlock);
  316. /*
  317. * Make sure we have enouth space in the virtqueue. If not
  318. * wait here until we have.
  319. *
  320. * Without that virtio_gpu_queue_ctrl_buffer_nolock might have
  321. * to wait for free space, which can result in fence ids being
  322. * submitted out-of-order.
  323. */
  324. if (vq->num_free < 3) {
  325. spin_unlock(&vgdev->ctrlq.qlock);
  326. wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3);
  327. goto again;
  328. }
  329. if (fence)
  330. virtio_gpu_fence_emit(vgdev, hdr, fence);
  331. rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
  332. spin_unlock(&vgdev->ctrlq.qlock);
  333. return rc;
  334. }
  335. static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
  336. struct virtio_gpu_vbuffer *vbuf)
  337. {
  338. struct virtqueue *vq = vgdev->cursorq.vq;
  339. struct scatterlist *sgs[1], ccmd;
  340. int ret;
  341. int outcnt;
  342. if (!vgdev->vqs_ready)
  343. return -ENODEV;
  344. sg_init_one(&ccmd, vbuf->buf, vbuf->size);
  345. sgs[0] = &ccmd;
  346. outcnt = 1;
  347. spin_lock(&vgdev->cursorq.qlock);
  348. retry:
  349. ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
  350. if (ret == -ENOSPC) {
  351. spin_unlock(&vgdev->cursorq.qlock);
  352. wait_event(vgdev->cursorq.ack_queue, vq->num_free);
  353. spin_lock(&vgdev->cursorq.qlock);
  354. goto retry;
  355. } else {
  356. virtqueue_kick(vq);
  357. }
  358. spin_unlock(&vgdev->cursorq.qlock);
  359. if (!ret)
  360. ret = vq->num_free;
  361. return ret;
  362. }
  363. /* just create gem objects for userspace and long lived objects,
  364. just use dma_alloced pages for the queue objects? */
  365. /* create a basic resource */
  366. void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
  367. uint32_t resource_id,
  368. uint32_t format,
  369. uint32_t width,
  370. uint32_t height)
  371. {
  372. struct virtio_gpu_resource_create_2d *cmd_p;
  373. struct virtio_gpu_vbuffer *vbuf;
  374. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  375. memset(cmd_p, 0, sizeof(*cmd_p));
  376. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
  377. cmd_p->resource_id = cpu_to_le32(resource_id);
  378. cmd_p->format = cpu_to_le32(format);
  379. cmd_p->width = cpu_to_le32(width);
  380. cmd_p->height = cpu_to_le32(height);
  381. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  382. }
  383. void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
  384. uint32_t resource_id)
  385. {
  386. struct virtio_gpu_resource_unref *cmd_p;
  387. struct virtio_gpu_vbuffer *vbuf;
  388. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  389. memset(cmd_p, 0, sizeof(*cmd_p));
  390. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
  391. cmd_p->resource_id = cpu_to_le32(resource_id);
  392. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  393. }
  394. void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev,
  395. uint32_t resource_id)
  396. {
  397. struct virtio_gpu_resource_detach_backing *cmd_p;
  398. struct virtio_gpu_vbuffer *vbuf;
  399. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  400. memset(cmd_p, 0, sizeof(*cmd_p));
  401. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
  402. cmd_p->resource_id = cpu_to_le32(resource_id);
  403. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  404. }
  405. void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
  406. uint32_t scanout_id, uint32_t resource_id,
  407. uint32_t width, uint32_t height,
  408. uint32_t x, uint32_t y)
  409. {
  410. struct virtio_gpu_set_scanout *cmd_p;
  411. struct virtio_gpu_vbuffer *vbuf;
  412. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  413. memset(cmd_p, 0, sizeof(*cmd_p));
  414. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
  415. cmd_p->resource_id = cpu_to_le32(resource_id);
  416. cmd_p->scanout_id = cpu_to_le32(scanout_id);
  417. cmd_p->r.width = cpu_to_le32(width);
  418. cmd_p->r.height = cpu_to_le32(height);
  419. cmd_p->r.x = cpu_to_le32(x);
  420. cmd_p->r.y = cpu_to_le32(y);
  421. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  422. }
  423. void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
  424. uint32_t resource_id,
  425. uint32_t x, uint32_t y,
  426. uint32_t width, uint32_t height)
  427. {
  428. struct virtio_gpu_resource_flush *cmd_p;
  429. struct virtio_gpu_vbuffer *vbuf;
  430. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  431. memset(cmd_p, 0, sizeof(*cmd_p));
  432. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
  433. cmd_p->resource_id = cpu_to_le32(resource_id);
  434. cmd_p->r.width = cpu_to_le32(width);
  435. cmd_p->r.height = cpu_to_le32(height);
  436. cmd_p->r.x = cpu_to_le32(x);
  437. cmd_p->r.y = cpu_to_le32(y);
  438. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  439. }
  440. void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
  441. uint32_t resource_id, uint64_t offset,
  442. __le32 width, __le32 height,
  443. __le32 x, __le32 y,
  444. struct virtio_gpu_fence **fence)
  445. {
  446. struct virtio_gpu_transfer_to_host_2d *cmd_p;
  447. struct virtio_gpu_vbuffer *vbuf;
  448. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  449. memset(cmd_p, 0, sizeof(*cmd_p));
  450. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
  451. cmd_p->resource_id = cpu_to_le32(resource_id);
  452. cmd_p->offset = cpu_to_le64(offset);
  453. cmd_p->r.width = width;
  454. cmd_p->r.height = height;
  455. cmd_p->r.x = x;
  456. cmd_p->r.y = y;
  457. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  458. }
  459. static void
  460. virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
  461. uint32_t resource_id,
  462. struct virtio_gpu_mem_entry *ents,
  463. uint32_t nents,
  464. struct virtio_gpu_fence **fence)
  465. {
  466. struct virtio_gpu_resource_attach_backing *cmd_p;
  467. struct virtio_gpu_vbuffer *vbuf;
  468. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  469. memset(cmd_p, 0, sizeof(*cmd_p));
  470. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
  471. cmd_p->resource_id = cpu_to_le32(resource_id);
  472. cmd_p->nr_entries = cpu_to_le32(nents);
  473. vbuf->data_buf = ents;
  474. vbuf->data_size = sizeof(*ents) * nents;
  475. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  476. }
  477. static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
  478. struct virtio_gpu_vbuffer *vbuf)
  479. {
  480. struct virtio_gpu_resp_display_info *resp =
  481. (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
  482. int i;
  483. spin_lock(&vgdev->display_info_lock);
  484. for (i = 0; i < vgdev->num_scanouts; i++) {
  485. vgdev->outputs[i].info = resp->pmodes[i];
  486. if (resp->pmodes[i].enabled) {
  487. DRM_DEBUG("output %d: %dx%d+%d+%d", i,
  488. le32_to_cpu(resp->pmodes[i].r.width),
  489. le32_to_cpu(resp->pmodes[i].r.height),
  490. le32_to_cpu(resp->pmodes[i].r.x),
  491. le32_to_cpu(resp->pmodes[i].r.y));
  492. } else {
  493. DRM_DEBUG("output %d: disabled", i);
  494. }
  495. }
  496. vgdev->display_info_pending = false;
  497. spin_unlock(&vgdev->display_info_lock);
  498. wake_up(&vgdev->resp_wq);
  499. if (!drm_helper_hpd_irq_event(vgdev->ddev))
  500. drm_kms_helper_hotplug_event(vgdev->ddev);
  501. }
  502. static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
  503. struct virtio_gpu_vbuffer *vbuf)
  504. {
  505. struct virtio_gpu_get_capset_info *cmd =
  506. (struct virtio_gpu_get_capset_info *)vbuf->buf;
  507. struct virtio_gpu_resp_capset_info *resp =
  508. (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
  509. int i = le32_to_cpu(cmd->capset_index);
  510. spin_lock(&vgdev->display_info_lock);
  511. vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
  512. vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
  513. vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
  514. spin_unlock(&vgdev->display_info_lock);
  515. wake_up(&vgdev->resp_wq);
  516. }
  517. static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
  518. struct virtio_gpu_vbuffer *vbuf)
  519. {
  520. struct virtio_gpu_get_capset *cmd =
  521. (struct virtio_gpu_get_capset *)vbuf->buf;
  522. struct virtio_gpu_resp_capset *resp =
  523. (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
  524. struct virtio_gpu_drv_cap_cache *cache_ent;
  525. spin_lock(&vgdev->display_info_lock);
  526. list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
  527. if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
  528. cache_ent->id == le32_to_cpu(cmd->capset_id)) {
  529. memcpy(cache_ent->caps_cache, resp->capset_data,
  530. cache_ent->size);
  531. atomic_set(&cache_ent->is_valid, 1);
  532. break;
  533. }
  534. }
  535. spin_unlock(&vgdev->display_info_lock);
  536. wake_up(&vgdev->resp_wq);
  537. }
  538. int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
  539. {
  540. struct virtio_gpu_ctrl_hdr *cmd_p;
  541. struct virtio_gpu_vbuffer *vbuf;
  542. void *resp_buf;
  543. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
  544. GFP_KERNEL);
  545. if (!resp_buf)
  546. return -ENOMEM;
  547. cmd_p = virtio_gpu_alloc_cmd_resp
  548. (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
  549. sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
  550. resp_buf);
  551. memset(cmd_p, 0, sizeof(*cmd_p));
  552. vgdev->display_info_pending = true;
  553. cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
  554. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  555. return 0;
  556. }
  557. int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
  558. {
  559. struct virtio_gpu_get_capset_info *cmd_p;
  560. struct virtio_gpu_vbuffer *vbuf;
  561. void *resp_buf;
  562. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
  563. GFP_KERNEL);
  564. if (!resp_buf)
  565. return -ENOMEM;
  566. cmd_p = virtio_gpu_alloc_cmd_resp
  567. (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
  568. sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
  569. resp_buf);
  570. memset(cmd_p, 0, sizeof(*cmd_p));
  571. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
  572. cmd_p->capset_index = cpu_to_le32(idx);
  573. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  574. return 0;
  575. }
  576. int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
  577. int idx, int version,
  578. struct virtio_gpu_drv_cap_cache **cache_p)
  579. {
  580. struct virtio_gpu_get_capset *cmd_p;
  581. struct virtio_gpu_vbuffer *vbuf;
  582. int max_size = vgdev->capsets[idx].max_size;
  583. struct virtio_gpu_drv_cap_cache *cache_ent;
  584. void *resp_buf;
  585. if (idx > vgdev->num_capsets)
  586. return -EINVAL;
  587. if (version > vgdev->capsets[idx].max_version)
  588. return -EINVAL;
  589. cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
  590. if (!cache_ent)
  591. return -ENOMEM;
  592. cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
  593. if (!cache_ent->caps_cache) {
  594. kfree(cache_ent);
  595. return -ENOMEM;
  596. }
  597. resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
  598. GFP_KERNEL);
  599. if (!resp_buf) {
  600. kfree(cache_ent->caps_cache);
  601. kfree(cache_ent);
  602. return -ENOMEM;
  603. }
  604. cache_ent->version = version;
  605. cache_ent->id = vgdev->capsets[idx].id;
  606. atomic_set(&cache_ent->is_valid, 0);
  607. cache_ent->size = max_size;
  608. spin_lock(&vgdev->display_info_lock);
  609. list_add_tail(&cache_ent->head, &vgdev->cap_cache);
  610. spin_unlock(&vgdev->display_info_lock);
  611. cmd_p = virtio_gpu_alloc_cmd_resp
  612. (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
  613. sizeof(struct virtio_gpu_resp_capset) + max_size,
  614. resp_buf);
  615. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
  616. cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
  617. cmd_p->capset_version = cpu_to_le32(version);
  618. *cache_p = cache_ent;
  619. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  620. return 0;
  621. }
  622. void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
  623. uint32_t nlen, const char *name)
  624. {
  625. struct virtio_gpu_ctx_create *cmd_p;
  626. struct virtio_gpu_vbuffer *vbuf;
  627. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  628. memset(cmd_p, 0, sizeof(*cmd_p));
  629. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
  630. cmd_p->hdr.ctx_id = cpu_to_le32(id);
  631. cmd_p->nlen = cpu_to_le32(nlen);
  632. strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name)-1);
  633. cmd_p->debug_name[sizeof(cmd_p->debug_name)-1] = 0;
  634. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  635. }
  636. void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
  637. uint32_t id)
  638. {
  639. struct virtio_gpu_ctx_destroy *cmd_p;
  640. struct virtio_gpu_vbuffer *vbuf;
  641. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  642. memset(cmd_p, 0, sizeof(*cmd_p));
  643. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
  644. cmd_p->hdr.ctx_id = cpu_to_le32(id);
  645. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  646. }
  647. void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
  648. uint32_t ctx_id,
  649. uint32_t resource_id)
  650. {
  651. struct virtio_gpu_ctx_resource *cmd_p;
  652. struct virtio_gpu_vbuffer *vbuf;
  653. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  654. memset(cmd_p, 0, sizeof(*cmd_p));
  655. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
  656. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  657. cmd_p->resource_id = cpu_to_le32(resource_id);
  658. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  659. }
  660. void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
  661. uint32_t ctx_id,
  662. uint32_t resource_id)
  663. {
  664. struct virtio_gpu_ctx_resource *cmd_p;
  665. struct virtio_gpu_vbuffer *vbuf;
  666. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  667. memset(cmd_p, 0, sizeof(*cmd_p));
  668. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
  669. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  670. cmd_p->resource_id = cpu_to_le32(resource_id);
  671. virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
  672. }
  673. void
  674. virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
  675. struct virtio_gpu_resource_create_3d *rc_3d,
  676. struct virtio_gpu_fence **fence)
  677. {
  678. struct virtio_gpu_resource_create_3d *cmd_p;
  679. struct virtio_gpu_vbuffer *vbuf;
  680. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  681. memset(cmd_p, 0, sizeof(*cmd_p));
  682. *cmd_p = *rc_3d;
  683. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
  684. cmd_p->hdr.flags = 0;
  685. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  686. }
  687. void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
  688. uint32_t resource_id, uint32_t ctx_id,
  689. uint64_t offset, uint32_t level,
  690. struct virtio_gpu_box *box,
  691. struct virtio_gpu_fence **fence)
  692. {
  693. struct virtio_gpu_transfer_host_3d *cmd_p;
  694. struct virtio_gpu_vbuffer *vbuf;
  695. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  696. memset(cmd_p, 0, sizeof(*cmd_p));
  697. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
  698. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  699. cmd_p->resource_id = cpu_to_le32(resource_id);
  700. cmd_p->box = *box;
  701. cmd_p->offset = cpu_to_le64(offset);
  702. cmd_p->level = cpu_to_le32(level);
  703. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  704. }
  705. void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
  706. uint32_t resource_id, uint32_t ctx_id,
  707. uint64_t offset, uint32_t level,
  708. struct virtio_gpu_box *box,
  709. struct virtio_gpu_fence **fence)
  710. {
  711. struct virtio_gpu_transfer_host_3d *cmd_p;
  712. struct virtio_gpu_vbuffer *vbuf;
  713. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  714. memset(cmd_p, 0, sizeof(*cmd_p));
  715. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
  716. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  717. cmd_p->resource_id = cpu_to_le32(resource_id);
  718. cmd_p->box = *box;
  719. cmd_p->offset = cpu_to_le64(offset);
  720. cmd_p->level = cpu_to_le32(level);
  721. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  722. }
  723. void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
  724. void *data, uint32_t data_size,
  725. uint32_t ctx_id, struct virtio_gpu_fence **fence)
  726. {
  727. struct virtio_gpu_cmd_submit *cmd_p;
  728. struct virtio_gpu_vbuffer *vbuf;
  729. cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
  730. memset(cmd_p, 0, sizeof(*cmd_p));
  731. vbuf->data_buf = data;
  732. vbuf->data_size = data_size;
  733. cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
  734. cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
  735. cmd_p->size = cpu_to_le32(data_size);
  736. virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
  737. }
  738. int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
  739. struct virtio_gpu_object *obj,
  740. uint32_t resource_id,
  741. struct virtio_gpu_fence **fence)
  742. {
  743. struct virtio_gpu_mem_entry *ents;
  744. struct scatterlist *sg;
  745. int si;
  746. if (!obj->pages) {
  747. int ret;
  748. ret = virtio_gpu_object_get_sg_table(vgdev, obj);
  749. if (ret)
  750. return ret;
  751. }
  752. /* gets freed when the ring has consumed it */
  753. ents = kmalloc_array(obj->pages->nents,
  754. sizeof(struct virtio_gpu_mem_entry),
  755. GFP_KERNEL);
  756. if (!ents) {
  757. DRM_ERROR("failed to allocate ent list\n");
  758. return -ENOMEM;
  759. }
  760. for_each_sg(obj->pages->sgl, sg, obj->pages->nents, si) {
  761. ents[si].addr = cpu_to_le64(sg_phys(sg));
  762. ents[si].length = cpu_to_le32(sg->length);
  763. ents[si].padding = 0;
  764. }
  765. virtio_gpu_cmd_resource_attach_backing(vgdev, resource_id,
  766. ents, obj->pages->nents,
  767. fence);
  768. obj->hw_res_handle = resource_id;
  769. return 0;
  770. }
  771. void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
  772. struct virtio_gpu_output *output)
  773. {
  774. struct virtio_gpu_vbuffer *vbuf;
  775. struct virtio_gpu_update_cursor *cur_p;
  776. output->cursor.pos.scanout_id = cpu_to_le32(output->index);
  777. cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
  778. memcpy(cur_p, &output->cursor, sizeof(output->cursor));
  779. virtio_gpu_queue_cursor(vgdev, vbuf);
  780. }