virtgpu_plane.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. */
  25. #include "virtgpu_drv.h"
  26. #include <drm/drm_plane_helper.h>
  27. #include <drm/drm_atomic_helper.h>
  28. static const uint32_t virtio_gpu_formats[] = {
  29. DRM_FORMAT_XRGB8888,
  30. DRM_FORMAT_ARGB8888,
  31. DRM_FORMAT_BGRX8888,
  32. DRM_FORMAT_BGRA8888,
  33. DRM_FORMAT_RGBX8888,
  34. DRM_FORMAT_RGBA8888,
  35. DRM_FORMAT_XBGR8888,
  36. DRM_FORMAT_ABGR8888,
  37. };
  38. static const uint32_t virtio_gpu_cursor_formats[] = {
  39. DRM_FORMAT_ARGB8888,
  40. };
  41. static void virtio_gpu_plane_destroy(struct drm_plane *plane)
  42. {
  43. kfree(plane);
  44. }
  45. static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
  46. .update_plane = drm_atomic_helper_update_plane,
  47. .disable_plane = drm_atomic_helper_disable_plane,
  48. .destroy = virtio_gpu_plane_destroy,
  49. .reset = drm_atomic_helper_plane_reset,
  50. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  51. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  52. };
  53. static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
  54. struct drm_plane_state *state)
  55. {
  56. return 0;
  57. }
  58. static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
  59. struct drm_plane_state *old_state)
  60. {
  61. struct drm_device *dev = plane->dev;
  62. struct virtio_gpu_device *vgdev = dev->dev_private;
  63. struct virtio_gpu_output *output = NULL;
  64. struct virtio_gpu_framebuffer *vgfb;
  65. struct virtio_gpu_object *bo;
  66. uint32_t handle;
  67. if (plane->state->crtc)
  68. output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
  69. if (old_state->crtc)
  70. output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
  71. if (WARN_ON(!output))
  72. return;
  73. if (plane->state->fb) {
  74. vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
  75. bo = gem_to_virtio_gpu_obj(vgfb->obj);
  76. handle = bo->hw_res_handle;
  77. if (bo->dumb) {
  78. virtio_gpu_cmd_transfer_to_host_2d
  79. (vgdev, handle, 0,
  80. cpu_to_le32(plane->state->src_w >> 16),
  81. cpu_to_le32(plane->state->src_h >> 16),
  82. cpu_to_le32(plane->state->src_x >> 16),
  83. cpu_to_le32(plane->state->src_y >> 16), NULL);
  84. }
  85. } else {
  86. handle = 0;
  87. }
  88. DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle,
  89. plane->state->crtc_w, plane->state->crtc_h,
  90. plane->state->crtc_x, plane->state->crtc_y,
  91. plane->state->src_w >> 16,
  92. plane->state->src_h >> 16,
  93. plane->state->src_x >> 16,
  94. plane->state->src_y >> 16);
  95. virtio_gpu_cmd_set_scanout(vgdev, output->index, handle,
  96. plane->state->src_w >> 16,
  97. plane->state->src_h >> 16,
  98. plane->state->src_x >> 16,
  99. plane->state->src_y >> 16);
  100. virtio_gpu_cmd_resource_flush(vgdev, handle,
  101. plane->state->src_x >> 16,
  102. plane->state->src_y >> 16,
  103. plane->state->src_w >> 16,
  104. plane->state->src_h >> 16);
  105. }
  106. static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
  107. struct drm_plane_state *old_state)
  108. {
  109. struct drm_device *dev = plane->dev;
  110. struct virtio_gpu_device *vgdev = dev->dev_private;
  111. struct virtio_gpu_output *output = NULL;
  112. struct virtio_gpu_framebuffer *vgfb;
  113. struct virtio_gpu_fence *fence = NULL;
  114. struct virtio_gpu_object *bo = NULL;
  115. uint32_t handle;
  116. int ret = 0;
  117. if (plane->state->crtc)
  118. output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
  119. if (old_state->crtc)
  120. output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
  121. if (WARN_ON(!output))
  122. return;
  123. if (plane->state->fb) {
  124. vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
  125. bo = gem_to_virtio_gpu_obj(vgfb->obj);
  126. handle = bo->hw_res_handle;
  127. } else {
  128. handle = 0;
  129. }
  130. if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
  131. /* new cursor -- update & wait */
  132. virtio_gpu_cmd_transfer_to_host_2d
  133. (vgdev, handle, 0,
  134. cpu_to_le32(plane->state->crtc_w),
  135. cpu_to_le32(plane->state->crtc_h),
  136. 0, 0, &fence);
  137. ret = virtio_gpu_object_reserve(bo, false);
  138. if (!ret) {
  139. reservation_object_add_excl_fence(bo->tbo.resv,
  140. &fence->f);
  141. dma_fence_put(&fence->f);
  142. fence = NULL;
  143. virtio_gpu_object_unreserve(bo);
  144. virtio_gpu_object_wait(bo, false);
  145. }
  146. }
  147. if (plane->state->fb != old_state->fb) {
  148. DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
  149. plane->state->crtc_x,
  150. plane->state->crtc_y,
  151. plane->state->fb ? plane->state->fb->hot_x : 0,
  152. plane->state->fb ? plane->state->fb->hot_y : 0);
  153. output->cursor.hdr.type =
  154. cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
  155. output->cursor.resource_id = cpu_to_le32(handle);
  156. if (plane->state->fb) {
  157. output->cursor.hot_x =
  158. cpu_to_le32(plane->state->fb->hot_x);
  159. output->cursor.hot_y =
  160. cpu_to_le32(plane->state->fb->hot_y);
  161. } else {
  162. output->cursor.hot_x = cpu_to_le32(0);
  163. output->cursor.hot_y = cpu_to_le32(0);
  164. }
  165. } else {
  166. DRM_DEBUG("move +%d+%d\n",
  167. plane->state->crtc_x,
  168. plane->state->crtc_y);
  169. output->cursor.hdr.type =
  170. cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
  171. }
  172. output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
  173. output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
  174. virtio_gpu_cursor_ping(vgdev, output);
  175. }
  176. static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
  177. .atomic_check = virtio_gpu_plane_atomic_check,
  178. .atomic_update = virtio_gpu_primary_plane_update,
  179. };
  180. static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
  181. .atomic_check = virtio_gpu_plane_atomic_check,
  182. .atomic_update = virtio_gpu_cursor_plane_update,
  183. };
  184. struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
  185. enum drm_plane_type type,
  186. int index)
  187. {
  188. struct drm_device *dev = vgdev->ddev;
  189. const struct drm_plane_helper_funcs *funcs;
  190. struct drm_plane *plane;
  191. const uint32_t *formats;
  192. int ret, nformats;
  193. plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  194. if (!plane)
  195. return ERR_PTR(-ENOMEM);
  196. if (type == DRM_PLANE_TYPE_CURSOR) {
  197. formats = virtio_gpu_cursor_formats;
  198. nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
  199. funcs = &virtio_gpu_cursor_helper_funcs;
  200. } else {
  201. formats = virtio_gpu_formats;
  202. nformats = ARRAY_SIZE(virtio_gpu_formats);
  203. funcs = &virtio_gpu_primary_helper_funcs;
  204. }
  205. ret = drm_universal_plane_init(dev, plane, 1 << index,
  206. &virtio_gpu_plane_funcs,
  207. formats, nformats,
  208. type, NULL);
  209. if (ret)
  210. goto err_plane_init;
  211. drm_plane_helper_add(plane, funcs);
  212. return plane;
  213. err_plane_init:
  214. kfree(plane);
  215. return ERR_PTR(ret);
  216. }