tilcdc_drv.c 18 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include <linux/component.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/suspend.h>
  21. #include <drm/drm_atomic.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include "tilcdc_drv.h"
  24. #include "tilcdc_regs.h"
  25. #include "tilcdc_tfp410.h"
  26. #include "tilcdc_panel.h"
  27. #include "tilcdc_external.h"
  28. #include "drm_fb_helper.h"
  29. static LIST_HEAD(module_list);
  30. static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  31. static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  32. DRM_FORMAT_BGR888,
  33. DRM_FORMAT_XBGR8888 };
  34. static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  35. DRM_FORMAT_RGB888,
  36. DRM_FORMAT_XRGB8888 };
  37. static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  38. DRM_FORMAT_RGB888,
  39. DRM_FORMAT_XRGB8888 };
  40. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  41. const struct tilcdc_module_ops *funcs)
  42. {
  43. mod->name = name;
  44. mod->funcs = funcs;
  45. INIT_LIST_HEAD(&mod->list);
  46. list_add(&mod->list, &module_list);
  47. }
  48. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  49. {
  50. list_del(&mod->list);
  51. }
  52. static struct of_device_id tilcdc_of_match[];
  53. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  54. struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  55. {
  56. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  57. }
  58. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  59. {
  60. struct tilcdc_drm_private *priv = dev->dev_private;
  61. drm_fbdev_cma_hotplug_event(priv->fbdev);
  62. }
  63. static int tilcdc_atomic_check(struct drm_device *dev,
  64. struct drm_atomic_state *state)
  65. {
  66. int ret;
  67. ret = drm_atomic_helper_check_modeset(dev, state);
  68. if (ret)
  69. return ret;
  70. ret = drm_atomic_helper_check_planes(dev, state);
  71. if (ret)
  72. return ret;
  73. /*
  74. * tilcdc ->atomic_check can update ->mode_changed if pixel format
  75. * changes, hence will we check modeset changes again.
  76. */
  77. ret = drm_atomic_helper_check_modeset(dev, state);
  78. if (ret)
  79. return ret;
  80. return ret;
  81. }
  82. static int tilcdc_commit(struct drm_device *dev,
  83. struct drm_atomic_state *state,
  84. bool async)
  85. {
  86. int ret;
  87. ret = drm_atomic_helper_prepare_planes(dev, state);
  88. if (ret)
  89. return ret;
  90. drm_atomic_helper_swap_state(state, true);
  91. /*
  92. * Everything below can be run asynchronously without the need to grab
  93. * any modeset locks at all under one condition: It must be guaranteed
  94. * that the asynchronous work has either been cancelled (if the driver
  95. * supports it, which at least requires that the framebuffers get
  96. * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
  97. * before the new state gets committed on the software side with
  98. * drm_atomic_helper_swap_state().
  99. *
  100. * This scheme allows new atomic state updates to be prepared and
  101. * checked in parallel to the asynchronous completion of the previous
  102. * update. Which is important since compositors need to figure out the
  103. * composition of the next frame right after having submitted the
  104. * current layout.
  105. */
  106. drm_atomic_helper_commit_modeset_disables(dev, state);
  107. drm_atomic_helper_commit_planes(dev, state, 0);
  108. drm_atomic_helper_commit_modeset_enables(dev, state);
  109. drm_atomic_helper_wait_for_vblanks(dev, state);
  110. drm_atomic_helper_cleanup_planes(dev, state);
  111. return 0;
  112. }
  113. static const struct drm_mode_config_funcs mode_config_funcs = {
  114. .fb_create = tilcdc_fb_create,
  115. .output_poll_changed = tilcdc_fb_output_poll_changed,
  116. .atomic_check = tilcdc_atomic_check,
  117. .atomic_commit = tilcdc_commit,
  118. };
  119. static void modeset_init(struct drm_device *dev)
  120. {
  121. struct tilcdc_drm_private *priv = dev->dev_private;
  122. struct tilcdc_module *mod;
  123. list_for_each_entry(mod, &module_list, list) {
  124. DBG("loading module: %s", mod->name);
  125. mod->funcs->modeset_init(mod, dev);
  126. }
  127. dev->mode_config.min_width = 0;
  128. dev->mode_config.min_height = 0;
  129. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  130. dev->mode_config.max_height = 2048;
  131. dev->mode_config.funcs = &mode_config_funcs;
  132. }
  133. #ifdef CONFIG_CPU_FREQ
  134. static int cpufreq_transition(struct notifier_block *nb,
  135. unsigned long val, void *data)
  136. {
  137. struct tilcdc_drm_private *priv = container_of(nb,
  138. struct tilcdc_drm_private, freq_transition);
  139. if (val == CPUFREQ_POSTCHANGE)
  140. tilcdc_crtc_update_clk(priv->crtc);
  141. return 0;
  142. }
  143. #endif
  144. /*
  145. * DRM operations:
  146. */
  147. static void tilcdc_fini(struct drm_device *dev)
  148. {
  149. struct tilcdc_drm_private *priv = dev->dev_private;
  150. if (priv->crtc)
  151. tilcdc_crtc_shutdown(priv->crtc);
  152. if (priv->is_registered)
  153. drm_dev_unregister(dev);
  154. drm_kms_helper_poll_fini(dev);
  155. if (priv->fbdev)
  156. drm_fbdev_cma_fini(priv->fbdev);
  157. drm_irq_uninstall(dev);
  158. drm_mode_config_cleanup(dev);
  159. tilcdc_remove_external_device(dev);
  160. #ifdef CONFIG_CPU_FREQ
  161. if (priv->freq_transition.notifier_call)
  162. cpufreq_unregister_notifier(&priv->freq_transition,
  163. CPUFREQ_TRANSITION_NOTIFIER);
  164. #endif
  165. if (priv->clk)
  166. clk_put(priv->clk);
  167. if (priv->mmio)
  168. iounmap(priv->mmio);
  169. if (priv->wq) {
  170. flush_workqueue(priv->wq);
  171. destroy_workqueue(priv->wq);
  172. }
  173. dev->dev_private = NULL;
  174. pm_runtime_disable(dev->dev);
  175. drm_dev_unref(dev);
  176. }
  177. static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
  178. {
  179. struct drm_device *ddev;
  180. struct platform_device *pdev = to_platform_device(dev);
  181. struct device_node *node = dev->of_node;
  182. struct tilcdc_drm_private *priv;
  183. struct resource *res;
  184. u32 bpp = 0;
  185. int ret;
  186. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  187. if (!priv) {
  188. dev_err(dev, "failed to allocate private data\n");
  189. return -ENOMEM;
  190. }
  191. ddev = drm_dev_alloc(ddrv, dev);
  192. if (IS_ERR(ddev))
  193. return PTR_ERR(ddev);
  194. ddev->platformdev = pdev;
  195. ddev->dev_private = priv;
  196. platform_set_drvdata(pdev, ddev);
  197. drm_mode_config_init(ddev);
  198. priv->is_componentized =
  199. tilcdc_get_external_components(dev, NULL) > 0;
  200. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  201. if (!priv->wq) {
  202. ret = -ENOMEM;
  203. goto init_failed;
  204. }
  205. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  206. if (!res) {
  207. dev_err(dev, "failed to get memory resource\n");
  208. ret = -EINVAL;
  209. goto init_failed;
  210. }
  211. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  212. if (!priv->mmio) {
  213. dev_err(dev, "failed to ioremap\n");
  214. ret = -ENOMEM;
  215. goto init_failed;
  216. }
  217. priv->clk = clk_get(dev, "fck");
  218. if (IS_ERR(priv->clk)) {
  219. dev_err(dev, "failed to get functional clock\n");
  220. ret = -ENODEV;
  221. goto init_failed;
  222. }
  223. #ifdef CONFIG_CPU_FREQ
  224. priv->freq_transition.notifier_call = cpufreq_transition;
  225. ret = cpufreq_register_notifier(&priv->freq_transition,
  226. CPUFREQ_TRANSITION_NOTIFIER);
  227. if (ret) {
  228. dev_err(dev, "failed to register cpufreq notifier\n");
  229. priv->freq_transition.notifier_call = NULL;
  230. goto init_failed;
  231. }
  232. #endif
  233. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  234. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  235. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  236. if (of_property_read_u32(node, "max-width", &priv->max_width))
  237. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  238. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  239. if (of_property_read_u32(node, "max-pixelclock",
  240. &priv->max_pixelclock))
  241. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  242. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  243. pm_runtime_enable(dev);
  244. /* Determine LCD IP Version */
  245. pm_runtime_get_sync(dev);
  246. switch (tilcdc_read(ddev, LCDC_PID_REG)) {
  247. case 0x4c100102:
  248. priv->rev = 1;
  249. break;
  250. case 0x4f200800:
  251. case 0x4f201000:
  252. priv->rev = 2;
  253. break;
  254. default:
  255. dev_warn(dev, "Unknown PID Reg value 0x%08x, "
  256. "defaulting to LCD revision 1\n",
  257. tilcdc_read(ddev, LCDC_PID_REG));
  258. priv->rev = 1;
  259. break;
  260. }
  261. pm_runtime_put_sync(dev);
  262. if (priv->rev == 1) {
  263. DBG("Revision 1 LCDC supports only RGB565 format");
  264. priv->pixelformats = tilcdc_rev1_formats;
  265. priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
  266. bpp = 16;
  267. } else {
  268. const char *str = "\0";
  269. of_property_read_string(node, "blue-and-red-wiring", &str);
  270. if (0 == strcmp(str, "crossed")) {
  271. DBG("Configured for crossed blue and red wires");
  272. priv->pixelformats = tilcdc_crossed_formats;
  273. priv->num_pixelformats =
  274. ARRAY_SIZE(tilcdc_crossed_formats);
  275. bpp = 32; /* Choose bpp with RGB support for fbdef */
  276. } else if (0 == strcmp(str, "straight")) {
  277. DBG("Configured for straight blue and red wires");
  278. priv->pixelformats = tilcdc_straight_formats;
  279. priv->num_pixelformats =
  280. ARRAY_SIZE(tilcdc_straight_formats);
  281. bpp = 16; /* Choose bpp with RGB support for fbdef */
  282. } else {
  283. DBG("Blue and red wiring '%s' unknown, use legacy mode",
  284. str);
  285. priv->pixelformats = tilcdc_legacy_formats;
  286. priv->num_pixelformats =
  287. ARRAY_SIZE(tilcdc_legacy_formats);
  288. bpp = 16; /* This is just a guess */
  289. }
  290. }
  291. ret = tilcdc_crtc_create(ddev);
  292. if (ret < 0) {
  293. dev_err(dev, "failed to create crtc\n");
  294. goto init_failed;
  295. }
  296. modeset_init(ddev);
  297. if (priv->is_componentized) {
  298. ret = component_bind_all(dev, ddev);
  299. if (ret < 0)
  300. goto init_failed;
  301. ret = tilcdc_add_component_encoder(ddev);
  302. if (ret < 0)
  303. goto init_failed;
  304. } else {
  305. ret = tilcdc_attach_external_device(ddev);
  306. if (ret)
  307. goto init_failed;
  308. }
  309. if (!priv->external_connector &&
  310. ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
  311. dev_err(dev, "no encoders/connectors found\n");
  312. ret = -ENXIO;
  313. goto init_failed;
  314. }
  315. ret = drm_vblank_init(ddev, 1);
  316. if (ret < 0) {
  317. dev_err(dev, "failed to initialize vblank\n");
  318. goto init_failed;
  319. }
  320. ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
  321. if (ret < 0) {
  322. dev_err(dev, "failed to install IRQ handler\n");
  323. goto init_failed;
  324. }
  325. drm_mode_config_reset(ddev);
  326. priv->fbdev = drm_fbdev_cma_init(ddev, bpp,
  327. ddev->mode_config.num_connector);
  328. if (IS_ERR(priv->fbdev)) {
  329. ret = PTR_ERR(priv->fbdev);
  330. goto init_failed;
  331. }
  332. drm_kms_helper_poll_init(ddev);
  333. ret = drm_dev_register(ddev, 0);
  334. if (ret)
  335. goto init_failed;
  336. priv->is_registered = true;
  337. return 0;
  338. init_failed:
  339. tilcdc_fini(ddev);
  340. return ret;
  341. }
  342. static void tilcdc_lastclose(struct drm_device *dev)
  343. {
  344. struct tilcdc_drm_private *priv = dev->dev_private;
  345. drm_fbdev_cma_restore_mode(priv->fbdev);
  346. }
  347. static irqreturn_t tilcdc_irq(int irq, void *arg)
  348. {
  349. struct drm_device *dev = arg;
  350. struct tilcdc_drm_private *priv = dev->dev_private;
  351. return tilcdc_crtc_irq(priv->crtc);
  352. }
  353. static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
  354. {
  355. return 0;
  356. }
  357. static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
  358. {
  359. return;
  360. }
  361. #if defined(CONFIG_DEBUG_FS)
  362. static const struct {
  363. const char *name;
  364. uint8_t rev;
  365. uint8_t save;
  366. uint32_t reg;
  367. } registers[] = {
  368. #define REG(rev, save, reg) { #reg, rev, save, reg }
  369. /* exists in revision 1: */
  370. REG(1, false, LCDC_PID_REG),
  371. REG(1, true, LCDC_CTRL_REG),
  372. REG(1, false, LCDC_STAT_REG),
  373. REG(1, true, LCDC_RASTER_CTRL_REG),
  374. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  375. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  376. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  377. REG(1, true, LCDC_DMA_CTRL_REG),
  378. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  379. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  380. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  381. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  382. /* new in revision 2: */
  383. REG(2, false, LCDC_RAW_STAT_REG),
  384. REG(2, false, LCDC_MASKED_STAT_REG),
  385. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  386. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  387. REG(2, false, LCDC_END_OF_INT_IND_REG),
  388. REG(2, true, LCDC_CLK_ENABLE_REG),
  389. #undef REG
  390. };
  391. #endif
  392. #ifdef CONFIG_DEBUG_FS
  393. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  394. {
  395. struct drm_info_node *node = (struct drm_info_node *) m->private;
  396. struct drm_device *dev = node->minor->dev;
  397. struct tilcdc_drm_private *priv = dev->dev_private;
  398. unsigned i;
  399. pm_runtime_get_sync(dev->dev);
  400. seq_printf(m, "revision: %d\n", priv->rev);
  401. for (i = 0; i < ARRAY_SIZE(registers); i++)
  402. if (priv->rev >= registers[i].rev)
  403. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  404. tilcdc_read(dev, registers[i].reg));
  405. pm_runtime_put_sync(dev->dev);
  406. return 0;
  407. }
  408. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  409. {
  410. struct drm_info_node *node = (struct drm_info_node *) m->private;
  411. struct drm_device *dev = node->minor->dev;
  412. struct drm_printer p = drm_seq_file_printer(m);
  413. drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
  414. return 0;
  415. }
  416. static struct drm_info_list tilcdc_debugfs_list[] = {
  417. { "regs", tilcdc_regs_show, 0 },
  418. { "mm", tilcdc_mm_show, 0 },
  419. { "fb", drm_fb_cma_debugfs_show, 0 },
  420. };
  421. static int tilcdc_debugfs_init(struct drm_minor *minor)
  422. {
  423. struct drm_device *dev = minor->dev;
  424. struct tilcdc_module *mod;
  425. int ret;
  426. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  427. ARRAY_SIZE(tilcdc_debugfs_list),
  428. minor->debugfs_root, minor);
  429. list_for_each_entry(mod, &module_list, list)
  430. if (mod->funcs->debugfs_init)
  431. mod->funcs->debugfs_init(mod, minor);
  432. if (ret) {
  433. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  434. return ret;
  435. }
  436. return ret;
  437. }
  438. #endif
  439. static const struct file_operations fops = {
  440. .owner = THIS_MODULE,
  441. .open = drm_open,
  442. .release = drm_release,
  443. .unlocked_ioctl = drm_ioctl,
  444. .compat_ioctl = drm_compat_ioctl,
  445. .poll = drm_poll,
  446. .read = drm_read,
  447. .llseek = no_llseek,
  448. .mmap = drm_gem_cma_mmap,
  449. };
  450. static struct drm_driver tilcdc_driver = {
  451. .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
  452. DRIVER_PRIME | DRIVER_ATOMIC),
  453. .lastclose = tilcdc_lastclose,
  454. .irq_handler = tilcdc_irq,
  455. .get_vblank_counter = drm_vblank_no_hw_counter,
  456. .enable_vblank = tilcdc_enable_vblank,
  457. .disable_vblank = tilcdc_disable_vblank,
  458. .gem_free_object_unlocked = drm_gem_cma_free_object,
  459. .gem_vm_ops = &drm_gem_cma_vm_ops,
  460. .dumb_create = drm_gem_cma_dumb_create,
  461. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  462. .dumb_destroy = drm_gem_dumb_destroy,
  463. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  464. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  465. .gem_prime_import = drm_gem_prime_import,
  466. .gem_prime_export = drm_gem_prime_export,
  467. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  468. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  469. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  470. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  471. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  472. #ifdef CONFIG_DEBUG_FS
  473. .debugfs_init = tilcdc_debugfs_init,
  474. #endif
  475. .fops = &fops,
  476. .name = "tilcdc",
  477. .desc = "TI LCD Controller DRM",
  478. .date = "20121205",
  479. .major = 1,
  480. .minor = 0,
  481. };
  482. /*
  483. * Power management:
  484. */
  485. #ifdef CONFIG_PM_SLEEP
  486. static int tilcdc_pm_suspend(struct device *dev)
  487. {
  488. struct drm_device *ddev = dev_get_drvdata(dev);
  489. struct tilcdc_drm_private *priv = ddev->dev_private;
  490. priv->saved_state = drm_atomic_helper_suspend(ddev);
  491. /* Select sleep pin state */
  492. pinctrl_pm_select_sleep_state(dev);
  493. return 0;
  494. }
  495. static int tilcdc_pm_resume(struct device *dev)
  496. {
  497. struct drm_device *ddev = dev_get_drvdata(dev);
  498. struct tilcdc_drm_private *priv = ddev->dev_private;
  499. int ret = 0;
  500. /* Select default pin state */
  501. pinctrl_pm_select_default_state(dev);
  502. if (priv->saved_state)
  503. ret = drm_atomic_helper_resume(ddev, priv->saved_state);
  504. return ret;
  505. }
  506. #endif
  507. static const struct dev_pm_ops tilcdc_pm_ops = {
  508. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  509. };
  510. /*
  511. * Platform driver:
  512. */
  513. static int tilcdc_bind(struct device *dev)
  514. {
  515. return tilcdc_init(&tilcdc_driver, dev);
  516. }
  517. static void tilcdc_unbind(struct device *dev)
  518. {
  519. struct drm_device *ddev = dev_get_drvdata(dev);
  520. /* Check if a subcomponent has already triggered the unloading. */
  521. if (!ddev->dev_private)
  522. return;
  523. tilcdc_fini(dev_get_drvdata(dev));
  524. }
  525. static const struct component_master_ops tilcdc_comp_ops = {
  526. .bind = tilcdc_bind,
  527. .unbind = tilcdc_unbind,
  528. };
  529. static int tilcdc_pdev_probe(struct platform_device *pdev)
  530. {
  531. struct component_match *match = NULL;
  532. int ret;
  533. /* bail out early if no DT data: */
  534. if (!pdev->dev.of_node) {
  535. dev_err(&pdev->dev, "device-tree data is missing\n");
  536. return -ENXIO;
  537. }
  538. ret = tilcdc_get_external_components(&pdev->dev, &match);
  539. if (ret < 0)
  540. return ret;
  541. else if (ret == 0)
  542. return tilcdc_init(&tilcdc_driver, &pdev->dev);
  543. else
  544. return component_master_add_with_match(&pdev->dev,
  545. &tilcdc_comp_ops,
  546. match);
  547. }
  548. static int tilcdc_pdev_remove(struct platform_device *pdev)
  549. {
  550. int ret;
  551. ret = tilcdc_get_external_components(&pdev->dev, NULL);
  552. if (ret < 0)
  553. return ret;
  554. else if (ret == 0)
  555. tilcdc_fini(platform_get_drvdata(pdev));
  556. else
  557. component_master_del(&pdev->dev, &tilcdc_comp_ops);
  558. return 0;
  559. }
  560. static struct of_device_id tilcdc_of_match[] = {
  561. { .compatible = "ti,am33xx-tilcdc", },
  562. { .compatible = "ti,da850-tilcdc", },
  563. { },
  564. };
  565. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  566. static struct platform_driver tilcdc_platform_driver = {
  567. .probe = tilcdc_pdev_probe,
  568. .remove = tilcdc_pdev_remove,
  569. .driver = {
  570. .name = "tilcdc",
  571. .pm = &tilcdc_pm_ops,
  572. .of_match_table = tilcdc_of_match,
  573. },
  574. };
  575. static int __init tilcdc_drm_init(void)
  576. {
  577. DBG("init");
  578. tilcdc_tfp410_init();
  579. tilcdc_panel_init();
  580. return platform_driver_register(&tilcdc_platform_driver);
  581. }
  582. static void __exit tilcdc_drm_fini(void)
  583. {
  584. DBG("fini");
  585. platform_driver_unregister(&tilcdc_platform_driver);
  586. tilcdc_panel_fini();
  587. tilcdc_tfp410_fini();
  588. }
  589. module_init(tilcdc_drm_init);
  590. module_exit(tilcdc_drm_fini);
  591. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  592. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  593. MODULE_LICENSE("GPL");