amdgpu_sched.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. *
  23. */
  24. #include <linux/kthread.h>
  25. #include <linux/wait.h>
  26. #include <linux/sched.h>
  27. #include <drm/drmP.h>
  28. #include "amdgpu.h"
  29. static int amdgpu_sched_prepare_job(struct amd_gpu_scheduler *sched,
  30. struct amd_sched_entity *entity,
  31. struct amd_sched_job *job)
  32. {
  33. int r = 0;
  34. struct amdgpu_cs_parser *sched_job;
  35. if (!job || !job->data) {
  36. DRM_ERROR("job is null\n");
  37. return -EINVAL;
  38. }
  39. sched_job = (struct amdgpu_cs_parser *)job->data;
  40. if (sched_job->prepare_job) {
  41. r = sched_job->prepare_job(sched_job);
  42. if (r) {
  43. DRM_ERROR("Prepare job error\n");
  44. schedule_work(&sched_job->job_work);
  45. }
  46. }
  47. return r;
  48. }
  49. static struct fence *amdgpu_sched_run_job(struct amd_gpu_scheduler *sched,
  50. struct amd_sched_entity *entity,
  51. struct amd_sched_job *job)
  52. {
  53. int r = 0;
  54. struct amdgpu_cs_parser *sched_job;
  55. struct amdgpu_fence *fence;
  56. if (!job || !job->data) {
  57. DRM_ERROR("job is null\n");
  58. return NULL;
  59. }
  60. sched_job = (struct amdgpu_cs_parser *)job->data;
  61. mutex_lock(&sched_job->job_lock);
  62. r = amdgpu_ib_schedule(sched_job->adev,
  63. sched_job->num_ibs,
  64. sched_job->ibs,
  65. sched_job->filp);
  66. if (r)
  67. goto err;
  68. fence = amdgpu_fence_ref(sched_job->ibs[sched_job->num_ibs - 1].fence);
  69. if (sched_job->run_job) {
  70. r = sched_job->run_job(sched_job);
  71. if (r)
  72. goto err;
  73. }
  74. amd_sched_emit(entity, sched_job->ibs[sched_job->num_ibs - 1].sequence);
  75. mutex_unlock(&sched_job->job_lock);
  76. return &fence->base;
  77. err:
  78. DRM_ERROR("Run job error\n");
  79. mutex_unlock(&sched_job->job_lock);
  80. schedule_work(&sched_job->job_work);
  81. return NULL;
  82. }
  83. static void amdgpu_sched_process_job(struct amd_gpu_scheduler *sched,
  84. struct amd_sched_job *job)
  85. {
  86. struct amdgpu_cs_parser *sched_job;
  87. if (!job || !job->data) {
  88. DRM_ERROR("job is null\n");
  89. return;
  90. }
  91. sched_job = (struct amdgpu_cs_parser *)job->data;
  92. schedule_work(&sched_job->job_work);
  93. }
  94. struct amd_sched_backend_ops amdgpu_sched_ops = {
  95. .prepare_job = amdgpu_sched_prepare_job,
  96. .run_job = amdgpu_sched_run_job,
  97. .process_job = amdgpu_sched_process_job
  98. };
  99. int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
  100. struct amdgpu_ring *ring,
  101. struct amdgpu_ib *ibs,
  102. unsigned num_ibs,
  103. int (*free_job)(struct amdgpu_cs_parser *),
  104. void *owner,
  105. struct fence **f)
  106. {
  107. int r = 0;
  108. if (amdgpu_enable_scheduler) {
  109. uint64_t v_seq;
  110. struct amdgpu_cs_parser *sched_job =
  111. amdgpu_cs_parser_create(adev, owner, &adev->kernel_ctx,
  112. ibs, 1);
  113. if(!sched_job) {
  114. return -ENOMEM;
  115. }
  116. sched_job->free_job = free_job;
  117. v_seq = atomic64_inc_return(&adev->kernel_ctx.rings[ring->idx].entity.last_queued_v_seq);
  118. ibs[num_ibs - 1].sequence = v_seq;
  119. amd_sched_push_job(ring->scheduler,
  120. &adev->kernel_ctx.rings[ring->idx].entity,
  121. sched_job);
  122. r = amd_sched_wait_emit(
  123. &adev->kernel_ctx.rings[ring->idx].entity,
  124. v_seq,
  125. false,
  126. -1);
  127. if (r)
  128. WARN(true, "emit timeout\n");
  129. } else
  130. r = amdgpu_ib_schedule(adev, 1, ibs, owner);
  131. if (r)
  132. return r;
  133. *f = &ibs[num_ibs - 1].fence->base;
  134. return 0;
  135. }