nvme.h 8.3 KB

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  1. /*
  2. * Copyright (c) 2011-2014, Intel Corporation.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. */
  13. #ifndef _NVME_H
  14. #define _NVME_H
  15. #include <linux/nvme.h>
  16. #include <linux/pci.h>
  17. #include <linux/kref.h>
  18. #include <linux/blk-mq.h>
  19. enum {
  20. /*
  21. * Driver internal status code for commands that were cancelled due
  22. * to timeouts or controller shutdown. The value is negative so
  23. * that it a) doesn't overlap with the unsigned hardware error codes,
  24. * and b) can easily be tested for.
  25. */
  26. NVME_SC_CANCELLED = -EINTR,
  27. };
  28. extern unsigned char nvme_io_timeout;
  29. #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
  30. extern unsigned char admin_timeout;
  31. #define ADMIN_TIMEOUT (admin_timeout * HZ)
  32. extern unsigned char shutdown_timeout;
  33. #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
  34. enum {
  35. NVME_NS_LBA = 0,
  36. NVME_NS_LIGHTNVM = 1,
  37. };
  38. /*
  39. * List of workarounds for devices that required behavior not specified in
  40. * the standard.
  41. */
  42. enum nvme_quirks {
  43. /*
  44. * Prefers I/O aligned to a stripe size specified in a vendor
  45. * specific Identify field.
  46. */
  47. NVME_QUIRK_STRIPE_SIZE = (1 << 0),
  48. /*
  49. * The controller doesn't handle Identify value others than 0 or 1
  50. * correctly.
  51. */
  52. NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
  53. /*
  54. * The controller deterministically returns O's on reads to discarded
  55. * logical blocks.
  56. */
  57. NVME_QUIRK_DISCARD_ZEROES = (1 << 2),
  58. };
  59. struct nvme_ctrl {
  60. const struct nvme_ctrl_ops *ops;
  61. struct request_queue *admin_q;
  62. struct device *dev;
  63. struct kref kref;
  64. int instance;
  65. struct blk_mq_tag_set *tagset;
  66. struct list_head namespaces;
  67. struct mutex namespaces_mutex;
  68. struct device *device; /* char device */
  69. struct list_head node;
  70. struct ida ns_ida;
  71. char name[12];
  72. char serial[20];
  73. char model[40];
  74. char firmware_rev[8];
  75. int cntlid;
  76. u32 ctrl_config;
  77. u32 page_size;
  78. u32 max_hw_sectors;
  79. u32 stripe_size;
  80. u16 oncs;
  81. u16 vid;
  82. atomic_t abort_limit;
  83. u8 event_limit;
  84. u8 vwc;
  85. u32 vs;
  86. bool subsystem;
  87. unsigned long quirks;
  88. };
  89. /*
  90. * An NVM Express namespace is equivalent to a SCSI LUN
  91. */
  92. struct nvme_ns {
  93. struct list_head list;
  94. struct nvme_ctrl *ctrl;
  95. struct request_queue *queue;
  96. struct gendisk *disk;
  97. struct kref kref;
  98. int instance;
  99. u8 eui[8];
  100. u8 uuid[16];
  101. unsigned ns_id;
  102. int lba_shift;
  103. u16 ms;
  104. bool ext;
  105. u8 pi_type;
  106. int type;
  107. unsigned long flags;
  108. #define NVME_NS_REMOVING 0
  109. #define NVME_NS_DEAD 1
  110. u64 mode_select_num_blocks;
  111. u32 mode_select_block_len;
  112. };
  113. struct nvme_ctrl_ops {
  114. struct module *module;
  115. int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
  116. int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
  117. int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
  118. bool (*io_incapable)(struct nvme_ctrl *ctrl);
  119. int (*reset_ctrl)(struct nvme_ctrl *ctrl);
  120. void (*free_ctrl)(struct nvme_ctrl *ctrl);
  121. };
  122. static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
  123. {
  124. u32 val = 0;
  125. if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
  126. return false;
  127. return val & NVME_CSTS_RDY;
  128. }
  129. static inline bool nvme_io_incapable(struct nvme_ctrl *ctrl)
  130. {
  131. u32 val = 0;
  132. if (ctrl->ops->io_incapable(ctrl))
  133. return true;
  134. if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
  135. return true;
  136. return val & NVME_CSTS_CFS;
  137. }
  138. static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
  139. {
  140. if (!ctrl->subsystem)
  141. return -ENOTTY;
  142. return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
  143. }
  144. static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
  145. {
  146. return (sector >> (ns->lba_shift - 9));
  147. }
  148. static inline void nvme_setup_flush(struct nvme_ns *ns,
  149. struct nvme_command *cmnd)
  150. {
  151. memset(cmnd, 0, sizeof(*cmnd));
  152. cmnd->common.opcode = nvme_cmd_flush;
  153. cmnd->common.nsid = cpu_to_le32(ns->ns_id);
  154. }
  155. static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
  156. struct nvme_command *cmnd)
  157. {
  158. u16 control = 0;
  159. u32 dsmgmt = 0;
  160. if (req->cmd_flags & REQ_FUA)
  161. control |= NVME_RW_FUA;
  162. if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
  163. control |= NVME_RW_LR;
  164. if (req->cmd_flags & REQ_RAHEAD)
  165. dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
  166. memset(cmnd, 0, sizeof(*cmnd));
  167. cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
  168. cmnd->rw.command_id = req->tag;
  169. cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
  170. cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
  171. cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
  172. if (ns->ms) {
  173. switch (ns->pi_type) {
  174. case NVME_NS_DPS_PI_TYPE3:
  175. control |= NVME_RW_PRINFO_PRCHK_GUARD;
  176. break;
  177. case NVME_NS_DPS_PI_TYPE1:
  178. case NVME_NS_DPS_PI_TYPE2:
  179. control |= NVME_RW_PRINFO_PRCHK_GUARD |
  180. NVME_RW_PRINFO_PRCHK_REF;
  181. cmnd->rw.reftag = cpu_to_le32(
  182. nvme_block_nr(ns, blk_rq_pos(req)));
  183. break;
  184. }
  185. if (!blk_integrity_rq(req))
  186. control |= NVME_RW_PRINFO_PRACT;
  187. }
  188. cmnd->rw.control = cpu_to_le16(control);
  189. cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
  190. }
  191. static inline int nvme_error_status(u16 status)
  192. {
  193. switch (status & 0x7ff) {
  194. case NVME_SC_SUCCESS:
  195. return 0;
  196. case NVME_SC_CAP_EXCEEDED:
  197. return -ENOSPC;
  198. default:
  199. return -EIO;
  200. }
  201. }
  202. static inline bool nvme_req_needs_retry(struct request *req, u16 status)
  203. {
  204. return !(status & NVME_SC_DNR || blk_noretry_request(req)) &&
  205. (jiffies - req->start_time) < req->timeout;
  206. }
  207. int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
  208. int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
  209. int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
  210. int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
  211. const struct nvme_ctrl_ops *ops, unsigned long quirks);
  212. void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
  213. void nvme_put_ctrl(struct nvme_ctrl *ctrl);
  214. int nvme_init_identify(struct nvme_ctrl *ctrl);
  215. void nvme_scan_namespaces(struct nvme_ctrl *ctrl);
  216. void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
  217. void nvme_stop_queues(struct nvme_ctrl *ctrl);
  218. void nvme_start_queues(struct nvme_ctrl *ctrl);
  219. void nvme_kill_queues(struct nvme_ctrl *ctrl);
  220. struct request *nvme_alloc_request(struct request_queue *q,
  221. struct nvme_command *cmd, unsigned int flags);
  222. void nvme_requeue_req(struct request *req);
  223. int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  224. void *buf, unsigned bufflen);
  225. int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  226. struct nvme_completion *cqe, void *buffer, unsigned bufflen,
  227. unsigned timeout);
  228. int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
  229. void __user *ubuffer, unsigned bufflen, u32 *result,
  230. unsigned timeout);
  231. int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
  232. void __user *ubuffer, unsigned bufflen,
  233. void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
  234. u32 *result, unsigned timeout);
  235. int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
  236. int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
  237. struct nvme_id_ns **id);
  238. int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
  239. int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
  240. dma_addr_t dma_addr, u32 *result);
  241. int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
  242. dma_addr_t dma_addr, u32 *result);
  243. int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
  244. struct sg_io_hdr;
  245. int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
  246. int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
  247. int nvme_sg_get_version_num(int __user *ip);
  248. #ifdef CONFIG_NVM
  249. int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
  250. int nvme_nvm_register(struct request_queue *q, char *disk_name);
  251. void nvme_nvm_unregister(struct request_queue *q, char *disk_name);
  252. #else
  253. static inline int nvme_nvm_register(struct request_queue *q, char *disk_name)
  254. {
  255. return 0;
  256. }
  257. static inline void nvme_nvm_unregister(struct request_queue *q, char *disk_name) {};
  258. static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
  259. {
  260. return 0;
  261. }
  262. #endif /* CONFIG_NVM */
  263. int __init nvme_core_init(void);
  264. void nvme_core_exit(void);
  265. #endif /* _NVME_H */