nvm.c 25 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * Copyright(c) 2016 Intel Deutschland GmbH
  38. * All rights reserved.
  39. *
  40. * Redistribution and use in source and binary forms, with or without
  41. * modification, are permitted provided that the following conditions
  42. * are met:
  43. *
  44. * * Redistributions of source code must retain the above copyright
  45. * notice, this list of conditions and the following disclaimer.
  46. * * Redistributions in binary form must reproduce the above copyright
  47. * notice, this list of conditions and the following disclaimer in
  48. * the documentation and/or other materials provided with the
  49. * distribution.
  50. * * Neither the name Intel Corporation nor the names of its
  51. * contributors may be used to endorse or promote products derived
  52. * from this software without specific prior written permission.
  53. *
  54. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65. *
  66. *****************************************************************************/
  67. #include <linux/firmware.h>
  68. #include <linux/rtnetlink.h>
  69. #include <linux/pci.h>
  70. #include <linux/acpi.h>
  71. #include "iwl-trans.h"
  72. #include "iwl-csr.h"
  73. #include "mvm.h"
  74. #include "iwl-eeprom-parse.h"
  75. #include "iwl-eeprom-read.h"
  76. #include "iwl-nvm-parse.h"
  77. #include "iwl-prph.h"
  78. /* Default NVM size to read */
  79. #define IWL_NVM_DEFAULT_CHUNK_SIZE (2*1024)
  80. #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
  81. #define IWL_MAX_NVM_8000_SECTION_SIZE 0x1ffc
  82. #define NVM_WRITE_OPCODE 1
  83. #define NVM_READ_OPCODE 0
  84. /* load nvm chunk response */
  85. enum {
  86. READ_NVM_CHUNK_SUCCEED = 0,
  87. READ_NVM_CHUNK_NOT_VALID_ADDRESS = 1
  88. };
  89. /*
  90. * prepare the NVM host command w/ the pointers to the nvm buffer
  91. * and send it to fw
  92. */
  93. static int iwl_nvm_write_chunk(struct iwl_mvm *mvm, u16 section,
  94. u16 offset, u16 length, const u8 *data)
  95. {
  96. struct iwl_nvm_access_cmd nvm_access_cmd = {
  97. .offset = cpu_to_le16(offset),
  98. .length = cpu_to_le16(length),
  99. .type = cpu_to_le16(section),
  100. .op_code = NVM_WRITE_OPCODE,
  101. };
  102. struct iwl_host_cmd cmd = {
  103. .id = NVM_ACCESS_CMD,
  104. .len = { sizeof(struct iwl_nvm_access_cmd), length },
  105. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  106. .data = { &nvm_access_cmd, data },
  107. /* data may come from vmalloc, so use _DUP */
  108. .dataflags = { 0, IWL_HCMD_DFL_DUP },
  109. };
  110. struct iwl_rx_packet *pkt;
  111. struct iwl_nvm_access_resp *nvm_resp;
  112. int ret;
  113. ret = iwl_mvm_send_cmd(mvm, &cmd);
  114. if (ret)
  115. return ret;
  116. pkt = cmd.resp_pkt;
  117. if (!pkt) {
  118. IWL_ERR(mvm, "Error in NVM_ACCESS response\n");
  119. return -EINVAL;
  120. }
  121. /* Extract & check NVM write response */
  122. nvm_resp = (void *)pkt->data;
  123. if (le16_to_cpu(nvm_resp->status) != READ_NVM_CHUNK_SUCCEED) {
  124. IWL_ERR(mvm,
  125. "NVM access write command failed for section %u (status = 0x%x)\n",
  126. section, le16_to_cpu(nvm_resp->status));
  127. ret = -EIO;
  128. }
  129. iwl_free_resp(&cmd);
  130. return ret;
  131. }
  132. static int iwl_nvm_read_chunk(struct iwl_mvm *mvm, u16 section,
  133. u16 offset, u16 length, u8 *data)
  134. {
  135. struct iwl_nvm_access_cmd nvm_access_cmd = {
  136. .offset = cpu_to_le16(offset),
  137. .length = cpu_to_le16(length),
  138. .type = cpu_to_le16(section),
  139. .op_code = NVM_READ_OPCODE,
  140. };
  141. struct iwl_nvm_access_resp *nvm_resp;
  142. struct iwl_rx_packet *pkt;
  143. struct iwl_host_cmd cmd = {
  144. .id = NVM_ACCESS_CMD,
  145. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  146. .data = { &nvm_access_cmd, },
  147. };
  148. int ret, bytes_read, offset_read;
  149. u8 *resp_data;
  150. cmd.len[0] = sizeof(struct iwl_nvm_access_cmd);
  151. ret = iwl_mvm_send_cmd(mvm, &cmd);
  152. if (ret)
  153. return ret;
  154. pkt = cmd.resp_pkt;
  155. /* Extract NVM response */
  156. nvm_resp = (void *)pkt->data;
  157. ret = le16_to_cpu(nvm_resp->status);
  158. bytes_read = le16_to_cpu(nvm_resp->length);
  159. offset_read = le16_to_cpu(nvm_resp->offset);
  160. resp_data = nvm_resp->data;
  161. if (ret) {
  162. if ((offset != 0) &&
  163. (ret == READ_NVM_CHUNK_NOT_VALID_ADDRESS)) {
  164. /*
  165. * meaning of NOT_VALID_ADDRESS:
  166. * driver try to read chunk from address that is
  167. * multiple of 2K and got an error since addr is empty.
  168. * meaning of (offset != 0): driver already
  169. * read valid data from another chunk so this case
  170. * is not an error.
  171. */
  172. IWL_DEBUG_EEPROM(mvm->trans->dev,
  173. "NVM access command failed on offset 0x%x since that section size is multiple 2K\n",
  174. offset);
  175. ret = 0;
  176. } else {
  177. IWL_DEBUG_EEPROM(mvm->trans->dev,
  178. "NVM access command failed with status %d (device: %s)\n",
  179. ret, mvm->cfg->name);
  180. ret = -EIO;
  181. }
  182. goto exit;
  183. }
  184. if (offset_read != offset) {
  185. IWL_ERR(mvm, "NVM ACCESS response with invalid offset %d\n",
  186. offset_read);
  187. ret = -EINVAL;
  188. goto exit;
  189. }
  190. /* Write data to NVM */
  191. memcpy(data + offset, resp_data, bytes_read);
  192. ret = bytes_read;
  193. exit:
  194. iwl_free_resp(&cmd);
  195. return ret;
  196. }
  197. static int iwl_nvm_write_section(struct iwl_mvm *mvm, u16 section,
  198. const u8 *data, u16 length)
  199. {
  200. int offset = 0;
  201. /* copy data in chunks of 2k (and remainder if any) */
  202. while (offset < length) {
  203. int chunk_size, ret;
  204. chunk_size = min(IWL_NVM_DEFAULT_CHUNK_SIZE,
  205. length - offset);
  206. ret = iwl_nvm_write_chunk(mvm, section, offset,
  207. chunk_size, data + offset);
  208. if (ret < 0)
  209. return ret;
  210. offset += chunk_size;
  211. }
  212. return 0;
  213. }
  214. static void iwl_mvm_nvm_fixups(struct iwl_mvm *mvm, unsigned int section,
  215. u8 *data, unsigned int len)
  216. {
  217. #define IWL_4165_DEVICE_ID 0x5501
  218. #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
  219. if (section == NVM_SECTION_TYPE_PHY_SKU &&
  220. mvm->trans->hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
  221. (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
  222. /* OTP 0x52 bug work around: it's a 1x1 device */
  223. data[3] = ANT_B | (ANT_B << 4);
  224. }
  225. /*
  226. * Reads an NVM section completely.
  227. * NICs prior to 7000 family doesn't have a real NVM, but just read
  228. * section 0 which is the EEPROM. Because the EEPROM reading is unlimited
  229. * by uCode, we need to manually check in this case that we don't
  230. * overflow and try to read more than the EEPROM size.
  231. * For 7000 family NICs, we supply the maximal size we can read, and
  232. * the uCode fills the response with as much data as we can,
  233. * without overflowing, so no check is needed.
  234. */
  235. static int iwl_nvm_read_section(struct iwl_mvm *mvm, u16 section,
  236. u8 *data, u32 size_read)
  237. {
  238. u16 length, offset = 0;
  239. int ret;
  240. /* Set nvm section read length */
  241. length = IWL_NVM_DEFAULT_CHUNK_SIZE;
  242. ret = length;
  243. /* Read the NVM until exhausted (reading less than requested) */
  244. while (ret == length) {
  245. /* Check no memory assumptions fail and cause an overflow */
  246. if ((size_read + offset + length) >
  247. mvm->cfg->base_params->eeprom_size) {
  248. IWL_ERR(mvm, "EEPROM size is too small for NVM\n");
  249. return -ENOBUFS;
  250. }
  251. ret = iwl_nvm_read_chunk(mvm, section, offset, length, data);
  252. if (ret < 0) {
  253. IWL_DEBUG_EEPROM(mvm->trans->dev,
  254. "Cannot read NVM from section %d offset %d, length %d\n",
  255. section, offset, length);
  256. return ret;
  257. }
  258. offset += ret;
  259. }
  260. iwl_mvm_nvm_fixups(mvm, section, data, offset);
  261. IWL_DEBUG_EEPROM(mvm->trans->dev,
  262. "NVM section %d read completed\n", section);
  263. return offset;
  264. }
  265. static struct iwl_nvm_data *
  266. iwl_parse_nvm_sections(struct iwl_mvm *mvm)
  267. {
  268. struct iwl_nvm_section *sections = mvm->nvm_sections;
  269. const __le16 *hw, *sw, *calib, *regulatory, *mac_override, *phy_sku;
  270. bool lar_enabled;
  271. /* Checking for required sections */
  272. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  273. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  274. !mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data) {
  275. IWL_ERR(mvm, "Can't parse empty OTP/NVM sections\n");
  276. return NULL;
  277. }
  278. } else {
  279. /* SW and REGULATORY sections are mandatory */
  280. if (!mvm->nvm_sections[NVM_SECTION_TYPE_SW].data ||
  281. !mvm->nvm_sections[NVM_SECTION_TYPE_REGULATORY].data) {
  282. IWL_ERR(mvm,
  283. "Can't parse empty family 8000 OTP/NVM sections\n");
  284. return NULL;
  285. }
  286. /* MAC_OVERRIDE or at least HW section must exist */
  287. if (!mvm->nvm_sections[mvm->cfg->nvm_hw_section_num].data &&
  288. !mvm->nvm_sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data) {
  289. IWL_ERR(mvm,
  290. "Can't parse mac_address, empty sections\n");
  291. return NULL;
  292. }
  293. /* PHY_SKU section is mandatory in B0 */
  294. if (!mvm->nvm_sections[NVM_SECTION_TYPE_PHY_SKU].data) {
  295. IWL_ERR(mvm,
  296. "Can't parse phy_sku in B0, empty sections\n");
  297. return NULL;
  298. }
  299. }
  300. if (WARN_ON(!mvm->cfg))
  301. return NULL;
  302. hw = (const __le16 *)sections[mvm->cfg->nvm_hw_section_num].data;
  303. sw = (const __le16 *)sections[NVM_SECTION_TYPE_SW].data;
  304. calib = (const __le16 *)sections[NVM_SECTION_TYPE_CALIBRATION].data;
  305. regulatory = (const __le16 *)sections[NVM_SECTION_TYPE_REGULATORY].data;
  306. mac_override =
  307. (const __le16 *)sections[NVM_SECTION_TYPE_MAC_OVERRIDE].data;
  308. phy_sku = (const __le16 *)sections[NVM_SECTION_TYPE_PHY_SKU].data;
  309. lar_enabled = !iwlwifi_mod_params.lar_disable &&
  310. fw_has_capa(&mvm->fw->ucode_capa,
  311. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  312. return iwl_parse_nvm_data(mvm->trans, mvm->cfg, hw, sw, calib,
  313. regulatory, mac_override, phy_sku,
  314. mvm->fw->valid_tx_ant, mvm->fw->valid_rx_ant,
  315. lar_enabled);
  316. }
  317. #define MAX_NVM_FILE_LEN 16384
  318. /*
  319. * Reads external NVM from a file into mvm->nvm_sections
  320. *
  321. * HOW TO CREATE THE NVM FILE FORMAT:
  322. * ------------------------------
  323. * 1. create hex file, format:
  324. * 3800 -> header
  325. * 0000 -> header
  326. * 5a40 -> data
  327. *
  328. * rev - 6 bit (word1)
  329. * len - 10 bit (word1)
  330. * id - 4 bit (word2)
  331. * rsv - 12 bit (word2)
  332. *
  333. * 2. flip 8bits with 8 bits per line to get the right NVM file format
  334. *
  335. * 3. create binary file from the hex file
  336. *
  337. * 4. save as "iNVM_xxx.bin" under /lib/firmware
  338. */
  339. static int iwl_mvm_read_external_nvm(struct iwl_mvm *mvm)
  340. {
  341. int ret, section_size;
  342. u16 section_id;
  343. const struct firmware *fw_entry;
  344. const struct {
  345. __le16 word1;
  346. __le16 word2;
  347. u8 data[];
  348. } *file_sec;
  349. const u8 *eof;
  350. u8 *temp;
  351. int max_section_size;
  352. const __le32 *dword_buff;
  353. #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
  354. #define NVM_WORD2_ID(x) (x >> 12)
  355. #define NVM_WORD2_LEN_FAMILY_8000(x) (2 * ((x & 0xFF) << 8 | x >> 8))
  356. #define NVM_WORD1_ID_FAMILY_8000(x) (x >> 4)
  357. #define NVM_HEADER_0 (0x2A504C54)
  358. #define NVM_HEADER_1 (0x4E564D2A)
  359. #define NVM_HEADER_SIZE (4 * sizeof(u32))
  360. IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from external NVM\n");
  361. /* Maximal size depends on HW family and step */
  362. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
  363. max_section_size = IWL_MAX_NVM_SECTION_SIZE;
  364. else
  365. max_section_size = IWL_MAX_NVM_8000_SECTION_SIZE;
  366. /*
  367. * Obtain NVM image via request_firmware. Since we already used
  368. * request_firmware_nowait() for the firmware binary load and only
  369. * get here after that we assume the NVM request can be satisfied
  370. * synchronously.
  371. */
  372. ret = request_firmware(&fw_entry, mvm->nvm_file_name,
  373. mvm->trans->dev);
  374. if (ret) {
  375. IWL_ERR(mvm, "ERROR: %s isn't available %d\n",
  376. mvm->nvm_file_name, ret);
  377. return ret;
  378. }
  379. IWL_INFO(mvm, "Loaded NVM file %s (%zu bytes)\n",
  380. mvm->nvm_file_name, fw_entry->size);
  381. if (fw_entry->size > MAX_NVM_FILE_LEN) {
  382. IWL_ERR(mvm, "NVM file too large\n");
  383. ret = -EINVAL;
  384. goto out;
  385. }
  386. eof = fw_entry->data + fw_entry->size;
  387. dword_buff = (__le32 *)fw_entry->data;
  388. /* some NVM file will contain a header.
  389. * The header is identified by 2 dwords header as follow:
  390. * dword[0] = 0x2A504C54
  391. * dword[1] = 0x4E564D2A
  392. *
  393. * This header must be skipped when providing the NVM data to the FW.
  394. */
  395. if (fw_entry->size > NVM_HEADER_SIZE &&
  396. dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
  397. dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
  398. file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
  399. IWL_INFO(mvm, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
  400. IWL_INFO(mvm, "NVM Manufacturing date %08X\n",
  401. le32_to_cpu(dword_buff[3]));
  402. /* nvm file validation, dword_buff[2] holds the file version */
  403. if ((CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_C_STEP &&
  404. le32_to_cpu(dword_buff[2]) < 0xE4A) ||
  405. (CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP &&
  406. le32_to_cpu(dword_buff[2]) >= 0xE4A)) {
  407. ret = -EFAULT;
  408. goto out;
  409. }
  410. } else {
  411. file_sec = (void *)fw_entry->data;
  412. }
  413. while (true) {
  414. if (file_sec->data > eof) {
  415. IWL_ERR(mvm,
  416. "ERROR - NVM file too short for section header\n");
  417. ret = -EINVAL;
  418. break;
  419. }
  420. /* check for EOF marker */
  421. if (!file_sec->word1 && !file_sec->word2) {
  422. ret = 0;
  423. break;
  424. }
  425. if (mvm->trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  426. section_size =
  427. 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
  428. section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
  429. } else {
  430. section_size = 2 * NVM_WORD2_LEN_FAMILY_8000(
  431. le16_to_cpu(file_sec->word2));
  432. section_id = NVM_WORD1_ID_FAMILY_8000(
  433. le16_to_cpu(file_sec->word1));
  434. }
  435. if (section_size > max_section_size) {
  436. IWL_ERR(mvm, "ERROR - section too large (%d)\n",
  437. section_size);
  438. ret = -EINVAL;
  439. break;
  440. }
  441. if (!section_size) {
  442. IWL_ERR(mvm, "ERROR - section empty\n");
  443. ret = -EINVAL;
  444. break;
  445. }
  446. if (file_sec->data + section_size > eof) {
  447. IWL_ERR(mvm,
  448. "ERROR - NVM file too short for section (%d bytes)\n",
  449. section_size);
  450. ret = -EINVAL;
  451. break;
  452. }
  453. if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
  454. "Invalid NVM section ID %d\n", section_id)) {
  455. ret = -EINVAL;
  456. break;
  457. }
  458. temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
  459. if (!temp) {
  460. ret = -ENOMEM;
  461. break;
  462. }
  463. iwl_mvm_nvm_fixups(mvm, section_id, temp, section_size);
  464. kfree(mvm->nvm_sections[section_id].data);
  465. mvm->nvm_sections[section_id].data = temp;
  466. mvm->nvm_sections[section_id].length = section_size;
  467. /* advance to the next section */
  468. file_sec = (void *)(file_sec->data + section_size);
  469. }
  470. out:
  471. release_firmware(fw_entry);
  472. return ret;
  473. }
  474. /* Loads the NVM data stored in mvm->nvm_sections into the NIC */
  475. int iwl_mvm_load_nvm_to_nic(struct iwl_mvm *mvm)
  476. {
  477. int i, ret = 0;
  478. struct iwl_nvm_section *sections = mvm->nvm_sections;
  479. IWL_DEBUG_EEPROM(mvm->trans->dev, "'Write to NVM\n");
  480. for (i = 0; i < ARRAY_SIZE(mvm->nvm_sections); i++) {
  481. if (!mvm->nvm_sections[i].data || !mvm->nvm_sections[i].length)
  482. continue;
  483. ret = iwl_nvm_write_section(mvm, i, sections[i].data,
  484. sections[i].length);
  485. if (ret < 0) {
  486. IWL_ERR(mvm, "iwl_mvm_send_cmd failed: %d\n", ret);
  487. break;
  488. }
  489. }
  490. return ret;
  491. }
  492. int iwl_nvm_init(struct iwl_mvm *mvm, bool read_nvm_from_nic)
  493. {
  494. int ret, section;
  495. u32 size_read = 0;
  496. u8 *nvm_buffer, *temp;
  497. const char *nvm_file_B = mvm->cfg->default_nvm_file_B_step;
  498. const char *nvm_file_C = mvm->cfg->default_nvm_file_C_step;
  499. if (WARN_ON_ONCE(mvm->cfg->nvm_hw_section_num >= NVM_MAX_NUM_SECTIONS))
  500. return -EINVAL;
  501. /* load NVM values from nic */
  502. if (read_nvm_from_nic) {
  503. /* Read From FW NVM */
  504. IWL_DEBUG_EEPROM(mvm->trans->dev, "Read from NVM\n");
  505. nvm_buffer = kmalloc(mvm->cfg->base_params->eeprom_size,
  506. GFP_KERNEL);
  507. if (!nvm_buffer)
  508. return -ENOMEM;
  509. for (section = 0; section < NVM_MAX_NUM_SECTIONS; section++) {
  510. /* we override the constness for initial read */
  511. ret = iwl_nvm_read_section(mvm, section, nvm_buffer,
  512. size_read);
  513. if (ret < 0)
  514. continue;
  515. size_read += ret;
  516. temp = kmemdup(nvm_buffer, ret, GFP_KERNEL);
  517. if (!temp) {
  518. ret = -ENOMEM;
  519. break;
  520. }
  521. iwl_mvm_nvm_fixups(mvm, section, temp, ret);
  522. mvm->nvm_sections[section].data = temp;
  523. mvm->nvm_sections[section].length = ret;
  524. #ifdef CONFIG_IWLWIFI_DEBUGFS
  525. switch (section) {
  526. case NVM_SECTION_TYPE_SW:
  527. mvm->nvm_sw_blob.data = temp;
  528. mvm->nvm_sw_blob.size = ret;
  529. break;
  530. case NVM_SECTION_TYPE_CALIBRATION:
  531. mvm->nvm_calib_blob.data = temp;
  532. mvm->nvm_calib_blob.size = ret;
  533. break;
  534. case NVM_SECTION_TYPE_PRODUCTION:
  535. mvm->nvm_prod_blob.data = temp;
  536. mvm->nvm_prod_blob.size = ret;
  537. break;
  538. case NVM_SECTION_TYPE_PHY_SKU:
  539. mvm->nvm_phy_sku_blob.data = temp;
  540. mvm->nvm_phy_sku_blob.size = ret;
  541. break;
  542. default:
  543. if (section == mvm->cfg->nvm_hw_section_num) {
  544. mvm->nvm_hw_blob.data = temp;
  545. mvm->nvm_hw_blob.size = ret;
  546. break;
  547. }
  548. }
  549. #endif
  550. }
  551. if (!size_read)
  552. IWL_ERR(mvm, "OTP is blank\n");
  553. kfree(nvm_buffer);
  554. }
  555. /* Only if PNVM selected in the mod param - load external NVM */
  556. if (mvm->nvm_file_name) {
  557. /* read External NVM file from the mod param */
  558. ret = iwl_mvm_read_external_nvm(mvm);
  559. if (ret) {
  560. /* choose the nvm_file name according to the
  561. * HW step
  562. */
  563. if (CSR_HW_REV_STEP(mvm->trans->hw_rev) ==
  564. SILICON_B_STEP)
  565. mvm->nvm_file_name = nvm_file_B;
  566. else
  567. mvm->nvm_file_name = nvm_file_C;
  568. if ((ret == -EFAULT || ret == -ENOENT) &&
  569. mvm->nvm_file_name) {
  570. /* in case nvm file was failed try again */
  571. ret = iwl_mvm_read_external_nvm(mvm);
  572. if (ret)
  573. return ret;
  574. } else {
  575. return ret;
  576. }
  577. }
  578. }
  579. /* parse the relevant nvm sections */
  580. mvm->nvm_data = iwl_parse_nvm_sections(mvm);
  581. if (!mvm->nvm_data)
  582. return -ENODATA;
  583. IWL_DEBUG_EEPROM(mvm->trans->dev, "nvm version = %x\n",
  584. mvm->nvm_data->nvm_version);
  585. return 0;
  586. }
  587. struct iwl_mcc_update_resp *
  588. iwl_mvm_update_mcc(struct iwl_mvm *mvm, const char *alpha2,
  589. enum iwl_mcc_source src_id)
  590. {
  591. struct iwl_mcc_update_cmd mcc_update_cmd = {
  592. .mcc = cpu_to_le16(alpha2[0] << 8 | alpha2[1]),
  593. .source_id = (u8)src_id,
  594. };
  595. struct iwl_mcc_update_resp *mcc_resp, *resp_cp = NULL;
  596. struct iwl_mcc_update_resp_v1 *mcc_resp_v1 = NULL;
  597. struct iwl_rx_packet *pkt;
  598. struct iwl_host_cmd cmd = {
  599. .id = MCC_UPDATE_CMD,
  600. .flags = CMD_WANT_SKB,
  601. .data = { &mcc_update_cmd },
  602. };
  603. int ret;
  604. u32 status;
  605. int resp_len, n_channels;
  606. u16 mcc;
  607. bool resp_v2 = fw_has_capa(&mvm->fw->ucode_capa,
  608. IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V2);
  609. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  610. return ERR_PTR(-EOPNOTSUPP);
  611. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd);
  612. if (!resp_v2)
  613. cmd.len[0] = sizeof(struct iwl_mcc_update_cmd_v1);
  614. IWL_DEBUG_LAR(mvm, "send MCC update to FW with '%c%c' src = %d\n",
  615. alpha2[0], alpha2[1], src_id);
  616. ret = iwl_mvm_send_cmd(mvm, &cmd);
  617. if (ret)
  618. return ERR_PTR(ret);
  619. pkt = cmd.resp_pkt;
  620. /* Extract MCC response */
  621. if (resp_v2) {
  622. mcc_resp = (void *)pkt->data;
  623. n_channels = __le32_to_cpu(mcc_resp->n_channels);
  624. } else {
  625. mcc_resp_v1 = (void *)pkt->data;
  626. n_channels = __le32_to_cpu(mcc_resp_v1->n_channels);
  627. }
  628. resp_len = sizeof(struct iwl_mcc_update_resp) + n_channels *
  629. sizeof(__le32);
  630. resp_cp = kzalloc(resp_len, GFP_KERNEL);
  631. if (!resp_cp) {
  632. ret = -ENOMEM;
  633. goto exit;
  634. }
  635. if (resp_v2) {
  636. memcpy(resp_cp, mcc_resp, resp_len);
  637. } else {
  638. resp_cp->status = mcc_resp_v1->status;
  639. resp_cp->mcc = mcc_resp_v1->mcc;
  640. resp_cp->cap = mcc_resp_v1->cap;
  641. resp_cp->source_id = mcc_resp_v1->source_id;
  642. resp_cp->n_channels = mcc_resp_v1->n_channels;
  643. memcpy(resp_cp->channels, mcc_resp_v1->channels,
  644. n_channels * sizeof(__le32));
  645. }
  646. status = le32_to_cpu(resp_cp->status);
  647. mcc = le16_to_cpu(resp_cp->mcc);
  648. /* W/A for a FW/NVM issue - returns 0x00 for the world domain */
  649. if (mcc == 0) {
  650. mcc = 0x3030; /* "00" - world */
  651. resp_cp->mcc = cpu_to_le16(mcc);
  652. }
  653. IWL_DEBUG_LAR(mvm,
  654. "MCC response status: 0x%x. new MCC: 0x%x ('%c%c') change: %d n_chans: %d\n",
  655. status, mcc, mcc >> 8, mcc & 0xff,
  656. !!(status == MCC_RESP_NEW_CHAN_PROFILE), n_channels);
  657. exit:
  658. iwl_free_resp(&cmd);
  659. if (ret)
  660. return ERR_PTR(ret);
  661. return resp_cp;
  662. }
  663. #ifdef CONFIG_ACPI
  664. #define WRD_METHOD "WRDD"
  665. #define WRDD_WIFI (0x07)
  666. #define WRDD_WIGIG (0x10)
  667. static u32 iwl_mvm_wrdd_get_mcc(struct iwl_mvm *mvm, union acpi_object *wrdd)
  668. {
  669. union acpi_object *mcc_pkg, *domain_type, *mcc_value;
  670. u32 i;
  671. if (wrdd->type != ACPI_TYPE_PACKAGE ||
  672. wrdd->package.count < 2 ||
  673. wrdd->package.elements[0].type != ACPI_TYPE_INTEGER ||
  674. wrdd->package.elements[0].integer.value != 0) {
  675. IWL_DEBUG_LAR(mvm, "Unsupported wrdd structure\n");
  676. return 0;
  677. }
  678. for (i = 1 ; i < wrdd->package.count ; ++i) {
  679. mcc_pkg = &wrdd->package.elements[i];
  680. if (mcc_pkg->type != ACPI_TYPE_PACKAGE ||
  681. mcc_pkg->package.count < 2 ||
  682. mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER ||
  683. mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) {
  684. mcc_pkg = NULL;
  685. continue;
  686. }
  687. domain_type = &mcc_pkg->package.elements[0];
  688. if (domain_type->integer.value == WRDD_WIFI)
  689. break;
  690. mcc_pkg = NULL;
  691. }
  692. if (mcc_pkg) {
  693. mcc_value = &mcc_pkg->package.elements[1];
  694. return mcc_value->integer.value;
  695. }
  696. return 0;
  697. }
  698. static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc)
  699. {
  700. acpi_handle root_handle;
  701. acpi_handle handle;
  702. struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL};
  703. acpi_status status;
  704. u32 mcc_val;
  705. struct pci_dev *pdev = to_pci_dev(mvm->dev);
  706. root_handle = ACPI_HANDLE(&pdev->dev);
  707. if (!root_handle) {
  708. IWL_DEBUG_LAR(mvm,
  709. "Could not retrieve root port ACPI handle\n");
  710. return -ENOENT;
  711. }
  712. /* Get the method's handle */
  713. status = acpi_get_handle(root_handle, (acpi_string)WRD_METHOD, &handle);
  714. if (ACPI_FAILURE(status)) {
  715. IWL_DEBUG_LAR(mvm, "WRD method not found\n");
  716. return -ENOENT;
  717. }
  718. /* Call WRDD with no arguments */
  719. status = acpi_evaluate_object(handle, NULL, NULL, &wrdd);
  720. if (ACPI_FAILURE(status)) {
  721. IWL_DEBUG_LAR(mvm, "WRDC invocation failed (0x%x)\n", status);
  722. return -ENOENT;
  723. }
  724. mcc_val = iwl_mvm_wrdd_get_mcc(mvm, wrdd.pointer);
  725. kfree(wrdd.pointer);
  726. if (!mcc_val)
  727. return -ENOENT;
  728. mcc[0] = (mcc_val >> 8) & 0xff;
  729. mcc[1] = mcc_val & 0xff;
  730. mcc[2] = '\0';
  731. return 0;
  732. }
  733. #else /* CONFIG_ACPI */
  734. static int iwl_mvm_get_bios_mcc(struct iwl_mvm *mvm, char *mcc)
  735. {
  736. return -ENOENT;
  737. }
  738. #endif
  739. int iwl_mvm_init_mcc(struct iwl_mvm *mvm)
  740. {
  741. bool tlv_lar;
  742. bool nvm_lar;
  743. int retval;
  744. struct ieee80211_regdomain *regd;
  745. char mcc[3];
  746. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
  747. tlv_lar = fw_has_capa(&mvm->fw->ucode_capa,
  748. IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
  749. nvm_lar = mvm->nvm_data->lar_enabled;
  750. if (tlv_lar != nvm_lar)
  751. IWL_INFO(mvm,
  752. "Conflict between TLV & NVM regarding enabling LAR (TLV = %s NVM =%s)\n",
  753. tlv_lar ? "enabled" : "disabled",
  754. nvm_lar ? "enabled" : "disabled");
  755. }
  756. if (!iwl_mvm_is_lar_supported(mvm))
  757. return 0;
  758. /*
  759. * try to replay the last set MCC to FW. If it doesn't exist,
  760. * queue an update to cfg80211 to retrieve the default alpha2 from FW.
  761. */
  762. retval = iwl_mvm_init_fw_regd(mvm);
  763. if (retval != -ENOENT)
  764. return retval;
  765. /*
  766. * Driver regulatory hint for initial update, this also informs the
  767. * firmware we support wifi location updates.
  768. * Disallow scans that might crash the FW while the LAR regdomain
  769. * is not set.
  770. */
  771. mvm->lar_regdom_set = false;
  772. regd = iwl_mvm_get_current_regdomain(mvm, NULL);
  773. if (IS_ERR_OR_NULL(regd))
  774. return -EIO;
  775. if (iwl_mvm_is_wifi_mcc_supported(mvm) &&
  776. !iwl_mvm_get_bios_mcc(mvm, mcc)) {
  777. kfree(regd);
  778. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc,
  779. MCC_SOURCE_BIOS, NULL);
  780. if (IS_ERR_OR_NULL(regd))
  781. return -EIO;
  782. }
  783. retval = regulatory_set_wiphy_regd_sync_rtnl(mvm->hw->wiphy, regd);
  784. kfree(regd);
  785. return retval;
  786. }
  787. void iwl_mvm_rx_chub_update_mcc(struct iwl_mvm *mvm,
  788. struct iwl_rx_cmd_buffer *rxb)
  789. {
  790. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  791. struct iwl_mcc_chub_notif *notif = (void *)pkt->data;
  792. enum iwl_mcc_source src;
  793. char mcc[3];
  794. struct ieee80211_regdomain *regd;
  795. lockdep_assert_held(&mvm->mutex);
  796. if (WARN_ON_ONCE(!iwl_mvm_is_lar_supported(mvm)))
  797. return;
  798. mcc[0] = notif->mcc >> 8;
  799. mcc[1] = notif->mcc & 0xff;
  800. mcc[2] = '\0';
  801. src = notif->source_id;
  802. IWL_DEBUG_LAR(mvm,
  803. "RX: received chub update mcc cmd (mcc '%s' src %d)\n",
  804. mcc, src);
  805. regd = iwl_mvm_get_regdomain(mvm->hw->wiphy, mcc, src, NULL);
  806. if (IS_ERR_OR_NULL(regd))
  807. return;
  808. regulatory_set_wiphy_regd(mvm->hw->wiphy, regd);
  809. kfree(regd);
  810. }