eeprom.c 16 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
  18. {
  19. REG_WRITE(ah, reg, val);
  20. if (ah->config.analog_shiftreg)
  21. udelay(100);
  22. }
  23. void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
  24. u32 shift, u32 val)
  25. {
  26. REG_RMW(ah, reg, ((val << shift) & mask), mask);
  27. if (ah->config.analog_shiftreg)
  28. udelay(100);
  29. }
  30. int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
  31. int16_t targetLeft, int16_t targetRight)
  32. {
  33. int16_t rv;
  34. if (srcRight == srcLeft) {
  35. rv = targetLeft;
  36. } else {
  37. rv = (int16_t) (((target - srcLeft) * targetRight +
  38. (srcRight - target) * targetLeft) /
  39. (srcRight - srcLeft));
  40. }
  41. return rv;
  42. }
  43. bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
  44. u16 *indexL, u16 *indexR)
  45. {
  46. u16 i;
  47. if (target <= pList[0]) {
  48. *indexL = *indexR = 0;
  49. return true;
  50. }
  51. if (target >= pList[listSize - 1]) {
  52. *indexL = *indexR = (u16) (listSize - 1);
  53. return true;
  54. }
  55. for (i = 0; i < listSize - 1; i++) {
  56. if (pList[i] == target) {
  57. *indexL = *indexR = i;
  58. return true;
  59. }
  60. if (target < pList[i + 1]) {
  61. *indexL = i;
  62. *indexR = (u16) (i + 1);
  63. return false;
  64. }
  65. }
  66. return false;
  67. }
  68. void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
  69. int eep_start_loc, int size)
  70. {
  71. int i = 0, j, addr;
  72. u32 addrdata[8];
  73. u32 data[8];
  74. for (addr = 0; addr < size; addr++) {
  75. addrdata[i] = AR5416_EEPROM_OFFSET +
  76. ((addr + eep_start_loc) << AR5416_EEPROM_S);
  77. i++;
  78. if (i == 8) {
  79. REG_READ_MULTI(ah, addrdata, data, i);
  80. for (j = 0; j < i; j++) {
  81. *eep_data = data[j];
  82. eep_data++;
  83. }
  84. i = 0;
  85. }
  86. }
  87. if (i != 0) {
  88. REG_READ_MULTI(ah, addrdata, data, i);
  89. for (j = 0; j < i; j++) {
  90. *eep_data = data[j];
  91. eep_data++;
  92. }
  93. }
  94. }
  95. static bool ath9k_hw_nvram_read_blob(struct ath_hw *ah, u32 off,
  96. u16 *data)
  97. {
  98. u16 *blob_data;
  99. if (off * sizeof(u16) > ah->eeprom_blob->size)
  100. return false;
  101. blob_data = (u16 *)ah->eeprom_blob->data;
  102. *data = blob_data[off];
  103. return true;
  104. }
  105. bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
  106. {
  107. struct ath_common *common = ath9k_hw_common(ah);
  108. bool ret;
  109. if (ah->eeprom_blob)
  110. ret = ath9k_hw_nvram_read_blob(ah, off, data);
  111. else
  112. ret = common->bus_ops->eeprom_read(common, off, data);
  113. if (!ret)
  114. ath_dbg(common, EEPROM,
  115. "unable to read eeprom region at offset %u\n", off);
  116. return ret;
  117. }
  118. int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size)
  119. {
  120. u16 magic;
  121. u16 *eepdata;
  122. int i;
  123. struct ath_common *common = ath9k_hw_common(ah);
  124. if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
  125. ath_err(common, "Reading Magic # failed\n");
  126. return -EIO;
  127. }
  128. *swap_needed = false;
  129. if (swab16(magic) == AR5416_EEPROM_MAGIC) {
  130. if (ah->ah_flags & AH_NO_EEP_SWAP) {
  131. ath_info(common,
  132. "Ignoring endianness difference in EEPROM magic bytes.\n");
  133. } else {
  134. *swap_needed = true;
  135. }
  136. } else if (magic != AR5416_EEPROM_MAGIC) {
  137. if (ath9k_hw_use_flash(ah))
  138. return 0;
  139. ath_err(common,
  140. "Invalid EEPROM Magic (0x%04x).\n", magic);
  141. return -EINVAL;
  142. }
  143. eepdata = (u16 *)(&ah->eeprom);
  144. if (*swap_needed) {
  145. ath_dbg(common, EEPROM,
  146. "EEPROM Endianness is not native.. Changing.\n");
  147. for (i = 0; i < size; i++)
  148. eepdata[i] = swab16(eepdata[i]);
  149. }
  150. return 0;
  151. }
  152. bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size)
  153. {
  154. u32 i, sum = 0;
  155. u16 *eepdata = (u16 *)(&ah->eeprom);
  156. struct ath_common *common = ath9k_hw_common(ah);
  157. for (i = 0; i < size; i++)
  158. sum ^= eepdata[i];
  159. if (sum != 0xffff) {
  160. ath_err(common, "Bad EEPROM checksum 0x%x\n", sum);
  161. return false;
  162. }
  163. return true;
  164. }
  165. bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev)
  166. {
  167. struct ath_common *common = ath9k_hw_common(ah);
  168. if (ah->eep_ops->get_eeprom_ver(ah) != version ||
  169. ah->eep_ops->get_eeprom_rev(ah) < minrev) {
  170. ath_err(common, "Bad EEPROM VER 0x%04x or REV 0x%04x\n",
  171. ah->eep_ops->get_eeprom_ver(ah),
  172. ah->eep_ops->get_eeprom_rev(ah));
  173. return false;
  174. }
  175. return true;
  176. }
  177. void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  178. u8 *pVpdList, u16 numIntercepts,
  179. u8 *pRetVpdList)
  180. {
  181. u16 i, k;
  182. u8 currPwr = pwrMin;
  183. u16 idxL = 0, idxR = 0;
  184. for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
  185. ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
  186. numIntercepts, &(idxL),
  187. &(idxR));
  188. if (idxR < 1)
  189. idxR = 1;
  190. if (idxL == numIntercepts - 1)
  191. idxL = (u16) (numIntercepts - 2);
  192. if (pPwrList[idxL] == pPwrList[idxR])
  193. k = pVpdList[idxL];
  194. else
  195. k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
  196. (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
  197. (pPwrList[idxR] - pPwrList[idxL]));
  198. pRetVpdList[i] = (u8) k;
  199. currPwr += 2;
  200. }
  201. }
  202. void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
  203. struct ath9k_channel *chan,
  204. struct cal_target_power_leg *powInfo,
  205. u16 numChannels,
  206. struct cal_target_power_leg *pNewPower,
  207. u16 numRates, bool isExtTarget)
  208. {
  209. struct chan_centers centers;
  210. u16 clo, chi;
  211. int i;
  212. int matchIndex = -1, lowIndex = -1;
  213. u16 freq;
  214. ath9k_hw_get_channel_centers(ah, chan, &centers);
  215. freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
  216. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
  217. IS_CHAN_2GHZ(chan))) {
  218. matchIndex = 0;
  219. } else {
  220. for (i = 0; (i < numChannels) &&
  221. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  222. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  223. IS_CHAN_2GHZ(chan))) {
  224. matchIndex = i;
  225. break;
  226. } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  227. IS_CHAN_2GHZ(chan)) && i > 0 &&
  228. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  229. IS_CHAN_2GHZ(chan))) {
  230. lowIndex = i - 1;
  231. break;
  232. }
  233. }
  234. if ((matchIndex == -1) && (lowIndex == -1))
  235. matchIndex = i - 1;
  236. }
  237. if (matchIndex != -1) {
  238. *pNewPower = powInfo[matchIndex];
  239. } else {
  240. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  241. IS_CHAN_2GHZ(chan));
  242. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  243. IS_CHAN_2GHZ(chan));
  244. for (i = 0; i < numRates; i++) {
  245. pNewPower->tPow2x[i] =
  246. (u8)ath9k_hw_interpolate(freq, clo, chi,
  247. powInfo[lowIndex].tPow2x[i],
  248. powInfo[lowIndex + 1].tPow2x[i]);
  249. }
  250. }
  251. }
  252. void ath9k_hw_get_target_powers(struct ath_hw *ah,
  253. struct ath9k_channel *chan,
  254. struct cal_target_power_ht *powInfo,
  255. u16 numChannels,
  256. struct cal_target_power_ht *pNewPower,
  257. u16 numRates, bool isHt40Target)
  258. {
  259. struct chan_centers centers;
  260. u16 clo, chi;
  261. int i;
  262. int matchIndex = -1, lowIndex = -1;
  263. u16 freq;
  264. ath9k_hw_get_channel_centers(ah, chan, &centers);
  265. freq = isHt40Target ? centers.synth_center : centers.ctl_center;
  266. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
  267. matchIndex = 0;
  268. } else {
  269. for (i = 0; (i < numChannels) &&
  270. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  271. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  272. IS_CHAN_2GHZ(chan))) {
  273. matchIndex = i;
  274. break;
  275. } else
  276. if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  277. IS_CHAN_2GHZ(chan)) && i > 0 &&
  278. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  279. IS_CHAN_2GHZ(chan))) {
  280. lowIndex = i - 1;
  281. break;
  282. }
  283. }
  284. if ((matchIndex == -1) && (lowIndex == -1))
  285. matchIndex = i - 1;
  286. }
  287. if (matchIndex != -1) {
  288. *pNewPower = powInfo[matchIndex];
  289. } else {
  290. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  291. IS_CHAN_2GHZ(chan));
  292. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  293. IS_CHAN_2GHZ(chan));
  294. for (i = 0; i < numRates; i++) {
  295. pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
  296. clo, chi,
  297. powInfo[lowIndex].tPow2x[i],
  298. powInfo[lowIndex + 1].tPow2x[i]);
  299. }
  300. }
  301. }
  302. u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
  303. bool is2GHz, int num_band_edges)
  304. {
  305. u16 twiceMaxEdgePower = MAX_RATE_POWER;
  306. int i;
  307. for (i = 0; (i < num_band_edges) &&
  308. (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  309. if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
  310. twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
  311. break;
  312. } else if ((i > 0) &&
  313. (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
  314. is2GHz))) {
  315. if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
  316. is2GHz) < freq &&
  317. CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
  318. twiceMaxEdgePower =
  319. CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
  320. }
  321. break;
  322. }
  323. }
  324. return twiceMaxEdgePower;
  325. }
  326. u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
  327. u8 antenna_reduction)
  328. {
  329. u16 reduction = antenna_reduction;
  330. /*
  331. * Reduce scaled Power by number of chains active
  332. * to get the per chain tx power level.
  333. */
  334. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  335. case 1:
  336. break;
  337. case 2:
  338. reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
  339. break;
  340. case 3:
  341. reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
  342. break;
  343. }
  344. if (power_limit > reduction)
  345. power_limit -= reduction;
  346. else
  347. power_limit = 0;
  348. return power_limit;
  349. }
  350. void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
  351. {
  352. struct ath_common *common = ath9k_hw_common(ah);
  353. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  354. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  355. case 1:
  356. break;
  357. case 2:
  358. regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
  359. break;
  360. case 3:
  361. regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
  362. break;
  363. default:
  364. ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
  365. break;
  366. }
  367. }
  368. void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
  369. struct ath9k_channel *chan,
  370. void *pRawDataSet,
  371. u8 *bChans, u16 availPiers,
  372. u16 tPdGainOverlap,
  373. u16 *pPdGainBoundaries, u8 *pPDADCValues,
  374. u16 numXpdGains)
  375. {
  376. int i, j, k;
  377. int16_t ss;
  378. u16 idxL = 0, idxR = 0, numPiers;
  379. static u8 vpdTableL[AR5416_NUM_PD_GAINS]
  380. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  381. static u8 vpdTableR[AR5416_NUM_PD_GAINS]
  382. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  383. static u8 vpdTableI[AR5416_NUM_PD_GAINS]
  384. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  385. u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
  386. u8 minPwrT4[AR5416_NUM_PD_GAINS];
  387. u8 maxPwrT4[AR5416_NUM_PD_GAINS];
  388. int16_t vpdStep;
  389. int16_t tmpVal;
  390. u16 sizeCurrVpdTable, maxIndex, tgtIndex;
  391. bool match;
  392. int16_t minDelta = 0;
  393. struct chan_centers centers;
  394. int pdgain_boundary_default;
  395. struct cal_data_per_freq *data_def = pRawDataSet;
  396. struct cal_data_per_freq_4k *data_4k = pRawDataSet;
  397. struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
  398. bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
  399. int intercepts;
  400. if (AR_SREV_9287(ah))
  401. intercepts = AR9287_PD_GAIN_ICEPTS;
  402. else
  403. intercepts = AR5416_PD_GAIN_ICEPTS;
  404. memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
  405. ath9k_hw_get_channel_centers(ah, chan, &centers);
  406. for (numPiers = 0; numPiers < availPiers; numPiers++) {
  407. if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
  408. break;
  409. }
  410. match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
  411. IS_CHAN_2GHZ(chan)),
  412. bChans, numPiers, &idxL, &idxR);
  413. if (match) {
  414. if (AR_SREV_9287(ah)) {
  415. for (i = 0; i < numXpdGains; i++) {
  416. minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
  417. maxPwrT4[i] = data_9287[idxL].pwrPdg[i][intercepts - 1];
  418. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  419. data_9287[idxL].pwrPdg[i],
  420. data_9287[idxL].vpdPdg[i],
  421. intercepts,
  422. vpdTableI[i]);
  423. }
  424. } else if (eeprom_4k) {
  425. for (i = 0; i < numXpdGains; i++) {
  426. minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
  427. maxPwrT4[i] = data_4k[idxL].pwrPdg[i][intercepts - 1];
  428. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  429. data_4k[idxL].pwrPdg[i],
  430. data_4k[idxL].vpdPdg[i],
  431. intercepts,
  432. vpdTableI[i]);
  433. }
  434. } else {
  435. for (i = 0; i < numXpdGains; i++) {
  436. minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
  437. maxPwrT4[i] = data_def[idxL].pwrPdg[i][intercepts - 1];
  438. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  439. data_def[idxL].pwrPdg[i],
  440. data_def[idxL].vpdPdg[i],
  441. intercepts,
  442. vpdTableI[i]);
  443. }
  444. }
  445. } else {
  446. for (i = 0; i < numXpdGains; i++) {
  447. if (AR_SREV_9287(ah)) {
  448. pVpdL = data_9287[idxL].vpdPdg[i];
  449. pPwrL = data_9287[idxL].pwrPdg[i];
  450. pVpdR = data_9287[idxR].vpdPdg[i];
  451. pPwrR = data_9287[idxR].pwrPdg[i];
  452. } else if (eeprom_4k) {
  453. pVpdL = data_4k[idxL].vpdPdg[i];
  454. pPwrL = data_4k[idxL].pwrPdg[i];
  455. pVpdR = data_4k[idxR].vpdPdg[i];
  456. pPwrR = data_4k[idxR].pwrPdg[i];
  457. } else {
  458. pVpdL = data_def[idxL].vpdPdg[i];
  459. pPwrL = data_def[idxL].pwrPdg[i];
  460. pVpdR = data_def[idxR].vpdPdg[i];
  461. pPwrR = data_def[idxR].pwrPdg[i];
  462. }
  463. minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
  464. maxPwrT4[i] =
  465. min(pPwrL[intercepts - 1],
  466. pPwrR[intercepts - 1]);
  467. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  468. pPwrL, pVpdL,
  469. intercepts,
  470. vpdTableL[i]);
  471. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  472. pPwrR, pVpdR,
  473. intercepts,
  474. vpdTableR[i]);
  475. for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
  476. vpdTableI[i][j] =
  477. (u8)(ath9k_hw_interpolate((u16)
  478. FREQ2FBIN(centers.
  479. synth_center,
  480. IS_CHAN_2GHZ
  481. (chan)),
  482. bChans[idxL], bChans[idxR],
  483. vpdTableL[i][j], vpdTableR[i][j]));
  484. }
  485. }
  486. }
  487. k = 0;
  488. for (i = 0; i < numXpdGains; i++) {
  489. if (i == (numXpdGains - 1))
  490. pPdGainBoundaries[i] =
  491. (u16)(maxPwrT4[i] / 2);
  492. else
  493. pPdGainBoundaries[i] =
  494. (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
  495. pPdGainBoundaries[i] =
  496. min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
  497. minDelta = 0;
  498. if (i == 0) {
  499. if (AR_SREV_9280_20_OR_LATER(ah))
  500. ss = (int16_t)(0 - (minPwrT4[i] / 2));
  501. else
  502. ss = 0;
  503. } else {
  504. ss = (int16_t)((pPdGainBoundaries[i - 1] -
  505. (minPwrT4[i] / 2)) -
  506. tPdGainOverlap + 1 + minDelta);
  507. }
  508. vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
  509. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  510. while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  511. tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
  512. pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
  513. ss++;
  514. }
  515. sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
  516. tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
  517. (minPwrT4[i] / 2));
  518. maxIndex = (tgtIndex < sizeCurrVpdTable) ?
  519. tgtIndex : sizeCurrVpdTable;
  520. while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  521. pPDADCValues[k++] = vpdTableI[i][ss++];
  522. }
  523. vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
  524. vpdTableI[i][sizeCurrVpdTable - 2]);
  525. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  526. if (tgtIndex >= maxIndex) {
  527. while ((ss <= tgtIndex) &&
  528. (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  529. tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
  530. (ss - maxIndex + 1) * vpdStep));
  531. pPDADCValues[k++] = (u8)((tmpVal > 255) ?
  532. 255 : tmpVal);
  533. ss++;
  534. }
  535. }
  536. }
  537. if (eeprom_4k)
  538. pdgain_boundary_default = 58;
  539. else
  540. pdgain_boundary_default = pPdGainBoundaries[i - 1];
  541. while (i < AR5416_PD_GAINS_IN_MASK) {
  542. pPdGainBoundaries[i] = pdgain_boundary_default;
  543. i++;
  544. }
  545. while (k < AR5416_NUM_PDADC_VALUES) {
  546. pPDADCValues[k] = pPDADCValues[k - 1];
  547. k++;
  548. }
  549. }
  550. int ath9k_hw_eeprom_init(struct ath_hw *ah)
  551. {
  552. int status;
  553. if (AR_SREV_9300_20_OR_LATER(ah))
  554. ah->eep_ops = &eep_ar9300_ops;
  555. else if (AR_SREV_9287(ah)) {
  556. ah->eep_ops = &eep_ar9287_ops;
  557. } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
  558. ah->eep_ops = &eep_4k_ops;
  559. } else {
  560. ah->eep_ops = &eep_def_ops;
  561. }
  562. if (!ah->eep_ops->fill_eeprom(ah))
  563. return -EIO;
  564. status = ah->eep_ops->check_eeprom(ah);
  565. return status;
  566. }