core.c 52 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include "core.h"
  21. #include "mac.h"
  22. #include "htc.h"
  23. #include "hif.h"
  24. #include "wmi.h"
  25. #include "bmi.h"
  26. #include "debug.h"
  27. #include "htt.h"
  28. #include "testmode.h"
  29. #include "wmi-ops.h"
  30. unsigned int ath10k_debug_mask;
  31. static unsigned int ath10k_cryptmode_param;
  32. static bool uart_print;
  33. static bool skip_otp;
  34. static bool rawmode;
  35. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  36. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  37. module_param(uart_print, bool, 0644);
  38. module_param(skip_otp, bool, 0644);
  39. module_param(rawmode, bool, 0644);
  40. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  41. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  42. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  43. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  44. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  45. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  46. {
  47. .id = QCA988X_HW_2_0_VERSION,
  48. .dev_id = QCA988X_2_0_DEVICE_ID,
  49. .name = "qca988x hw2.0",
  50. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  51. .uart_pin = 7,
  52. .has_shifted_cc_wraparound = true,
  53. .otp_exe_param = 0,
  54. .channel_counters_freq_hz = 88000,
  55. .max_probe_resp_desc_thres = 0,
  56. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  57. .fw = {
  58. .dir = QCA988X_HW_2_0_FW_DIR,
  59. .fw = QCA988X_HW_2_0_FW_FILE,
  60. .otp = QCA988X_HW_2_0_OTP_FILE,
  61. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  62. .board_size = QCA988X_BOARD_DATA_SZ,
  63. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  64. },
  65. },
  66. {
  67. .id = QCA6174_HW_2_1_VERSION,
  68. .dev_id = QCA6164_2_1_DEVICE_ID,
  69. .name = "qca6164 hw2.1",
  70. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  71. .uart_pin = 6,
  72. .otp_exe_param = 0,
  73. .channel_counters_freq_hz = 88000,
  74. .max_probe_resp_desc_thres = 0,
  75. .fw = {
  76. .dir = QCA6174_HW_2_1_FW_DIR,
  77. .fw = QCA6174_HW_2_1_FW_FILE,
  78. .otp = QCA6174_HW_2_1_OTP_FILE,
  79. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  80. .board_size = QCA6174_BOARD_DATA_SZ,
  81. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  82. },
  83. },
  84. {
  85. .id = QCA6174_HW_2_1_VERSION,
  86. .dev_id = QCA6174_2_1_DEVICE_ID,
  87. .name = "qca6174 hw2.1",
  88. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  89. .uart_pin = 6,
  90. .otp_exe_param = 0,
  91. .channel_counters_freq_hz = 88000,
  92. .max_probe_resp_desc_thres = 0,
  93. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  94. .fw = {
  95. .dir = QCA6174_HW_2_1_FW_DIR,
  96. .fw = QCA6174_HW_2_1_FW_FILE,
  97. .otp = QCA6174_HW_2_1_OTP_FILE,
  98. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  99. .board_size = QCA6174_BOARD_DATA_SZ,
  100. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  101. },
  102. },
  103. {
  104. .id = QCA6174_HW_3_0_VERSION,
  105. .dev_id = QCA6174_2_1_DEVICE_ID,
  106. .name = "qca6174 hw3.0",
  107. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  108. .uart_pin = 6,
  109. .otp_exe_param = 0,
  110. .channel_counters_freq_hz = 88000,
  111. .max_probe_resp_desc_thres = 0,
  112. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  113. .fw = {
  114. .dir = QCA6174_HW_3_0_FW_DIR,
  115. .fw = QCA6174_HW_3_0_FW_FILE,
  116. .otp = QCA6174_HW_3_0_OTP_FILE,
  117. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  118. .board_size = QCA6174_BOARD_DATA_SZ,
  119. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  120. },
  121. },
  122. {
  123. .id = QCA6174_HW_3_2_VERSION,
  124. .dev_id = QCA6174_2_1_DEVICE_ID,
  125. .name = "qca6174 hw3.2",
  126. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  127. .uart_pin = 6,
  128. .otp_exe_param = 0,
  129. .channel_counters_freq_hz = 88000,
  130. .max_probe_resp_desc_thres = 0,
  131. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  132. .fw = {
  133. /* uses same binaries as hw3.0 */
  134. .dir = QCA6174_HW_3_0_FW_DIR,
  135. .fw = QCA6174_HW_3_0_FW_FILE,
  136. .otp = QCA6174_HW_3_0_OTP_FILE,
  137. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  138. .board_size = QCA6174_BOARD_DATA_SZ,
  139. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  140. },
  141. },
  142. {
  143. .id = QCA99X0_HW_2_0_DEV_VERSION,
  144. .dev_id = QCA99X0_2_0_DEVICE_ID,
  145. .name = "qca99x0 hw2.0",
  146. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  147. .uart_pin = 7,
  148. .otp_exe_param = 0x00000700,
  149. .continuous_frag_desc = true,
  150. .channel_counters_freq_hz = 150000,
  151. .max_probe_resp_desc_thres = 24,
  152. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  153. .num_msdu_desc = 1424,
  154. .qcache_active_peers = 50,
  155. .tx_chain_mask = 0xf,
  156. .rx_chain_mask = 0xf,
  157. .max_spatial_stream = 4,
  158. .fw = {
  159. .dir = QCA99X0_HW_2_0_FW_DIR,
  160. .fw = QCA99X0_HW_2_0_FW_FILE,
  161. .otp = QCA99X0_HW_2_0_OTP_FILE,
  162. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  163. .board_size = QCA99X0_BOARD_DATA_SZ,
  164. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  165. },
  166. },
  167. {
  168. .id = QCA9377_HW_1_0_DEV_VERSION,
  169. .dev_id = QCA9377_1_0_DEVICE_ID,
  170. .name = "qca9377 hw1.0",
  171. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  172. .uart_pin = 6,
  173. .otp_exe_param = 0,
  174. .channel_counters_freq_hz = 88000,
  175. .max_probe_resp_desc_thres = 0,
  176. .fw = {
  177. .dir = QCA9377_HW_1_0_FW_DIR,
  178. .fw = QCA9377_HW_1_0_FW_FILE,
  179. .otp = QCA9377_HW_1_0_OTP_FILE,
  180. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  181. .board_size = QCA9377_BOARD_DATA_SZ,
  182. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  183. },
  184. },
  185. {
  186. .id = QCA9377_HW_1_1_DEV_VERSION,
  187. .dev_id = QCA9377_1_0_DEVICE_ID,
  188. .name = "qca9377 hw1.1",
  189. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  190. .uart_pin = 6,
  191. .otp_exe_param = 0,
  192. .channel_counters_freq_hz = 88000,
  193. .max_probe_resp_desc_thres = 0,
  194. .fw = {
  195. .dir = QCA9377_HW_1_0_FW_DIR,
  196. .fw = QCA9377_HW_1_0_FW_FILE,
  197. .otp = QCA9377_HW_1_0_OTP_FILE,
  198. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  199. .board_size = QCA9377_BOARD_DATA_SZ,
  200. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  201. },
  202. },
  203. {
  204. .id = QCA4019_HW_1_0_DEV_VERSION,
  205. .dev_id = 0,
  206. .name = "qca4019 hw1.0",
  207. .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
  208. .uart_pin = 7,
  209. .otp_exe_param = 0x0010000,
  210. .continuous_frag_desc = true,
  211. .channel_counters_freq_hz = 125000,
  212. .max_probe_resp_desc_thres = 24,
  213. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  214. .num_msdu_desc = 2500,
  215. .qcache_active_peers = 35,
  216. .tx_chain_mask = 0x3,
  217. .rx_chain_mask = 0x3,
  218. .max_spatial_stream = 2,
  219. .fw = {
  220. .dir = QCA4019_HW_1_0_FW_DIR,
  221. .fw = QCA4019_HW_1_0_FW_FILE,
  222. .otp = QCA4019_HW_1_0_OTP_FILE,
  223. .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
  224. .board_size = QCA4019_BOARD_DATA_SZ,
  225. .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
  226. },
  227. },
  228. };
  229. static const char *const ath10k_core_fw_feature_str[] = {
  230. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  231. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  232. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  233. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  234. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  235. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  236. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  237. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  238. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  239. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  240. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  241. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  242. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  243. [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
  244. };
  245. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  246. size_t buf_len,
  247. enum ath10k_fw_features feat)
  248. {
  249. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  250. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  251. ATH10K_FW_FEATURE_COUNT);
  252. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  253. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  254. return scnprintf(buf, buf_len, "bit%d", feat);
  255. }
  256. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  257. }
  258. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  259. char *buf,
  260. size_t buf_len)
  261. {
  262. unsigned int len = 0;
  263. int i;
  264. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  265. if (test_bit(i, ar->fw_features)) {
  266. if (len > 0)
  267. len += scnprintf(buf + len, buf_len - len, ",");
  268. len += ath10k_core_get_fw_feature_str(buf + len,
  269. buf_len - len,
  270. i);
  271. }
  272. }
  273. }
  274. static void ath10k_send_suspend_complete(struct ath10k *ar)
  275. {
  276. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  277. complete(&ar->target_suspend);
  278. }
  279. static int ath10k_init_configure_target(struct ath10k *ar)
  280. {
  281. u32 param_host;
  282. int ret;
  283. /* tell target which HTC version it is used*/
  284. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  285. HTC_PROTOCOL_VERSION);
  286. if (ret) {
  287. ath10k_err(ar, "settings HTC version failed\n");
  288. return ret;
  289. }
  290. /* set the firmware mode to STA/IBSS/AP */
  291. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  292. if (ret) {
  293. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  294. return ret;
  295. }
  296. /* TODO following parameters need to be re-visited. */
  297. /* num_device */
  298. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  299. /* Firmware mode */
  300. /* FIXME: Why FW_MODE_AP ??.*/
  301. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  302. /* mac_addr_method */
  303. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  304. /* firmware_bridge */
  305. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  306. /* fwsubmode */
  307. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  308. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  309. if (ret) {
  310. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  311. return ret;
  312. }
  313. /* We do all byte-swapping on the host */
  314. ret = ath10k_bmi_write32(ar, hi_be, 0);
  315. if (ret) {
  316. ath10k_err(ar, "setting host CPU BE mode failed\n");
  317. return ret;
  318. }
  319. /* FW descriptor/Data swap flags */
  320. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  321. if (ret) {
  322. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  323. return ret;
  324. }
  325. /* Some devices have a special sanity check that verifies the PCI
  326. * Device ID is written to this host interest var. It is known to be
  327. * required to boot QCA6164.
  328. */
  329. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  330. ar->dev_id);
  331. if (ret) {
  332. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  333. return ret;
  334. }
  335. return 0;
  336. }
  337. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  338. const char *dir,
  339. const char *file)
  340. {
  341. char filename[100];
  342. const struct firmware *fw;
  343. int ret;
  344. if (file == NULL)
  345. return ERR_PTR(-ENOENT);
  346. if (dir == NULL)
  347. dir = ".";
  348. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  349. ret = request_firmware(&fw, filename, ar->dev);
  350. if (ret)
  351. return ERR_PTR(ret);
  352. return fw;
  353. }
  354. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  355. size_t data_len)
  356. {
  357. u32 board_data_size = ar->hw_params.fw.board_size;
  358. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  359. u32 board_ext_data_addr;
  360. int ret;
  361. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  362. if (ret) {
  363. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  364. ret);
  365. return ret;
  366. }
  367. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  368. "boot push board extended data addr 0x%x\n",
  369. board_ext_data_addr);
  370. if (board_ext_data_addr == 0)
  371. return 0;
  372. if (data_len != (board_data_size + board_ext_data_size)) {
  373. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  374. data_len, board_data_size, board_ext_data_size);
  375. return -EINVAL;
  376. }
  377. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  378. data + board_data_size,
  379. board_ext_data_size);
  380. if (ret) {
  381. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  382. return ret;
  383. }
  384. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  385. (board_ext_data_size << 16) | 1);
  386. if (ret) {
  387. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  388. ret);
  389. return ret;
  390. }
  391. return 0;
  392. }
  393. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  394. size_t data_len)
  395. {
  396. u32 board_data_size = ar->hw_params.fw.board_size;
  397. u32 address;
  398. int ret;
  399. ret = ath10k_push_board_ext_data(ar, data, data_len);
  400. if (ret) {
  401. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  402. goto exit;
  403. }
  404. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  405. if (ret) {
  406. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  407. goto exit;
  408. }
  409. ret = ath10k_bmi_write_memory(ar, address, data,
  410. min_t(u32, board_data_size,
  411. data_len));
  412. if (ret) {
  413. ath10k_err(ar, "could not write board data (%d)\n", ret);
  414. goto exit;
  415. }
  416. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  417. if (ret) {
  418. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  419. goto exit;
  420. }
  421. exit:
  422. return ret;
  423. }
  424. static int ath10k_download_cal_file(struct ath10k *ar)
  425. {
  426. int ret;
  427. if (!ar->cal_file)
  428. return -ENOENT;
  429. if (IS_ERR(ar->cal_file))
  430. return PTR_ERR(ar->cal_file);
  431. ret = ath10k_download_board_data(ar, ar->cal_file->data,
  432. ar->cal_file->size);
  433. if (ret) {
  434. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  435. return ret;
  436. }
  437. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  438. return 0;
  439. }
  440. static int ath10k_download_cal_dt(struct ath10k *ar)
  441. {
  442. struct device_node *node;
  443. int data_len;
  444. void *data;
  445. int ret;
  446. node = ar->dev->of_node;
  447. if (!node)
  448. /* Device Tree is optional, don't print any warnings if
  449. * there's no node for ath10k.
  450. */
  451. return -ENOENT;
  452. if (!of_get_property(node, "qcom,ath10k-calibration-data",
  453. &data_len)) {
  454. /* The calibration data node is optional */
  455. return -ENOENT;
  456. }
  457. if (data_len != QCA988X_CAL_DATA_LEN) {
  458. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  459. data_len);
  460. ret = -EMSGSIZE;
  461. goto out;
  462. }
  463. data = kmalloc(data_len, GFP_KERNEL);
  464. if (!data) {
  465. ret = -ENOMEM;
  466. goto out;
  467. }
  468. ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data",
  469. data, data_len);
  470. if (ret) {
  471. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  472. ret);
  473. goto out_free;
  474. }
  475. ret = ath10k_download_board_data(ar, data, data_len);
  476. if (ret) {
  477. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  478. ret);
  479. goto out_free;
  480. }
  481. ret = 0;
  482. out_free:
  483. kfree(data);
  484. out:
  485. return ret;
  486. }
  487. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  488. {
  489. u32 result, address;
  490. u8 board_id, chip_id;
  491. int ret;
  492. address = ar->hw_params.patch_load_addr;
  493. if (!ar->otp_data || !ar->otp_len) {
  494. ath10k_warn(ar,
  495. "failed to retrieve board id because of invalid otp\n");
  496. return -ENODATA;
  497. }
  498. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  499. "boot upload otp to 0x%x len %zd for board id\n",
  500. address, ar->otp_len);
  501. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  502. if (ret) {
  503. ath10k_err(ar, "could not write otp for board id check: %d\n",
  504. ret);
  505. return ret;
  506. }
  507. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  508. &result);
  509. if (ret) {
  510. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  511. ret);
  512. return ret;
  513. }
  514. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  515. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  516. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  517. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  518. result, board_id, chip_id);
  519. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0)
  520. return -EOPNOTSUPP;
  521. ar->id.bmi_ids_valid = true;
  522. ar->id.bmi_board_id = board_id;
  523. ar->id.bmi_chip_id = chip_id;
  524. return 0;
  525. }
  526. static int ath10k_download_and_run_otp(struct ath10k *ar)
  527. {
  528. u32 result, address = ar->hw_params.patch_load_addr;
  529. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  530. int ret;
  531. ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len);
  532. if (ret) {
  533. ath10k_err(ar, "failed to download board data: %d\n", ret);
  534. return ret;
  535. }
  536. /* OTP is optional */
  537. if (!ar->otp_data || !ar->otp_len) {
  538. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
  539. ar->otp_data, ar->otp_len);
  540. return 0;
  541. }
  542. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  543. address, ar->otp_len);
  544. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  545. if (ret) {
  546. ath10k_err(ar, "could not write otp (%d)\n", ret);
  547. return ret;
  548. }
  549. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  550. if (ret) {
  551. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  552. return ret;
  553. }
  554. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  555. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  556. ar->fw_features)) &&
  557. result != 0) {
  558. ath10k_err(ar, "otp calibration failed: %d", result);
  559. return -EINVAL;
  560. }
  561. return 0;
  562. }
  563. static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode)
  564. {
  565. u32 address, data_len;
  566. const char *mode_name;
  567. const void *data;
  568. int ret;
  569. address = ar->hw_params.patch_load_addr;
  570. switch (mode) {
  571. case ATH10K_FIRMWARE_MODE_NORMAL:
  572. data = ar->firmware_data;
  573. data_len = ar->firmware_len;
  574. mode_name = "normal";
  575. ret = ath10k_swap_code_seg_configure(ar,
  576. ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
  577. if (ret) {
  578. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  579. ret);
  580. return ret;
  581. }
  582. break;
  583. case ATH10K_FIRMWARE_MODE_UTF:
  584. data = ar->testmode.utf_firmware_data;
  585. data_len = ar->testmode.utf_firmware_len;
  586. mode_name = "utf";
  587. break;
  588. default:
  589. ath10k_err(ar, "unknown firmware mode: %d\n", mode);
  590. return -EINVAL;
  591. }
  592. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  593. "boot uploading firmware image %p len %d mode %s\n",
  594. data, data_len, mode_name);
  595. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  596. if (ret) {
  597. ath10k_err(ar, "failed to download %s firmware: %d\n",
  598. mode_name, ret);
  599. return ret;
  600. }
  601. return ret;
  602. }
  603. static void ath10k_core_free_board_files(struct ath10k *ar)
  604. {
  605. if (!IS_ERR(ar->board))
  606. release_firmware(ar->board);
  607. ar->board = NULL;
  608. ar->board_data = NULL;
  609. ar->board_len = 0;
  610. }
  611. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  612. {
  613. if (!IS_ERR(ar->otp))
  614. release_firmware(ar->otp);
  615. if (!IS_ERR(ar->firmware))
  616. release_firmware(ar->firmware);
  617. if (!IS_ERR(ar->cal_file))
  618. release_firmware(ar->cal_file);
  619. ath10k_swap_code_seg_release(ar);
  620. ar->otp = NULL;
  621. ar->otp_data = NULL;
  622. ar->otp_len = 0;
  623. ar->firmware = NULL;
  624. ar->firmware_data = NULL;
  625. ar->firmware_len = 0;
  626. ar->cal_file = NULL;
  627. }
  628. static int ath10k_fetch_cal_file(struct ath10k *ar)
  629. {
  630. char filename[100];
  631. /* cal-<bus>-<id>.bin */
  632. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  633. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  634. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  635. if (IS_ERR(ar->cal_file))
  636. /* calibration file is optional, don't print any warnings */
  637. return PTR_ERR(ar->cal_file);
  638. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  639. ATH10K_FW_DIR, filename);
  640. return 0;
  641. }
  642. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  643. {
  644. if (!ar->hw_params.fw.board) {
  645. ath10k_err(ar, "failed to find board file fw entry\n");
  646. return -EINVAL;
  647. }
  648. ar->board = ath10k_fetch_fw_file(ar,
  649. ar->hw_params.fw.dir,
  650. ar->hw_params.fw.board);
  651. if (IS_ERR(ar->board))
  652. return PTR_ERR(ar->board);
  653. ar->board_data = ar->board->data;
  654. ar->board_len = ar->board->size;
  655. return 0;
  656. }
  657. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  658. const void *buf, size_t buf_len,
  659. const char *boardname)
  660. {
  661. const struct ath10k_fw_ie *hdr;
  662. bool name_match_found;
  663. int ret, board_ie_id;
  664. size_t board_ie_len;
  665. const void *board_ie_data;
  666. name_match_found = false;
  667. /* go through ATH10K_BD_IE_BOARD_ elements */
  668. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  669. hdr = buf;
  670. board_ie_id = le32_to_cpu(hdr->id);
  671. board_ie_len = le32_to_cpu(hdr->len);
  672. board_ie_data = hdr->data;
  673. buf_len -= sizeof(*hdr);
  674. buf += sizeof(*hdr);
  675. if (buf_len < ALIGN(board_ie_len, 4)) {
  676. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  677. buf_len, ALIGN(board_ie_len, 4));
  678. ret = -EINVAL;
  679. goto out;
  680. }
  681. switch (board_ie_id) {
  682. case ATH10K_BD_IE_BOARD_NAME:
  683. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  684. board_ie_data, board_ie_len);
  685. if (board_ie_len != strlen(boardname))
  686. break;
  687. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  688. if (ret)
  689. break;
  690. name_match_found = true;
  691. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  692. "boot found match for name '%s'",
  693. boardname);
  694. break;
  695. case ATH10K_BD_IE_BOARD_DATA:
  696. if (!name_match_found)
  697. /* no match found */
  698. break;
  699. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  700. "boot found board data for '%s'",
  701. boardname);
  702. ar->board_data = board_ie_data;
  703. ar->board_len = board_ie_len;
  704. ret = 0;
  705. goto out;
  706. default:
  707. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  708. board_ie_id);
  709. break;
  710. }
  711. /* jump over the padding */
  712. board_ie_len = ALIGN(board_ie_len, 4);
  713. buf_len -= board_ie_len;
  714. buf += board_ie_len;
  715. }
  716. /* no match found */
  717. ret = -ENOENT;
  718. out:
  719. return ret;
  720. }
  721. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  722. const char *boardname,
  723. const char *filename)
  724. {
  725. size_t len, magic_len, ie_len;
  726. struct ath10k_fw_ie *hdr;
  727. const u8 *data;
  728. int ret, ie_id;
  729. ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename);
  730. if (IS_ERR(ar->board))
  731. return PTR_ERR(ar->board);
  732. data = ar->board->data;
  733. len = ar->board->size;
  734. /* magic has extra null byte padded */
  735. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  736. if (len < magic_len) {
  737. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  738. ar->hw_params.fw.dir, filename, len);
  739. ret = -EINVAL;
  740. goto err;
  741. }
  742. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  743. ath10k_err(ar, "found invalid board magic\n");
  744. ret = -EINVAL;
  745. goto err;
  746. }
  747. /* magic is padded to 4 bytes */
  748. magic_len = ALIGN(magic_len, 4);
  749. if (len < magic_len) {
  750. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  751. ar->hw_params.fw.dir, filename, len);
  752. ret = -EINVAL;
  753. goto err;
  754. }
  755. data += magic_len;
  756. len -= magic_len;
  757. while (len > sizeof(struct ath10k_fw_ie)) {
  758. hdr = (struct ath10k_fw_ie *)data;
  759. ie_id = le32_to_cpu(hdr->id);
  760. ie_len = le32_to_cpu(hdr->len);
  761. len -= sizeof(*hdr);
  762. data = hdr->data;
  763. if (len < ALIGN(ie_len, 4)) {
  764. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  765. ie_id, ie_len, len);
  766. ret = -EINVAL;
  767. goto err;
  768. }
  769. switch (ie_id) {
  770. case ATH10K_BD_IE_BOARD:
  771. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  772. boardname);
  773. if (ret == -ENOENT)
  774. /* no match found, continue */
  775. break;
  776. else if (ret)
  777. /* there was an error, bail out */
  778. goto err;
  779. /* board data found */
  780. goto out;
  781. }
  782. /* jump over the padding */
  783. ie_len = ALIGN(ie_len, 4);
  784. len -= ie_len;
  785. data += ie_len;
  786. }
  787. out:
  788. if (!ar->board_data || !ar->board_len) {
  789. ath10k_err(ar,
  790. "failed to fetch board data for %s from %s/%s\n",
  791. boardname, ar->hw_params.fw.dir, filename);
  792. ret = -ENODATA;
  793. goto err;
  794. }
  795. return 0;
  796. err:
  797. ath10k_core_free_board_files(ar);
  798. return ret;
  799. }
  800. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  801. size_t name_len)
  802. {
  803. if (ar->id.bmi_ids_valid) {
  804. scnprintf(name, name_len,
  805. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  806. ath10k_bus_str(ar->hif.bus),
  807. ar->id.bmi_chip_id,
  808. ar->id.bmi_board_id);
  809. goto out;
  810. }
  811. scnprintf(name, name_len,
  812. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  813. ath10k_bus_str(ar->hif.bus),
  814. ar->id.vendor, ar->id.device,
  815. ar->id.subsystem_vendor, ar->id.subsystem_device);
  816. out:
  817. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  818. return 0;
  819. }
  820. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  821. {
  822. char boardname[100];
  823. int ret;
  824. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  825. if (ret) {
  826. ath10k_err(ar, "failed to create board name: %d", ret);
  827. return ret;
  828. }
  829. ar->bd_api = 2;
  830. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  831. ATH10K_BOARD_API2_FILE);
  832. if (!ret)
  833. goto success;
  834. ar->bd_api = 1;
  835. ret = ath10k_core_fetch_board_data_api_1(ar);
  836. if (ret) {
  837. ath10k_err(ar, "failed to fetch board data\n");
  838. return ret;
  839. }
  840. success:
  841. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  842. return 0;
  843. }
  844. static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
  845. {
  846. int ret = 0;
  847. if (ar->hw_params.fw.fw == NULL) {
  848. ath10k_err(ar, "firmware file not defined\n");
  849. return -EINVAL;
  850. }
  851. ar->firmware = ath10k_fetch_fw_file(ar,
  852. ar->hw_params.fw.dir,
  853. ar->hw_params.fw.fw);
  854. if (IS_ERR(ar->firmware)) {
  855. ret = PTR_ERR(ar->firmware);
  856. ath10k_err(ar, "could not fetch firmware (%d)\n", ret);
  857. goto err;
  858. }
  859. ar->firmware_data = ar->firmware->data;
  860. ar->firmware_len = ar->firmware->size;
  861. /* OTP may be undefined. If so, don't fetch it at all */
  862. if (ar->hw_params.fw.otp == NULL)
  863. return 0;
  864. ar->otp = ath10k_fetch_fw_file(ar,
  865. ar->hw_params.fw.dir,
  866. ar->hw_params.fw.otp);
  867. if (IS_ERR(ar->otp)) {
  868. ret = PTR_ERR(ar->otp);
  869. ath10k_err(ar, "could not fetch otp (%d)\n", ret);
  870. goto err;
  871. }
  872. ar->otp_data = ar->otp->data;
  873. ar->otp_len = ar->otp->size;
  874. return 0;
  875. err:
  876. ath10k_core_free_firmware_files(ar);
  877. return ret;
  878. }
  879. static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
  880. {
  881. size_t magic_len, len, ie_len;
  882. int ie_id, i, index, bit, ret;
  883. struct ath10k_fw_ie *hdr;
  884. const u8 *data;
  885. __le32 *timestamp, *version;
  886. /* first fetch the firmware file (firmware-*.bin) */
  887. ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name);
  888. if (IS_ERR(ar->firmware)) {
  889. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  890. ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware));
  891. return PTR_ERR(ar->firmware);
  892. }
  893. data = ar->firmware->data;
  894. len = ar->firmware->size;
  895. /* magic also includes the null byte, check that as well */
  896. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  897. if (len < magic_len) {
  898. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  899. ar->hw_params.fw.dir, name, len);
  900. ret = -EINVAL;
  901. goto err;
  902. }
  903. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  904. ath10k_err(ar, "invalid firmware magic\n");
  905. ret = -EINVAL;
  906. goto err;
  907. }
  908. /* jump over the padding */
  909. magic_len = ALIGN(magic_len, 4);
  910. len -= magic_len;
  911. data += magic_len;
  912. /* loop elements */
  913. while (len > sizeof(struct ath10k_fw_ie)) {
  914. hdr = (struct ath10k_fw_ie *)data;
  915. ie_id = le32_to_cpu(hdr->id);
  916. ie_len = le32_to_cpu(hdr->len);
  917. len -= sizeof(*hdr);
  918. data += sizeof(*hdr);
  919. if (len < ie_len) {
  920. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  921. ie_id, len, ie_len);
  922. ret = -EINVAL;
  923. goto err;
  924. }
  925. switch (ie_id) {
  926. case ATH10K_FW_IE_FW_VERSION:
  927. if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1)
  928. break;
  929. memcpy(ar->hw->wiphy->fw_version, data, ie_len);
  930. ar->hw->wiphy->fw_version[ie_len] = '\0';
  931. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  932. "found fw version %s\n",
  933. ar->hw->wiphy->fw_version);
  934. break;
  935. case ATH10K_FW_IE_TIMESTAMP:
  936. if (ie_len != sizeof(u32))
  937. break;
  938. timestamp = (__le32 *)data;
  939. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  940. le32_to_cpup(timestamp));
  941. break;
  942. case ATH10K_FW_IE_FEATURES:
  943. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  944. "found firmware features ie (%zd B)\n",
  945. ie_len);
  946. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  947. index = i / 8;
  948. bit = i % 8;
  949. if (index == ie_len)
  950. break;
  951. if (data[index] & (1 << bit)) {
  952. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  953. "Enabling feature bit: %i\n",
  954. i);
  955. __set_bit(i, ar->fw_features);
  956. }
  957. }
  958. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  959. ar->fw_features,
  960. sizeof(ar->fw_features));
  961. break;
  962. case ATH10K_FW_IE_FW_IMAGE:
  963. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  964. "found fw image ie (%zd B)\n",
  965. ie_len);
  966. ar->firmware_data = data;
  967. ar->firmware_len = ie_len;
  968. break;
  969. case ATH10K_FW_IE_OTP_IMAGE:
  970. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  971. "found otp image ie (%zd B)\n",
  972. ie_len);
  973. ar->otp_data = data;
  974. ar->otp_len = ie_len;
  975. break;
  976. case ATH10K_FW_IE_WMI_OP_VERSION:
  977. if (ie_len != sizeof(u32))
  978. break;
  979. version = (__le32 *)data;
  980. ar->wmi.op_version = le32_to_cpup(version);
  981. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  982. ar->wmi.op_version);
  983. break;
  984. case ATH10K_FW_IE_HTT_OP_VERSION:
  985. if (ie_len != sizeof(u32))
  986. break;
  987. version = (__le32 *)data;
  988. ar->htt.op_version = le32_to_cpup(version);
  989. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  990. ar->htt.op_version);
  991. break;
  992. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  993. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  994. "found fw code swap image ie (%zd B)\n",
  995. ie_len);
  996. ar->swap.firmware_codeswap_data = data;
  997. ar->swap.firmware_codeswap_len = ie_len;
  998. break;
  999. default:
  1000. ath10k_warn(ar, "Unknown FW IE: %u\n",
  1001. le32_to_cpu(hdr->id));
  1002. break;
  1003. }
  1004. /* jump over the padding */
  1005. ie_len = ALIGN(ie_len, 4);
  1006. len -= ie_len;
  1007. data += ie_len;
  1008. }
  1009. if (!ar->firmware_data || !ar->firmware_len) {
  1010. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  1011. ar->hw_params.fw.dir, name);
  1012. ret = -ENOMEDIUM;
  1013. goto err;
  1014. }
  1015. return 0;
  1016. err:
  1017. ath10k_core_free_firmware_files(ar);
  1018. return ret;
  1019. }
  1020. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  1021. {
  1022. int ret;
  1023. /* calibration file is optional, don't check for any errors */
  1024. ath10k_fetch_cal_file(ar);
  1025. ar->fw_api = 5;
  1026. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1027. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE);
  1028. if (ret == 0)
  1029. goto success;
  1030. ar->fw_api = 4;
  1031. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1032. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE);
  1033. if (ret == 0)
  1034. goto success;
  1035. ar->fw_api = 3;
  1036. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1037. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE);
  1038. if (ret == 0)
  1039. goto success;
  1040. ar->fw_api = 2;
  1041. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1042. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE);
  1043. if (ret == 0)
  1044. goto success;
  1045. ar->fw_api = 1;
  1046. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1047. ret = ath10k_core_fetch_firmware_api_1(ar);
  1048. if (ret)
  1049. return ret;
  1050. success:
  1051. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1052. return 0;
  1053. }
  1054. static int ath10k_download_cal_data(struct ath10k *ar)
  1055. {
  1056. int ret;
  1057. ret = ath10k_download_cal_file(ar);
  1058. if (ret == 0) {
  1059. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1060. goto done;
  1061. }
  1062. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1063. "boot did not find a calibration file, try DT next: %d\n",
  1064. ret);
  1065. ret = ath10k_download_cal_dt(ar);
  1066. if (ret == 0) {
  1067. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1068. goto done;
  1069. }
  1070. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1071. "boot did not find DT entry, try OTP next: %d\n",
  1072. ret);
  1073. ret = ath10k_download_and_run_otp(ar);
  1074. if (ret) {
  1075. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1076. return ret;
  1077. }
  1078. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1079. done:
  1080. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1081. ath10k_cal_mode_str(ar->cal_mode));
  1082. return 0;
  1083. }
  1084. static int ath10k_init_uart(struct ath10k *ar)
  1085. {
  1086. int ret;
  1087. /*
  1088. * Explicitly setting UART prints to zero as target turns it on
  1089. * based on scratch registers.
  1090. */
  1091. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1092. if (ret) {
  1093. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1094. return ret;
  1095. }
  1096. if (!uart_print)
  1097. return 0;
  1098. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1099. if (ret) {
  1100. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1101. return ret;
  1102. }
  1103. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1104. if (ret) {
  1105. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1106. return ret;
  1107. }
  1108. /* Set the UART baud rate to 19200. */
  1109. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1110. if (ret) {
  1111. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1112. return ret;
  1113. }
  1114. ath10k_info(ar, "UART prints enabled\n");
  1115. return 0;
  1116. }
  1117. static int ath10k_init_hw_params(struct ath10k *ar)
  1118. {
  1119. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1120. int i;
  1121. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1122. hw_params = &ath10k_hw_params_list[i];
  1123. if (hw_params->id == ar->target_version &&
  1124. hw_params->dev_id == ar->dev_id)
  1125. break;
  1126. }
  1127. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1128. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1129. ar->target_version);
  1130. return -EINVAL;
  1131. }
  1132. ar->hw_params = *hw_params;
  1133. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1134. ar->hw_params.name, ar->target_version);
  1135. return 0;
  1136. }
  1137. static void ath10k_core_restart(struct work_struct *work)
  1138. {
  1139. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1140. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1141. /* Place a barrier to make sure the compiler doesn't reorder
  1142. * CRASH_FLUSH and calling other functions.
  1143. */
  1144. barrier();
  1145. ieee80211_stop_queues(ar->hw);
  1146. ath10k_drain_tx(ar);
  1147. complete_all(&ar->scan.started);
  1148. complete_all(&ar->scan.completed);
  1149. complete_all(&ar->scan.on_channel);
  1150. complete_all(&ar->offchan_tx_completed);
  1151. complete_all(&ar->install_key_done);
  1152. complete_all(&ar->vdev_setup_done);
  1153. complete_all(&ar->thermal.wmi_sync);
  1154. wake_up(&ar->htt.empty_tx_wq);
  1155. wake_up(&ar->wmi.tx_credits_wq);
  1156. wake_up(&ar->peer_mapping_wq);
  1157. mutex_lock(&ar->conf_mutex);
  1158. switch (ar->state) {
  1159. case ATH10K_STATE_ON:
  1160. ar->state = ATH10K_STATE_RESTARTING;
  1161. ath10k_hif_stop(ar);
  1162. ath10k_scan_finish(ar);
  1163. ieee80211_restart_hw(ar->hw);
  1164. break;
  1165. case ATH10K_STATE_OFF:
  1166. /* this can happen if driver is being unloaded
  1167. * or if the crash happens during FW probing */
  1168. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1169. break;
  1170. case ATH10K_STATE_RESTARTING:
  1171. /* hw restart might be requested from multiple places */
  1172. break;
  1173. case ATH10K_STATE_RESTARTED:
  1174. ar->state = ATH10K_STATE_WEDGED;
  1175. /* fall through */
  1176. case ATH10K_STATE_WEDGED:
  1177. ath10k_warn(ar, "device is wedged, will not restart\n");
  1178. break;
  1179. case ATH10K_STATE_UTF:
  1180. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1181. break;
  1182. }
  1183. mutex_unlock(&ar->conf_mutex);
  1184. }
  1185. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1186. {
  1187. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) &&
  1188. !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1189. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1190. return -EINVAL;
  1191. }
  1192. if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1193. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1194. ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version);
  1195. return -EINVAL;
  1196. }
  1197. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1198. switch (ath10k_cryptmode_param) {
  1199. case ATH10K_CRYPT_MODE_HW:
  1200. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1201. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1202. break;
  1203. case ATH10K_CRYPT_MODE_SW:
  1204. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1205. ar->fw_features)) {
  1206. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1207. return -EINVAL;
  1208. }
  1209. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1210. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1211. break;
  1212. default:
  1213. ath10k_info(ar, "invalid cryptmode: %d\n",
  1214. ath10k_cryptmode_param);
  1215. return -EINVAL;
  1216. }
  1217. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1218. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1219. if (rawmode) {
  1220. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1221. ar->fw_features)) {
  1222. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1223. return -EINVAL;
  1224. }
  1225. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1226. }
  1227. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1228. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1229. /* Workaround:
  1230. *
  1231. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1232. * and causes enormous performance issues (malformed frames,
  1233. * etc).
  1234. *
  1235. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1236. * albeit a bit slower compared to regular operation.
  1237. */
  1238. ar->htt.max_num_amsdu = 1;
  1239. }
  1240. /* Backwards compatibility for firmwares without
  1241. * ATH10K_FW_IE_WMI_OP_VERSION.
  1242. */
  1243. if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1244. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1245. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1246. ar->fw_features))
  1247. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1248. else
  1249. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1250. } else {
  1251. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1252. }
  1253. }
  1254. switch (ar->wmi.op_version) {
  1255. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1256. ar->max_num_peers = TARGET_NUM_PEERS;
  1257. ar->max_num_stations = TARGET_NUM_STATIONS;
  1258. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1259. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1260. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1261. WMI_STAT_PEER;
  1262. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1263. break;
  1264. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1265. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1266. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1267. if (test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) {
  1268. ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
  1269. ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
  1270. } else {
  1271. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1272. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1273. }
  1274. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1275. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1276. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1277. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1278. break;
  1279. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1280. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1281. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1282. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1283. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1284. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1285. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1286. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1287. WMI_STAT_PEER;
  1288. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1289. break;
  1290. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1291. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1292. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1293. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1294. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1295. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1296. ar->htt.max_num_pending_tx = ar->hw_params.num_msdu_desc;
  1297. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1298. ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
  1299. break;
  1300. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1301. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1302. WARN_ON(1);
  1303. return -EINVAL;
  1304. }
  1305. /* Backwards compatibility for firmwares without
  1306. * ATH10K_FW_IE_HTT_OP_VERSION.
  1307. */
  1308. if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1309. switch (ar->wmi.op_version) {
  1310. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1311. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1312. break;
  1313. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1314. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1315. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1316. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1317. break;
  1318. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1319. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1320. break;
  1321. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1322. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1323. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1324. WARN_ON(1);
  1325. return -EINVAL;
  1326. }
  1327. }
  1328. return 0;
  1329. }
  1330. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
  1331. {
  1332. int status;
  1333. lockdep_assert_held(&ar->conf_mutex);
  1334. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1335. ath10k_bmi_start(ar);
  1336. if (ath10k_init_configure_target(ar)) {
  1337. status = -EINVAL;
  1338. goto err;
  1339. }
  1340. status = ath10k_download_cal_data(ar);
  1341. if (status)
  1342. goto err;
  1343. /* Some of of qca988x solutions are having global reset issue
  1344. * during target initialization. Bypassing PLL setting before
  1345. * downloading firmware and letting the SoC run on REF_CLK is
  1346. * fixing the problem. Corresponding firmware change is also needed
  1347. * to set the clock source once the target is initialized.
  1348. */
  1349. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1350. ar->fw_features)) {
  1351. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1352. if (status) {
  1353. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1354. status);
  1355. goto err;
  1356. }
  1357. }
  1358. status = ath10k_download_fw(ar, mode);
  1359. if (status)
  1360. goto err;
  1361. status = ath10k_init_uart(ar);
  1362. if (status)
  1363. goto err;
  1364. ar->htc.htc_ops.target_send_suspend_complete =
  1365. ath10k_send_suspend_complete;
  1366. status = ath10k_htc_init(ar);
  1367. if (status) {
  1368. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1369. goto err;
  1370. }
  1371. status = ath10k_bmi_done(ar);
  1372. if (status)
  1373. goto err;
  1374. status = ath10k_wmi_attach(ar);
  1375. if (status) {
  1376. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1377. goto err;
  1378. }
  1379. status = ath10k_htt_init(ar);
  1380. if (status) {
  1381. ath10k_err(ar, "failed to init htt: %d\n", status);
  1382. goto err_wmi_detach;
  1383. }
  1384. status = ath10k_htt_tx_alloc(&ar->htt);
  1385. if (status) {
  1386. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1387. goto err_wmi_detach;
  1388. }
  1389. status = ath10k_htt_rx_alloc(&ar->htt);
  1390. if (status) {
  1391. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1392. goto err_htt_tx_detach;
  1393. }
  1394. status = ath10k_hif_start(ar);
  1395. if (status) {
  1396. ath10k_err(ar, "could not start HIF: %d\n", status);
  1397. goto err_htt_rx_detach;
  1398. }
  1399. status = ath10k_htc_wait_target(&ar->htc);
  1400. if (status) {
  1401. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1402. goto err_hif_stop;
  1403. }
  1404. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1405. status = ath10k_htt_connect(&ar->htt);
  1406. if (status) {
  1407. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1408. goto err_hif_stop;
  1409. }
  1410. }
  1411. status = ath10k_wmi_connect(ar);
  1412. if (status) {
  1413. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1414. goto err_hif_stop;
  1415. }
  1416. status = ath10k_htc_start(&ar->htc);
  1417. if (status) {
  1418. ath10k_err(ar, "failed to start htc: %d\n", status);
  1419. goto err_hif_stop;
  1420. }
  1421. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1422. status = ath10k_wmi_wait_for_service_ready(ar);
  1423. if (status) {
  1424. ath10k_warn(ar, "wmi service ready event not received");
  1425. goto err_hif_stop;
  1426. }
  1427. }
  1428. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1429. ar->hw->wiphy->fw_version);
  1430. status = ath10k_wmi_cmd_init(ar);
  1431. if (status) {
  1432. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1433. status);
  1434. goto err_hif_stop;
  1435. }
  1436. status = ath10k_wmi_wait_for_unified_ready(ar);
  1437. if (status) {
  1438. ath10k_err(ar, "wmi unified ready event not received\n");
  1439. goto err_hif_stop;
  1440. }
  1441. /* If firmware indicates Full Rx Reorder support it must be used in a
  1442. * slightly different manner. Let HTT code know.
  1443. */
  1444. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1445. ar->wmi.svc_map));
  1446. status = ath10k_htt_rx_ring_refill(ar);
  1447. if (status) {
  1448. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1449. goto err_hif_stop;
  1450. }
  1451. /* we don't care about HTT in UTF mode */
  1452. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1453. status = ath10k_htt_setup(&ar->htt);
  1454. if (status) {
  1455. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1456. goto err_hif_stop;
  1457. }
  1458. }
  1459. status = ath10k_debug_start(ar);
  1460. if (status)
  1461. goto err_hif_stop;
  1462. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1463. INIT_LIST_HEAD(&ar->arvifs);
  1464. return 0;
  1465. err_hif_stop:
  1466. ath10k_hif_stop(ar);
  1467. err_htt_rx_detach:
  1468. ath10k_htt_rx_free(&ar->htt);
  1469. err_htt_tx_detach:
  1470. ath10k_htt_tx_free(&ar->htt);
  1471. err_wmi_detach:
  1472. ath10k_wmi_detach(ar);
  1473. err:
  1474. return status;
  1475. }
  1476. EXPORT_SYMBOL(ath10k_core_start);
  1477. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1478. {
  1479. int ret;
  1480. unsigned long time_left;
  1481. reinit_completion(&ar->target_suspend);
  1482. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1483. if (ret) {
  1484. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1485. return ret;
  1486. }
  1487. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1488. if (!time_left) {
  1489. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1490. return -ETIMEDOUT;
  1491. }
  1492. return 0;
  1493. }
  1494. void ath10k_core_stop(struct ath10k *ar)
  1495. {
  1496. lockdep_assert_held(&ar->conf_mutex);
  1497. ath10k_debug_stop(ar);
  1498. /* try to suspend target */
  1499. if (ar->state != ATH10K_STATE_RESTARTING &&
  1500. ar->state != ATH10K_STATE_UTF)
  1501. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1502. ath10k_hif_stop(ar);
  1503. ath10k_htt_tx_free(&ar->htt);
  1504. ath10k_htt_rx_free(&ar->htt);
  1505. ath10k_wmi_detach(ar);
  1506. }
  1507. EXPORT_SYMBOL(ath10k_core_stop);
  1508. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1509. * order to know what hw capabilities should be advertised to mac80211 it is
  1510. * necessary to load the firmware (and tear it down immediately since start
  1511. * hook will try to init it again) before registering */
  1512. static int ath10k_core_probe_fw(struct ath10k *ar)
  1513. {
  1514. struct bmi_target_info target_info;
  1515. int ret = 0;
  1516. ret = ath10k_hif_power_up(ar);
  1517. if (ret) {
  1518. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1519. return ret;
  1520. }
  1521. memset(&target_info, 0, sizeof(target_info));
  1522. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1523. if (ret) {
  1524. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1525. goto err_power_down;
  1526. }
  1527. ar->target_version = target_info.version;
  1528. ar->hw->wiphy->hw_version = target_info.version;
  1529. ret = ath10k_init_hw_params(ar);
  1530. if (ret) {
  1531. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1532. goto err_power_down;
  1533. }
  1534. ret = ath10k_core_fetch_firmware_files(ar);
  1535. if (ret) {
  1536. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1537. goto err_power_down;
  1538. }
  1539. ath10k_debug_print_hwfw_info(ar);
  1540. ret = ath10k_core_get_board_id_from_otp(ar);
  1541. if (ret && ret != -EOPNOTSUPP) {
  1542. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1543. ret);
  1544. return ret;
  1545. }
  1546. ret = ath10k_core_fetch_board_file(ar);
  1547. if (ret) {
  1548. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1549. goto err_free_firmware_files;
  1550. }
  1551. ath10k_debug_print_board_info(ar);
  1552. ret = ath10k_core_init_firmware_features(ar);
  1553. if (ret) {
  1554. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1555. ret);
  1556. goto err_free_firmware_files;
  1557. }
  1558. ret = ath10k_swap_code_seg_init(ar);
  1559. if (ret) {
  1560. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1561. ret);
  1562. goto err_free_firmware_files;
  1563. }
  1564. mutex_lock(&ar->conf_mutex);
  1565. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL);
  1566. if (ret) {
  1567. ath10k_err(ar, "could not init core (%d)\n", ret);
  1568. goto err_unlock;
  1569. }
  1570. ath10k_debug_print_boot_info(ar);
  1571. ath10k_core_stop(ar);
  1572. mutex_unlock(&ar->conf_mutex);
  1573. ath10k_hif_power_down(ar);
  1574. return 0;
  1575. err_unlock:
  1576. mutex_unlock(&ar->conf_mutex);
  1577. err_free_firmware_files:
  1578. ath10k_core_free_firmware_files(ar);
  1579. err_power_down:
  1580. ath10k_hif_power_down(ar);
  1581. return ret;
  1582. }
  1583. static void ath10k_core_register_work(struct work_struct *work)
  1584. {
  1585. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1586. int status;
  1587. status = ath10k_core_probe_fw(ar);
  1588. if (status) {
  1589. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1590. goto err;
  1591. }
  1592. status = ath10k_mac_register(ar);
  1593. if (status) {
  1594. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1595. goto err_release_fw;
  1596. }
  1597. status = ath10k_debug_register(ar);
  1598. if (status) {
  1599. ath10k_err(ar, "unable to initialize debugfs\n");
  1600. goto err_unregister_mac;
  1601. }
  1602. status = ath10k_spectral_create(ar);
  1603. if (status) {
  1604. ath10k_err(ar, "failed to initialize spectral\n");
  1605. goto err_debug_destroy;
  1606. }
  1607. status = ath10k_thermal_register(ar);
  1608. if (status) {
  1609. ath10k_err(ar, "could not register thermal device: %d\n",
  1610. status);
  1611. goto err_spectral_destroy;
  1612. }
  1613. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1614. return;
  1615. err_spectral_destroy:
  1616. ath10k_spectral_destroy(ar);
  1617. err_debug_destroy:
  1618. ath10k_debug_destroy(ar);
  1619. err_unregister_mac:
  1620. ath10k_mac_unregister(ar);
  1621. err_release_fw:
  1622. ath10k_core_free_firmware_files(ar);
  1623. err:
  1624. /* TODO: It's probably a good idea to release device from the driver
  1625. * but calling device_release_driver() here will cause a deadlock.
  1626. */
  1627. return;
  1628. }
  1629. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1630. {
  1631. ar->chip_id = chip_id;
  1632. queue_work(ar->workqueue, &ar->register_work);
  1633. return 0;
  1634. }
  1635. EXPORT_SYMBOL(ath10k_core_register);
  1636. void ath10k_core_unregister(struct ath10k *ar)
  1637. {
  1638. cancel_work_sync(&ar->register_work);
  1639. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1640. return;
  1641. ath10k_thermal_unregister(ar);
  1642. /* Stop spectral before unregistering from mac80211 to remove the
  1643. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1644. * would be already be free'd recursively, leading to a double free.
  1645. */
  1646. ath10k_spectral_destroy(ar);
  1647. /* We must unregister from mac80211 before we stop HTC and HIF.
  1648. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1649. * unhappy about callback failures. */
  1650. ath10k_mac_unregister(ar);
  1651. ath10k_testmode_destroy(ar);
  1652. ath10k_core_free_firmware_files(ar);
  1653. ath10k_core_free_board_files(ar);
  1654. ath10k_debug_unregister(ar);
  1655. }
  1656. EXPORT_SYMBOL(ath10k_core_unregister);
  1657. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1658. enum ath10k_bus bus,
  1659. enum ath10k_hw_rev hw_rev,
  1660. const struct ath10k_hif_ops *hif_ops)
  1661. {
  1662. struct ath10k *ar;
  1663. int ret;
  1664. ar = ath10k_mac_create(priv_size);
  1665. if (!ar)
  1666. return NULL;
  1667. ar->ath_common.priv = ar;
  1668. ar->ath_common.hw = ar->hw;
  1669. ar->dev = dev;
  1670. ar->hw_rev = hw_rev;
  1671. ar->hif.ops = hif_ops;
  1672. ar->hif.bus = bus;
  1673. switch (hw_rev) {
  1674. case ATH10K_HW_QCA988X:
  1675. ar->regs = &qca988x_regs;
  1676. ar->hw_values = &qca988x_values;
  1677. break;
  1678. case ATH10K_HW_QCA6174:
  1679. case ATH10K_HW_QCA9377:
  1680. ar->regs = &qca6174_regs;
  1681. ar->hw_values = &qca6174_values;
  1682. break;
  1683. case ATH10K_HW_QCA99X0:
  1684. ar->regs = &qca99x0_regs;
  1685. ar->hw_values = &qca99x0_values;
  1686. break;
  1687. case ATH10K_HW_QCA4019:
  1688. ar->regs = &qca4019_regs;
  1689. ar->hw_values = &qca4019_values;
  1690. break;
  1691. default:
  1692. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1693. hw_rev);
  1694. ret = -ENOTSUPP;
  1695. goto err_free_mac;
  1696. }
  1697. init_completion(&ar->scan.started);
  1698. init_completion(&ar->scan.completed);
  1699. init_completion(&ar->scan.on_channel);
  1700. init_completion(&ar->target_suspend);
  1701. init_completion(&ar->wow.wakeup_completed);
  1702. init_completion(&ar->install_key_done);
  1703. init_completion(&ar->vdev_setup_done);
  1704. init_completion(&ar->thermal.wmi_sync);
  1705. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1706. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1707. if (!ar->workqueue)
  1708. goto err_free_mac;
  1709. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1710. if (!ar->workqueue_aux)
  1711. goto err_free_wq;
  1712. mutex_init(&ar->conf_mutex);
  1713. spin_lock_init(&ar->data_lock);
  1714. INIT_LIST_HEAD(&ar->peers);
  1715. init_waitqueue_head(&ar->peer_mapping_wq);
  1716. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1717. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1718. init_completion(&ar->offchan_tx_completed);
  1719. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1720. skb_queue_head_init(&ar->offchan_tx_queue);
  1721. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1722. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1723. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1724. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1725. ret = ath10k_debug_create(ar);
  1726. if (ret)
  1727. goto err_free_aux_wq;
  1728. return ar;
  1729. err_free_aux_wq:
  1730. destroy_workqueue(ar->workqueue_aux);
  1731. err_free_wq:
  1732. destroy_workqueue(ar->workqueue);
  1733. err_free_mac:
  1734. ath10k_mac_destroy(ar);
  1735. return NULL;
  1736. }
  1737. EXPORT_SYMBOL(ath10k_core_create);
  1738. void ath10k_core_destroy(struct ath10k *ar)
  1739. {
  1740. flush_workqueue(ar->workqueue);
  1741. destroy_workqueue(ar->workqueue);
  1742. flush_workqueue(ar->workqueue_aux);
  1743. destroy_workqueue(ar->workqueue_aux);
  1744. ath10k_debug_destroy(ar);
  1745. ath10k_wmi_free_host_mem(ar);
  1746. ath10k_mac_destroy(ar);
  1747. }
  1748. EXPORT_SYMBOL(ath10k_core_destroy);
  1749. MODULE_AUTHOR("Qualcomm Atheros");
  1750. MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
  1751. MODULE_LICENSE("Dual BSD/GPL");