r8152.c 98 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. #include <linux/suspend.h>
  28. /* Information for net-next */
  29. #define NETNEXT_VERSION "08"
  30. /* Information for net */
  31. #define NET_VERSION "3"
  32. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  33. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  34. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  35. #define MODULENAME "r8152"
  36. #define R8152_PHY_ID 32
  37. #define PLA_IDR 0xc000
  38. #define PLA_RCR 0xc010
  39. #define PLA_RMS 0xc016
  40. #define PLA_RXFIFO_CTRL0 0xc0a0
  41. #define PLA_RXFIFO_CTRL1 0xc0a4
  42. #define PLA_RXFIFO_CTRL2 0xc0a8
  43. #define PLA_DMY_REG0 0xc0b0
  44. #define PLA_FMC 0xc0b4
  45. #define PLA_CFG_WOL 0xc0b6
  46. #define PLA_TEREDO_CFG 0xc0bc
  47. #define PLA_MAR 0xcd00
  48. #define PLA_BACKUP 0xd000
  49. #define PAL_BDC_CR 0xd1a0
  50. #define PLA_TEREDO_TIMER 0xd2cc
  51. #define PLA_REALWOW_TIMER 0xd2e8
  52. #define PLA_LEDSEL 0xdd90
  53. #define PLA_LED_FEATURE 0xdd92
  54. #define PLA_PHYAR 0xde00
  55. #define PLA_BOOT_CTRL 0xe004
  56. #define PLA_GPHY_INTR_IMR 0xe022
  57. #define PLA_EEE_CR 0xe040
  58. #define PLA_EEEP_CR 0xe080
  59. #define PLA_MAC_PWR_CTRL 0xe0c0
  60. #define PLA_MAC_PWR_CTRL2 0xe0ca
  61. #define PLA_MAC_PWR_CTRL3 0xe0cc
  62. #define PLA_MAC_PWR_CTRL4 0xe0ce
  63. #define PLA_WDT6_CTRL 0xe428
  64. #define PLA_TCR0 0xe610
  65. #define PLA_TCR1 0xe612
  66. #define PLA_MTPS 0xe615
  67. #define PLA_TXFIFO_CTRL 0xe618
  68. #define PLA_RSTTALLY 0xe800
  69. #define PLA_CR 0xe813
  70. #define PLA_CRWECR 0xe81c
  71. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  72. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  73. #define PLA_CONFIG5 0xe822
  74. #define PLA_PHY_PWR 0xe84c
  75. #define PLA_OOB_CTRL 0xe84f
  76. #define PLA_CPCR 0xe854
  77. #define PLA_MISC_0 0xe858
  78. #define PLA_MISC_1 0xe85a
  79. #define PLA_OCP_GPHY_BASE 0xe86c
  80. #define PLA_TALLYCNT 0xe890
  81. #define PLA_SFF_STS_7 0xe8de
  82. #define PLA_PHYSTATUS 0xe908
  83. #define PLA_BP_BA 0xfc26
  84. #define PLA_BP_0 0xfc28
  85. #define PLA_BP_1 0xfc2a
  86. #define PLA_BP_2 0xfc2c
  87. #define PLA_BP_3 0xfc2e
  88. #define PLA_BP_4 0xfc30
  89. #define PLA_BP_5 0xfc32
  90. #define PLA_BP_6 0xfc34
  91. #define PLA_BP_7 0xfc36
  92. #define PLA_BP_EN 0xfc38
  93. #define USB_USB2PHY 0xb41e
  94. #define USB_SSPHYLINK2 0xb428
  95. #define USB_U2P3_CTRL 0xb460
  96. #define USB_CSR_DUMMY1 0xb464
  97. #define USB_CSR_DUMMY2 0xb466
  98. #define USB_DEV_STAT 0xb808
  99. #define USB_CONNECT_TIMER 0xcbf8
  100. #define USB_BURST_SIZE 0xcfc0
  101. #define USB_USB_CTRL 0xd406
  102. #define USB_PHY_CTRL 0xd408
  103. #define USB_TX_AGG 0xd40a
  104. #define USB_RX_BUF_TH 0xd40c
  105. #define USB_USB_TIMER 0xd428
  106. #define USB_RX_EARLY_TIMEOUT 0xd42c
  107. #define USB_RX_EARLY_SIZE 0xd42e
  108. #define USB_PM_CTRL_STATUS 0xd432
  109. #define USB_TX_DMA 0xd434
  110. #define USB_TOLERANCE 0xd490
  111. #define USB_LPM_CTRL 0xd41a
  112. #define USB_UPS_CTRL 0xd800
  113. #define USB_MISC_0 0xd81a
  114. #define USB_POWER_CUT 0xd80a
  115. #define USB_AFE_CTRL2 0xd824
  116. #define USB_WDT11_CTRL 0xe43c
  117. #define USB_BP_BA 0xfc26
  118. #define USB_BP_0 0xfc28
  119. #define USB_BP_1 0xfc2a
  120. #define USB_BP_2 0xfc2c
  121. #define USB_BP_3 0xfc2e
  122. #define USB_BP_4 0xfc30
  123. #define USB_BP_5 0xfc32
  124. #define USB_BP_6 0xfc34
  125. #define USB_BP_7 0xfc36
  126. #define USB_BP_EN 0xfc38
  127. /* OCP Registers */
  128. #define OCP_ALDPS_CONFIG 0x2010
  129. #define OCP_EEE_CONFIG1 0x2080
  130. #define OCP_EEE_CONFIG2 0x2092
  131. #define OCP_EEE_CONFIG3 0x2094
  132. #define OCP_BASE_MII 0xa400
  133. #define OCP_EEE_AR 0xa41a
  134. #define OCP_EEE_DATA 0xa41c
  135. #define OCP_PHY_STATUS 0xa420
  136. #define OCP_POWER_CFG 0xa430
  137. #define OCP_EEE_CFG 0xa432
  138. #define OCP_SRAM_ADDR 0xa436
  139. #define OCP_SRAM_DATA 0xa438
  140. #define OCP_DOWN_SPEED 0xa442
  141. #define OCP_EEE_ABLE 0xa5c4
  142. #define OCP_EEE_ADV 0xa5d0
  143. #define OCP_EEE_LPABLE 0xa5d2
  144. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  145. #define OCP_ADC_CFG 0xbc06
  146. /* SRAM Register */
  147. #define SRAM_LPF_CFG 0x8012
  148. #define SRAM_10M_AMP1 0x8080
  149. #define SRAM_10M_AMP2 0x8082
  150. #define SRAM_IMPEDANCE 0x8084
  151. /* PLA_RCR */
  152. #define RCR_AAP 0x00000001
  153. #define RCR_APM 0x00000002
  154. #define RCR_AM 0x00000004
  155. #define RCR_AB 0x00000008
  156. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  157. /* PLA_RXFIFO_CTRL0 */
  158. #define RXFIFO_THR1_NORMAL 0x00080002
  159. #define RXFIFO_THR1_OOB 0x01800003
  160. /* PLA_RXFIFO_CTRL1 */
  161. #define RXFIFO_THR2_FULL 0x00000060
  162. #define RXFIFO_THR2_HIGH 0x00000038
  163. #define RXFIFO_THR2_OOB 0x0000004a
  164. #define RXFIFO_THR2_NORMAL 0x00a0
  165. /* PLA_RXFIFO_CTRL2 */
  166. #define RXFIFO_THR3_FULL 0x00000078
  167. #define RXFIFO_THR3_HIGH 0x00000048
  168. #define RXFIFO_THR3_OOB 0x0000005a
  169. #define RXFIFO_THR3_NORMAL 0x0110
  170. /* PLA_TXFIFO_CTRL */
  171. #define TXFIFO_THR_NORMAL 0x00400008
  172. #define TXFIFO_THR_NORMAL2 0x01000008
  173. /* PLA_DMY_REG0 */
  174. #define ECM_ALDPS 0x0002
  175. /* PLA_FMC */
  176. #define FMC_FCR_MCU_EN 0x0001
  177. /* PLA_EEEP_CR */
  178. #define EEEP_CR_EEEP_TX 0x0002
  179. /* PLA_WDT6_CTRL */
  180. #define WDT6_SET_MODE 0x0010
  181. /* PLA_TCR0 */
  182. #define TCR0_TX_EMPTY 0x0800
  183. #define TCR0_AUTO_FIFO 0x0080
  184. /* PLA_TCR1 */
  185. #define VERSION_MASK 0x7cf0
  186. /* PLA_MTPS */
  187. #define MTPS_JUMBO (12 * 1024 / 64)
  188. #define MTPS_DEFAULT (6 * 1024 / 64)
  189. /* PLA_RSTTALLY */
  190. #define TALLY_RESET 0x0001
  191. /* PLA_CR */
  192. #define CR_RST 0x10
  193. #define CR_RE 0x08
  194. #define CR_TE 0x04
  195. /* PLA_CRWECR */
  196. #define CRWECR_NORAML 0x00
  197. #define CRWECR_CONFIG 0xc0
  198. /* PLA_OOB_CTRL */
  199. #define NOW_IS_OOB 0x80
  200. #define TXFIFO_EMPTY 0x20
  201. #define RXFIFO_EMPTY 0x10
  202. #define LINK_LIST_READY 0x02
  203. #define DIS_MCU_CLROOB 0x01
  204. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  205. /* PLA_MISC_1 */
  206. #define RXDY_GATED_EN 0x0008
  207. /* PLA_SFF_STS_7 */
  208. #define RE_INIT_LL 0x8000
  209. #define MCU_BORW_EN 0x4000
  210. /* PLA_CPCR */
  211. #define CPCR_RX_VLAN 0x0040
  212. /* PLA_CFG_WOL */
  213. #define MAGIC_EN 0x0001
  214. /* PLA_TEREDO_CFG */
  215. #define TEREDO_SEL 0x8000
  216. #define TEREDO_WAKE_MASK 0x7f00
  217. #define TEREDO_RS_EVENT_MASK 0x00fe
  218. #define OOB_TEREDO_EN 0x0001
  219. /* PAL_BDC_CR */
  220. #define ALDPS_PROXY_MODE 0x0001
  221. /* PLA_CONFIG34 */
  222. #define LINK_ON_WAKE_EN 0x0010
  223. #define LINK_OFF_WAKE_EN 0x0008
  224. /* PLA_CONFIG5 */
  225. #define BWF_EN 0x0040
  226. #define MWF_EN 0x0020
  227. #define UWF_EN 0x0010
  228. #define LAN_WAKE_EN 0x0002
  229. /* PLA_LED_FEATURE */
  230. #define LED_MODE_MASK 0x0700
  231. /* PLA_PHY_PWR */
  232. #define TX_10M_IDLE_EN 0x0080
  233. #define PFM_PWM_SWITCH 0x0040
  234. /* PLA_MAC_PWR_CTRL */
  235. #define D3_CLK_GATED_EN 0x00004000
  236. #define MCU_CLK_RATIO 0x07010f07
  237. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  238. #define ALDPS_SPDWN_RATIO 0x0f87
  239. /* PLA_MAC_PWR_CTRL2 */
  240. #define EEE_SPDWN_RATIO 0x8007
  241. /* PLA_MAC_PWR_CTRL3 */
  242. #define PKT_AVAIL_SPDWN_EN 0x0100
  243. #define SUSPEND_SPDWN_EN 0x0004
  244. #define U1U2_SPDWN_EN 0x0002
  245. #define L1_SPDWN_EN 0x0001
  246. /* PLA_MAC_PWR_CTRL4 */
  247. #define PWRSAVE_SPDWN_EN 0x1000
  248. #define RXDV_SPDWN_EN 0x0800
  249. #define TX10MIDLE_EN 0x0100
  250. #define TP100_SPDWN_EN 0x0020
  251. #define TP500_SPDWN_EN 0x0010
  252. #define TP1000_SPDWN_EN 0x0008
  253. #define EEE_SPDWN_EN 0x0001
  254. /* PLA_GPHY_INTR_IMR */
  255. #define GPHY_STS_MSK 0x0001
  256. #define SPEED_DOWN_MSK 0x0002
  257. #define SPDWN_RXDV_MSK 0x0004
  258. #define SPDWN_LINKCHG_MSK 0x0008
  259. /* PLA_PHYAR */
  260. #define PHYAR_FLAG 0x80000000
  261. /* PLA_EEE_CR */
  262. #define EEE_RX_EN 0x0001
  263. #define EEE_TX_EN 0x0002
  264. /* PLA_BOOT_CTRL */
  265. #define AUTOLOAD_DONE 0x0002
  266. /* USB_USB2PHY */
  267. #define USB2PHY_SUSPEND 0x0001
  268. #define USB2PHY_L1 0x0002
  269. /* USB_SSPHYLINK2 */
  270. #define pwd_dn_scale_mask 0x3ffe
  271. #define pwd_dn_scale(x) ((x) << 1)
  272. /* USB_CSR_DUMMY1 */
  273. #define DYNAMIC_BURST 0x0001
  274. /* USB_CSR_DUMMY2 */
  275. #define EP4_FULL_FC 0x0001
  276. /* USB_DEV_STAT */
  277. #define STAT_SPEED_MASK 0x0006
  278. #define STAT_SPEED_HIGH 0x0000
  279. #define STAT_SPEED_FULL 0x0002
  280. /* USB_TX_AGG */
  281. #define TX_AGG_MAX_THRESHOLD 0x03
  282. /* USB_RX_BUF_TH */
  283. #define RX_THR_SUPPER 0x0c350180
  284. #define RX_THR_HIGH 0x7a120180
  285. #define RX_THR_SLOW 0xffff0180
  286. /* USB_TX_DMA */
  287. #define TEST_MODE_DISABLE 0x00000001
  288. #define TX_SIZE_ADJUST1 0x00000100
  289. /* USB_UPS_CTRL */
  290. #define POWER_CUT 0x0100
  291. /* USB_PM_CTRL_STATUS */
  292. #define RESUME_INDICATE 0x0001
  293. /* USB_USB_CTRL */
  294. #define RX_AGG_DISABLE 0x0010
  295. #define RX_ZERO_EN 0x0080
  296. /* USB_U2P3_CTRL */
  297. #define U2P3_ENABLE 0x0001
  298. /* USB_POWER_CUT */
  299. #define PWR_EN 0x0001
  300. #define PHASE2_EN 0x0008
  301. /* USB_MISC_0 */
  302. #define PCUT_STATUS 0x0001
  303. /* USB_RX_EARLY_TIMEOUT */
  304. #define COALESCE_SUPER 85000U
  305. #define COALESCE_HIGH 250000U
  306. #define COALESCE_SLOW 524280U
  307. /* USB_WDT11_CTRL */
  308. #define TIMER11_EN 0x0001
  309. /* USB_LPM_CTRL */
  310. /* bit 4 ~ 5: fifo empty boundary */
  311. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  312. /* bit 2 ~ 3: LMP timer */
  313. #define LPM_TIMER_MASK 0x0c
  314. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  315. #define LPM_TIMER_500US 0x0c /* 500 us */
  316. #define ROK_EXIT_LPM 0x02
  317. /* USB_AFE_CTRL2 */
  318. #define SEN_VAL_MASK 0xf800
  319. #define SEN_VAL_NORMAL 0xa000
  320. #define SEL_RXIDLE 0x0100
  321. /* OCP_ALDPS_CONFIG */
  322. #define ENPWRSAVE 0x8000
  323. #define ENPDNPS 0x0200
  324. #define LINKENA 0x0100
  325. #define DIS_SDSAVE 0x0010
  326. /* OCP_PHY_STATUS */
  327. #define PHY_STAT_MASK 0x0007
  328. #define PHY_STAT_LAN_ON 3
  329. #define PHY_STAT_PWRDN 5
  330. /* OCP_POWER_CFG */
  331. #define EEE_CLKDIV_EN 0x8000
  332. #define EN_ALDPS 0x0004
  333. #define EN_10M_PLLOFF 0x0001
  334. /* OCP_EEE_CONFIG1 */
  335. #define RG_TXLPI_MSK_HFDUP 0x8000
  336. #define RG_MATCLR_EN 0x4000
  337. #define EEE_10_CAP 0x2000
  338. #define EEE_NWAY_EN 0x1000
  339. #define TX_QUIET_EN 0x0200
  340. #define RX_QUIET_EN 0x0100
  341. #define sd_rise_time_mask 0x0070
  342. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  343. #define RG_RXLPI_MSK_HFDUP 0x0008
  344. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  345. /* OCP_EEE_CONFIG2 */
  346. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  347. #define RG_DACQUIET_EN 0x0400
  348. #define RG_LDVQUIET_EN 0x0200
  349. #define RG_CKRSEL 0x0020
  350. #define RG_EEEPRG_EN 0x0010
  351. /* OCP_EEE_CONFIG3 */
  352. #define fast_snr_mask 0xff80
  353. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  354. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  355. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  356. /* OCP_EEE_AR */
  357. /* bit[15:14] function */
  358. #define FUN_ADDR 0x0000
  359. #define FUN_DATA 0x4000
  360. /* bit[4:0] device addr */
  361. /* OCP_EEE_CFG */
  362. #define CTAP_SHORT_EN 0x0040
  363. #define EEE10_EN 0x0010
  364. /* OCP_DOWN_SPEED */
  365. #define EN_10M_BGOFF 0x0080
  366. /* OCP_PHY_STATE */
  367. #define TXDIS_STATE 0x01
  368. #define ABD_STATE 0x02
  369. /* OCP_ADC_CFG */
  370. #define CKADSEL_L 0x0100
  371. #define ADC_EN 0x0080
  372. #define EN_EMI_L 0x0040
  373. /* SRAM_LPF_CFG */
  374. #define LPF_AUTO_TUNE 0x8000
  375. /* SRAM_10M_AMP1 */
  376. #define GDAC_IB_UPALL 0x0008
  377. /* SRAM_10M_AMP2 */
  378. #define AMP_DN 0x0200
  379. /* SRAM_IMPEDANCE */
  380. #define RX_DRIVING_MASK 0x6000
  381. enum rtl_register_content {
  382. _1000bps = 0x10,
  383. _100bps = 0x08,
  384. _10bps = 0x04,
  385. LINK_STATUS = 0x02,
  386. FULL_DUP = 0x01,
  387. };
  388. #define RTL8152_MAX_TX 4
  389. #define RTL8152_MAX_RX 10
  390. #define INTBUFSIZE 2
  391. #define CRC_SIZE 4
  392. #define TX_ALIGN 4
  393. #define RX_ALIGN 8
  394. #define INTR_LINK 0x0004
  395. #define RTL8152_REQT_READ 0xc0
  396. #define RTL8152_REQT_WRITE 0x40
  397. #define RTL8152_REQ_GET_REGS 0x05
  398. #define RTL8152_REQ_SET_REGS 0x05
  399. #define BYTE_EN_DWORD 0xff
  400. #define BYTE_EN_WORD 0x33
  401. #define BYTE_EN_BYTE 0x11
  402. #define BYTE_EN_SIX_BYTES 0x3f
  403. #define BYTE_EN_START_MASK 0x0f
  404. #define BYTE_EN_END_MASK 0xf0
  405. #define RTL8153_MAX_PACKET 9216 /* 9K */
  406. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  407. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  408. #define RTL8153_RMS RTL8153_MAX_PACKET
  409. #define RTL8152_TX_TIMEOUT (5 * HZ)
  410. #define RTL8152_NAPI_WEIGHT 64
  411. /* rtl8152 flags */
  412. enum rtl8152_flags {
  413. RTL8152_UNPLUG = 0,
  414. RTL8152_SET_RX_MODE,
  415. WORK_ENABLE,
  416. RTL8152_LINK_CHG,
  417. SELECTIVE_SUSPEND,
  418. PHY_RESET,
  419. SCHEDULE_NAPI,
  420. };
  421. /* Define these values to match your device */
  422. #define VENDOR_ID_REALTEK 0x0bda
  423. #define VENDOR_ID_SAMSUNG 0x04e8
  424. #define VENDOR_ID_LENOVO 0x17ef
  425. #define VENDOR_ID_NVIDIA 0x0955
  426. #define MCU_TYPE_PLA 0x0100
  427. #define MCU_TYPE_USB 0x0000
  428. struct tally_counter {
  429. __le64 tx_packets;
  430. __le64 rx_packets;
  431. __le64 tx_errors;
  432. __le32 rx_errors;
  433. __le16 rx_missed;
  434. __le16 align_errors;
  435. __le32 tx_one_collision;
  436. __le32 tx_multi_collision;
  437. __le64 rx_unicast;
  438. __le64 rx_broadcast;
  439. __le32 rx_multicast;
  440. __le16 tx_aborted;
  441. __le16 tx_underrun;
  442. };
  443. struct rx_desc {
  444. __le32 opts1;
  445. #define RX_LEN_MASK 0x7fff
  446. __le32 opts2;
  447. #define RD_UDP_CS BIT(23)
  448. #define RD_TCP_CS BIT(22)
  449. #define RD_IPV6_CS BIT(20)
  450. #define RD_IPV4_CS BIT(19)
  451. __le32 opts3;
  452. #define IPF BIT(23) /* IP checksum fail */
  453. #define UDPF BIT(22) /* UDP checksum fail */
  454. #define TCPF BIT(21) /* TCP checksum fail */
  455. #define RX_VLAN_TAG BIT(16)
  456. __le32 opts4;
  457. __le32 opts5;
  458. __le32 opts6;
  459. };
  460. struct tx_desc {
  461. __le32 opts1;
  462. #define TX_FS BIT(31) /* First segment of a packet */
  463. #define TX_LS BIT(30) /* Final segment of a packet */
  464. #define GTSENDV4 BIT(28)
  465. #define GTSENDV6 BIT(27)
  466. #define GTTCPHO_SHIFT 18
  467. #define GTTCPHO_MAX 0x7fU
  468. #define TX_LEN_MAX 0x3ffffU
  469. __le32 opts2;
  470. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  471. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  472. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  473. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  474. #define MSS_SHIFT 17
  475. #define MSS_MAX 0x7ffU
  476. #define TCPHO_SHIFT 17
  477. #define TCPHO_MAX 0x7ffU
  478. #define TX_VLAN_TAG BIT(16)
  479. };
  480. struct r8152;
  481. struct rx_agg {
  482. struct list_head list;
  483. struct urb *urb;
  484. struct r8152 *context;
  485. void *buffer;
  486. void *head;
  487. };
  488. struct tx_agg {
  489. struct list_head list;
  490. struct urb *urb;
  491. struct r8152 *context;
  492. void *buffer;
  493. void *head;
  494. u32 skb_num;
  495. u32 skb_len;
  496. };
  497. struct r8152 {
  498. unsigned long flags;
  499. struct usb_device *udev;
  500. struct napi_struct napi;
  501. struct usb_interface *intf;
  502. struct net_device *netdev;
  503. struct urb *intr_urb;
  504. struct tx_agg tx_info[RTL8152_MAX_TX];
  505. struct rx_agg rx_info[RTL8152_MAX_RX];
  506. struct list_head rx_done, tx_free;
  507. struct sk_buff_head tx_queue, rx_queue;
  508. spinlock_t rx_lock, tx_lock;
  509. struct delayed_work schedule;
  510. struct mii_if_info mii;
  511. struct mutex control; /* use for hw setting */
  512. #ifdef CONFIG_PM_SLEEP
  513. struct notifier_block pm_notifier;
  514. #endif
  515. struct rtl_ops {
  516. void (*init)(struct r8152 *);
  517. int (*enable)(struct r8152 *);
  518. void (*disable)(struct r8152 *);
  519. void (*up)(struct r8152 *);
  520. void (*down)(struct r8152 *);
  521. void (*unload)(struct r8152 *);
  522. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  523. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  524. bool (*in_nway)(struct r8152 *);
  525. } rtl_ops;
  526. int intr_interval;
  527. u32 saved_wolopts;
  528. u32 msg_enable;
  529. u32 tx_qlen;
  530. u32 coalesce;
  531. u16 ocp_base;
  532. u8 *intr_buff;
  533. u8 version;
  534. };
  535. enum rtl_version {
  536. RTL_VER_UNKNOWN = 0,
  537. RTL_VER_01,
  538. RTL_VER_02,
  539. RTL_VER_03,
  540. RTL_VER_04,
  541. RTL_VER_05,
  542. RTL_VER_06,
  543. RTL_VER_MAX
  544. };
  545. enum tx_csum_stat {
  546. TX_CSUM_SUCCESS = 0,
  547. TX_CSUM_TSO,
  548. TX_CSUM_NONE
  549. };
  550. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  551. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  552. */
  553. static const int multicast_filter_limit = 32;
  554. static unsigned int agg_buf_sz = 16384;
  555. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  556. VLAN_ETH_HLEN - VLAN_HLEN)
  557. static
  558. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  559. {
  560. int ret;
  561. void *tmp;
  562. tmp = kmalloc(size, GFP_KERNEL);
  563. if (!tmp)
  564. return -ENOMEM;
  565. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  566. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  567. value, index, tmp, size, 500);
  568. memcpy(data, tmp, size);
  569. kfree(tmp);
  570. return ret;
  571. }
  572. static
  573. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  574. {
  575. int ret;
  576. void *tmp;
  577. tmp = kmemdup(data, size, GFP_KERNEL);
  578. if (!tmp)
  579. return -ENOMEM;
  580. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  581. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  582. value, index, tmp, size, 500);
  583. kfree(tmp);
  584. return ret;
  585. }
  586. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  587. void *data, u16 type)
  588. {
  589. u16 limit = 64;
  590. int ret = 0;
  591. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  592. return -ENODEV;
  593. /* both size and indix must be 4 bytes align */
  594. if ((size & 3) || !size || (index & 3) || !data)
  595. return -EPERM;
  596. if ((u32)index + (u32)size > 0xffff)
  597. return -EPERM;
  598. while (size) {
  599. if (size > limit) {
  600. ret = get_registers(tp, index, type, limit, data);
  601. if (ret < 0)
  602. break;
  603. index += limit;
  604. data += limit;
  605. size -= limit;
  606. } else {
  607. ret = get_registers(tp, index, type, size, data);
  608. if (ret < 0)
  609. break;
  610. index += size;
  611. data += size;
  612. size = 0;
  613. break;
  614. }
  615. }
  616. if (ret == -ENODEV)
  617. set_bit(RTL8152_UNPLUG, &tp->flags);
  618. return ret;
  619. }
  620. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  621. u16 size, void *data, u16 type)
  622. {
  623. int ret;
  624. u16 byteen_start, byteen_end, byen;
  625. u16 limit = 512;
  626. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  627. return -ENODEV;
  628. /* both size and indix must be 4 bytes align */
  629. if ((size & 3) || !size || (index & 3) || !data)
  630. return -EPERM;
  631. if ((u32)index + (u32)size > 0xffff)
  632. return -EPERM;
  633. byteen_start = byteen & BYTE_EN_START_MASK;
  634. byteen_end = byteen & BYTE_EN_END_MASK;
  635. byen = byteen_start | (byteen_start << 4);
  636. ret = set_registers(tp, index, type | byen, 4, data);
  637. if (ret < 0)
  638. goto error1;
  639. index += 4;
  640. data += 4;
  641. size -= 4;
  642. if (size) {
  643. size -= 4;
  644. while (size) {
  645. if (size > limit) {
  646. ret = set_registers(tp, index,
  647. type | BYTE_EN_DWORD,
  648. limit, data);
  649. if (ret < 0)
  650. goto error1;
  651. index += limit;
  652. data += limit;
  653. size -= limit;
  654. } else {
  655. ret = set_registers(tp, index,
  656. type | BYTE_EN_DWORD,
  657. size, data);
  658. if (ret < 0)
  659. goto error1;
  660. index += size;
  661. data += size;
  662. size = 0;
  663. break;
  664. }
  665. }
  666. byen = byteen_end | (byteen_end >> 4);
  667. ret = set_registers(tp, index, type | byen, 4, data);
  668. if (ret < 0)
  669. goto error1;
  670. }
  671. error1:
  672. if (ret == -ENODEV)
  673. set_bit(RTL8152_UNPLUG, &tp->flags);
  674. return ret;
  675. }
  676. static inline
  677. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  678. {
  679. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  680. }
  681. static inline
  682. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  683. {
  684. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  685. }
  686. static inline
  687. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  688. {
  689. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  690. }
  691. static inline
  692. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  693. {
  694. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  695. }
  696. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  697. {
  698. __le32 data;
  699. generic_ocp_read(tp, index, sizeof(data), &data, type);
  700. return __le32_to_cpu(data);
  701. }
  702. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  703. {
  704. __le32 tmp = __cpu_to_le32(data);
  705. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  706. }
  707. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  708. {
  709. u32 data;
  710. __le32 tmp;
  711. u8 shift = index & 2;
  712. index &= ~3;
  713. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  714. data = __le32_to_cpu(tmp);
  715. data >>= (shift * 8);
  716. data &= 0xffff;
  717. return (u16)data;
  718. }
  719. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  720. {
  721. u32 mask = 0xffff;
  722. __le32 tmp;
  723. u16 byen = BYTE_EN_WORD;
  724. u8 shift = index & 2;
  725. data &= mask;
  726. if (index & 2) {
  727. byen <<= shift;
  728. mask <<= (shift * 8);
  729. data <<= (shift * 8);
  730. index &= ~3;
  731. }
  732. tmp = __cpu_to_le32(data);
  733. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  734. }
  735. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  736. {
  737. u32 data;
  738. __le32 tmp;
  739. u8 shift = index & 3;
  740. index &= ~3;
  741. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  742. data = __le32_to_cpu(tmp);
  743. data >>= (shift * 8);
  744. data &= 0xff;
  745. return (u8)data;
  746. }
  747. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  748. {
  749. u32 mask = 0xff;
  750. __le32 tmp;
  751. u16 byen = BYTE_EN_BYTE;
  752. u8 shift = index & 3;
  753. data &= mask;
  754. if (index & 3) {
  755. byen <<= shift;
  756. mask <<= (shift * 8);
  757. data <<= (shift * 8);
  758. index &= ~3;
  759. }
  760. tmp = __cpu_to_le32(data);
  761. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  762. }
  763. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  764. {
  765. u16 ocp_base, ocp_index;
  766. ocp_base = addr & 0xf000;
  767. if (ocp_base != tp->ocp_base) {
  768. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  769. tp->ocp_base = ocp_base;
  770. }
  771. ocp_index = (addr & 0x0fff) | 0xb000;
  772. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  773. }
  774. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  775. {
  776. u16 ocp_base, ocp_index;
  777. ocp_base = addr & 0xf000;
  778. if (ocp_base != tp->ocp_base) {
  779. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  780. tp->ocp_base = ocp_base;
  781. }
  782. ocp_index = (addr & 0x0fff) | 0xb000;
  783. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  784. }
  785. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  786. {
  787. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  788. }
  789. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  790. {
  791. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  792. }
  793. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  794. {
  795. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  796. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  797. }
  798. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  799. {
  800. struct r8152 *tp = netdev_priv(netdev);
  801. int ret;
  802. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  803. return -ENODEV;
  804. if (phy_id != R8152_PHY_ID)
  805. return -EINVAL;
  806. ret = r8152_mdio_read(tp, reg);
  807. return ret;
  808. }
  809. static
  810. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  811. {
  812. struct r8152 *tp = netdev_priv(netdev);
  813. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  814. return;
  815. if (phy_id != R8152_PHY_ID)
  816. return;
  817. r8152_mdio_write(tp, reg, val);
  818. }
  819. static int
  820. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  821. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  822. {
  823. struct r8152 *tp = netdev_priv(netdev);
  824. struct sockaddr *addr = p;
  825. int ret = -EADDRNOTAVAIL;
  826. if (!is_valid_ether_addr(addr->sa_data))
  827. goto out1;
  828. ret = usb_autopm_get_interface(tp->intf);
  829. if (ret < 0)
  830. goto out1;
  831. mutex_lock(&tp->control);
  832. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  833. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  834. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  835. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  836. mutex_unlock(&tp->control);
  837. usb_autopm_put_interface(tp->intf);
  838. out1:
  839. return ret;
  840. }
  841. static int set_ethernet_addr(struct r8152 *tp)
  842. {
  843. struct net_device *dev = tp->netdev;
  844. struct sockaddr sa;
  845. int ret;
  846. if (tp->version == RTL_VER_01)
  847. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  848. else
  849. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  850. if (ret < 0) {
  851. netif_err(tp, probe, dev, "Get ether addr fail\n");
  852. } else if (!is_valid_ether_addr(sa.sa_data)) {
  853. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  854. sa.sa_data);
  855. eth_hw_addr_random(dev);
  856. ether_addr_copy(sa.sa_data, dev->dev_addr);
  857. ret = rtl8152_set_mac_address(dev, &sa);
  858. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  859. sa.sa_data);
  860. } else {
  861. if (tp->version == RTL_VER_01)
  862. ether_addr_copy(dev->dev_addr, sa.sa_data);
  863. else
  864. ret = rtl8152_set_mac_address(dev, &sa);
  865. }
  866. return ret;
  867. }
  868. static void read_bulk_callback(struct urb *urb)
  869. {
  870. struct net_device *netdev;
  871. int status = urb->status;
  872. struct rx_agg *agg;
  873. struct r8152 *tp;
  874. agg = urb->context;
  875. if (!agg)
  876. return;
  877. tp = agg->context;
  878. if (!tp)
  879. return;
  880. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  881. return;
  882. if (!test_bit(WORK_ENABLE, &tp->flags))
  883. return;
  884. netdev = tp->netdev;
  885. /* When link down, the driver would cancel all bulks. */
  886. /* This avoid the re-submitting bulk */
  887. if (!netif_carrier_ok(netdev))
  888. return;
  889. usb_mark_last_busy(tp->udev);
  890. switch (status) {
  891. case 0:
  892. if (urb->actual_length < ETH_ZLEN)
  893. break;
  894. spin_lock(&tp->rx_lock);
  895. list_add_tail(&agg->list, &tp->rx_done);
  896. spin_unlock(&tp->rx_lock);
  897. napi_schedule(&tp->napi);
  898. return;
  899. case -ESHUTDOWN:
  900. set_bit(RTL8152_UNPLUG, &tp->flags);
  901. netif_device_detach(tp->netdev);
  902. return;
  903. case -ENOENT:
  904. return; /* the urb is in unlink state */
  905. case -ETIME:
  906. if (net_ratelimit())
  907. netdev_warn(netdev, "maybe reset is needed?\n");
  908. break;
  909. default:
  910. if (net_ratelimit())
  911. netdev_warn(netdev, "Rx status %d\n", status);
  912. break;
  913. }
  914. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  915. }
  916. static void write_bulk_callback(struct urb *urb)
  917. {
  918. struct net_device_stats *stats;
  919. struct net_device *netdev;
  920. struct tx_agg *agg;
  921. struct r8152 *tp;
  922. int status = urb->status;
  923. agg = urb->context;
  924. if (!agg)
  925. return;
  926. tp = agg->context;
  927. if (!tp)
  928. return;
  929. netdev = tp->netdev;
  930. stats = &netdev->stats;
  931. if (status) {
  932. if (net_ratelimit())
  933. netdev_warn(netdev, "Tx status %d\n", status);
  934. stats->tx_errors += agg->skb_num;
  935. } else {
  936. stats->tx_packets += agg->skb_num;
  937. stats->tx_bytes += agg->skb_len;
  938. }
  939. spin_lock(&tp->tx_lock);
  940. list_add_tail(&agg->list, &tp->tx_free);
  941. spin_unlock(&tp->tx_lock);
  942. usb_autopm_put_interface_async(tp->intf);
  943. if (!netif_carrier_ok(netdev))
  944. return;
  945. if (!test_bit(WORK_ENABLE, &tp->flags))
  946. return;
  947. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  948. return;
  949. if (!skb_queue_empty(&tp->tx_queue))
  950. napi_schedule(&tp->napi);
  951. }
  952. static void intr_callback(struct urb *urb)
  953. {
  954. struct r8152 *tp;
  955. __le16 *d;
  956. int status = urb->status;
  957. int res;
  958. tp = urb->context;
  959. if (!tp)
  960. return;
  961. if (!test_bit(WORK_ENABLE, &tp->flags))
  962. return;
  963. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  964. return;
  965. switch (status) {
  966. case 0: /* success */
  967. break;
  968. case -ECONNRESET: /* unlink */
  969. case -ESHUTDOWN:
  970. netif_device_detach(tp->netdev);
  971. case -ENOENT:
  972. case -EPROTO:
  973. netif_info(tp, intr, tp->netdev,
  974. "Stop submitting intr, status %d\n", status);
  975. return;
  976. case -EOVERFLOW:
  977. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  978. goto resubmit;
  979. /* -EPIPE: should clear the halt */
  980. default:
  981. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  982. goto resubmit;
  983. }
  984. d = urb->transfer_buffer;
  985. if (INTR_LINK & __le16_to_cpu(d[0])) {
  986. if (!netif_carrier_ok(tp->netdev)) {
  987. set_bit(RTL8152_LINK_CHG, &tp->flags);
  988. schedule_delayed_work(&tp->schedule, 0);
  989. }
  990. } else {
  991. if (netif_carrier_ok(tp->netdev)) {
  992. set_bit(RTL8152_LINK_CHG, &tp->flags);
  993. schedule_delayed_work(&tp->schedule, 0);
  994. }
  995. }
  996. resubmit:
  997. res = usb_submit_urb(urb, GFP_ATOMIC);
  998. if (res == -ENODEV) {
  999. set_bit(RTL8152_UNPLUG, &tp->flags);
  1000. netif_device_detach(tp->netdev);
  1001. } else if (res) {
  1002. netif_err(tp, intr, tp->netdev,
  1003. "can't resubmit intr, status %d\n", res);
  1004. }
  1005. }
  1006. static inline void *rx_agg_align(void *data)
  1007. {
  1008. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1009. }
  1010. static inline void *tx_agg_align(void *data)
  1011. {
  1012. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1013. }
  1014. static void free_all_mem(struct r8152 *tp)
  1015. {
  1016. int i;
  1017. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1018. usb_free_urb(tp->rx_info[i].urb);
  1019. tp->rx_info[i].urb = NULL;
  1020. kfree(tp->rx_info[i].buffer);
  1021. tp->rx_info[i].buffer = NULL;
  1022. tp->rx_info[i].head = NULL;
  1023. }
  1024. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1025. usb_free_urb(tp->tx_info[i].urb);
  1026. tp->tx_info[i].urb = NULL;
  1027. kfree(tp->tx_info[i].buffer);
  1028. tp->tx_info[i].buffer = NULL;
  1029. tp->tx_info[i].head = NULL;
  1030. }
  1031. usb_free_urb(tp->intr_urb);
  1032. tp->intr_urb = NULL;
  1033. kfree(tp->intr_buff);
  1034. tp->intr_buff = NULL;
  1035. }
  1036. static int alloc_all_mem(struct r8152 *tp)
  1037. {
  1038. struct net_device *netdev = tp->netdev;
  1039. struct usb_interface *intf = tp->intf;
  1040. struct usb_host_interface *alt = intf->cur_altsetting;
  1041. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1042. struct urb *urb;
  1043. int node, i;
  1044. u8 *buf;
  1045. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1046. spin_lock_init(&tp->rx_lock);
  1047. spin_lock_init(&tp->tx_lock);
  1048. INIT_LIST_HEAD(&tp->tx_free);
  1049. skb_queue_head_init(&tp->tx_queue);
  1050. skb_queue_head_init(&tp->rx_queue);
  1051. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1052. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1053. if (!buf)
  1054. goto err1;
  1055. if (buf != rx_agg_align(buf)) {
  1056. kfree(buf);
  1057. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1058. node);
  1059. if (!buf)
  1060. goto err1;
  1061. }
  1062. urb = usb_alloc_urb(0, GFP_KERNEL);
  1063. if (!urb) {
  1064. kfree(buf);
  1065. goto err1;
  1066. }
  1067. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1068. tp->rx_info[i].context = tp;
  1069. tp->rx_info[i].urb = urb;
  1070. tp->rx_info[i].buffer = buf;
  1071. tp->rx_info[i].head = rx_agg_align(buf);
  1072. }
  1073. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1074. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1075. if (!buf)
  1076. goto err1;
  1077. if (buf != tx_agg_align(buf)) {
  1078. kfree(buf);
  1079. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1080. node);
  1081. if (!buf)
  1082. goto err1;
  1083. }
  1084. urb = usb_alloc_urb(0, GFP_KERNEL);
  1085. if (!urb) {
  1086. kfree(buf);
  1087. goto err1;
  1088. }
  1089. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1090. tp->tx_info[i].context = tp;
  1091. tp->tx_info[i].urb = urb;
  1092. tp->tx_info[i].buffer = buf;
  1093. tp->tx_info[i].head = tx_agg_align(buf);
  1094. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1095. }
  1096. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1097. if (!tp->intr_urb)
  1098. goto err1;
  1099. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1100. if (!tp->intr_buff)
  1101. goto err1;
  1102. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1103. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1104. tp->intr_buff, INTBUFSIZE, intr_callback,
  1105. tp, tp->intr_interval);
  1106. return 0;
  1107. err1:
  1108. free_all_mem(tp);
  1109. return -ENOMEM;
  1110. }
  1111. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1112. {
  1113. struct tx_agg *agg = NULL;
  1114. unsigned long flags;
  1115. if (list_empty(&tp->tx_free))
  1116. return NULL;
  1117. spin_lock_irqsave(&tp->tx_lock, flags);
  1118. if (!list_empty(&tp->tx_free)) {
  1119. struct list_head *cursor;
  1120. cursor = tp->tx_free.next;
  1121. list_del_init(cursor);
  1122. agg = list_entry(cursor, struct tx_agg, list);
  1123. }
  1124. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1125. return agg;
  1126. }
  1127. /* r8152_csum_workaround()
  1128. * The hw limites the value the transport offset. When the offset is out of the
  1129. * range, calculate the checksum by sw.
  1130. */
  1131. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1132. struct sk_buff_head *list)
  1133. {
  1134. if (skb_shinfo(skb)->gso_size) {
  1135. netdev_features_t features = tp->netdev->features;
  1136. struct sk_buff_head seg_list;
  1137. struct sk_buff *segs, *nskb;
  1138. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1139. segs = skb_gso_segment(skb, features);
  1140. if (IS_ERR(segs) || !segs)
  1141. goto drop;
  1142. __skb_queue_head_init(&seg_list);
  1143. do {
  1144. nskb = segs;
  1145. segs = segs->next;
  1146. nskb->next = NULL;
  1147. __skb_queue_tail(&seg_list, nskb);
  1148. } while (segs);
  1149. skb_queue_splice(&seg_list, list);
  1150. dev_kfree_skb(skb);
  1151. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1152. if (skb_checksum_help(skb) < 0)
  1153. goto drop;
  1154. __skb_queue_head(list, skb);
  1155. } else {
  1156. struct net_device_stats *stats;
  1157. drop:
  1158. stats = &tp->netdev->stats;
  1159. stats->tx_dropped++;
  1160. dev_kfree_skb(skb);
  1161. }
  1162. }
  1163. /* msdn_giant_send_check()
  1164. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1165. * packet length for IPv6 TCP large packets.
  1166. */
  1167. static int msdn_giant_send_check(struct sk_buff *skb)
  1168. {
  1169. const struct ipv6hdr *ipv6h;
  1170. struct tcphdr *th;
  1171. int ret;
  1172. ret = skb_cow_head(skb, 0);
  1173. if (ret)
  1174. return ret;
  1175. ipv6h = ipv6_hdr(skb);
  1176. th = tcp_hdr(skb);
  1177. th->check = 0;
  1178. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1179. return ret;
  1180. }
  1181. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1182. {
  1183. if (skb_vlan_tag_present(skb)) {
  1184. u32 opts2;
  1185. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1186. desc->opts2 |= cpu_to_le32(opts2);
  1187. }
  1188. }
  1189. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1190. {
  1191. u32 opts2 = le32_to_cpu(desc->opts2);
  1192. if (opts2 & RX_VLAN_TAG)
  1193. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1194. swab16(opts2 & 0xffff));
  1195. }
  1196. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1197. struct sk_buff *skb, u32 len, u32 transport_offset)
  1198. {
  1199. u32 mss = skb_shinfo(skb)->gso_size;
  1200. u32 opts1, opts2 = 0;
  1201. int ret = TX_CSUM_SUCCESS;
  1202. WARN_ON_ONCE(len > TX_LEN_MAX);
  1203. opts1 = len | TX_FS | TX_LS;
  1204. if (mss) {
  1205. if (transport_offset > GTTCPHO_MAX) {
  1206. netif_warn(tp, tx_err, tp->netdev,
  1207. "Invalid transport offset 0x%x for TSO\n",
  1208. transport_offset);
  1209. ret = TX_CSUM_TSO;
  1210. goto unavailable;
  1211. }
  1212. switch (vlan_get_protocol(skb)) {
  1213. case htons(ETH_P_IP):
  1214. opts1 |= GTSENDV4;
  1215. break;
  1216. case htons(ETH_P_IPV6):
  1217. if (msdn_giant_send_check(skb)) {
  1218. ret = TX_CSUM_TSO;
  1219. goto unavailable;
  1220. }
  1221. opts1 |= GTSENDV6;
  1222. break;
  1223. default:
  1224. WARN_ON_ONCE(1);
  1225. break;
  1226. }
  1227. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1228. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1229. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1230. u8 ip_protocol;
  1231. if (transport_offset > TCPHO_MAX) {
  1232. netif_warn(tp, tx_err, tp->netdev,
  1233. "Invalid transport offset 0x%x\n",
  1234. transport_offset);
  1235. ret = TX_CSUM_NONE;
  1236. goto unavailable;
  1237. }
  1238. switch (vlan_get_protocol(skb)) {
  1239. case htons(ETH_P_IP):
  1240. opts2 |= IPV4_CS;
  1241. ip_protocol = ip_hdr(skb)->protocol;
  1242. break;
  1243. case htons(ETH_P_IPV6):
  1244. opts2 |= IPV6_CS;
  1245. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1246. break;
  1247. default:
  1248. ip_protocol = IPPROTO_RAW;
  1249. break;
  1250. }
  1251. if (ip_protocol == IPPROTO_TCP)
  1252. opts2 |= TCP_CS;
  1253. else if (ip_protocol == IPPROTO_UDP)
  1254. opts2 |= UDP_CS;
  1255. else
  1256. WARN_ON_ONCE(1);
  1257. opts2 |= transport_offset << TCPHO_SHIFT;
  1258. }
  1259. desc->opts2 = cpu_to_le32(opts2);
  1260. desc->opts1 = cpu_to_le32(opts1);
  1261. unavailable:
  1262. return ret;
  1263. }
  1264. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1265. {
  1266. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1267. int remain, ret;
  1268. u8 *tx_data;
  1269. __skb_queue_head_init(&skb_head);
  1270. spin_lock(&tx_queue->lock);
  1271. skb_queue_splice_init(tx_queue, &skb_head);
  1272. spin_unlock(&tx_queue->lock);
  1273. tx_data = agg->head;
  1274. agg->skb_num = 0;
  1275. agg->skb_len = 0;
  1276. remain = agg_buf_sz;
  1277. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1278. struct tx_desc *tx_desc;
  1279. struct sk_buff *skb;
  1280. unsigned int len;
  1281. u32 offset;
  1282. skb = __skb_dequeue(&skb_head);
  1283. if (!skb)
  1284. break;
  1285. len = skb->len + sizeof(*tx_desc);
  1286. if (len > remain) {
  1287. __skb_queue_head(&skb_head, skb);
  1288. break;
  1289. }
  1290. tx_data = tx_agg_align(tx_data);
  1291. tx_desc = (struct tx_desc *)tx_data;
  1292. offset = (u32)skb_transport_offset(skb);
  1293. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1294. r8152_csum_workaround(tp, skb, &skb_head);
  1295. continue;
  1296. }
  1297. rtl_tx_vlan_tag(tx_desc, skb);
  1298. tx_data += sizeof(*tx_desc);
  1299. len = skb->len;
  1300. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1301. struct net_device_stats *stats = &tp->netdev->stats;
  1302. stats->tx_dropped++;
  1303. dev_kfree_skb_any(skb);
  1304. tx_data -= sizeof(*tx_desc);
  1305. continue;
  1306. }
  1307. tx_data += len;
  1308. agg->skb_len += len;
  1309. agg->skb_num++;
  1310. dev_kfree_skb_any(skb);
  1311. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1312. }
  1313. if (!skb_queue_empty(&skb_head)) {
  1314. spin_lock(&tx_queue->lock);
  1315. skb_queue_splice(&skb_head, tx_queue);
  1316. spin_unlock(&tx_queue->lock);
  1317. }
  1318. netif_tx_lock(tp->netdev);
  1319. if (netif_queue_stopped(tp->netdev) &&
  1320. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1321. netif_wake_queue(tp->netdev);
  1322. netif_tx_unlock(tp->netdev);
  1323. ret = usb_autopm_get_interface_async(tp->intf);
  1324. if (ret < 0)
  1325. goto out_tx_fill;
  1326. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1327. agg->head, (int)(tx_data - (u8 *)agg->head),
  1328. (usb_complete_t)write_bulk_callback, agg);
  1329. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1330. if (ret < 0)
  1331. usb_autopm_put_interface_async(tp->intf);
  1332. out_tx_fill:
  1333. return ret;
  1334. }
  1335. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1336. {
  1337. u8 checksum = CHECKSUM_NONE;
  1338. u32 opts2, opts3;
  1339. if (tp->version == RTL_VER_01)
  1340. goto return_result;
  1341. opts2 = le32_to_cpu(rx_desc->opts2);
  1342. opts3 = le32_to_cpu(rx_desc->opts3);
  1343. if (opts2 & RD_IPV4_CS) {
  1344. if (opts3 & IPF)
  1345. checksum = CHECKSUM_NONE;
  1346. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1347. checksum = CHECKSUM_NONE;
  1348. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1349. checksum = CHECKSUM_NONE;
  1350. else
  1351. checksum = CHECKSUM_UNNECESSARY;
  1352. } else if (RD_IPV6_CS) {
  1353. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1354. checksum = CHECKSUM_UNNECESSARY;
  1355. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1356. checksum = CHECKSUM_UNNECESSARY;
  1357. }
  1358. return_result:
  1359. return checksum;
  1360. }
  1361. static int rx_bottom(struct r8152 *tp, int budget)
  1362. {
  1363. unsigned long flags;
  1364. struct list_head *cursor, *next, rx_queue;
  1365. int ret = 0, work_done = 0;
  1366. if (!skb_queue_empty(&tp->rx_queue)) {
  1367. while (work_done < budget) {
  1368. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1369. struct net_device *netdev = tp->netdev;
  1370. struct net_device_stats *stats = &netdev->stats;
  1371. unsigned int pkt_len;
  1372. if (!skb)
  1373. break;
  1374. pkt_len = skb->len;
  1375. napi_gro_receive(&tp->napi, skb);
  1376. work_done++;
  1377. stats->rx_packets++;
  1378. stats->rx_bytes += pkt_len;
  1379. }
  1380. }
  1381. if (list_empty(&tp->rx_done))
  1382. goto out1;
  1383. INIT_LIST_HEAD(&rx_queue);
  1384. spin_lock_irqsave(&tp->rx_lock, flags);
  1385. list_splice_init(&tp->rx_done, &rx_queue);
  1386. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1387. list_for_each_safe(cursor, next, &rx_queue) {
  1388. struct rx_desc *rx_desc;
  1389. struct rx_agg *agg;
  1390. int len_used = 0;
  1391. struct urb *urb;
  1392. u8 *rx_data;
  1393. list_del_init(cursor);
  1394. agg = list_entry(cursor, struct rx_agg, list);
  1395. urb = agg->urb;
  1396. if (urb->actual_length < ETH_ZLEN)
  1397. goto submit;
  1398. rx_desc = agg->head;
  1399. rx_data = agg->head;
  1400. len_used += sizeof(struct rx_desc);
  1401. while (urb->actual_length > len_used) {
  1402. struct net_device *netdev = tp->netdev;
  1403. struct net_device_stats *stats = &netdev->stats;
  1404. unsigned int pkt_len;
  1405. struct sk_buff *skb;
  1406. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1407. if (pkt_len < ETH_ZLEN)
  1408. break;
  1409. len_used += pkt_len;
  1410. if (urb->actual_length < len_used)
  1411. break;
  1412. pkt_len -= CRC_SIZE;
  1413. rx_data += sizeof(struct rx_desc);
  1414. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1415. if (!skb) {
  1416. stats->rx_dropped++;
  1417. goto find_next_rx;
  1418. }
  1419. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1420. memcpy(skb->data, rx_data, pkt_len);
  1421. skb_put(skb, pkt_len);
  1422. skb->protocol = eth_type_trans(skb, netdev);
  1423. rtl_rx_vlan_tag(rx_desc, skb);
  1424. if (work_done < budget) {
  1425. napi_gro_receive(&tp->napi, skb);
  1426. work_done++;
  1427. stats->rx_packets++;
  1428. stats->rx_bytes += pkt_len;
  1429. } else {
  1430. __skb_queue_tail(&tp->rx_queue, skb);
  1431. }
  1432. find_next_rx:
  1433. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1434. rx_desc = (struct rx_desc *)rx_data;
  1435. len_used = (int)(rx_data - (u8 *)agg->head);
  1436. len_used += sizeof(struct rx_desc);
  1437. }
  1438. submit:
  1439. if (!ret) {
  1440. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1441. } else {
  1442. urb->actual_length = 0;
  1443. list_add_tail(&agg->list, next);
  1444. }
  1445. }
  1446. if (!list_empty(&rx_queue)) {
  1447. spin_lock_irqsave(&tp->rx_lock, flags);
  1448. list_splice_tail(&rx_queue, &tp->rx_done);
  1449. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1450. }
  1451. out1:
  1452. return work_done;
  1453. }
  1454. static void tx_bottom(struct r8152 *tp)
  1455. {
  1456. int res;
  1457. do {
  1458. struct tx_agg *agg;
  1459. if (skb_queue_empty(&tp->tx_queue))
  1460. break;
  1461. agg = r8152_get_tx_agg(tp);
  1462. if (!agg)
  1463. break;
  1464. res = r8152_tx_agg_fill(tp, agg);
  1465. if (res) {
  1466. struct net_device *netdev = tp->netdev;
  1467. if (res == -ENODEV) {
  1468. set_bit(RTL8152_UNPLUG, &tp->flags);
  1469. netif_device_detach(netdev);
  1470. } else {
  1471. struct net_device_stats *stats = &netdev->stats;
  1472. unsigned long flags;
  1473. netif_warn(tp, tx_err, netdev,
  1474. "failed tx_urb %d\n", res);
  1475. stats->tx_dropped += agg->skb_num;
  1476. spin_lock_irqsave(&tp->tx_lock, flags);
  1477. list_add_tail(&agg->list, &tp->tx_free);
  1478. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1479. }
  1480. }
  1481. } while (res == 0);
  1482. }
  1483. static void bottom_half(struct r8152 *tp)
  1484. {
  1485. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1486. return;
  1487. if (!test_bit(WORK_ENABLE, &tp->flags))
  1488. return;
  1489. /* When link down, the driver would cancel all bulks. */
  1490. /* This avoid the re-submitting bulk */
  1491. if (!netif_carrier_ok(tp->netdev))
  1492. return;
  1493. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1494. tx_bottom(tp);
  1495. }
  1496. static int r8152_poll(struct napi_struct *napi, int budget)
  1497. {
  1498. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1499. int work_done;
  1500. work_done = rx_bottom(tp, budget);
  1501. bottom_half(tp);
  1502. if (work_done < budget) {
  1503. napi_complete(napi);
  1504. if (!list_empty(&tp->rx_done))
  1505. napi_schedule(napi);
  1506. }
  1507. return work_done;
  1508. }
  1509. static
  1510. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1511. {
  1512. int ret;
  1513. /* The rx would be stopped, so skip submitting */
  1514. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1515. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1516. return 0;
  1517. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1518. agg->head, agg_buf_sz,
  1519. (usb_complete_t)read_bulk_callback, agg);
  1520. ret = usb_submit_urb(agg->urb, mem_flags);
  1521. if (ret == -ENODEV) {
  1522. set_bit(RTL8152_UNPLUG, &tp->flags);
  1523. netif_device_detach(tp->netdev);
  1524. } else if (ret) {
  1525. struct urb *urb = agg->urb;
  1526. unsigned long flags;
  1527. urb->actual_length = 0;
  1528. spin_lock_irqsave(&tp->rx_lock, flags);
  1529. list_add_tail(&agg->list, &tp->rx_done);
  1530. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1531. netif_err(tp, rx_err, tp->netdev,
  1532. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1533. napi_schedule(&tp->napi);
  1534. }
  1535. return ret;
  1536. }
  1537. static void rtl_drop_queued_tx(struct r8152 *tp)
  1538. {
  1539. struct net_device_stats *stats = &tp->netdev->stats;
  1540. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1541. struct sk_buff *skb;
  1542. if (skb_queue_empty(tx_queue))
  1543. return;
  1544. __skb_queue_head_init(&skb_head);
  1545. spin_lock_bh(&tx_queue->lock);
  1546. skb_queue_splice_init(tx_queue, &skb_head);
  1547. spin_unlock_bh(&tx_queue->lock);
  1548. while ((skb = __skb_dequeue(&skb_head))) {
  1549. dev_kfree_skb(skb);
  1550. stats->tx_dropped++;
  1551. }
  1552. }
  1553. static void rtl8152_tx_timeout(struct net_device *netdev)
  1554. {
  1555. struct r8152 *tp = netdev_priv(netdev);
  1556. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1557. usb_queue_reset_device(tp->intf);
  1558. }
  1559. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1560. {
  1561. struct r8152 *tp = netdev_priv(netdev);
  1562. if (netif_carrier_ok(netdev)) {
  1563. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1564. schedule_delayed_work(&tp->schedule, 0);
  1565. }
  1566. }
  1567. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1568. {
  1569. struct r8152 *tp = netdev_priv(netdev);
  1570. u32 mc_filter[2]; /* Multicast hash filter */
  1571. __le32 tmp[2];
  1572. u32 ocp_data;
  1573. netif_stop_queue(netdev);
  1574. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1575. ocp_data &= ~RCR_ACPT_ALL;
  1576. ocp_data |= RCR_AB | RCR_APM;
  1577. if (netdev->flags & IFF_PROMISC) {
  1578. /* Unconditionally log net taps. */
  1579. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1580. ocp_data |= RCR_AM | RCR_AAP;
  1581. mc_filter[1] = 0xffffffff;
  1582. mc_filter[0] = 0xffffffff;
  1583. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1584. (netdev->flags & IFF_ALLMULTI)) {
  1585. /* Too many to filter perfectly -- accept all multicasts. */
  1586. ocp_data |= RCR_AM;
  1587. mc_filter[1] = 0xffffffff;
  1588. mc_filter[0] = 0xffffffff;
  1589. } else {
  1590. struct netdev_hw_addr *ha;
  1591. mc_filter[1] = 0;
  1592. mc_filter[0] = 0;
  1593. netdev_for_each_mc_addr(ha, netdev) {
  1594. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1595. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1596. ocp_data |= RCR_AM;
  1597. }
  1598. }
  1599. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1600. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1601. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1602. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1603. netif_wake_queue(netdev);
  1604. }
  1605. static netdev_features_t
  1606. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1607. netdev_features_t features)
  1608. {
  1609. u32 mss = skb_shinfo(skb)->gso_size;
  1610. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1611. int offset = skb_transport_offset(skb);
  1612. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1613. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  1614. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1615. features &= ~NETIF_F_GSO_MASK;
  1616. return features;
  1617. }
  1618. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1619. struct net_device *netdev)
  1620. {
  1621. struct r8152 *tp = netdev_priv(netdev);
  1622. skb_tx_timestamp(skb);
  1623. skb_queue_tail(&tp->tx_queue, skb);
  1624. if (!list_empty(&tp->tx_free)) {
  1625. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1626. set_bit(SCHEDULE_NAPI, &tp->flags);
  1627. schedule_delayed_work(&tp->schedule, 0);
  1628. } else {
  1629. usb_mark_last_busy(tp->udev);
  1630. napi_schedule(&tp->napi);
  1631. }
  1632. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1633. netif_stop_queue(netdev);
  1634. }
  1635. return NETDEV_TX_OK;
  1636. }
  1637. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1638. {
  1639. u32 ocp_data;
  1640. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1641. ocp_data &= ~FMC_FCR_MCU_EN;
  1642. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1643. ocp_data |= FMC_FCR_MCU_EN;
  1644. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1645. }
  1646. static void rtl8152_nic_reset(struct r8152 *tp)
  1647. {
  1648. int i;
  1649. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1650. for (i = 0; i < 1000; i++) {
  1651. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1652. break;
  1653. usleep_range(100, 400);
  1654. }
  1655. }
  1656. static void set_tx_qlen(struct r8152 *tp)
  1657. {
  1658. struct net_device *netdev = tp->netdev;
  1659. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1660. sizeof(struct tx_desc));
  1661. }
  1662. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1663. {
  1664. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1665. }
  1666. static void rtl_set_eee_plus(struct r8152 *tp)
  1667. {
  1668. u32 ocp_data;
  1669. u8 speed;
  1670. speed = rtl8152_get_speed(tp);
  1671. if (speed & _10bps) {
  1672. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1673. ocp_data |= EEEP_CR_EEEP_TX;
  1674. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1675. } else {
  1676. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1677. ocp_data &= ~EEEP_CR_EEEP_TX;
  1678. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1679. }
  1680. }
  1681. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1682. {
  1683. u32 ocp_data;
  1684. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1685. if (enable)
  1686. ocp_data |= RXDY_GATED_EN;
  1687. else
  1688. ocp_data &= ~RXDY_GATED_EN;
  1689. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1690. }
  1691. static int rtl_start_rx(struct r8152 *tp)
  1692. {
  1693. int i, ret = 0;
  1694. INIT_LIST_HEAD(&tp->rx_done);
  1695. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1696. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1697. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1698. if (ret)
  1699. break;
  1700. }
  1701. if (ret && ++i < RTL8152_MAX_RX) {
  1702. struct list_head rx_queue;
  1703. unsigned long flags;
  1704. INIT_LIST_HEAD(&rx_queue);
  1705. do {
  1706. struct rx_agg *agg = &tp->rx_info[i++];
  1707. struct urb *urb = agg->urb;
  1708. urb->actual_length = 0;
  1709. list_add_tail(&agg->list, &rx_queue);
  1710. } while (i < RTL8152_MAX_RX);
  1711. spin_lock_irqsave(&tp->rx_lock, flags);
  1712. list_splice_tail(&rx_queue, &tp->rx_done);
  1713. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1714. }
  1715. return ret;
  1716. }
  1717. static int rtl_stop_rx(struct r8152 *tp)
  1718. {
  1719. int i;
  1720. for (i = 0; i < RTL8152_MAX_RX; i++)
  1721. usb_kill_urb(tp->rx_info[i].urb);
  1722. while (!skb_queue_empty(&tp->rx_queue))
  1723. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1724. return 0;
  1725. }
  1726. static int rtl_enable(struct r8152 *tp)
  1727. {
  1728. u32 ocp_data;
  1729. r8152b_reset_packet_filter(tp);
  1730. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1731. ocp_data |= CR_RE | CR_TE;
  1732. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1733. rxdy_gated_en(tp, false);
  1734. return 0;
  1735. }
  1736. static int rtl8152_enable(struct r8152 *tp)
  1737. {
  1738. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1739. return -ENODEV;
  1740. set_tx_qlen(tp);
  1741. rtl_set_eee_plus(tp);
  1742. return rtl_enable(tp);
  1743. }
  1744. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1745. {
  1746. u32 ocp_data = tp->coalesce / 8;
  1747. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1748. }
  1749. static void r8153_set_rx_early_size(struct r8152 *tp)
  1750. {
  1751. u32 mtu = tp->netdev->mtu;
  1752. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1753. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1754. }
  1755. static int rtl8153_enable(struct r8152 *tp)
  1756. {
  1757. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1758. return -ENODEV;
  1759. usb_disable_lpm(tp->udev);
  1760. set_tx_qlen(tp);
  1761. rtl_set_eee_plus(tp);
  1762. r8153_set_rx_early_timeout(tp);
  1763. r8153_set_rx_early_size(tp);
  1764. return rtl_enable(tp);
  1765. }
  1766. static void rtl_disable(struct r8152 *tp)
  1767. {
  1768. u32 ocp_data;
  1769. int i;
  1770. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1771. rtl_drop_queued_tx(tp);
  1772. return;
  1773. }
  1774. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1775. ocp_data &= ~RCR_ACPT_ALL;
  1776. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1777. rtl_drop_queued_tx(tp);
  1778. for (i = 0; i < RTL8152_MAX_TX; i++)
  1779. usb_kill_urb(tp->tx_info[i].urb);
  1780. rxdy_gated_en(tp, true);
  1781. for (i = 0; i < 1000; i++) {
  1782. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1783. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1784. break;
  1785. usleep_range(1000, 2000);
  1786. }
  1787. for (i = 0; i < 1000; i++) {
  1788. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1789. break;
  1790. usleep_range(1000, 2000);
  1791. }
  1792. rtl_stop_rx(tp);
  1793. rtl8152_nic_reset(tp);
  1794. }
  1795. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1796. {
  1797. u32 ocp_data;
  1798. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1799. if (enable)
  1800. ocp_data |= POWER_CUT;
  1801. else
  1802. ocp_data &= ~POWER_CUT;
  1803. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1804. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1805. ocp_data &= ~RESUME_INDICATE;
  1806. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1807. }
  1808. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1809. {
  1810. u32 ocp_data;
  1811. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1812. if (enable)
  1813. ocp_data |= CPCR_RX_VLAN;
  1814. else
  1815. ocp_data &= ~CPCR_RX_VLAN;
  1816. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1817. }
  1818. static int rtl8152_set_features(struct net_device *dev,
  1819. netdev_features_t features)
  1820. {
  1821. netdev_features_t changed = features ^ dev->features;
  1822. struct r8152 *tp = netdev_priv(dev);
  1823. int ret;
  1824. ret = usb_autopm_get_interface(tp->intf);
  1825. if (ret < 0)
  1826. goto out;
  1827. mutex_lock(&tp->control);
  1828. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1829. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1830. rtl_rx_vlan_en(tp, true);
  1831. else
  1832. rtl_rx_vlan_en(tp, false);
  1833. }
  1834. mutex_unlock(&tp->control);
  1835. usb_autopm_put_interface(tp->intf);
  1836. out:
  1837. return ret;
  1838. }
  1839. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1840. static u32 __rtl_get_wol(struct r8152 *tp)
  1841. {
  1842. u32 ocp_data;
  1843. u32 wolopts = 0;
  1844. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1845. if (!(ocp_data & LAN_WAKE_EN))
  1846. return 0;
  1847. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1848. if (ocp_data & LINK_ON_WAKE_EN)
  1849. wolopts |= WAKE_PHY;
  1850. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1851. if (ocp_data & UWF_EN)
  1852. wolopts |= WAKE_UCAST;
  1853. if (ocp_data & BWF_EN)
  1854. wolopts |= WAKE_BCAST;
  1855. if (ocp_data & MWF_EN)
  1856. wolopts |= WAKE_MCAST;
  1857. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1858. if (ocp_data & MAGIC_EN)
  1859. wolopts |= WAKE_MAGIC;
  1860. return wolopts;
  1861. }
  1862. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1863. {
  1864. u32 ocp_data;
  1865. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1866. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1867. ocp_data &= ~LINK_ON_WAKE_EN;
  1868. if (wolopts & WAKE_PHY)
  1869. ocp_data |= LINK_ON_WAKE_EN;
  1870. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1871. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1872. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1873. if (wolopts & WAKE_UCAST)
  1874. ocp_data |= UWF_EN;
  1875. if (wolopts & WAKE_BCAST)
  1876. ocp_data |= BWF_EN;
  1877. if (wolopts & WAKE_MCAST)
  1878. ocp_data |= MWF_EN;
  1879. if (wolopts & WAKE_ANY)
  1880. ocp_data |= LAN_WAKE_EN;
  1881. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1882. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1883. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1884. ocp_data &= ~MAGIC_EN;
  1885. if (wolopts & WAKE_MAGIC)
  1886. ocp_data |= MAGIC_EN;
  1887. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1888. if (wolopts & WAKE_ANY)
  1889. device_set_wakeup_enable(&tp->udev->dev, true);
  1890. else
  1891. device_set_wakeup_enable(&tp->udev->dev, false);
  1892. }
  1893. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1894. {
  1895. u8 u1u2[8];
  1896. if (enable)
  1897. memset(u1u2, 0xff, sizeof(u1u2));
  1898. else
  1899. memset(u1u2, 0x00, sizeof(u1u2));
  1900. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1901. }
  1902. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1903. {
  1904. u32 ocp_data;
  1905. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1906. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1907. ocp_data |= U2P3_ENABLE;
  1908. else
  1909. ocp_data &= ~U2P3_ENABLE;
  1910. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1911. }
  1912. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1913. {
  1914. u32 ocp_data;
  1915. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1916. if (enable)
  1917. ocp_data |= PWR_EN | PHASE2_EN;
  1918. else
  1919. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1920. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1921. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1922. ocp_data &= ~PCUT_STATUS;
  1923. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  1924. }
  1925. static bool rtl_can_wakeup(struct r8152 *tp)
  1926. {
  1927. struct usb_device *udev = tp->udev;
  1928. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  1929. }
  1930. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1931. {
  1932. if (enable) {
  1933. u32 ocp_data;
  1934. r8153_u1u2en(tp, false);
  1935. r8153_u2p3en(tp, false);
  1936. __rtl_set_wol(tp, WAKE_ANY);
  1937. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1938. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1939. ocp_data |= LINK_OFF_WAKE_EN;
  1940. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1941. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1942. } else {
  1943. __rtl_set_wol(tp, tp->saved_wolopts);
  1944. r8153_u2p3en(tp, true);
  1945. r8153_u1u2en(tp, true);
  1946. }
  1947. }
  1948. static void rtl_phy_reset(struct r8152 *tp)
  1949. {
  1950. u16 data;
  1951. int i;
  1952. data = r8152_mdio_read(tp, MII_BMCR);
  1953. /* don't reset again before the previous one complete */
  1954. if (data & BMCR_RESET)
  1955. return;
  1956. data |= BMCR_RESET;
  1957. r8152_mdio_write(tp, MII_BMCR, data);
  1958. for (i = 0; i < 50; i++) {
  1959. msleep(20);
  1960. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1961. break;
  1962. }
  1963. }
  1964. static void r8153_teredo_off(struct r8152 *tp)
  1965. {
  1966. u32 ocp_data;
  1967. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1968. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1969. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1970. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1971. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1972. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1973. }
  1974. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  1975. {
  1976. if (enable) {
  1977. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1978. LINKENA | DIS_SDSAVE);
  1979. } else {
  1980. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  1981. DIS_SDSAVE);
  1982. msleep(20);
  1983. }
  1984. }
  1985. static void rtl8152_disable(struct r8152 *tp)
  1986. {
  1987. r8152_aldps_en(tp, false);
  1988. rtl_disable(tp);
  1989. r8152_aldps_en(tp, true);
  1990. }
  1991. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1992. {
  1993. u16 data;
  1994. data = r8152_mdio_read(tp, MII_BMCR);
  1995. if (data & BMCR_PDOWN) {
  1996. data &= ~BMCR_PDOWN;
  1997. r8152_mdio_write(tp, MII_BMCR, data);
  1998. }
  1999. set_bit(PHY_RESET, &tp->flags);
  2000. }
  2001. static void r8152b_exit_oob(struct r8152 *tp)
  2002. {
  2003. u32 ocp_data;
  2004. int i;
  2005. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2006. ocp_data &= ~RCR_ACPT_ALL;
  2007. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2008. rxdy_gated_en(tp, true);
  2009. r8153_teredo_off(tp);
  2010. r8152b_hw_phy_cfg(tp);
  2011. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2012. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2013. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2014. ocp_data &= ~NOW_IS_OOB;
  2015. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2016. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2017. ocp_data &= ~MCU_BORW_EN;
  2018. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2019. for (i = 0; i < 1000; i++) {
  2020. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2021. if (ocp_data & LINK_LIST_READY)
  2022. break;
  2023. usleep_range(1000, 2000);
  2024. }
  2025. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2026. ocp_data |= RE_INIT_LL;
  2027. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2028. for (i = 0; i < 1000; i++) {
  2029. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2030. if (ocp_data & LINK_LIST_READY)
  2031. break;
  2032. usleep_range(1000, 2000);
  2033. }
  2034. rtl8152_nic_reset(tp);
  2035. /* rx share fifo credit full threshold */
  2036. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2037. if (tp->udev->speed == USB_SPEED_FULL ||
  2038. tp->udev->speed == USB_SPEED_LOW) {
  2039. /* rx share fifo credit near full threshold */
  2040. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2041. RXFIFO_THR2_FULL);
  2042. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2043. RXFIFO_THR3_FULL);
  2044. } else {
  2045. /* rx share fifo credit near full threshold */
  2046. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2047. RXFIFO_THR2_HIGH);
  2048. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2049. RXFIFO_THR3_HIGH);
  2050. }
  2051. /* TX share fifo free credit full threshold */
  2052. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2053. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2054. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2055. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2056. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2057. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2058. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2059. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2060. ocp_data |= TCR0_AUTO_FIFO;
  2061. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2062. }
  2063. static void r8152b_enter_oob(struct r8152 *tp)
  2064. {
  2065. u32 ocp_data;
  2066. int i;
  2067. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2068. ocp_data &= ~NOW_IS_OOB;
  2069. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2070. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2071. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2072. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2073. rtl_disable(tp);
  2074. for (i = 0; i < 1000; i++) {
  2075. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2076. if (ocp_data & LINK_LIST_READY)
  2077. break;
  2078. usleep_range(1000, 2000);
  2079. }
  2080. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2081. ocp_data |= RE_INIT_LL;
  2082. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2083. for (i = 0; i < 1000; i++) {
  2084. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2085. if (ocp_data & LINK_LIST_READY)
  2086. break;
  2087. usleep_range(1000, 2000);
  2088. }
  2089. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2090. rtl_rx_vlan_en(tp, true);
  2091. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2092. ocp_data |= ALDPS_PROXY_MODE;
  2093. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2094. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2095. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2096. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2097. rxdy_gated_en(tp, false);
  2098. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2099. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2100. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2101. }
  2102. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2103. {
  2104. u32 ocp_data;
  2105. u16 data;
  2106. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2107. tp->version == RTL_VER_05)
  2108. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2109. data = r8152_mdio_read(tp, MII_BMCR);
  2110. if (data & BMCR_PDOWN) {
  2111. data &= ~BMCR_PDOWN;
  2112. r8152_mdio_write(tp, MII_BMCR, data);
  2113. }
  2114. if (tp->version == RTL_VER_03) {
  2115. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2116. data &= ~CTAP_SHORT_EN;
  2117. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2118. }
  2119. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2120. data |= EEE_CLKDIV_EN;
  2121. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2122. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2123. data |= EN_10M_BGOFF;
  2124. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2125. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2126. data |= EN_10M_PLLOFF;
  2127. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2128. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2129. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2130. ocp_data |= PFM_PWM_SWITCH;
  2131. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2132. /* Enable LPF corner auto tune */
  2133. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2134. /* Adjust 10M Amplitude */
  2135. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2136. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2137. set_bit(PHY_RESET, &tp->flags);
  2138. }
  2139. static void r8153_first_init(struct r8152 *tp)
  2140. {
  2141. u32 ocp_data;
  2142. int i;
  2143. rxdy_gated_en(tp, true);
  2144. r8153_teredo_off(tp);
  2145. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2146. ocp_data &= ~RCR_ACPT_ALL;
  2147. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2148. r8153_hw_phy_cfg(tp);
  2149. rtl8152_nic_reset(tp);
  2150. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2151. ocp_data &= ~NOW_IS_OOB;
  2152. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2153. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2154. ocp_data &= ~MCU_BORW_EN;
  2155. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2156. for (i = 0; i < 1000; i++) {
  2157. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2158. if (ocp_data & LINK_LIST_READY)
  2159. break;
  2160. usleep_range(1000, 2000);
  2161. }
  2162. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2163. ocp_data |= RE_INIT_LL;
  2164. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2165. for (i = 0; i < 1000; i++) {
  2166. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2167. if (ocp_data & LINK_LIST_READY)
  2168. break;
  2169. usleep_range(1000, 2000);
  2170. }
  2171. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2172. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2173. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2174. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2175. ocp_data |= TCR0_AUTO_FIFO;
  2176. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2177. rtl8152_nic_reset(tp);
  2178. /* rx share fifo credit full threshold */
  2179. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2180. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2181. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2182. /* TX share fifo free credit full threshold */
  2183. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2184. /* rx aggregation */
  2185. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2186. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2187. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2188. }
  2189. static void r8153_enter_oob(struct r8152 *tp)
  2190. {
  2191. u32 ocp_data;
  2192. int i;
  2193. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2194. ocp_data &= ~NOW_IS_OOB;
  2195. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2196. rtl_disable(tp);
  2197. for (i = 0; i < 1000; i++) {
  2198. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2199. if (ocp_data & LINK_LIST_READY)
  2200. break;
  2201. usleep_range(1000, 2000);
  2202. }
  2203. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2204. ocp_data |= RE_INIT_LL;
  2205. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2206. for (i = 0; i < 1000; i++) {
  2207. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2208. if (ocp_data & LINK_LIST_READY)
  2209. break;
  2210. usleep_range(1000, 2000);
  2211. }
  2212. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2213. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2214. ocp_data &= ~TEREDO_WAKE_MASK;
  2215. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2216. rtl_rx_vlan_en(tp, true);
  2217. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2218. ocp_data |= ALDPS_PROXY_MODE;
  2219. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2220. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2221. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2222. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2223. rxdy_gated_en(tp, false);
  2224. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2225. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2226. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2227. }
  2228. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2229. {
  2230. u16 data;
  2231. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2232. if (enable) {
  2233. data |= EN_ALDPS;
  2234. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2235. } else {
  2236. data &= ~EN_ALDPS;
  2237. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2238. msleep(20);
  2239. }
  2240. }
  2241. static void rtl8153_disable(struct r8152 *tp)
  2242. {
  2243. r8153_aldps_en(tp, false);
  2244. rtl_disable(tp);
  2245. r8153_aldps_en(tp, true);
  2246. usb_enable_lpm(tp->udev);
  2247. }
  2248. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2249. {
  2250. u16 bmcr, anar, gbcr;
  2251. int ret = 0;
  2252. cancel_delayed_work_sync(&tp->schedule);
  2253. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2254. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2255. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2256. if (tp->mii.supports_gmii) {
  2257. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2258. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2259. } else {
  2260. gbcr = 0;
  2261. }
  2262. if (autoneg == AUTONEG_DISABLE) {
  2263. if (speed == SPEED_10) {
  2264. bmcr = 0;
  2265. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2266. } else if (speed == SPEED_100) {
  2267. bmcr = BMCR_SPEED100;
  2268. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2269. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2270. bmcr = BMCR_SPEED1000;
  2271. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2272. } else {
  2273. ret = -EINVAL;
  2274. goto out;
  2275. }
  2276. if (duplex == DUPLEX_FULL)
  2277. bmcr |= BMCR_FULLDPLX;
  2278. } else {
  2279. if (speed == SPEED_10) {
  2280. if (duplex == DUPLEX_FULL)
  2281. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2282. else
  2283. anar |= ADVERTISE_10HALF;
  2284. } else if (speed == SPEED_100) {
  2285. if (duplex == DUPLEX_FULL) {
  2286. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2287. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2288. } else {
  2289. anar |= ADVERTISE_10HALF;
  2290. anar |= ADVERTISE_100HALF;
  2291. }
  2292. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2293. if (duplex == DUPLEX_FULL) {
  2294. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2295. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2296. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2297. } else {
  2298. anar |= ADVERTISE_10HALF;
  2299. anar |= ADVERTISE_100HALF;
  2300. gbcr |= ADVERTISE_1000HALF;
  2301. }
  2302. } else {
  2303. ret = -EINVAL;
  2304. goto out;
  2305. }
  2306. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2307. }
  2308. if (test_bit(PHY_RESET, &tp->flags))
  2309. bmcr |= BMCR_RESET;
  2310. if (tp->mii.supports_gmii)
  2311. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2312. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2313. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2314. if (test_and_clear_bit(PHY_RESET, &tp->flags)) {
  2315. int i;
  2316. for (i = 0; i < 50; i++) {
  2317. msleep(20);
  2318. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2319. break;
  2320. }
  2321. }
  2322. out:
  2323. return ret;
  2324. }
  2325. static void rtl8152_up(struct r8152 *tp)
  2326. {
  2327. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2328. return;
  2329. r8152_aldps_en(tp, false);
  2330. r8152b_exit_oob(tp);
  2331. r8152_aldps_en(tp, true);
  2332. }
  2333. static void rtl8152_down(struct r8152 *tp)
  2334. {
  2335. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2336. rtl_drop_queued_tx(tp);
  2337. return;
  2338. }
  2339. r8152_power_cut_en(tp, false);
  2340. r8152_aldps_en(tp, false);
  2341. r8152b_enter_oob(tp);
  2342. r8152_aldps_en(tp, true);
  2343. }
  2344. static void rtl8153_up(struct r8152 *tp)
  2345. {
  2346. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2347. return;
  2348. r8153_u1u2en(tp, false);
  2349. r8153_aldps_en(tp, false);
  2350. r8153_first_init(tp);
  2351. r8153_aldps_en(tp, true);
  2352. r8153_u2p3en(tp, true);
  2353. r8153_u1u2en(tp, true);
  2354. usb_enable_lpm(tp->udev);
  2355. }
  2356. static void rtl8153_down(struct r8152 *tp)
  2357. {
  2358. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2359. rtl_drop_queued_tx(tp);
  2360. return;
  2361. }
  2362. r8153_u1u2en(tp, false);
  2363. r8153_u2p3en(tp, false);
  2364. r8153_power_cut_en(tp, false);
  2365. r8153_aldps_en(tp, false);
  2366. r8153_enter_oob(tp);
  2367. r8153_aldps_en(tp, true);
  2368. }
  2369. static bool rtl8152_in_nway(struct r8152 *tp)
  2370. {
  2371. u16 nway_state;
  2372. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2373. tp->ocp_base = 0x2000;
  2374. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2375. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2376. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2377. if (nway_state & 0xc000)
  2378. return false;
  2379. else
  2380. return true;
  2381. }
  2382. static bool rtl8153_in_nway(struct r8152 *tp)
  2383. {
  2384. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2385. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2386. return false;
  2387. else
  2388. return true;
  2389. }
  2390. static void set_carrier(struct r8152 *tp)
  2391. {
  2392. struct net_device *netdev = tp->netdev;
  2393. u8 speed;
  2394. speed = rtl8152_get_speed(tp);
  2395. if (speed & LINK_STATUS) {
  2396. if (!netif_carrier_ok(netdev)) {
  2397. tp->rtl_ops.enable(tp);
  2398. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2399. napi_disable(&tp->napi);
  2400. netif_carrier_on(netdev);
  2401. rtl_start_rx(tp);
  2402. napi_enable(&tp->napi);
  2403. }
  2404. } else {
  2405. if (netif_carrier_ok(netdev)) {
  2406. netif_carrier_off(netdev);
  2407. napi_disable(&tp->napi);
  2408. tp->rtl_ops.disable(tp);
  2409. napi_enable(&tp->napi);
  2410. }
  2411. }
  2412. }
  2413. static void rtl_work_func_t(struct work_struct *work)
  2414. {
  2415. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2416. /* If the device is unplugged or !netif_running(), the workqueue
  2417. * doesn't need to wake the device, and could return directly.
  2418. */
  2419. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2420. return;
  2421. if (usb_autopm_get_interface(tp->intf) < 0)
  2422. return;
  2423. if (!test_bit(WORK_ENABLE, &tp->flags))
  2424. goto out1;
  2425. if (!mutex_trylock(&tp->control)) {
  2426. schedule_delayed_work(&tp->schedule, 0);
  2427. goto out1;
  2428. }
  2429. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2430. set_carrier(tp);
  2431. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2432. _rtl8152_set_rx_mode(tp->netdev);
  2433. /* don't schedule napi before linking */
  2434. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2435. netif_carrier_ok(tp->netdev))
  2436. napi_schedule(&tp->napi);
  2437. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2438. rtl_phy_reset(tp);
  2439. mutex_unlock(&tp->control);
  2440. out1:
  2441. usb_autopm_put_interface(tp->intf);
  2442. }
  2443. #ifdef CONFIG_PM_SLEEP
  2444. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  2445. void *data)
  2446. {
  2447. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  2448. switch (action) {
  2449. case PM_HIBERNATION_PREPARE:
  2450. case PM_SUSPEND_PREPARE:
  2451. usb_autopm_get_interface(tp->intf);
  2452. break;
  2453. case PM_POST_HIBERNATION:
  2454. case PM_POST_SUSPEND:
  2455. usb_autopm_put_interface(tp->intf);
  2456. break;
  2457. case PM_POST_RESTORE:
  2458. case PM_RESTORE_PREPARE:
  2459. default:
  2460. break;
  2461. }
  2462. return NOTIFY_DONE;
  2463. }
  2464. #endif
  2465. static int rtl8152_open(struct net_device *netdev)
  2466. {
  2467. struct r8152 *tp = netdev_priv(netdev);
  2468. int res = 0;
  2469. res = alloc_all_mem(tp);
  2470. if (res)
  2471. goto out;
  2472. netif_carrier_off(netdev);
  2473. res = usb_autopm_get_interface(tp->intf);
  2474. if (res < 0) {
  2475. free_all_mem(tp);
  2476. goto out;
  2477. }
  2478. mutex_lock(&tp->control);
  2479. tp->rtl_ops.up(tp);
  2480. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2481. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2482. DUPLEX_FULL);
  2483. netif_carrier_off(netdev);
  2484. netif_start_queue(netdev);
  2485. set_bit(WORK_ENABLE, &tp->flags);
  2486. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2487. if (res) {
  2488. if (res == -ENODEV)
  2489. netif_device_detach(tp->netdev);
  2490. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2491. res);
  2492. free_all_mem(tp);
  2493. } else {
  2494. napi_enable(&tp->napi);
  2495. }
  2496. mutex_unlock(&tp->control);
  2497. usb_autopm_put_interface(tp->intf);
  2498. #ifdef CONFIG_PM_SLEEP
  2499. tp->pm_notifier.notifier_call = rtl_notifier;
  2500. register_pm_notifier(&tp->pm_notifier);
  2501. #endif
  2502. out:
  2503. return res;
  2504. }
  2505. static int rtl8152_close(struct net_device *netdev)
  2506. {
  2507. struct r8152 *tp = netdev_priv(netdev);
  2508. int res = 0;
  2509. #ifdef CONFIG_PM_SLEEP
  2510. unregister_pm_notifier(&tp->pm_notifier);
  2511. #endif
  2512. napi_disable(&tp->napi);
  2513. clear_bit(WORK_ENABLE, &tp->flags);
  2514. usb_kill_urb(tp->intr_urb);
  2515. cancel_delayed_work_sync(&tp->schedule);
  2516. netif_stop_queue(netdev);
  2517. res = usb_autopm_get_interface(tp->intf);
  2518. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2519. rtl_drop_queued_tx(tp);
  2520. rtl_stop_rx(tp);
  2521. } else {
  2522. mutex_lock(&tp->control);
  2523. tp->rtl_ops.down(tp);
  2524. mutex_unlock(&tp->control);
  2525. usb_autopm_put_interface(tp->intf);
  2526. }
  2527. free_all_mem(tp);
  2528. return res;
  2529. }
  2530. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2531. {
  2532. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2533. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2534. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2535. }
  2536. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2537. {
  2538. u16 data;
  2539. r8152_mmd_indirect(tp, dev, reg);
  2540. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2541. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2542. return data;
  2543. }
  2544. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2545. {
  2546. r8152_mmd_indirect(tp, dev, reg);
  2547. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2548. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2549. }
  2550. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2551. {
  2552. u16 config1, config2, config3;
  2553. u32 ocp_data;
  2554. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2555. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2556. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2557. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2558. if (enable) {
  2559. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2560. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2561. config1 |= sd_rise_time(1);
  2562. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2563. config3 |= fast_snr(42);
  2564. } else {
  2565. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2566. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2567. RX_QUIET_EN);
  2568. config1 |= sd_rise_time(7);
  2569. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2570. config3 |= fast_snr(511);
  2571. }
  2572. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2573. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2574. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2575. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2576. }
  2577. static void r8152b_enable_eee(struct r8152 *tp)
  2578. {
  2579. r8152_eee_en(tp, true);
  2580. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2581. }
  2582. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2583. {
  2584. u32 ocp_data;
  2585. u16 config;
  2586. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2587. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2588. if (enable) {
  2589. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2590. config |= EEE10_EN;
  2591. } else {
  2592. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2593. config &= ~EEE10_EN;
  2594. }
  2595. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2596. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2597. }
  2598. static void r8153_enable_eee(struct r8152 *tp)
  2599. {
  2600. r8153_eee_en(tp, true);
  2601. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2602. }
  2603. static void r8152b_enable_fc(struct r8152 *tp)
  2604. {
  2605. u16 anar;
  2606. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2607. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2608. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2609. }
  2610. static void rtl_tally_reset(struct r8152 *tp)
  2611. {
  2612. u32 ocp_data;
  2613. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2614. ocp_data |= TALLY_RESET;
  2615. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2616. }
  2617. static void r8152b_init(struct r8152 *tp)
  2618. {
  2619. u32 ocp_data;
  2620. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2621. return;
  2622. r8152_aldps_en(tp, false);
  2623. if (tp->version == RTL_VER_01) {
  2624. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2625. ocp_data &= ~LED_MODE_MASK;
  2626. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2627. }
  2628. r8152_power_cut_en(tp, false);
  2629. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2630. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2631. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2632. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2633. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2634. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2635. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2636. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2637. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2638. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2639. r8152b_enable_eee(tp);
  2640. r8152_aldps_en(tp, true);
  2641. r8152b_enable_fc(tp);
  2642. rtl_tally_reset(tp);
  2643. /* enable rx aggregation */
  2644. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2645. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2646. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2647. }
  2648. static void r8153_init(struct r8152 *tp)
  2649. {
  2650. u32 ocp_data;
  2651. int i;
  2652. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2653. return;
  2654. r8153_aldps_en(tp, false);
  2655. r8153_u1u2en(tp, false);
  2656. for (i = 0; i < 500; i++) {
  2657. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2658. AUTOLOAD_DONE)
  2659. break;
  2660. msleep(20);
  2661. }
  2662. for (i = 0; i < 500; i++) {
  2663. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2664. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2665. break;
  2666. msleep(20);
  2667. }
  2668. usb_disable_lpm(tp->udev);
  2669. r8153_u2p3en(tp, false);
  2670. if (tp->version == RTL_VER_04) {
  2671. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2672. ocp_data &= ~pwd_dn_scale_mask;
  2673. ocp_data |= pwd_dn_scale(96);
  2674. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2675. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2676. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2677. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2678. } else if (tp->version == RTL_VER_05) {
  2679. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2680. ocp_data &= ~ECM_ALDPS;
  2681. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2682. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2683. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2684. ocp_data &= ~DYNAMIC_BURST;
  2685. else
  2686. ocp_data |= DYNAMIC_BURST;
  2687. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2688. } else if (tp->version == RTL_VER_06) {
  2689. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2690. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2691. ocp_data &= ~DYNAMIC_BURST;
  2692. else
  2693. ocp_data |= DYNAMIC_BURST;
  2694. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2695. }
  2696. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2697. ocp_data |= EP4_FULL_FC;
  2698. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2699. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2700. ocp_data &= ~TIMER11_EN;
  2701. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2702. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2703. ocp_data &= ~LED_MODE_MASK;
  2704. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2705. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2706. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2707. ocp_data |= LPM_TIMER_500MS;
  2708. else
  2709. ocp_data |= LPM_TIMER_500US;
  2710. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2711. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2712. ocp_data &= ~SEN_VAL_MASK;
  2713. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2714. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2715. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2716. r8153_power_cut_en(tp, false);
  2717. r8153_u1u2en(tp, true);
  2718. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2719. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2720. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2721. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2722. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2723. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2724. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2725. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2726. EEE_SPDWN_EN);
  2727. r8153_enable_eee(tp);
  2728. r8153_aldps_en(tp, true);
  2729. r8152b_enable_fc(tp);
  2730. rtl_tally_reset(tp);
  2731. r8153_u2p3en(tp, true);
  2732. }
  2733. static int rtl8152_pre_reset(struct usb_interface *intf)
  2734. {
  2735. struct r8152 *tp = usb_get_intfdata(intf);
  2736. struct net_device *netdev;
  2737. if (!tp)
  2738. return 0;
  2739. netdev = tp->netdev;
  2740. if (!netif_running(netdev))
  2741. return 0;
  2742. napi_disable(&tp->napi);
  2743. clear_bit(WORK_ENABLE, &tp->flags);
  2744. usb_kill_urb(tp->intr_urb);
  2745. cancel_delayed_work_sync(&tp->schedule);
  2746. if (netif_carrier_ok(netdev)) {
  2747. netif_stop_queue(netdev);
  2748. mutex_lock(&tp->control);
  2749. tp->rtl_ops.disable(tp);
  2750. mutex_unlock(&tp->control);
  2751. }
  2752. return 0;
  2753. }
  2754. static int rtl8152_post_reset(struct usb_interface *intf)
  2755. {
  2756. struct r8152 *tp = usb_get_intfdata(intf);
  2757. struct net_device *netdev;
  2758. if (!tp)
  2759. return 0;
  2760. netdev = tp->netdev;
  2761. if (!netif_running(netdev))
  2762. return 0;
  2763. set_bit(WORK_ENABLE, &tp->flags);
  2764. if (netif_carrier_ok(netdev)) {
  2765. mutex_lock(&tp->control);
  2766. tp->rtl_ops.enable(tp);
  2767. rtl8152_set_rx_mode(netdev);
  2768. mutex_unlock(&tp->control);
  2769. netif_wake_queue(netdev);
  2770. }
  2771. napi_enable(&tp->napi);
  2772. return 0;
  2773. }
  2774. static bool delay_autosuspend(struct r8152 *tp)
  2775. {
  2776. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2777. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2778. /* This means a linking change occurs and the driver doesn't detect it,
  2779. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2780. * device wouldn't wake up by receiving any packet.
  2781. */
  2782. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2783. return true;
  2784. /* If the linking down is occurred by nway, the device may miss the
  2785. * linking change event. And it wouldn't wake when linking on.
  2786. */
  2787. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2788. return true;
  2789. else
  2790. return false;
  2791. }
  2792. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2793. {
  2794. struct r8152 *tp = usb_get_intfdata(intf);
  2795. struct net_device *netdev = tp->netdev;
  2796. int ret = 0;
  2797. mutex_lock(&tp->control);
  2798. if (PMSG_IS_AUTO(message)) {
  2799. if (netif_running(netdev) && delay_autosuspend(tp)) {
  2800. ret = -EBUSY;
  2801. goto out1;
  2802. }
  2803. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2804. } else {
  2805. netif_device_detach(netdev);
  2806. }
  2807. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2808. clear_bit(WORK_ENABLE, &tp->flags);
  2809. usb_kill_urb(tp->intr_urb);
  2810. napi_disable(&tp->napi);
  2811. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2812. rtl_stop_rx(tp);
  2813. rtl_runtime_suspend_enable(tp, true);
  2814. } else {
  2815. cancel_delayed_work_sync(&tp->schedule);
  2816. tp->rtl_ops.down(tp);
  2817. }
  2818. napi_enable(&tp->napi);
  2819. }
  2820. out1:
  2821. mutex_unlock(&tp->control);
  2822. return ret;
  2823. }
  2824. static int rtl8152_resume(struct usb_interface *intf)
  2825. {
  2826. struct r8152 *tp = usb_get_intfdata(intf);
  2827. mutex_lock(&tp->control);
  2828. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2829. tp->rtl_ops.init(tp);
  2830. netif_device_attach(tp->netdev);
  2831. }
  2832. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2833. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2834. rtl_runtime_suspend_enable(tp, false);
  2835. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2836. napi_disable(&tp->napi);
  2837. set_bit(WORK_ENABLE, &tp->flags);
  2838. if (netif_carrier_ok(tp->netdev))
  2839. rtl_start_rx(tp);
  2840. napi_enable(&tp->napi);
  2841. } else {
  2842. tp->rtl_ops.up(tp);
  2843. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2844. tp->mii.supports_gmii ?
  2845. SPEED_1000 : SPEED_100,
  2846. DUPLEX_FULL);
  2847. netif_carrier_off(tp->netdev);
  2848. set_bit(WORK_ENABLE, &tp->flags);
  2849. }
  2850. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2851. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2852. if (tp->netdev->flags & IFF_UP)
  2853. rtl_runtime_suspend_enable(tp, false);
  2854. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2855. }
  2856. mutex_unlock(&tp->control);
  2857. return 0;
  2858. }
  2859. static int rtl8152_reset_resume(struct usb_interface *intf)
  2860. {
  2861. struct r8152 *tp = usb_get_intfdata(intf);
  2862. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2863. return rtl8152_resume(intf);
  2864. }
  2865. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2866. {
  2867. struct r8152 *tp = netdev_priv(dev);
  2868. if (usb_autopm_get_interface(tp->intf) < 0)
  2869. return;
  2870. if (!rtl_can_wakeup(tp)) {
  2871. wol->supported = 0;
  2872. wol->wolopts = 0;
  2873. } else {
  2874. mutex_lock(&tp->control);
  2875. wol->supported = WAKE_ANY;
  2876. wol->wolopts = __rtl_get_wol(tp);
  2877. mutex_unlock(&tp->control);
  2878. }
  2879. usb_autopm_put_interface(tp->intf);
  2880. }
  2881. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2882. {
  2883. struct r8152 *tp = netdev_priv(dev);
  2884. int ret;
  2885. if (!rtl_can_wakeup(tp))
  2886. return -EOPNOTSUPP;
  2887. ret = usb_autopm_get_interface(tp->intf);
  2888. if (ret < 0)
  2889. goto out_set_wol;
  2890. mutex_lock(&tp->control);
  2891. __rtl_set_wol(tp, wol->wolopts);
  2892. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2893. mutex_unlock(&tp->control);
  2894. usb_autopm_put_interface(tp->intf);
  2895. out_set_wol:
  2896. return ret;
  2897. }
  2898. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2899. {
  2900. struct r8152 *tp = netdev_priv(dev);
  2901. return tp->msg_enable;
  2902. }
  2903. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2904. {
  2905. struct r8152 *tp = netdev_priv(dev);
  2906. tp->msg_enable = value;
  2907. }
  2908. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2909. struct ethtool_drvinfo *info)
  2910. {
  2911. struct r8152 *tp = netdev_priv(netdev);
  2912. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2913. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2914. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2915. }
  2916. static
  2917. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2918. {
  2919. struct r8152 *tp = netdev_priv(netdev);
  2920. int ret;
  2921. if (!tp->mii.mdio_read)
  2922. return -EOPNOTSUPP;
  2923. ret = usb_autopm_get_interface(tp->intf);
  2924. if (ret < 0)
  2925. goto out;
  2926. mutex_lock(&tp->control);
  2927. ret = mii_ethtool_gset(&tp->mii, cmd);
  2928. mutex_unlock(&tp->control);
  2929. usb_autopm_put_interface(tp->intf);
  2930. out:
  2931. return ret;
  2932. }
  2933. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2934. {
  2935. struct r8152 *tp = netdev_priv(dev);
  2936. int ret;
  2937. ret = usb_autopm_get_interface(tp->intf);
  2938. if (ret < 0)
  2939. goto out;
  2940. mutex_lock(&tp->control);
  2941. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2942. mutex_unlock(&tp->control);
  2943. usb_autopm_put_interface(tp->intf);
  2944. out:
  2945. return ret;
  2946. }
  2947. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2948. "tx_packets",
  2949. "rx_packets",
  2950. "tx_errors",
  2951. "rx_errors",
  2952. "rx_missed",
  2953. "align_errors",
  2954. "tx_single_collisions",
  2955. "tx_multi_collisions",
  2956. "rx_unicast",
  2957. "rx_broadcast",
  2958. "rx_multicast",
  2959. "tx_aborted",
  2960. "tx_underrun",
  2961. };
  2962. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2963. {
  2964. switch (sset) {
  2965. case ETH_SS_STATS:
  2966. return ARRAY_SIZE(rtl8152_gstrings);
  2967. default:
  2968. return -EOPNOTSUPP;
  2969. }
  2970. }
  2971. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2972. struct ethtool_stats *stats, u64 *data)
  2973. {
  2974. struct r8152 *tp = netdev_priv(dev);
  2975. struct tally_counter tally;
  2976. if (usb_autopm_get_interface(tp->intf) < 0)
  2977. return;
  2978. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2979. usb_autopm_put_interface(tp->intf);
  2980. data[0] = le64_to_cpu(tally.tx_packets);
  2981. data[1] = le64_to_cpu(tally.rx_packets);
  2982. data[2] = le64_to_cpu(tally.tx_errors);
  2983. data[3] = le32_to_cpu(tally.rx_errors);
  2984. data[4] = le16_to_cpu(tally.rx_missed);
  2985. data[5] = le16_to_cpu(tally.align_errors);
  2986. data[6] = le32_to_cpu(tally.tx_one_collision);
  2987. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2988. data[8] = le64_to_cpu(tally.rx_unicast);
  2989. data[9] = le64_to_cpu(tally.rx_broadcast);
  2990. data[10] = le32_to_cpu(tally.rx_multicast);
  2991. data[11] = le16_to_cpu(tally.tx_aborted);
  2992. data[12] = le16_to_cpu(tally.tx_underrun);
  2993. }
  2994. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2995. {
  2996. switch (stringset) {
  2997. case ETH_SS_STATS:
  2998. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2999. break;
  3000. }
  3001. }
  3002. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3003. {
  3004. u32 ocp_data, lp, adv, supported = 0;
  3005. u16 val;
  3006. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  3007. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3008. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  3009. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3010. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  3011. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3012. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3013. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3014. eee->eee_enabled = !!ocp_data;
  3015. eee->eee_active = !!(supported & adv & lp);
  3016. eee->supported = supported;
  3017. eee->advertised = adv;
  3018. eee->lp_advertised = lp;
  3019. return 0;
  3020. }
  3021. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3022. {
  3023. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3024. r8152_eee_en(tp, eee->eee_enabled);
  3025. if (!eee->eee_enabled)
  3026. val = 0;
  3027. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3028. return 0;
  3029. }
  3030. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3031. {
  3032. u32 ocp_data, lp, adv, supported = 0;
  3033. u16 val;
  3034. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3035. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3036. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3037. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3038. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3039. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3040. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3041. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3042. eee->eee_enabled = !!ocp_data;
  3043. eee->eee_active = !!(supported & adv & lp);
  3044. eee->supported = supported;
  3045. eee->advertised = adv;
  3046. eee->lp_advertised = lp;
  3047. return 0;
  3048. }
  3049. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3050. {
  3051. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3052. r8153_eee_en(tp, eee->eee_enabled);
  3053. if (!eee->eee_enabled)
  3054. val = 0;
  3055. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3056. return 0;
  3057. }
  3058. static int
  3059. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3060. {
  3061. struct r8152 *tp = netdev_priv(net);
  3062. int ret;
  3063. ret = usb_autopm_get_interface(tp->intf);
  3064. if (ret < 0)
  3065. goto out;
  3066. mutex_lock(&tp->control);
  3067. ret = tp->rtl_ops.eee_get(tp, edata);
  3068. mutex_unlock(&tp->control);
  3069. usb_autopm_put_interface(tp->intf);
  3070. out:
  3071. return ret;
  3072. }
  3073. static int
  3074. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3075. {
  3076. struct r8152 *tp = netdev_priv(net);
  3077. int ret;
  3078. ret = usb_autopm_get_interface(tp->intf);
  3079. if (ret < 0)
  3080. goto out;
  3081. mutex_lock(&tp->control);
  3082. ret = tp->rtl_ops.eee_set(tp, edata);
  3083. if (!ret)
  3084. ret = mii_nway_restart(&tp->mii);
  3085. mutex_unlock(&tp->control);
  3086. usb_autopm_put_interface(tp->intf);
  3087. out:
  3088. return ret;
  3089. }
  3090. static int rtl8152_nway_reset(struct net_device *dev)
  3091. {
  3092. struct r8152 *tp = netdev_priv(dev);
  3093. int ret;
  3094. ret = usb_autopm_get_interface(tp->intf);
  3095. if (ret < 0)
  3096. goto out;
  3097. mutex_lock(&tp->control);
  3098. ret = mii_nway_restart(&tp->mii);
  3099. mutex_unlock(&tp->control);
  3100. usb_autopm_put_interface(tp->intf);
  3101. out:
  3102. return ret;
  3103. }
  3104. static int rtl8152_get_coalesce(struct net_device *netdev,
  3105. struct ethtool_coalesce *coalesce)
  3106. {
  3107. struct r8152 *tp = netdev_priv(netdev);
  3108. switch (tp->version) {
  3109. case RTL_VER_01:
  3110. case RTL_VER_02:
  3111. return -EOPNOTSUPP;
  3112. default:
  3113. break;
  3114. }
  3115. coalesce->rx_coalesce_usecs = tp->coalesce;
  3116. return 0;
  3117. }
  3118. static int rtl8152_set_coalesce(struct net_device *netdev,
  3119. struct ethtool_coalesce *coalesce)
  3120. {
  3121. struct r8152 *tp = netdev_priv(netdev);
  3122. int ret;
  3123. switch (tp->version) {
  3124. case RTL_VER_01:
  3125. case RTL_VER_02:
  3126. return -EOPNOTSUPP;
  3127. default:
  3128. break;
  3129. }
  3130. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3131. return -EINVAL;
  3132. ret = usb_autopm_get_interface(tp->intf);
  3133. if (ret < 0)
  3134. return ret;
  3135. mutex_lock(&tp->control);
  3136. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3137. tp->coalesce = coalesce->rx_coalesce_usecs;
  3138. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3139. r8153_set_rx_early_timeout(tp);
  3140. }
  3141. mutex_unlock(&tp->control);
  3142. usb_autopm_put_interface(tp->intf);
  3143. return ret;
  3144. }
  3145. static struct ethtool_ops ops = {
  3146. .get_drvinfo = rtl8152_get_drvinfo,
  3147. .get_settings = rtl8152_get_settings,
  3148. .set_settings = rtl8152_set_settings,
  3149. .get_link = ethtool_op_get_link,
  3150. .nway_reset = rtl8152_nway_reset,
  3151. .get_msglevel = rtl8152_get_msglevel,
  3152. .set_msglevel = rtl8152_set_msglevel,
  3153. .get_wol = rtl8152_get_wol,
  3154. .set_wol = rtl8152_set_wol,
  3155. .get_strings = rtl8152_get_strings,
  3156. .get_sset_count = rtl8152_get_sset_count,
  3157. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3158. .get_coalesce = rtl8152_get_coalesce,
  3159. .set_coalesce = rtl8152_set_coalesce,
  3160. .get_eee = rtl_ethtool_get_eee,
  3161. .set_eee = rtl_ethtool_set_eee,
  3162. };
  3163. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3164. {
  3165. struct r8152 *tp = netdev_priv(netdev);
  3166. struct mii_ioctl_data *data = if_mii(rq);
  3167. int res;
  3168. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3169. return -ENODEV;
  3170. res = usb_autopm_get_interface(tp->intf);
  3171. if (res < 0)
  3172. goto out;
  3173. switch (cmd) {
  3174. case SIOCGMIIPHY:
  3175. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3176. break;
  3177. case SIOCGMIIREG:
  3178. mutex_lock(&tp->control);
  3179. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3180. mutex_unlock(&tp->control);
  3181. break;
  3182. case SIOCSMIIREG:
  3183. if (!capable(CAP_NET_ADMIN)) {
  3184. res = -EPERM;
  3185. break;
  3186. }
  3187. mutex_lock(&tp->control);
  3188. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3189. mutex_unlock(&tp->control);
  3190. break;
  3191. default:
  3192. res = -EOPNOTSUPP;
  3193. }
  3194. usb_autopm_put_interface(tp->intf);
  3195. out:
  3196. return res;
  3197. }
  3198. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3199. {
  3200. struct r8152 *tp = netdev_priv(dev);
  3201. int ret;
  3202. switch (tp->version) {
  3203. case RTL_VER_01:
  3204. case RTL_VER_02:
  3205. return eth_change_mtu(dev, new_mtu);
  3206. default:
  3207. break;
  3208. }
  3209. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3210. return -EINVAL;
  3211. ret = usb_autopm_get_interface(tp->intf);
  3212. if (ret < 0)
  3213. return ret;
  3214. mutex_lock(&tp->control);
  3215. dev->mtu = new_mtu;
  3216. if (netif_running(dev) && netif_carrier_ok(dev))
  3217. r8153_set_rx_early_size(tp);
  3218. mutex_unlock(&tp->control);
  3219. usb_autopm_put_interface(tp->intf);
  3220. return ret;
  3221. }
  3222. static const struct net_device_ops rtl8152_netdev_ops = {
  3223. .ndo_open = rtl8152_open,
  3224. .ndo_stop = rtl8152_close,
  3225. .ndo_do_ioctl = rtl8152_ioctl,
  3226. .ndo_start_xmit = rtl8152_start_xmit,
  3227. .ndo_tx_timeout = rtl8152_tx_timeout,
  3228. .ndo_set_features = rtl8152_set_features,
  3229. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3230. .ndo_set_mac_address = rtl8152_set_mac_address,
  3231. .ndo_change_mtu = rtl8152_change_mtu,
  3232. .ndo_validate_addr = eth_validate_addr,
  3233. .ndo_features_check = rtl8152_features_check,
  3234. };
  3235. static void r8152b_get_version(struct r8152 *tp)
  3236. {
  3237. u32 ocp_data;
  3238. u16 version;
  3239. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3240. version = (u16)(ocp_data & VERSION_MASK);
  3241. switch (version) {
  3242. case 0x4c00:
  3243. tp->version = RTL_VER_01;
  3244. break;
  3245. case 0x4c10:
  3246. tp->version = RTL_VER_02;
  3247. break;
  3248. case 0x5c00:
  3249. tp->version = RTL_VER_03;
  3250. tp->mii.supports_gmii = 1;
  3251. break;
  3252. case 0x5c10:
  3253. tp->version = RTL_VER_04;
  3254. tp->mii.supports_gmii = 1;
  3255. break;
  3256. case 0x5c20:
  3257. tp->version = RTL_VER_05;
  3258. tp->mii.supports_gmii = 1;
  3259. break;
  3260. case 0x5c30:
  3261. tp->version = RTL_VER_06;
  3262. tp->mii.supports_gmii = 1;
  3263. break;
  3264. default:
  3265. netif_info(tp, probe, tp->netdev,
  3266. "Unknown version 0x%04x\n", version);
  3267. break;
  3268. }
  3269. }
  3270. static void rtl8152_unload(struct r8152 *tp)
  3271. {
  3272. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3273. return;
  3274. if (tp->version != RTL_VER_01)
  3275. r8152_power_cut_en(tp, true);
  3276. }
  3277. static void rtl8153_unload(struct r8152 *tp)
  3278. {
  3279. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3280. return;
  3281. r8153_power_cut_en(tp, false);
  3282. }
  3283. static int rtl_ops_init(struct r8152 *tp)
  3284. {
  3285. struct rtl_ops *ops = &tp->rtl_ops;
  3286. int ret = 0;
  3287. switch (tp->version) {
  3288. case RTL_VER_01:
  3289. case RTL_VER_02:
  3290. ops->init = r8152b_init;
  3291. ops->enable = rtl8152_enable;
  3292. ops->disable = rtl8152_disable;
  3293. ops->up = rtl8152_up;
  3294. ops->down = rtl8152_down;
  3295. ops->unload = rtl8152_unload;
  3296. ops->eee_get = r8152_get_eee;
  3297. ops->eee_set = r8152_set_eee;
  3298. ops->in_nway = rtl8152_in_nway;
  3299. break;
  3300. case RTL_VER_03:
  3301. case RTL_VER_04:
  3302. case RTL_VER_05:
  3303. case RTL_VER_06:
  3304. ops->init = r8153_init;
  3305. ops->enable = rtl8153_enable;
  3306. ops->disable = rtl8153_disable;
  3307. ops->up = rtl8153_up;
  3308. ops->down = rtl8153_down;
  3309. ops->unload = rtl8153_unload;
  3310. ops->eee_get = r8153_get_eee;
  3311. ops->eee_set = r8153_set_eee;
  3312. ops->in_nway = rtl8153_in_nway;
  3313. break;
  3314. default:
  3315. ret = -ENODEV;
  3316. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3317. break;
  3318. }
  3319. return ret;
  3320. }
  3321. static int rtl8152_probe(struct usb_interface *intf,
  3322. const struct usb_device_id *id)
  3323. {
  3324. struct usb_device *udev = interface_to_usbdev(intf);
  3325. struct r8152 *tp;
  3326. struct net_device *netdev;
  3327. int ret;
  3328. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3329. usb_driver_set_configuration(udev, 1);
  3330. return -ENODEV;
  3331. }
  3332. usb_reset_device(udev);
  3333. netdev = alloc_etherdev(sizeof(struct r8152));
  3334. if (!netdev) {
  3335. dev_err(&intf->dev, "Out of memory\n");
  3336. return -ENOMEM;
  3337. }
  3338. SET_NETDEV_DEV(netdev, &intf->dev);
  3339. tp = netdev_priv(netdev);
  3340. tp->msg_enable = 0x7FFF;
  3341. tp->udev = udev;
  3342. tp->netdev = netdev;
  3343. tp->intf = intf;
  3344. r8152b_get_version(tp);
  3345. ret = rtl_ops_init(tp);
  3346. if (ret)
  3347. goto out;
  3348. mutex_init(&tp->control);
  3349. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3350. netdev->netdev_ops = &rtl8152_netdev_ops;
  3351. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3352. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3353. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3354. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3355. NETIF_F_HW_VLAN_CTAG_TX;
  3356. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3357. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3358. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3359. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3360. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3361. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3362. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3363. netdev->ethtool_ops = &ops;
  3364. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3365. tp->mii.dev = netdev;
  3366. tp->mii.mdio_read = read_mii_word;
  3367. tp->mii.mdio_write = write_mii_word;
  3368. tp->mii.phy_id_mask = 0x3f;
  3369. tp->mii.reg_num_mask = 0x1f;
  3370. tp->mii.phy_id = R8152_PHY_ID;
  3371. switch (udev->speed) {
  3372. case USB_SPEED_SUPER:
  3373. tp->coalesce = COALESCE_SUPER;
  3374. break;
  3375. case USB_SPEED_HIGH:
  3376. tp->coalesce = COALESCE_HIGH;
  3377. break;
  3378. default:
  3379. tp->coalesce = COALESCE_SLOW;
  3380. break;
  3381. }
  3382. intf->needs_remote_wakeup = 1;
  3383. tp->rtl_ops.init(tp);
  3384. set_ethernet_addr(tp);
  3385. usb_set_intfdata(intf, tp);
  3386. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3387. ret = register_netdev(netdev);
  3388. if (ret != 0) {
  3389. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3390. goto out1;
  3391. }
  3392. if (!rtl_can_wakeup(tp))
  3393. __rtl_set_wol(tp, 0);
  3394. tp->saved_wolopts = __rtl_get_wol(tp);
  3395. if (tp->saved_wolopts)
  3396. device_set_wakeup_enable(&udev->dev, true);
  3397. else
  3398. device_set_wakeup_enable(&udev->dev, false);
  3399. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3400. return 0;
  3401. out1:
  3402. netif_napi_del(&tp->napi);
  3403. usb_set_intfdata(intf, NULL);
  3404. out:
  3405. free_netdev(netdev);
  3406. return ret;
  3407. }
  3408. static void rtl8152_disconnect(struct usb_interface *intf)
  3409. {
  3410. struct r8152 *tp = usb_get_intfdata(intf);
  3411. usb_set_intfdata(intf, NULL);
  3412. if (tp) {
  3413. struct usb_device *udev = tp->udev;
  3414. if (udev->state == USB_STATE_NOTATTACHED)
  3415. set_bit(RTL8152_UNPLUG, &tp->flags);
  3416. netif_napi_del(&tp->napi);
  3417. unregister_netdev(tp->netdev);
  3418. tp->rtl_ops.unload(tp);
  3419. free_netdev(tp->netdev);
  3420. }
  3421. }
  3422. #define REALTEK_USB_DEVICE(vend, prod) \
  3423. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3424. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3425. .idVendor = (vend), \
  3426. .idProduct = (prod), \
  3427. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3428. }, \
  3429. { \
  3430. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3431. USB_DEVICE_ID_MATCH_DEVICE, \
  3432. .idVendor = (vend), \
  3433. .idProduct = (prod), \
  3434. .bInterfaceClass = USB_CLASS_COMM, \
  3435. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3436. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3437. /* table of devices that work with this driver */
  3438. static struct usb_device_id rtl8152_table[] = {
  3439. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3440. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3441. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3442. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3443. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3444. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3445. {}
  3446. };
  3447. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3448. static struct usb_driver rtl8152_driver = {
  3449. .name = MODULENAME,
  3450. .id_table = rtl8152_table,
  3451. .probe = rtl8152_probe,
  3452. .disconnect = rtl8152_disconnect,
  3453. .suspend = rtl8152_suspend,
  3454. .resume = rtl8152_resume,
  3455. .reset_resume = rtl8152_reset_resume,
  3456. .pre_reset = rtl8152_pre_reset,
  3457. .post_reset = rtl8152_post_reset,
  3458. .supports_autosuspend = 1,
  3459. .disable_hub_initiated_lpm = 1,
  3460. };
  3461. module_usb_driver(rtl8152_driver);
  3462. MODULE_AUTHOR(DRIVER_AUTHOR);
  3463. MODULE_DESCRIPTION(DRIVER_DESC);
  3464. MODULE_LICENSE("GPL");