hns_dsaf_main.c 75 KB

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  1. /*
  2. * Copyright (c) 2014-2015 Hisilicon Limited.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/device.h>
  19. #include <linux/vmalloc.h>
  20. #include "hns_dsaf_main.h"
  21. #include "hns_dsaf_rcb.h"
  22. #include "hns_dsaf_ppe.h"
  23. #include "hns_dsaf_mac.h"
  24. const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  25. [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  26. [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  27. [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  28. };
  29. int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  30. {
  31. int ret, i;
  32. u32 desc_num;
  33. u32 buf_size;
  34. const char *mode_str;
  35. struct device_node *np = dsaf_dev->dev->of_node;
  36. if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  37. dsaf_dev->dsaf_ver = AE_VERSION_1;
  38. else
  39. dsaf_dev->dsaf_ver = AE_VERSION_2;
  40. ret = of_property_read_string(np, "mode", &mode_str);
  41. if (ret) {
  42. dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  43. return ret;
  44. }
  45. for (i = 0; i < DSAF_MODE_MAX; i++) {
  46. if (g_dsaf_mode_match[i] &&
  47. !strcmp(mode_str, g_dsaf_mode_match[i]))
  48. break;
  49. }
  50. if (i >= DSAF_MODE_MAX ||
  51. i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  52. dev_err(dsaf_dev->dev,
  53. "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  54. return -EINVAL;
  55. }
  56. dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  57. if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  58. dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  59. else
  60. dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  61. if ((i == DSAF_MODE_ENABLE_16VM) ||
  62. (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
  63. (i == DSAF_MODE_DISABLE_6PORT_2VM))
  64. dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
  65. else
  66. dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
  67. dsaf_dev->sc_base = of_iomap(np, 0);
  68. if (!dsaf_dev->sc_base) {
  69. dev_err(dsaf_dev->dev,
  70. "%s of_iomap 0 fail!\n", dsaf_dev->ae_dev.name);
  71. ret = -ENOMEM;
  72. goto unmap_base_addr;
  73. }
  74. dsaf_dev->sds_base = of_iomap(np, 1);
  75. if (!dsaf_dev->sds_base) {
  76. dev_err(dsaf_dev->dev,
  77. "%s of_iomap 1 fail!\n", dsaf_dev->ae_dev.name);
  78. ret = -ENOMEM;
  79. goto unmap_base_addr;
  80. }
  81. dsaf_dev->ppe_base = of_iomap(np, 2);
  82. if (!dsaf_dev->ppe_base) {
  83. dev_err(dsaf_dev->dev,
  84. "%s of_iomap 2 fail!\n", dsaf_dev->ae_dev.name);
  85. ret = -ENOMEM;
  86. goto unmap_base_addr;
  87. }
  88. dsaf_dev->io_base = of_iomap(np, 3);
  89. if (!dsaf_dev->io_base) {
  90. dev_err(dsaf_dev->dev,
  91. "%s of_iomap 3 fail!\n", dsaf_dev->ae_dev.name);
  92. ret = -ENOMEM;
  93. goto unmap_base_addr;
  94. }
  95. dsaf_dev->cpld_base = of_iomap(np, 4);
  96. if (!dsaf_dev->cpld_base)
  97. dev_dbg(dsaf_dev->dev, "NO CPLD ADDR");
  98. ret = of_property_read_u32(np, "desc-num", &desc_num);
  99. if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
  100. desc_num > HNS_DSAF_MAX_DESC_CNT) {
  101. dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
  102. desc_num, ret);
  103. goto unmap_base_addr;
  104. }
  105. dsaf_dev->desc_num = desc_num;
  106. ret = of_property_read_u32(np, "buf-size", &buf_size);
  107. if (ret < 0) {
  108. dev_err(dsaf_dev->dev,
  109. "get buf-size fail, ret=%d!\r\n", ret);
  110. goto unmap_base_addr;
  111. }
  112. dsaf_dev->buf_size = buf_size;
  113. dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
  114. if (dsaf_dev->buf_size_type < 0) {
  115. dev_err(dsaf_dev->dev,
  116. "buf_size(%d) is wrong!\n", buf_size);
  117. goto unmap_base_addr;
  118. }
  119. if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
  120. dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
  121. else
  122. dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
  123. return 0;
  124. unmap_base_addr:
  125. if (dsaf_dev->io_base)
  126. iounmap(dsaf_dev->io_base);
  127. if (dsaf_dev->ppe_base)
  128. iounmap(dsaf_dev->ppe_base);
  129. if (dsaf_dev->sds_base)
  130. iounmap(dsaf_dev->sds_base);
  131. if (dsaf_dev->sc_base)
  132. iounmap(dsaf_dev->sc_base);
  133. if (dsaf_dev->cpld_base)
  134. iounmap(dsaf_dev->cpld_base);
  135. return ret;
  136. }
  137. static void hns_dsaf_free_cfg(struct dsaf_device *dsaf_dev)
  138. {
  139. if (dsaf_dev->io_base)
  140. iounmap(dsaf_dev->io_base);
  141. if (dsaf_dev->ppe_base)
  142. iounmap(dsaf_dev->ppe_base);
  143. if (dsaf_dev->sds_base)
  144. iounmap(dsaf_dev->sds_base);
  145. if (dsaf_dev->sc_base)
  146. iounmap(dsaf_dev->sc_base);
  147. if (dsaf_dev->cpld_base)
  148. iounmap(dsaf_dev->cpld_base);
  149. }
  150. /**
  151. * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
  152. * @dsaf_id: dsa fabric id
  153. */
  154. static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
  155. {
  156. dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
  157. }
  158. /**
  159. * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
  160. * @dsaf_id: dsa fabric id
  161. * @hns_dsaf_reg_cnt_clr_ce: config value
  162. */
  163. static void
  164. hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
  165. {
  166. dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
  167. DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
  168. }
  169. /**
  170. * hns_ppe_qid_cfg - config ppe qid
  171. * @dsaf_id: dsa fabric id
  172. * @pppe_qid_cfg: value array
  173. */
  174. static void
  175. hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
  176. {
  177. u32 i;
  178. for (i = 0; i < DSAF_COMM_CHN; i++) {
  179. dsaf_set_dev_field(dsaf_dev,
  180. DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
  181. DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
  182. qid_cfg);
  183. }
  184. }
  185. static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
  186. {
  187. u16 max_q_per_vf, max_vfn;
  188. u32 q_id, q_num_per_port;
  189. u32 i;
  190. hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode,
  191. HNS_DSAF_COMM_SERVICE_NW_IDX,
  192. &max_vfn, &max_q_per_vf);
  193. q_num_per_port = max_vfn * max_q_per_vf;
  194. for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
  195. dsaf_set_dev_field(dsaf_dev,
  196. DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
  197. 0xff, 0, q_id);
  198. q_id += q_num_per_port;
  199. }
  200. }
  201. static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
  202. {
  203. u16 max_q_per_vf, max_vfn;
  204. u32 q_id, q_num_per_port;
  205. u32 mac_id;
  206. if (AE_IS_VER1(dsaf_dev->dsaf_ver))
  207. return;
  208. hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode,
  209. HNS_DSAF_COMM_SERVICE_NW_IDX,
  210. &max_vfn, &max_q_per_vf);
  211. q_num_per_port = max_vfn * max_q_per_vf;
  212. for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
  213. dsaf_set_dev_field(dsaf_dev,
  214. DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
  215. DSAFV2_SERDES_LBK_QID_M,
  216. DSAFV2_SERDES_LBK_QID_S,
  217. q_id);
  218. q_id += q_num_per_port;
  219. }
  220. }
  221. /**
  222. * hns_dsaf_sw_port_type_cfg - cfg sw type
  223. * @dsaf_id: dsa fabric id
  224. * @psw_port_type: array
  225. */
  226. static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
  227. enum dsaf_sw_port_type port_type)
  228. {
  229. u32 i;
  230. for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
  231. dsaf_set_dev_field(dsaf_dev,
  232. DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
  233. DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
  234. port_type);
  235. }
  236. }
  237. /**
  238. * hns_dsaf_stp_port_type_cfg - cfg stp type
  239. * @dsaf_id: dsa fabric id
  240. * @pstp_port_type: array
  241. */
  242. static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
  243. enum dsaf_stp_port_type port_type)
  244. {
  245. u32 i;
  246. for (i = 0; i < DSAF_COMM_CHN; i++) {
  247. dsaf_set_dev_field(dsaf_dev,
  248. DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
  249. DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
  250. port_type);
  251. }
  252. }
  253. #define HNS_DSAF_SBM_NUM(dev) \
  254. (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
  255. /**
  256. * hns_dsaf_sbm_cfg - config sbm
  257. * @dsaf_id: dsa fabric id
  258. */
  259. static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
  260. {
  261. u32 o_sbm_cfg;
  262. u32 i;
  263. for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
  264. o_sbm_cfg = dsaf_read_dev(dsaf_dev,
  265. DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
  266. dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
  267. dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
  268. dsaf_write_dev(dsaf_dev,
  269. DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
  270. }
  271. }
  272. /**
  273. * hns_dsaf_sbm_cfg_mib_en - config sbm
  274. * @dsaf_id: dsa fabric id
  275. */
  276. static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
  277. {
  278. u32 sbm_cfg_mib_en;
  279. u32 i;
  280. u32 reg;
  281. u32 read_cnt;
  282. /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
  283. for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
  284. reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
  285. dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
  286. }
  287. for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
  288. reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
  289. dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
  290. }
  291. /* waitint for all sbm enable finished */
  292. for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
  293. read_cnt = 0;
  294. reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
  295. do {
  296. udelay(1);
  297. sbm_cfg_mib_en = dsaf_get_dev_bit(
  298. dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
  299. read_cnt++;
  300. } while (sbm_cfg_mib_en == 0 &&
  301. read_cnt < DSAF_CFG_READ_CNT);
  302. if (sbm_cfg_mib_en == 0) {
  303. dev_err(dsaf_dev->dev,
  304. "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
  305. dsaf_dev->ae_dev.name, i);
  306. return -ENODEV;
  307. }
  308. }
  309. return 0;
  310. }
  311. /**
  312. * hns_dsaf_sbm_bp_wl_cfg - config sbm
  313. * @dsaf_id: dsa fabric id
  314. */
  315. static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
  316. {
  317. u32 o_sbm_bp_cfg;
  318. u32 reg;
  319. u32 i;
  320. /* XGE */
  321. for (i = 0; i < DSAF_XGE_NUM; i++) {
  322. reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
  323. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  324. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
  325. DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
  326. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
  327. DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
  328. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
  329. DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
  330. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  331. reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
  332. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  333. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
  334. DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
  335. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
  336. DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
  337. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  338. reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
  339. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  340. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
  341. DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
  342. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
  343. DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
  344. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  345. reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
  346. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  347. dsaf_set_field(o_sbm_bp_cfg,
  348. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
  349. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
  350. dsaf_set_field(o_sbm_bp_cfg,
  351. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
  352. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
  353. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  354. /* for no enable pfc mode */
  355. reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
  356. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  357. dsaf_set_field(o_sbm_bp_cfg,
  358. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
  359. DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
  360. dsaf_set_field(o_sbm_bp_cfg,
  361. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
  362. DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
  363. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  364. }
  365. /* PPE */
  366. for (i = 0; i < DSAF_COMM_CHN; i++) {
  367. reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
  368. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  369. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
  370. DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
  371. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
  372. DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
  373. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  374. }
  375. /* RoCEE */
  376. for (i = 0; i < DSAF_COMM_CHN; i++) {
  377. reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
  378. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  379. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
  380. DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
  381. dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
  382. DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
  383. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  384. }
  385. }
  386. static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
  387. {
  388. u32 o_sbm_bp_cfg;
  389. u32 reg;
  390. u32 i;
  391. /* XGE */
  392. for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
  393. reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
  394. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  395. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
  396. DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
  397. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
  398. DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
  399. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
  400. DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
  401. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  402. reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
  403. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  404. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
  405. DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
  406. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
  407. DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
  408. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  409. reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
  410. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  411. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
  412. DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
  413. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
  414. DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
  415. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  416. reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
  417. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  418. dsaf_set_field(o_sbm_bp_cfg,
  419. DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
  420. DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
  421. dsaf_set_field(o_sbm_bp_cfg,
  422. DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
  423. DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
  424. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  425. /* for no enable pfc mode */
  426. reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
  427. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  428. dsaf_set_field(o_sbm_bp_cfg,
  429. DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
  430. DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
  431. dsaf_set_field(o_sbm_bp_cfg,
  432. DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
  433. DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
  434. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  435. }
  436. /* PPE */
  437. reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
  438. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  439. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
  440. DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 10);
  441. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
  442. DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 12);
  443. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  444. /* RoCEE */
  445. for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
  446. reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
  447. o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
  448. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
  449. DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 2);
  450. dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
  451. DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 4);
  452. dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
  453. }
  454. }
  455. /**
  456. * hns_dsaf_voq_bp_all_thrd_cfg - voq
  457. * @dsaf_id: dsa fabric id
  458. */
  459. static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
  460. {
  461. u32 voq_bp_all_thrd;
  462. u32 i;
  463. for (i = 0; i < DSAF_VOQ_NUM; i++) {
  464. voq_bp_all_thrd = dsaf_read_dev(
  465. dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
  466. if (i < DSAF_XGE_NUM) {
  467. dsaf_set_field(voq_bp_all_thrd,
  468. DSAF_VOQ_BP_ALL_DOWNTHRD_M,
  469. DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
  470. dsaf_set_field(voq_bp_all_thrd,
  471. DSAF_VOQ_BP_ALL_UPTHRD_M,
  472. DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
  473. } else {
  474. dsaf_set_field(voq_bp_all_thrd,
  475. DSAF_VOQ_BP_ALL_DOWNTHRD_M,
  476. DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
  477. dsaf_set_field(voq_bp_all_thrd,
  478. DSAF_VOQ_BP_ALL_UPTHRD_M,
  479. DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
  480. }
  481. dsaf_write_dev(
  482. dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
  483. voq_bp_all_thrd);
  484. }
  485. }
  486. /**
  487. * hns_dsaf_tbl_tcam_data_cfg - tbl
  488. * @dsaf_id: dsa fabric id
  489. * @ptbl_tcam_data: addr
  490. */
  491. static void hns_dsaf_tbl_tcam_data_cfg(
  492. struct dsaf_device *dsaf_dev,
  493. struct dsaf_tbl_tcam_data *ptbl_tcam_data)
  494. {
  495. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
  496. ptbl_tcam_data->tbl_tcam_data_low);
  497. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
  498. ptbl_tcam_data->tbl_tcam_data_high);
  499. }
  500. /**
  501. * dsaf_tbl_tcam_mcast_cfg - tbl
  502. * @dsaf_id: dsa fabric id
  503. * @ptbl_tcam_mcast: addr
  504. */
  505. static void hns_dsaf_tbl_tcam_mcast_cfg(
  506. struct dsaf_device *dsaf_dev,
  507. struct dsaf_tbl_tcam_mcast_cfg *mcast)
  508. {
  509. u32 mcast_cfg4;
  510. mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
  511. dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
  512. mcast->tbl_mcast_item_vld);
  513. dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
  514. mcast->tbl_mcast_old_en);
  515. dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
  516. DSAF_TBL_MCAST_CFG4_VM128_112_S,
  517. mcast->tbl_mcast_port_msk[4]);
  518. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
  519. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
  520. mcast->tbl_mcast_port_msk[3]);
  521. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
  522. mcast->tbl_mcast_port_msk[2]);
  523. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
  524. mcast->tbl_mcast_port_msk[1]);
  525. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
  526. mcast->tbl_mcast_port_msk[0]);
  527. }
  528. /**
  529. * hns_dsaf_tbl_tcam_ucast_cfg - tbl
  530. * @dsaf_id: dsa fabric id
  531. * @ptbl_tcam_ucast: addr
  532. */
  533. static void hns_dsaf_tbl_tcam_ucast_cfg(
  534. struct dsaf_device *dsaf_dev,
  535. struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
  536. {
  537. u32 ucast_cfg1;
  538. ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
  539. dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
  540. tbl_tcam_ucast->tbl_ucast_mac_discard);
  541. dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
  542. tbl_tcam_ucast->tbl_ucast_item_vld);
  543. dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
  544. tbl_tcam_ucast->tbl_ucast_old_en);
  545. dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
  546. tbl_tcam_ucast->tbl_ucast_dvc);
  547. dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
  548. DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
  549. tbl_tcam_ucast->tbl_ucast_out_port);
  550. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
  551. }
  552. /**
  553. * hns_dsaf_tbl_line_cfg - tbl
  554. * @dsaf_id: dsa fabric id
  555. * @ptbl_lin: addr
  556. */
  557. static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
  558. struct dsaf_tbl_line_cfg *tbl_lin)
  559. {
  560. u32 tbl_line;
  561. tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
  562. dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
  563. tbl_lin->tbl_line_mac_discard);
  564. dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
  565. tbl_lin->tbl_line_dvc);
  566. dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
  567. DSAF_TBL_LINE_CFG_OUT_PORT_S,
  568. tbl_lin->tbl_line_out_port);
  569. dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
  570. }
  571. /**
  572. * hns_dsaf_tbl_tcam_mcast_pul - tbl
  573. * @dsaf_id: dsa fabric id
  574. */
  575. static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
  576. {
  577. u32 o_tbl_pul;
  578. o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
  579. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
  580. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  581. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
  582. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  583. }
  584. /**
  585. * hns_dsaf_tbl_line_pul - tbl
  586. * @dsaf_id: dsa fabric id
  587. */
  588. static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
  589. {
  590. u32 tbl_pul;
  591. tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
  592. dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
  593. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
  594. dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
  595. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
  596. }
  597. /**
  598. * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
  599. * @dsaf_id: dsa fabric id
  600. */
  601. static void hns_dsaf_tbl_tcam_data_mcast_pul(
  602. struct dsaf_device *dsaf_dev)
  603. {
  604. u32 o_tbl_pul;
  605. o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
  606. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
  607. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
  608. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  609. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
  610. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
  611. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  612. }
  613. /**
  614. * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
  615. * @dsaf_id: dsa fabric id
  616. */
  617. static void hns_dsaf_tbl_tcam_data_ucast_pul(
  618. struct dsaf_device *dsaf_dev)
  619. {
  620. u32 o_tbl_pul;
  621. o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
  622. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
  623. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
  624. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  625. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
  626. dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
  627. dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
  628. }
  629. void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
  630. {
  631. dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_MIX_MODE_S, !!en);
  632. }
  633. void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en)
  634. {
  635. if (AE_IS_VER1(dsaf_dev->dsaf_ver) ||
  636. dsaf_dev->mac_cb[mac_id].mac_type == HNAE_PORT_DEBUG)
  637. return;
  638. dsaf_set_dev_bit(dsaf_dev, DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
  639. DSAFV2_SERDES_LBK_EN_B, !!en);
  640. }
  641. /**
  642. * hns_dsaf_tbl_stat_en - tbl
  643. * @dsaf_id: dsa fabric id
  644. * @ptbl_stat_en: addr
  645. */
  646. static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
  647. {
  648. u32 o_tbl_ctrl;
  649. o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
  650. dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
  651. dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
  652. dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
  653. dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
  654. dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
  655. }
  656. /**
  657. * hns_dsaf_rocee_bp_en - rocee back press enable
  658. * @dsaf_id: dsa fabric id
  659. */
  660. static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
  661. {
  662. if (AE_IS_VER1(dsaf_dev->dsaf_ver))
  663. dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
  664. DSAF_FC_XGE_TX_PAUSE_S, 1);
  665. }
  666. /* set msk for dsaf exception irq*/
  667. static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
  668. u32 chnn_num, u32 mask_set)
  669. {
  670. dsaf_write_dev(dsaf_dev,
  671. DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
  672. }
  673. static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
  674. u32 chnn_num, u32 msk_set)
  675. {
  676. dsaf_write_dev(dsaf_dev,
  677. DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
  678. }
  679. static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
  680. u32 chnn, u32 msk_set)
  681. {
  682. dsaf_write_dev(dsaf_dev,
  683. DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
  684. }
  685. static void
  686. hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
  687. {
  688. dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
  689. }
  690. /* clr dsaf exception irq*/
  691. static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
  692. u32 chnn_num, u32 int_src)
  693. {
  694. dsaf_write_dev(dsaf_dev,
  695. DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
  696. }
  697. static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
  698. u32 chnn, u32 int_src)
  699. {
  700. dsaf_write_dev(dsaf_dev,
  701. DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
  702. }
  703. static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
  704. u32 chnn, u32 int_src)
  705. {
  706. dsaf_write_dev(dsaf_dev,
  707. DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
  708. }
  709. static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
  710. u32 int_src)
  711. {
  712. dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
  713. }
  714. /**
  715. * hns_dsaf_single_line_tbl_cfg - INT
  716. * @dsaf_id: dsa fabric id
  717. * @address:
  718. * @ptbl_line:
  719. */
  720. static void hns_dsaf_single_line_tbl_cfg(
  721. struct dsaf_device *dsaf_dev,
  722. u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
  723. {
  724. /*Write Addr*/
  725. hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
  726. /*Write Line*/
  727. hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
  728. /*Write Plus*/
  729. hns_dsaf_tbl_line_pul(dsaf_dev);
  730. }
  731. /**
  732. * hns_dsaf_tcam_uc_cfg - INT
  733. * @dsaf_id: dsa fabric id
  734. * @address,
  735. * @ptbl_tcam_data,
  736. */
  737. static void hns_dsaf_tcam_uc_cfg(
  738. struct dsaf_device *dsaf_dev, u32 address,
  739. struct dsaf_tbl_tcam_data *ptbl_tcam_data,
  740. struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
  741. {
  742. /*Write Addr*/
  743. hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
  744. /*Write Tcam Data*/
  745. hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
  746. /*Write Tcam Ucast*/
  747. hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
  748. /*Write Plus*/
  749. hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
  750. }
  751. /**
  752. * hns_dsaf_tcam_mc_cfg - INT
  753. * @dsaf_id: dsa fabric id
  754. * @address,
  755. * @ptbl_tcam_data,
  756. * @ptbl_tcam_mcast,
  757. */
  758. static void hns_dsaf_tcam_mc_cfg(
  759. struct dsaf_device *dsaf_dev, u32 address,
  760. struct dsaf_tbl_tcam_data *ptbl_tcam_data,
  761. struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
  762. {
  763. /*Write Addr*/
  764. hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
  765. /*Write Tcam Data*/
  766. hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
  767. /*Write Tcam Mcast*/
  768. hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
  769. /*Write Plus*/
  770. hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
  771. }
  772. /**
  773. * hns_dsaf_tcam_mc_invld - INT
  774. * @dsaf_id: dsa fabric id
  775. * @address
  776. */
  777. static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
  778. {
  779. /*Write Addr*/
  780. hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
  781. /*write tcam mcast*/
  782. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
  783. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
  784. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
  785. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
  786. dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
  787. /*Write Plus*/
  788. hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
  789. }
  790. /**
  791. * hns_dsaf_tcam_uc_get - INT
  792. * @dsaf_id: dsa fabric id
  793. * @address
  794. * @ptbl_tcam_data
  795. * @ptbl_tcam_ucast
  796. */
  797. static void hns_dsaf_tcam_uc_get(
  798. struct dsaf_device *dsaf_dev, u32 address,
  799. struct dsaf_tbl_tcam_data *ptbl_tcam_data,
  800. struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
  801. {
  802. u32 tcam_read_data0;
  803. u32 tcam_read_data4;
  804. /*Write Addr*/
  805. hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
  806. /*read tcam item puls*/
  807. hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
  808. /*read tcam data*/
  809. ptbl_tcam_data->tbl_tcam_data_high
  810. = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
  811. ptbl_tcam_data->tbl_tcam_data_low
  812. = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
  813. /*read tcam mcast*/
  814. tcam_read_data0 = dsaf_read_dev(dsaf_dev,
  815. DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
  816. tcam_read_data4 = dsaf_read_dev(dsaf_dev,
  817. DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
  818. ptbl_tcam_ucast->tbl_ucast_item_vld
  819. = dsaf_get_bit(tcam_read_data4,
  820. DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
  821. ptbl_tcam_ucast->tbl_ucast_old_en
  822. = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
  823. ptbl_tcam_ucast->tbl_ucast_mac_discard
  824. = dsaf_get_bit(tcam_read_data0,
  825. DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
  826. ptbl_tcam_ucast->tbl_ucast_out_port
  827. = dsaf_get_field(tcam_read_data0,
  828. DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
  829. DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
  830. ptbl_tcam_ucast->tbl_ucast_dvc
  831. = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
  832. }
  833. /**
  834. * hns_dsaf_tcam_mc_get - INT
  835. * @dsaf_id: dsa fabric id
  836. * @address
  837. * @ptbl_tcam_data
  838. * @ptbl_tcam_ucast
  839. */
  840. static void hns_dsaf_tcam_mc_get(
  841. struct dsaf_device *dsaf_dev, u32 address,
  842. struct dsaf_tbl_tcam_data *ptbl_tcam_data,
  843. struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
  844. {
  845. u32 data_tmp;
  846. /*Write Addr*/
  847. hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
  848. /*read tcam item puls*/
  849. hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
  850. /*read tcam data*/
  851. ptbl_tcam_data->tbl_tcam_data_high =
  852. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
  853. ptbl_tcam_data->tbl_tcam_data_low =
  854. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
  855. /*read tcam mcast*/
  856. ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
  857. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
  858. ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
  859. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
  860. ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
  861. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
  862. ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
  863. dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
  864. data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
  865. ptbl_tcam_mcast->tbl_mcast_item_vld =
  866. dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
  867. ptbl_tcam_mcast->tbl_mcast_old_en =
  868. dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
  869. ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
  870. dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
  871. DSAF_TBL_MCAST_CFG4_VM128_112_S);
  872. }
  873. /**
  874. * hns_dsaf_tbl_line_init - INT
  875. * @dsaf_id: dsa fabric id
  876. */
  877. static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
  878. {
  879. u32 i;
  880. /* defaultly set all lineal mac table entry resulting discard */
  881. struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
  882. for (i = 0; i < DSAF_LINE_SUM; i++)
  883. hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
  884. }
  885. /**
  886. * hns_dsaf_tbl_tcam_init - INT
  887. * @dsaf_id: dsa fabric id
  888. */
  889. static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
  890. {
  891. u32 i;
  892. struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
  893. struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
  894. /*tcam tbl*/
  895. for (i = 0; i < DSAF_TCAM_SUM; i++)
  896. hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
  897. }
  898. /**
  899. * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
  900. * @mac_cb: mac contrl block
  901. */
  902. static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
  903. int mac_id, int en)
  904. {
  905. if (!en)
  906. dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, 0);
  907. else
  908. dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, 0xff);
  909. }
  910. /**
  911. * hns_dsaf_tbl_tcam_init - INT
  912. * @dsaf_id: dsa fabric id
  913. * @dsaf_mode
  914. */
  915. static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
  916. {
  917. u32 i;
  918. u32 o_dsaf_cfg;
  919. o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
  920. dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
  921. dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
  922. dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
  923. dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
  924. dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
  925. dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
  926. hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
  927. hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
  928. /* set 22 queue per tx ppe engine, only used in switch mode */
  929. hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
  930. /* set promisc def queue id */
  931. hns_dsaf_mix_def_qid_cfg(dsaf_dev);
  932. /* set inner loopback queue id */
  933. hns_dsaf_inner_qid_cfg(dsaf_dev);
  934. /* in non switch mode, set all port to access mode */
  935. hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
  936. /*set dsaf pfc to 0 for parseing rx pause*/
  937. for (i = 0; i < DSAF_COMM_CHN; i++)
  938. hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
  939. /*msk and clr exception irqs */
  940. for (i = 0; i < DSAF_COMM_CHN; i++) {
  941. hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
  942. hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
  943. hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
  944. hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
  945. hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
  946. hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
  947. }
  948. hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
  949. hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
  950. }
  951. /**
  952. * hns_dsaf_inode_init - INT
  953. * @dsaf_id: dsa fabric id
  954. */
  955. static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
  956. {
  957. u32 reg;
  958. u32 tc_cfg;
  959. u32 i;
  960. if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
  961. tc_cfg = HNS_DSAF_I4TC_CFG;
  962. else
  963. tc_cfg = HNS_DSAF_I8TC_CFG;
  964. if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
  965. for (i = 0; i < DSAF_INODE_NUM; i++) {
  966. reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
  967. dsaf_set_dev_field(dsaf_dev, reg,
  968. DSAF_INODE_IN_PORT_NUM_M,
  969. DSAF_INODE_IN_PORT_NUM_S,
  970. i % DSAF_XGE_NUM);
  971. }
  972. } else {
  973. for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
  974. reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
  975. dsaf_set_dev_field(dsaf_dev, reg,
  976. DSAF_INODE_IN_PORT_NUM_M,
  977. DSAF_INODE_IN_PORT_NUM_S, 0);
  978. dsaf_set_dev_field(dsaf_dev, reg,
  979. DSAFV2_INODE_IN_PORT1_NUM_M,
  980. DSAFV2_INODE_IN_PORT1_NUM_S, 1);
  981. dsaf_set_dev_field(dsaf_dev, reg,
  982. DSAFV2_INODE_IN_PORT2_NUM_M,
  983. DSAFV2_INODE_IN_PORT2_NUM_S, 2);
  984. dsaf_set_dev_field(dsaf_dev, reg,
  985. DSAFV2_INODE_IN_PORT3_NUM_M,
  986. DSAFV2_INODE_IN_PORT3_NUM_S, 3);
  987. dsaf_set_dev_field(dsaf_dev, reg,
  988. DSAFV2_INODE_IN_PORT4_NUM_M,
  989. DSAFV2_INODE_IN_PORT4_NUM_S, 4);
  990. dsaf_set_dev_field(dsaf_dev, reg,
  991. DSAFV2_INODE_IN_PORT5_NUM_M,
  992. DSAFV2_INODE_IN_PORT5_NUM_S, 5);
  993. }
  994. }
  995. for (i = 0; i < DSAF_INODE_NUM; i++) {
  996. reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
  997. dsaf_write_dev(dsaf_dev, reg, tc_cfg);
  998. }
  999. }
  1000. /**
  1001. * hns_dsaf_sbm_init - INT
  1002. * @dsaf_id: dsa fabric id
  1003. */
  1004. static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
  1005. {
  1006. u32 flag;
  1007. u32 finish_msk;
  1008. u32 cnt = 0;
  1009. int ret;
  1010. if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
  1011. hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
  1012. finish_msk = DSAF_SRAM_INIT_OVER_M;
  1013. } else {
  1014. hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
  1015. finish_msk = DSAFV2_SRAM_INIT_OVER_M;
  1016. }
  1017. /* enable sbm chanel, disable sbm chanel shcut function*/
  1018. hns_dsaf_sbm_cfg(dsaf_dev);
  1019. /* enable sbm mib */
  1020. ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
  1021. if (ret) {
  1022. dev_err(dsaf_dev->dev,
  1023. "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
  1024. dsaf_dev->ae_dev.name, ret);
  1025. return ret;
  1026. }
  1027. /* enable sbm initial link sram */
  1028. hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
  1029. do {
  1030. usleep_range(200, 210);/*udelay(200);*/
  1031. flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
  1032. finish_msk, DSAF_SRAM_INIT_OVER_S);
  1033. cnt++;
  1034. } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
  1035. cnt < DSAF_CFG_READ_CNT);
  1036. if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
  1037. dev_err(dsaf_dev->dev,
  1038. "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
  1039. dsaf_dev->ae_dev.name, flag, cnt);
  1040. return -ENODEV;
  1041. }
  1042. hns_dsaf_rocee_bp_en(dsaf_dev);
  1043. return 0;
  1044. }
  1045. /**
  1046. * hns_dsaf_tbl_init - INT
  1047. * @dsaf_id: dsa fabric id
  1048. */
  1049. static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
  1050. {
  1051. hns_dsaf_tbl_stat_en(dsaf_dev);
  1052. hns_dsaf_tbl_tcam_init(dsaf_dev);
  1053. hns_dsaf_tbl_line_init(dsaf_dev);
  1054. }
  1055. /**
  1056. * hns_dsaf_voq_init - INT
  1057. * @dsaf_id: dsa fabric id
  1058. */
  1059. static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
  1060. {
  1061. hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
  1062. }
  1063. /**
  1064. * hns_dsaf_init_hw - init dsa fabric hardware
  1065. * @dsaf_dev: dsa fabric device struct pointer
  1066. */
  1067. static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
  1068. {
  1069. int ret;
  1070. dev_dbg(dsaf_dev->dev,
  1071. "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
  1072. hns_dsaf_rst(dsaf_dev, 0);
  1073. mdelay(10);
  1074. hns_dsaf_rst(dsaf_dev, 1);
  1075. hns_dsaf_comm_init(dsaf_dev);
  1076. /*init XBAR_INODE*/
  1077. hns_dsaf_inode_init(dsaf_dev);
  1078. /*init SBM*/
  1079. ret = hns_dsaf_sbm_init(dsaf_dev);
  1080. if (ret)
  1081. return ret;
  1082. /*init TBL*/
  1083. hns_dsaf_tbl_init(dsaf_dev);
  1084. /*init VOQ*/
  1085. hns_dsaf_voq_init(dsaf_dev);
  1086. return 0;
  1087. }
  1088. /**
  1089. * hns_dsaf_remove_hw - uninit dsa fabric hardware
  1090. * @dsaf_dev: dsa fabric device struct pointer
  1091. */
  1092. static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
  1093. {
  1094. /*reset*/
  1095. hns_dsaf_rst(dsaf_dev, 0);
  1096. }
  1097. /**
  1098. * hns_dsaf_init - init dsa fabric
  1099. * @dsaf_dev: dsa fabric device struct pointer
  1100. * retuen 0 - success , negative --fail
  1101. */
  1102. static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
  1103. {
  1104. struct dsaf_drv_priv *priv =
  1105. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1106. u32 i;
  1107. int ret;
  1108. ret = hns_dsaf_init_hw(dsaf_dev);
  1109. if (ret)
  1110. return ret;
  1111. /* malloc mem for tcam mac key(vlan+mac) */
  1112. priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
  1113. * DSAF_TCAM_SUM);
  1114. if (!priv->soft_mac_tbl) {
  1115. ret = -ENOMEM;
  1116. goto remove_hw;
  1117. }
  1118. /*all entry invall */
  1119. for (i = 0; i < DSAF_TCAM_SUM; i++)
  1120. (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
  1121. return 0;
  1122. remove_hw:
  1123. hns_dsaf_remove_hw(dsaf_dev);
  1124. return ret;
  1125. }
  1126. /**
  1127. * hns_dsaf_free - free dsa fabric
  1128. * @dsaf_dev: dsa fabric device struct pointer
  1129. */
  1130. static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
  1131. {
  1132. struct dsaf_drv_priv *priv =
  1133. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1134. hns_dsaf_remove_hw(dsaf_dev);
  1135. /* free all mac mem */
  1136. vfree(priv->soft_mac_tbl);
  1137. priv->soft_mac_tbl = NULL;
  1138. }
  1139. /**
  1140. * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
  1141. * @dsaf_dev: dsa fabric device struct pointer
  1142. * @mac_key: mac entry struct pointer
  1143. */
  1144. static u16 hns_dsaf_find_soft_mac_entry(
  1145. struct dsaf_device *dsaf_dev,
  1146. struct dsaf_drv_tbl_tcam_key *mac_key)
  1147. {
  1148. struct dsaf_drv_priv *priv =
  1149. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1150. struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
  1151. u32 i;
  1152. soft_mac_entry = priv->soft_mac_tbl;
  1153. for (i = 0; i < DSAF_TCAM_SUM; i++) {
  1154. /* invall tab entry */
  1155. if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
  1156. (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
  1157. (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
  1158. /* return find result --soft index */
  1159. return soft_mac_entry->index;
  1160. soft_mac_entry++;
  1161. }
  1162. return DSAF_INVALID_ENTRY_IDX;
  1163. }
  1164. /**
  1165. * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
  1166. * @dsaf_dev: dsa fabric device struct pointer
  1167. */
  1168. static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
  1169. {
  1170. struct dsaf_drv_priv *priv =
  1171. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1172. struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
  1173. u32 i;
  1174. soft_mac_entry = priv->soft_mac_tbl;
  1175. for (i = 0; i < DSAF_TCAM_SUM; i++) {
  1176. /* inv all entry */
  1177. if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
  1178. /* return find result --soft index */
  1179. return i;
  1180. soft_mac_entry++;
  1181. }
  1182. return DSAF_INVALID_ENTRY_IDX;
  1183. }
  1184. /**
  1185. * hns_dsaf_set_mac_key - set mac key
  1186. * @dsaf_dev: dsa fabric device struct pointer
  1187. * @mac_key: tcam key pointer
  1188. * @vlan_id: vlan id
  1189. * @in_port_num: input port num
  1190. * @addr: mac addr
  1191. */
  1192. static void hns_dsaf_set_mac_key(
  1193. struct dsaf_device *dsaf_dev,
  1194. struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
  1195. u8 *addr)
  1196. {
  1197. u8 port;
  1198. if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
  1199. /*DSAF mode : in port id fixed 0*/
  1200. port = 0;
  1201. else
  1202. /*non-dsaf mode*/
  1203. port = in_port_num;
  1204. mac_key->high.bits.mac_0 = addr[0];
  1205. mac_key->high.bits.mac_1 = addr[1];
  1206. mac_key->high.bits.mac_2 = addr[2];
  1207. mac_key->high.bits.mac_3 = addr[3];
  1208. mac_key->low.bits.mac_4 = addr[4];
  1209. mac_key->low.bits.mac_5 = addr[5];
  1210. mac_key->low.bits.vlan = vlan_id;
  1211. mac_key->low.bits.port = port;
  1212. }
  1213. /**
  1214. * hns_dsaf_set_mac_uc_entry - set mac uc-entry
  1215. * @dsaf_dev: dsa fabric device struct pointer
  1216. * @mac_entry: uc-mac entry
  1217. */
  1218. int hns_dsaf_set_mac_uc_entry(
  1219. struct dsaf_device *dsaf_dev,
  1220. struct dsaf_drv_mac_single_dest_entry *mac_entry)
  1221. {
  1222. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1223. struct dsaf_drv_tbl_tcam_key mac_key;
  1224. struct dsaf_tbl_tcam_ucast_cfg mac_data;
  1225. struct dsaf_drv_priv *priv =
  1226. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1227. struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
  1228. /* mac addr check */
  1229. if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
  1230. MAC_IS_BROADCAST(mac_entry->addr) ||
  1231. MAC_IS_MULTICAST(mac_entry->addr)) {
  1232. dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
  1233. dsaf_dev->ae_dev.name, mac_entry->addr);
  1234. return -EINVAL;
  1235. }
  1236. /* config key */
  1237. hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
  1238. mac_entry->in_port_num, mac_entry->addr);
  1239. /* entry ie exist? */
  1240. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1241. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1242. /*if has not inv entry,find a empty entry */
  1243. entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
  1244. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1245. /* has not empty,return error */
  1246. dev_err(dsaf_dev->dev,
  1247. "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
  1248. dsaf_dev->ae_dev.name,
  1249. mac_key.high.val, mac_key.low.val);
  1250. return -EINVAL;
  1251. }
  1252. }
  1253. dev_dbg(dsaf_dev->dev,
  1254. "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
  1255. dsaf_dev->ae_dev.name, mac_key.high.val,
  1256. mac_key.low.val, entry_index);
  1257. /* config hardware entry */
  1258. mac_data.tbl_ucast_item_vld = 1;
  1259. mac_data.tbl_ucast_mac_discard = 0;
  1260. mac_data.tbl_ucast_old_en = 0;
  1261. /* default config dvc to 0 */
  1262. mac_data.tbl_ucast_dvc = 0;
  1263. mac_data.tbl_ucast_out_port = mac_entry->port_num;
  1264. hns_dsaf_tcam_uc_cfg(
  1265. dsaf_dev, entry_index,
  1266. (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
  1267. /* config software entry */
  1268. soft_mac_entry += entry_index;
  1269. soft_mac_entry->index = entry_index;
  1270. soft_mac_entry->tcam_key.high.val = mac_key.high.val;
  1271. soft_mac_entry->tcam_key.low.val = mac_key.low.val;
  1272. return 0;
  1273. }
  1274. /**
  1275. * hns_dsaf_set_mac_mc_entry - set mac mc-entry
  1276. * @dsaf_dev: dsa fabric device struct pointer
  1277. * @mac_entry: mc-mac entry
  1278. */
  1279. int hns_dsaf_set_mac_mc_entry(
  1280. struct dsaf_device *dsaf_dev,
  1281. struct dsaf_drv_mac_multi_dest_entry *mac_entry)
  1282. {
  1283. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1284. struct dsaf_drv_tbl_tcam_key mac_key;
  1285. struct dsaf_tbl_tcam_mcast_cfg mac_data;
  1286. struct dsaf_drv_priv *priv =
  1287. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1288. struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
  1289. struct dsaf_drv_tbl_tcam_key tmp_mac_key;
  1290. /* mac addr check */
  1291. if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
  1292. dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n",
  1293. dsaf_dev->ae_dev.name, mac_entry->addr);
  1294. return -EINVAL;
  1295. }
  1296. /*config key */
  1297. hns_dsaf_set_mac_key(dsaf_dev, &mac_key,
  1298. mac_entry->in_vlan_id,
  1299. mac_entry->in_port_num, mac_entry->addr);
  1300. /* entry ie exist? */
  1301. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1302. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1303. /*if hasnot, find enpty entry*/
  1304. entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
  1305. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1306. /*if hasnot empty, error*/
  1307. dev_err(dsaf_dev->dev,
  1308. "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
  1309. dsaf_dev->ae_dev.name,
  1310. mac_key.high.val, mac_key.low.val);
  1311. return -EINVAL;
  1312. }
  1313. /* config hardware entry */
  1314. memset(mac_data.tbl_mcast_port_msk,
  1315. 0, sizeof(mac_data.tbl_mcast_port_msk));
  1316. } else {
  1317. /* config hardware entry */
  1318. hns_dsaf_tcam_mc_get(
  1319. dsaf_dev, entry_index,
  1320. (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
  1321. }
  1322. mac_data.tbl_mcast_old_en = 0;
  1323. mac_data.tbl_mcast_item_vld = 1;
  1324. dsaf_set_field(mac_data.tbl_mcast_port_msk[0],
  1325. 0x3F, 0, mac_entry->port_mask[0]);
  1326. dev_dbg(dsaf_dev->dev,
  1327. "set_uc_entry, %s key(%#x:%#x) entry_index%d\n",
  1328. dsaf_dev->ae_dev.name, mac_key.high.val,
  1329. mac_key.low.val, entry_index);
  1330. hns_dsaf_tcam_mc_cfg(
  1331. dsaf_dev, entry_index,
  1332. (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
  1333. /* config software entry */
  1334. soft_mac_entry += entry_index;
  1335. soft_mac_entry->index = entry_index;
  1336. soft_mac_entry->tcam_key.high.val = mac_key.high.val;
  1337. soft_mac_entry->tcam_key.low.val = mac_key.low.val;
  1338. return 0;
  1339. }
  1340. /**
  1341. * hns_dsaf_add_mac_mc_port - add mac mc-port
  1342. * @dsaf_dev: dsa fabric device struct pointer
  1343. * @mac_entry: mc-mac entry
  1344. */
  1345. int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
  1346. struct dsaf_drv_mac_single_dest_entry *mac_entry)
  1347. {
  1348. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1349. struct dsaf_drv_tbl_tcam_key mac_key;
  1350. struct dsaf_tbl_tcam_mcast_cfg mac_data;
  1351. struct dsaf_drv_priv *priv =
  1352. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1353. struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
  1354. struct dsaf_drv_tbl_tcam_key tmp_mac_key;
  1355. int mskid;
  1356. /*chechk mac addr */
  1357. if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
  1358. dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
  1359. mac_entry->addr);
  1360. return -EINVAL;
  1361. }
  1362. /*config key */
  1363. hns_dsaf_set_mac_key(
  1364. dsaf_dev, &mac_key, mac_entry->in_vlan_id,
  1365. mac_entry->in_port_num, mac_entry->addr);
  1366. memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
  1367. /*check exist? */
  1368. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1369. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1370. /*if hasnot , find a empty*/
  1371. entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
  1372. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1373. /*if hasnot empty, error*/
  1374. dev_err(dsaf_dev->dev,
  1375. "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
  1376. dsaf_dev->ae_dev.name, mac_key.high.val,
  1377. mac_key.low.val);
  1378. return -EINVAL;
  1379. }
  1380. } else {
  1381. /*if exist, add in */
  1382. hns_dsaf_tcam_mc_get(
  1383. dsaf_dev, entry_index,
  1384. (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
  1385. }
  1386. /* config hardware entry */
  1387. if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
  1388. mskid = mac_entry->port_num;
  1389. } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
  1390. mskid = mac_entry->port_num -
  1391. DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
  1392. } else {
  1393. dev_err(dsaf_dev->dev,
  1394. "%s,pnum(%d)error,key(%#x:%#x)\n",
  1395. dsaf_dev->ae_dev.name, mac_entry->port_num,
  1396. mac_key.high.val, mac_key.low.val);
  1397. return -EINVAL;
  1398. }
  1399. dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
  1400. mac_data.tbl_mcast_old_en = 0;
  1401. mac_data.tbl_mcast_item_vld = 1;
  1402. dev_dbg(dsaf_dev->dev,
  1403. "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
  1404. dsaf_dev->ae_dev.name, mac_key.high.val,
  1405. mac_key.low.val, entry_index);
  1406. hns_dsaf_tcam_mc_cfg(
  1407. dsaf_dev, entry_index,
  1408. (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
  1409. /*config software entry */
  1410. soft_mac_entry += entry_index;
  1411. soft_mac_entry->index = entry_index;
  1412. soft_mac_entry->tcam_key.high.val = mac_key.high.val;
  1413. soft_mac_entry->tcam_key.low.val = mac_key.low.val;
  1414. return 0;
  1415. }
  1416. /**
  1417. * hns_dsaf_del_mac_entry - del mac mc-port
  1418. * @dsaf_dev: dsa fabric device struct pointer
  1419. * @vlan_id: vlian id
  1420. * @in_port_num: input port num
  1421. * @addr : mac addr
  1422. */
  1423. int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
  1424. u8 in_port_num, u8 *addr)
  1425. {
  1426. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1427. struct dsaf_drv_tbl_tcam_key mac_key;
  1428. struct dsaf_drv_priv *priv =
  1429. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1430. struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
  1431. /*check mac addr */
  1432. if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
  1433. dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
  1434. addr);
  1435. return -EINVAL;
  1436. }
  1437. /*config key */
  1438. hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
  1439. /*exist ?*/
  1440. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1441. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1442. /*not exist, error */
  1443. dev_err(dsaf_dev->dev,
  1444. "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
  1445. dsaf_dev->ae_dev.name,
  1446. mac_key.high.val, mac_key.low.val);
  1447. return -EINVAL;
  1448. }
  1449. dev_dbg(dsaf_dev->dev,
  1450. "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
  1451. dsaf_dev->ae_dev.name, mac_key.high.val,
  1452. mac_key.low.val, entry_index);
  1453. /*do del opt*/
  1454. hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
  1455. /*del soft emtry */
  1456. soft_mac_entry += entry_index;
  1457. soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
  1458. return 0;
  1459. }
  1460. /**
  1461. * hns_dsaf_del_mac_mc_port - del mac mc- port
  1462. * @dsaf_dev: dsa fabric device struct pointer
  1463. * @mac_entry: mac entry
  1464. */
  1465. int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
  1466. struct dsaf_drv_mac_single_dest_entry *mac_entry)
  1467. {
  1468. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1469. struct dsaf_drv_tbl_tcam_key mac_key;
  1470. struct dsaf_drv_priv *priv =
  1471. (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
  1472. struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
  1473. u16 vlan_id;
  1474. u8 in_port_num;
  1475. struct dsaf_tbl_tcam_mcast_cfg mac_data;
  1476. struct dsaf_drv_tbl_tcam_key tmp_mac_key;
  1477. int mskid;
  1478. const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
  1479. if (!(void *)mac_entry) {
  1480. dev_err(dsaf_dev->dev,
  1481. "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
  1482. return -EINVAL;
  1483. }
  1484. /*get key info*/
  1485. vlan_id = mac_entry->in_vlan_id;
  1486. in_port_num = mac_entry->in_port_num;
  1487. /*check mac addr */
  1488. if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
  1489. dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
  1490. mac_entry->addr);
  1491. return -EINVAL;
  1492. }
  1493. /*config key */
  1494. hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num,
  1495. mac_entry->addr);
  1496. /*check is exist? */
  1497. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1498. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1499. /*find none */
  1500. dev_err(dsaf_dev->dev,
  1501. "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
  1502. dsaf_dev->ae_dev.name,
  1503. mac_key.high.val, mac_key.low.val);
  1504. return -EINVAL;
  1505. }
  1506. dev_dbg(dsaf_dev->dev,
  1507. "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
  1508. dsaf_dev->ae_dev.name, mac_key.high.val,
  1509. mac_key.low.val, entry_index);
  1510. /*read entry*/
  1511. hns_dsaf_tcam_mc_get(
  1512. dsaf_dev, entry_index,
  1513. (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
  1514. /*del the port*/
  1515. if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
  1516. mskid = mac_entry->port_num;
  1517. } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
  1518. mskid = mac_entry->port_num -
  1519. DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
  1520. } else {
  1521. dev_err(dsaf_dev->dev,
  1522. "%s,pnum(%d)error,key(%#x:%#x)\n",
  1523. dsaf_dev->ae_dev.name, mac_entry->port_num,
  1524. mac_key.high.val, mac_key.low.val);
  1525. return -EINVAL;
  1526. }
  1527. dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
  1528. /*check non port, do del entry */
  1529. if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
  1530. sizeof(mac_data.tbl_mcast_port_msk))) {
  1531. hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
  1532. /* del soft entry */
  1533. soft_mac_entry += entry_index;
  1534. soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
  1535. } else { /* not zer, just del port, updata*/
  1536. hns_dsaf_tcam_mc_cfg(
  1537. dsaf_dev, entry_index,
  1538. (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data);
  1539. }
  1540. return 0;
  1541. }
  1542. /**
  1543. * hns_dsaf_get_mac_uc_entry - get mac uc entry
  1544. * @dsaf_dev: dsa fabric device struct pointer
  1545. * @mac_entry: mac entry
  1546. */
  1547. int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
  1548. struct dsaf_drv_mac_single_dest_entry *mac_entry)
  1549. {
  1550. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1551. struct dsaf_drv_tbl_tcam_key mac_key;
  1552. struct dsaf_tbl_tcam_ucast_cfg mac_data;
  1553. /* check macaddr */
  1554. if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
  1555. MAC_IS_BROADCAST(mac_entry->addr)) {
  1556. dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
  1557. mac_entry->addr);
  1558. return -EINVAL;
  1559. }
  1560. /*config key */
  1561. hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
  1562. mac_entry->in_port_num, mac_entry->addr);
  1563. /*check exist? */
  1564. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1565. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1566. /*find none, error */
  1567. dev_err(dsaf_dev->dev,
  1568. "get_uc_entry failed, %s Mac key(%#x:%#x)\n",
  1569. dsaf_dev->ae_dev.name,
  1570. mac_key.high.val, mac_key.low.val);
  1571. return -EINVAL;
  1572. }
  1573. dev_dbg(dsaf_dev->dev,
  1574. "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
  1575. dsaf_dev->ae_dev.name, mac_key.high.val,
  1576. mac_key.low.val, entry_index);
  1577. /*read entry*/
  1578. hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
  1579. (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
  1580. mac_entry->port_num = mac_data.tbl_ucast_out_port;
  1581. return 0;
  1582. }
  1583. /**
  1584. * hns_dsaf_get_mac_mc_entry - get mac mc entry
  1585. * @dsaf_dev: dsa fabric device struct pointer
  1586. * @mac_entry: mac entry
  1587. */
  1588. int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
  1589. struct dsaf_drv_mac_multi_dest_entry *mac_entry)
  1590. {
  1591. u16 entry_index = DSAF_INVALID_ENTRY_IDX;
  1592. struct dsaf_drv_tbl_tcam_key mac_key;
  1593. struct dsaf_tbl_tcam_mcast_cfg mac_data;
  1594. /*check mac addr */
  1595. if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
  1596. MAC_IS_BROADCAST(mac_entry->addr)) {
  1597. dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
  1598. mac_entry->addr);
  1599. return -EINVAL;
  1600. }
  1601. /*config key */
  1602. hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
  1603. mac_entry->in_port_num, mac_entry->addr);
  1604. /*check exist? */
  1605. entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
  1606. if (entry_index == DSAF_INVALID_ENTRY_IDX) {
  1607. /* find none, error */
  1608. dev_err(dsaf_dev->dev,
  1609. "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n",
  1610. dsaf_dev->ae_dev.name, mac_key.high.val,
  1611. mac_key.low.val);
  1612. return -EINVAL;
  1613. }
  1614. dev_dbg(dsaf_dev->dev,
  1615. "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
  1616. dsaf_dev->ae_dev.name, mac_key.high.val,
  1617. mac_key.low.val, entry_index);
  1618. /*read entry */
  1619. hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
  1620. (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
  1621. mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
  1622. return 0;
  1623. }
  1624. /**
  1625. * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index
  1626. * @dsaf_dev: dsa fabric device struct pointer
  1627. * @entry_index: tab entry index
  1628. * @mac_entry: mac entry
  1629. */
  1630. int hns_dsaf_get_mac_entry_by_index(
  1631. struct dsaf_device *dsaf_dev,
  1632. u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry)
  1633. {
  1634. struct dsaf_drv_tbl_tcam_key mac_key;
  1635. struct dsaf_tbl_tcam_mcast_cfg mac_data;
  1636. struct dsaf_tbl_tcam_ucast_cfg mac_uc_data;
  1637. char mac_addr[MAC_NUM_OCTETS_PER_ADDR] = {0};
  1638. if (entry_index >= DSAF_TCAM_SUM) {
  1639. /* find none, del error */
  1640. dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n",
  1641. dsaf_dev->ae_dev.name);
  1642. return -EINVAL;
  1643. }
  1644. /* mc entry, do read opt */
  1645. hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
  1646. (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
  1647. mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
  1648. /***get mac addr*/
  1649. mac_addr[0] = mac_key.high.bits.mac_0;
  1650. mac_addr[1] = mac_key.high.bits.mac_1;
  1651. mac_addr[2] = mac_key.high.bits.mac_2;
  1652. mac_addr[3] = mac_key.high.bits.mac_3;
  1653. mac_addr[4] = mac_key.low.bits.mac_4;
  1654. mac_addr[5] = mac_key.low.bits.mac_5;
  1655. /**is mc or uc*/
  1656. if (MAC_IS_MULTICAST((u8 *)mac_addr) ||
  1657. MAC_IS_L3_MULTICAST((u8 *)mac_addr)) {
  1658. /**mc donot do*/
  1659. } else {
  1660. /*is not mc, just uc... */
  1661. hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
  1662. (struct dsaf_tbl_tcam_data *)&mac_key,
  1663. &mac_uc_data);
  1664. mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port);
  1665. }
  1666. return 0;
  1667. }
  1668. static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
  1669. size_t sizeof_priv)
  1670. {
  1671. struct dsaf_device *dsaf_dev;
  1672. dsaf_dev = devm_kzalloc(dev,
  1673. sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
  1674. if (unlikely(!dsaf_dev)) {
  1675. dsaf_dev = ERR_PTR(-ENOMEM);
  1676. } else {
  1677. dsaf_dev->dev = dev;
  1678. dev_set_drvdata(dev, dsaf_dev);
  1679. }
  1680. return dsaf_dev;
  1681. }
  1682. /**
  1683. * hns_dsaf_free_dev - free dev mem
  1684. * @dev: struct device pointer
  1685. */
  1686. static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
  1687. {
  1688. (void)dev_set_drvdata(dsaf_dev->dev, NULL);
  1689. }
  1690. /**
  1691. * dsaf_pfc_unit_cnt - set pfc unit count
  1692. * @dsaf_id: dsa fabric id
  1693. * @pport_rate: value array
  1694. * @pdsaf_pfc_unit_cnt: value array
  1695. */
  1696. static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id,
  1697. enum dsaf_port_rate_mode rate)
  1698. {
  1699. u32 unit_cnt;
  1700. switch (rate) {
  1701. case DSAF_PORT_RATE_10000:
  1702. unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
  1703. break;
  1704. case DSAF_PORT_RATE_1000:
  1705. unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
  1706. break;
  1707. case DSAF_PORT_RATE_2500:
  1708. unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
  1709. break;
  1710. default:
  1711. unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
  1712. }
  1713. dsaf_set_dev_field(dsaf_dev,
  1714. (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
  1715. DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
  1716. unit_cnt);
  1717. }
  1718. /**
  1719. * dsaf_port_work_rate_cfg - fifo
  1720. * @dsaf_id: dsa fabric id
  1721. * @xge_ge_work_mode
  1722. */
  1723. void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
  1724. enum dsaf_port_rate_mode rate_mode)
  1725. {
  1726. u32 port_work_mode;
  1727. port_work_mode = dsaf_read_dev(
  1728. dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
  1729. if (rate_mode == DSAF_PORT_RATE_10000)
  1730. dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
  1731. else
  1732. dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
  1733. dsaf_write_dev(dsaf_dev,
  1734. DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
  1735. port_work_mode);
  1736. hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
  1737. }
  1738. /**
  1739. * hns_dsaf_fix_mac_mode - dsaf modify mac mode
  1740. * @mac_cb: mac contrl block
  1741. */
  1742. void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
  1743. {
  1744. enum dsaf_port_rate_mode mode;
  1745. struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
  1746. int mac_id = mac_cb->mac_id;
  1747. if (mac_cb->mac_type != HNAE_PORT_SERVICE)
  1748. return;
  1749. if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
  1750. mode = DSAF_PORT_RATE_10000;
  1751. else
  1752. mode = DSAF_PORT_RATE_1000;
  1753. hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
  1754. }
  1755. void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
  1756. {
  1757. struct dsaf_hw_stats *hw_stats
  1758. = &dsaf_dev->hw_stats[node_num];
  1759. hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
  1760. DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
  1761. hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
  1762. DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
  1763. hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
  1764. DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
  1765. hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
  1766. DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
  1767. hw_stats->rx_pause_frame += dsaf_read_dev(dsaf_dev,
  1768. DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG + 0x80 * (u64)node_num);
  1769. hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
  1770. DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
  1771. hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
  1772. DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
  1773. hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
  1774. DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
  1775. hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
  1776. DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
  1777. hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
  1778. DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
  1779. hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
  1780. DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
  1781. hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
  1782. DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
  1783. hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
  1784. DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
  1785. hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
  1786. DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
  1787. }
  1788. /**
  1789. *hns_dsaf_get_regs - dump dsaf regs
  1790. *@dsaf_dev: dsaf device
  1791. *@data:data for value of regs
  1792. */
  1793. void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
  1794. {
  1795. u32 i = 0;
  1796. u32 j;
  1797. u32 *p = data;
  1798. /* dsaf common registers */
  1799. p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
  1800. p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
  1801. p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
  1802. p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
  1803. p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
  1804. p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
  1805. p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
  1806. p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
  1807. p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
  1808. p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
  1809. p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
  1810. p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
  1811. p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
  1812. p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
  1813. p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
  1814. p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
  1815. p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
  1816. p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
  1817. p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
  1818. p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
  1819. p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
  1820. p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
  1821. p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
  1822. p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
  1823. for (i = 0; i < DSAF_SW_PORT_NUM; i++)
  1824. p[24 + i] = dsaf_read_dev(ddev,
  1825. DSAF_SW_PORT_TYPE_0_REG + i * 4);
  1826. p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
  1827. for (i = 0; i < DSAF_SW_PORT_NUM; i++)
  1828. p[33 + i] = dsaf_read_dev(ddev,
  1829. DSAF_PORT_DEF_VLAN_0_REG + i * 4);
  1830. for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
  1831. p[41 + i] = dsaf_read_dev(ddev,
  1832. DSAF_VM_DEF_VLAN_0_REG + i * 4);
  1833. /* dsaf inode registers */
  1834. p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
  1835. p[171] = dsaf_read_dev(ddev,
  1836. DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
  1837. for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
  1838. j = i * DSAF_COMM_CHN + port;
  1839. p[172 + i] = dsaf_read_dev(ddev,
  1840. DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
  1841. p[175 + i] = dsaf_read_dev(ddev,
  1842. DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
  1843. p[178 + i] = dsaf_read_dev(ddev,
  1844. DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
  1845. p[181 + i] = dsaf_read_dev(ddev,
  1846. DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
  1847. p[184 + i] = dsaf_read_dev(ddev,
  1848. DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
  1849. p[187 + i] = dsaf_read_dev(ddev,
  1850. DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
  1851. p[190 + i] = dsaf_read_dev(ddev,
  1852. DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
  1853. p[193 + i] = dsaf_read_dev(ddev,
  1854. DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG + j * 0x80);
  1855. p[196 + i] = dsaf_read_dev(ddev,
  1856. DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
  1857. p[199 + i] = dsaf_read_dev(ddev,
  1858. DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
  1859. p[202 + i] = dsaf_read_dev(ddev,
  1860. DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
  1861. p[205 + i] = dsaf_read_dev(ddev,
  1862. DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
  1863. p[208 + i] = dsaf_read_dev(ddev,
  1864. DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
  1865. p[211 + i] = dsaf_read_dev(ddev,
  1866. DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
  1867. p[214 + i] = dsaf_read_dev(ddev,
  1868. DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
  1869. p[217 + i] = dsaf_read_dev(ddev,
  1870. DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
  1871. p[220 + i] = dsaf_read_dev(ddev,
  1872. DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
  1873. p[223 + i] = dsaf_read_dev(ddev,
  1874. DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
  1875. p[224 + i] = dsaf_read_dev(ddev,
  1876. DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
  1877. }
  1878. p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
  1879. for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
  1880. j = i * DSAF_COMM_CHN + port;
  1881. p[228 + i] = dsaf_read_dev(ddev,
  1882. DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
  1883. }
  1884. p[231] = dsaf_read_dev(ddev,
  1885. DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
  1886. /* dsaf inode registers */
  1887. for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
  1888. j = i * DSAF_COMM_CHN + port;
  1889. p[232 + i] = dsaf_read_dev(ddev,
  1890. DSAF_SBM_CFG_REG_0_REG + j * 0x80);
  1891. p[235 + i] = dsaf_read_dev(ddev,
  1892. DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
  1893. p[238 + i] = dsaf_read_dev(ddev,
  1894. DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
  1895. p[241 + i] = dsaf_read_dev(ddev,
  1896. DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
  1897. p[244 + i] = dsaf_read_dev(ddev,
  1898. DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
  1899. p[245 + i] = dsaf_read_dev(ddev,
  1900. DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
  1901. p[248 + i] = dsaf_read_dev(ddev,
  1902. DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
  1903. p[251 + i] = dsaf_read_dev(ddev,
  1904. DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
  1905. p[254 + i] = dsaf_read_dev(ddev,
  1906. DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
  1907. p[257 + i] = dsaf_read_dev(ddev,
  1908. DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
  1909. p[260 + i] = dsaf_read_dev(ddev,
  1910. DSAF_SBM_INER_ST_0_REG + j * 0x80);
  1911. p[263 + i] = dsaf_read_dev(ddev,
  1912. DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
  1913. p[266 + i] = dsaf_read_dev(ddev,
  1914. DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
  1915. p[269 + i] = dsaf_read_dev(ddev,
  1916. DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
  1917. p[272 + i] = dsaf_read_dev(ddev,
  1918. DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
  1919. p[275 + i] = dsaf_read_dev(ddev,
  1920. DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
  1921. p[278 + i] = dsaf_read_dev(ddev,
  1922. DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
  1923. p[281 + i] = dsaf_read_dev(ddev,
  1924. DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
  1925. p[284 + i] = dsaf_read_dev(ddev,
  1926. DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
  1927. p[287 + i] = dsaf_read_dev(ddev,
  1928. DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
  1929. p[290 + i] = dsaf_read_dev(ddev,
  1930. DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
  1931. p[293 + i] = dsaf_read_dev(ddev,
  1932. DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
  1933. p[296 + i] = dsaf_read_dev(ddev,
  1934. DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
  1935. p[299 + i] = dsaf_read_dev(ddev,
  1936. DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
  1937. p[302 + i] = dsaf_read_dev(ddev,
  1938. DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
  1939. p[305 + i] = dsaf_read_dev(ddev,
  1940. DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
  1941. p[308 + i] = dsaf_read_dev(ddev,
  1942. DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
  1943. }
  1944. /* dsaf onode registers */
  1945. for (i = 0; i < DSAF_XOD_NUM; i++) {
  1946. p[311 + i] = dsaf_read_dev(ddev,
  1947. DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
  1948. p[319 + i] = dsaf_read_dev(ddev,
  1949. DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
  1950. p[327 + i] = dsaf_read_dev(ddev,
  1951. DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
  1952. p[335 + i] = dsaf_read_dev(ddev,
  1953. DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
  1954. p[343 + i] = dsaf_read_dev(ddev,
  1955. DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
  1956. p[351 + i] = dsaf_read_dev(ddev,
  1957. DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
  1958. }
  1959. p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
  1960. p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
  1961. p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
  1962. for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
  1963. j = i * DSAF_COMM_CHN + port;
  1964. p[362 + i] = dsaf_read_dev(ddev,
  1965. DSAF_XOD_GNT_L_0_REG + j * 0x90);
  1966. p[365 + i] = dsaf_read_dev(ddev,
  1967. DSAF_XOD_GNT_H_0_REG + j * 0x90);
  1968. p[368 + i] = dsaf_read_dev(ddev,
  1969. DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
  1970. p[371 + i] = dsaf_read_dev(ddev,
  1971. DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
  1972. p[374 + i] = dsaf_read_dev(ddev,
  1973. DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
  1974. p[377 + i] = dsaf_read_dev(ddev,
  1975. DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
  1976. p[380 + i] = dsaf_read_dev(ddev,
  1977. DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
  1978. p[383 + i] = dsaf_read_dev(ddev,
  1979. DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
  1980. p[386 + i] = dsaf_read_dev(ddev,
  1981. DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
  1982. p[389 + i] = dsaf_read_dev(ddev,
  1983. DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
  1984. }
  1985. p[392] = dsaf_read_dev(ddev,
  1986. DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
  1987. p[393] = dsaf_read_dev(ddev,
  1988. DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
  1989. p[394] = dsaf_read_dev(ddev,
  1990. DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
  1991. p[395] = dsaf_read_dev(ddev,
  1992. DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
  1993. p[396] = dsaf_read_dev(ddev,
  1994. DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
  1995. p[397] = dsaf_read_dev(ddev,
  1996. DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
  1997. p[398] = dsaf_read_dev(ddev,
  1998. DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
  1999. p[399] = dsaf_read_dev(ddev,
  2000. DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
  2001. p[400] = dsaf_read_dev(ddev,
  2002. DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
  2003. p[401] = dsaf_read_dev(ddev,
  2004. DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
  2005. p[402] = dsaf_read_dev(ddev,
  2006. DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
  2007. p[403] = dsaf_read_dev(ddev,
  2008. DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
  2009. p[404] = dsaf_read_dev(ddev,
  2010. DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
  2011. /* dsaf voq registers */
  2012. for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
  2013. j = (i * DSAF_COMM_CHN + port) * 0x90;
  2014. p[405 + i] = dsaf_read_dev(ddev,
  2015. DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
  2016. p[408 + i] = dsaf_read_dev(ddev,
  2017. DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
  2018. p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
  2019. p[414 + i] = dsaf_read_dev(ddev,
  2020. DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
  2021. p[417 + i] = dsaf_read_dev(ddev,
  2022. DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
  2023. p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
  2024. p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
  2025. p[426 + i] = dsaf_read_dev(ddev,
  2026. DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
  2027. p[429 + i] = dsaf_read_dev(ddev,
  2028. DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
  2029. p[432 + i] = dsaf_read_dev(ddev,
  2030. DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
  2031. p[435 + i] = dsaf_read_dev(ddev,
  2032. DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
  2033. p[438 + i] = dsaf_read_dev(ddev,
  2034. DSAF_VOQ_BP_ALL_THRD_0_REG + j);
  2035. }
  2036. /* dsaf tbl registers */
  2037. p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
  2038. p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
  2039. p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
  2040. p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
  2041. p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
  2042. p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
  2043. p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
  2044. p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
  2045. p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
  2046. p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
  2047. p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
  2048. p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
  2049. p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
  2050. p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
  2051. p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
  2052. p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
  2053. p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
  2054. p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
  2055. p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
  2056. p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
  2057. p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
  2058. p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
  2059. p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
  2060. for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
  2061. j = i * 0x8;
  2062. p[464 + 2 * i] = dsaf_read_dev(ddev,
  2063. DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
  2064. p[465 + 2 * i] = dsaf_read_dev(ddev,
  2065. DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
  2066. }
  2067. p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
  2068. p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
  2069. p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
  2070. p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
  2071. p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
  2072. p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
  2073. p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
  2074. p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
  2075. p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
  2076. p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
  2077. p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
  2078. p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
  2079. /* dsaf other registers */
  2080. p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
  2081. p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
  2082. p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
  2083. p[495] = dsaf_read_dev(ddev,
  2084. DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
  2085. p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
  2086. p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
  2087. /* mark end of dsaf regs */
  2088. for (i = 498; i < 504; i++)
  2089. p[i] = 0xdddddddd;
  2090. }
  2091. static char *hns_dsaf_get_node_stats_strings(char *data, int node)
  2092. {
  2093. char *buff = data;
  2094. snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
  2095. buff = buff + ETH_GSTRING_LEN;
  2096. snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
  2097. buff = buff + ETH_GSTRING_LEN;
  2098. snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
  2099. buff = buff + ETH_GSTRING_LEN;
  2100. snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
  2101. buff = buff + ETH_GSTRING_LEN;
  2102. snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
  2103. buff = buff + ETH_GSTRING_LEN;
  2104. snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
  2105. buff = buff + ETH_GSTRING_LEN;
  2106. snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
  2107. buff = buff + ETH_GSTRING_LEN;
  2108. snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
  2109. buff = buff + ETH_GSTRING_LEN;
  2110. snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
  2111. buff = buff + ETH_GSTRING_LEN;
  2112. snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
  2113. buff = buff + ETH_GSTRING_LEN;
  2114. snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
  2115. buff = buff + ETH_GSTRING_LEN;
  2116. snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
  2117. buff = buff + ETH_GSTRING_LEN;
  2118. snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
  2119. buff = buff + ETH_GSTRING_LEN;
  2120. snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
  2121. buff = buff + ETH_GSTRING_LEN;
  2122. return buff;
  2123. }
  2124. static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
  2125. int node_num)
  2126. {
  2127. u64 *p = data;
  2128. struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
  2129. p[0] = hw_stats->pad_drop;
  2130. p[1] = hw_stats->man_pkts;
  2131. p[2] = hw_stats->rx_pkts;
  2132. p[3] = hw_stats->rx_pkt_id;
  2133. p[4] = hw_stats->rx_pause_frame;
  2134. p[5] = hw_stats->release_buf_num;
  2135. p[6] = hw_stats->sbm_drop;
  2136. p[7] = hw_stats->crc_false;
  2137. p[8] = hw_stats->bp_drop;
  2138. p[9] = hw_stats->rslt_drop;
  2139. p[10] = hw_stats->local_addr_false;
  2140. p[11] = hw_stats->vlan_drop;
  2141. p[12] = hw_stats->stp_drop;
  2142. p[13] = hw_stats->tx_pkts;
  2143. return &p[14];
  2144. }
  2145. /**
  2146. *hns_dsaf_get_stats - get dsaf statistic
  2147. *@ddev: dsaf device
  2148. *@data:statistic value
  2149. *@port: port num
  2150. */
  2151. void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
  2152. {
  2153. u64 *p = data;
  2154. int node_num = port;
  2155. /* for ge/xge node info */
  2156. p = hns_dsaf_get_node_stats(ddev, p, node_num);
  2157. /* for ppe node info */
  2158. node_num = port + DSAF_PPE_INODE_BASE;
  2159. (void)hns_dsaf_get_node_stats(ddev, p, node_num);
  2160. }
  2161. /**
  2162. *hns_dsaf_get_sset_count - get dsaf string set count
  2163. *@stringset: type of values in data
  2164. *return dsaf string name count
  2165. */
  2166. int hns_dsaf_get_sset_count(int stringset)
  2167. {
  2168. if (stringset == ETH_SS_STATS)
  2169. return DSAF_STATIC_NUM;
  2170. return 0;
  2171. }
  2172. /**
  2173. *hns_dsaf_get_strings - get dsaf string set
  2174. *@stringset:srting set index
  2175. *@data:strings name value
  2176. *@port:port index
  2177. */
  2178. void hns_dsaf_get_strings(int stringset, u8 *data, int port)
  2179. {
  2180. char *buff = (char *)data;
  2181. int node = port;
  2182. if (stringset != ETH_SS_STATS)
  2183. return;
  2184. /* for ge/xge node info */
  2185. buff = hns_dsaf_get_node_stats_strings(buff, node);
  2186. /* for ppe node info */
  2187. node = port + DSAF_PPE_INODE_BASE;
  2188. (void)hns_dsaf_get_node_stats_strings(buff, node);
  2189. }
  2190. /**
  2191. *hns_dsaf_get_sset_count - get dsaf regs count
  2192. *return dsaf regs count
  2193. */
  2194. int hns_dsaf_get_regs_count(void)
  2195. {
  2196. return DSAF_DUMP_REGS_NUM;
  2197. }
  2198. /**
  2199. * dsaf_probe - probo dsaf dev
  2200. * @pdev: dasf platform device
  2201. * retuen 0 - success , negative --fail
  2202. */
  2203. static int hns_dsaf_probe(struct platform_device *pdev)
  2204. {
  2205. struct dsaf_device *dsaf_dev;
  2206. int ret;
  2207. dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
  2208. if (IS_ERR(dsaf_dev)) {
  2209. ret = PTR_ERR(dsaf_dev);
  2210. dev_err(&pdev->dev,
  2211. "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
  2212. return ret;
  2213. }
  2214. ret = hns_dsaf_get_cfg(dsaf_dev);
  2215. if (ret)
  2216. goto free_dev;
  2217. ret = hns_dsaf_init(dsaf_dev);
  2218. if (ret)
  2219. goto free_cfg;
  2220. ret = hns_mac_init(dsaf_dev);
  2221. if (ret)
  2222. goto uninit_dsaf;
  2223. ret = hns_ppe_init(dsaf_dev);
  2224. if (ret)
  2225. goto uninit_mac;
  2226. ret = hns_dsaf_ae_init(dsaf_dev);
  2227. if (ret)
  2228. goto uninit_ppe;
  2229. return 0;
  2230. uninit_ppe:
  2231. hns_ppe_uninit(dsaf_dev);
  2232. uninit_mac:
  2233. hns_mac_uninit(dsaf_dev);
  2234. uninit_dsaf:
  2235. hns_dsaf_free(dsaf_dev);
  2236. free_cfg:
  2237. hns_dsaf_free_cfg(dsaf_dev);
  2238. free_dev:
  2239. hns_dsaf_free_dev(dsaf_dev);
  2240. return ret;
  2241. }
  2242. /**
  2243. * dsaf_remove - remove dsaf dev
  2244. * @pdev: dasf platform device
  2245. */
  2246. static int hns_dsaf_remove(struct platform_device *pdev)
  2247. {
  2248. struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
  2249. hns_dsaf_ae_uninit(dsaf_dev);
  2250. hns_ppe_uninit(dsaf_dev);
  2251. hns_mac_uninit(dsaf_dev);
  2252. hns_dsaf_free(dsaf_dev);
  2253. hns_dsaf_free_cfg(dsaf_dev);
  2254. hns_dsaf_free_dev(dsaf_dev);
  2255. return 0;
  2256. }
  2257. static const struct of_device_id g_dsaf_match[] = {
  2258. {.compatible = "hisilicon,hns-dsaf-v1"},
  2259. {.compatible = "hisilicon,hns-dsaf-v2"},
  2260. {}
  2261. };
  2262. static struct platform_driver g_dsaf_driver = {
  2263. .probe = hns_dsaf_probe,
  2264. .remove = hns_dsaf_remove,
  2265. .driver = {
  2266. .name = DSAF_DRV_NAME,
  2267. .of_match_table = g_dsaf_match,
  2268. },
  2269. };
  2270. module_platform_driver(g_dsaf_driver);
  2271. MODULE_LICENSE("GPL");
  2272. MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
  2273. MODULE_DESCRIPTION("HNS DSAF driver");
  2274. MODULE_VERSION(DSAF_MOD_VERSION);