atl1c_main.c 78 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.1-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static const struct pci_device_id atl1c_pci_tbl[] = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcomm Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  63. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  64. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  65. {
  66. u32 mst_data, data;
  67. /* pclk sel could switch to 25M */
  68. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  69. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  70. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  71. /* WoL/PCIE related settings */
  72. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  73. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  74. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  75. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  76. } else { /* new dev set bit5 of MASTER */
  77. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  78. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  79. mst_data | MASTER_CTRL_WAKEN_25M);
  80. }
  81. /* aspm/PCIE setting only for l2cb 1.0 */
  82. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  83. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  84. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  85. L2CB1_PCIE_PHYMISC2_CDR_BW);
  86. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  87. L2CB1_PCIE_PHYMISC2_L0S_TH);
  88. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  89. /* extend L1 sync timer */
  90. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  91. data |= LINK_CTRL_EXT_SYNC;
  92. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  93. }
  94. /* l2cb 1.x & l1d 1.x */
  95. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  96. AT_READ_REG(hw, REG_PM_CTRL, &data);
  97. data |= PM_CTRL_L0S_BUFSRX_EN;
  98. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  99. /* clear vendor msg */
  100. AT_READ_REG(hw, REG_DMA_DBG, &data);
  101. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  102. }
  103. }
  104. /* FIXME: no need any more ? */
  105. /*
  106. * atl1c_init_pcie - init PCIE module
  107. */
  108. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  109. {
  110. u32 data;
  111. u32 pci_cmd;
  112. struct pci_dev *pdev = hw->adapter->pdev;
  113. int pos;
  114. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  115. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  116. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  117. PCI_COMMAND_IO);
  118. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  119. /*
  120. * Clear any PowerSaveing Settings
  121. */
  122. pci_enable_wake(pdev, PCI_D3hot, 0);
  123. pci_enable_wake(pdev, PCI_D3cold, 0);
  124. /* wol sts read-clear */
  125. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  126. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  127. /*
  128. * Mask some pcie error bits
  129. */
  130. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  131. if (pos) {
  132. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  133. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  134. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  135. }
  136. /* clear error status */
  137. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
  138. PCI_EXP_DEVSTA_NFED |
  139. PCI_EXP_DEVSTA_FED |
  140. PCI_EXP_DEVSTA_CED |
  141. PCI_EXP_DEVSTA_URD);
  142. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  143. data &= ~LTSSM_ID_EN_WRO;
  144. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  145. atl1c_pcie_patch(hw);
  146. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  147. atl1c_disable_l0s_l1(hw);
  148. msleep(5);
  149. }
  150. /**
  151. * atl1c_irq_enable - Enable default interrupt generation settings
  152. * @adapter: board private structure
  153. */
  154. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  155. {
  156. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  157. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  158. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  159. AT_WRITE_FLUSH(&adapter->hw);
  160. }
  161. }
  162. /**
  163. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  164. * @adapter: board private structure
  165. */
  166. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  167. {
  168. atomic_inc(&adapter->irq_sem);
  169. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  170. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  171. AT_WRITE_FLUSH(&adapter->hw);
  172. synchronize_irq(adapter->pdev->irq);
  173. }
  174. /**
  175. * atl1c_irq_reset - reset interrupt confiure on the NIC
  176. * @adapter: board private structure
  177. */
  178. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  179. {
  180. atomic_set(&adapter->irq_sem, 1);
  181. atl1c_irq_enable(adapter);
  182. }
  183. /*
  184. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  185. * of the idle status register until the device is actually idle
  186. */
  187. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  188. {
  189. int timeout;
  190. u32 data;
  191. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  192. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  193. if ((data & modu_ctrl) == 0)
  194. return 0;
  195. msleep(1);
  196. }
  197. return data;
  198. }
  199. /**
  200. * atl1c_phy_config - Timer Call-back
  201. * @data: pointer to netdev cast into an unsigned long
  202. */
  203. static void atl1c_phy_config(unsigned long data)
  204. {
  205. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  206. struct atl1c_hw *hw = &adapter->hw;
  207. unsigned long flags;
  208. spin_lock_irqsave(&adapter->mdio_lock, flags);
  209. atl1c_restart_autoneg(hw);
  210. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  211. }
  212. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  213. {
  214. WARN_ON(in_interrupt());
  215. atl1c_down(adapter);
  216. atl1c_up(adapter);
  217. clear_bit(__AT_RESETTING, &adapter->flags);
  218. }
  219. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  220. {
  221. struct atl1c_hw *hw = &adapter->hw;
  222. struct net_device *netdev = adapter->netdev;
  223. struct pci_dev *pdev = adapter->pdev;
  224. int err;
  225. unsigned long flags;
  226. u16 speed, duplex, phy_data;
  227. spin_lock_irqsave(&adapter->mdio_lock, flags);
  228. /* MII_BMSR must read twise */
  229. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  230. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  231. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  232. if ((phy_data & BMSR_LSTATUS) == 0) {
  233. /* link down */
  234. netif_carrier_off(netdev);
  235. hw->hibernate = true;
  236. if (atl1c_reset_mac(hw) != 0)
  237. if (netif_msg_hw(adapter))
  238. dev_warn(&pdev->dev, "reset mac failed\n");
  239. atl1c_set_aspm(hw, SPEED_0);
  240. atl1c_post_phy_linkchg(hw, SPEED_0);
  241. atl1c_reset_dma_ring(adapter);
  242. atl1c_configure(adapter);
  243. } else {
  244. /* Link Up */
  245. hw->hibernate = false;
  246. spin_lock_irqsave(&adapter->mdio_lock, flags);
  247. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  248. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  249. if (unlikely(err))
  250. return;
  251. /* link result is our setting */
  252. if (adapter->link_speed != speed ||
  253. adapter->link_duplex != duplex) {
  254. adapter->link_speed = speed;
  255. adapter->link_duplex = duplex;
  256. atl1c_set_aspm(hw, speed);
  257. atl1c_post_phy_linkchg(hw, speed);
  258. atl1c_start_mac(adapter);
  259. if (netif_msg_link(adapter))
  260. dev_info(&pdev->dev,
  261. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  262. atl1c_driver_name, netdev->name,
  263. adapter->link_speed,
  264. adapter->link_duplex == FULL_DUPLEX ?
  265. "Full Duplex" : "Half Duplex");
  266. }
  267. if (!netif_carrier_ok(netdev))
  268. netif_carrier_on(netdev);
  269. }
  270. }
  271. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  272. {
  273. struct net_device *netdev = adapter->netdev;
  274. struct pci_dev *pdev = adapter->pdev;
  275. u16 phy_data;
  276. u16 link_up;
  277. spin_lock(&adapter->mdio_lock);
  278. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  279. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  280. spin_unlock(&adapter->mdio_lock);
  281. link_up = phy_data & BMSR_LSTATUS;
  282. /* notify upper layer link down ASAP */
  283. if (!link_up) {
  284. if (netif_carrier_ok(netdev)) {
  285. /* old link state: Up */
  286. netif_carrier_off(netdev);
  287. if (netif_msg_link(adapter))
  288. dev_info(&pdev->dev,
  289. "%s: %s NIC Link is Down\n",
  290. atl1c_driver_name, netdev->name);
  291. adapter->link_speed = SPEED_0;
  292. }
  293. }
  294. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  295. schedule_work(&adapter->common_task);
  296. }
  297. static void atl1c_common_task(struct work_struct *work)
  298. {
  299. struct atl1c_adapter *adapter;
  300. struct net_device *netdev;
  301. adapter = container_of(work, struct atl1c_adapter, common_task);
  302. netdev = adapter->netdev;
  303. if (test_bit(__AT_DOWN, &adapter->flags))
  304. return;
  305. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  306. netif_device_detach(netdev);
  307. atl1c_down(adapter);
  308. atl1c_up(adapter);
  309. netif_device_attach(netdev);
  310. }
  311. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  312. &adapter->work_event)) {
  313. atl1c_irq_disable(adapter);
  314. atl1c_check_link_status(adapter);
  315. atl1c_irq_enable(adapter);
  316. }
  317. }
  318. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  319. {
  320. del_timer_sync(&adapter->phy_config_timer);
  321. }
  322. /**
  323. * atl1c_tx_timeout - Respond to a Tx Hang
  324. * @netdev: network interface device structure
  325. */
  326. static void atl1c_tx_timeout(struct net_device *netdev)
  327. {
  328. struct atl1c_adapter *adapter = netdev_priv(netdev);
  329. /* Do the reset outside of interrupt context */
  330. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  331. schedule_work(&adapter->common_task);
  332. }
  333. /**
  334. * atl1c_set_multi - Multicast and Promiscuous mode set
  335. * @netdev: network interface device structure
  336. *
  337. * The set_multi entry point is called whenever the multicast address
  338. * list or the network interface flags are updated. This routine is
  339. * responsible for configuring the hardware for proper multicast,
  340. * promiscuous mode, and all-multi behavior.
  341. */
  342. static void atl1c_set_multi(struct net_device *netdev)
  343. {
  344. struct atl1c_adapter *adapter = netdev_priv(netdev);
  345. struct atl1c_hw *hw = &adapter->hw;
  346. struct netdev_hw_addr *ha;
  347. u32 mac_ctrl_data;
  348. u32 hash_value;
  349. /* Check for Promiscuous and All Multicast modes */
  350. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  351. if (netdev->flags & IFF_PROMISC) {
  352. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  353. } else if (netdev->flags & IFF_ALLMULTI) {
  354. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  355. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  356. } else {
  357. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  358. }
  359. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  360. /* clear the old settings from the multicast hash table */
  361. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  362. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  363. /* comoute mc addresses' hash value ,and put it into hash table */
  364. netdev_for_each_mc_addr(ha, netdev) {
  365. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  366. atl1c_hash_set(hw, hash_value);
  367. }
  368. }
  369. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  370. {
  371. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  372. /* enable VLAN tag insert/strip */
  373. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  374. } else {
  375. /* disable VLAN tag insert/strip */
  376. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  377. }
  378. }
  379. static void atl1c_vlan_mode(struct net_device *netdev,
  380. netdev_features_t features)
  381. {
  382. struct atl1c_adapter *adapter = netdev_priv(netdev);
  383. struct pci_dev *pdev = adapter->pdev;
  384. u32 mac_ctrl_data = 0;
  385. if (netif_msg_pktdata(adapter))
  386. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  387. atl1c_irq_disable(adapter);
  388. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  389. __atl1c_vlan_mode(features, &mac_ctrl_data);
  390. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  391. atl1c_irq_enable(adapter);
  392. }
  393. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  394. {
  395. struct pci_dev *pdev = adapter->pdev;
  396. if (netif_msg_pktdata(adapter))
  397. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  398. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  399. }
  400. /**
  401. * atl1c_set_mac - Change the Ethernet Address of the NIC
  402. * @netdev: network interface device structure
  403. * @p: pointer to an address structure
  404. *
  405. * Returns 0 on success, negative on failure
  406. */
  407. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  408. {
  409. struct atl1c_adapter *adapter = netdev_priv(netdev);
  410. struct sockaddr *addr = p;
  411. if (!is_valid_ether_addr(addr->sa_data))
  412. return -EADDRNOTAVAIL;
  413. if (netif_running(netdev))
  414. return -EBUSY;
  415. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  416. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  417. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  418. return 0;
  419. }
  420. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  421. struct net_device *dev)
  422. {
  423. unsigned int head_size;
  424. int mtu = dev->mtu;
  425. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  426. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  427. head_size = SKB_DATA_ALIGN(adapter->rx_buffer_len + NET_SKB_PAD) +
  428. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  429. adapter->rx_frag_size = roundup_pow_of_two(head_size);
  430. }
  431. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  432. netdev_features_t features)
  433. {
  434. /*
  435. * Since there is no support for separate rx/tx vlan accel
  436. * enable/disable make sure tx flag is always in same state as rx.
  437. */
  438. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  439. features |= NETIF_F_HW_VLAN_CTAG_TX;
  440. else
  441. features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  442. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  443. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  444. return features;
  445. }
  446. static int atl1c_set_features(struct net_device *netdev,
  447. netdev_features_t features)
  448. {
  449. netdev_features_t changed = netdev->features ^ features;
  450. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  451. atl1c_vlan_mode(netdev, features);
  452. return 0;
  453. }
  454. /**
  455. * atl1c_change_mtu - Change the Maximum Transfer Unit
  456. * @netdev: network interface device structure
  457. * @new_mtu: new value for maximum frame size
  458. *
  459. * Returns 0 on success, negative on failure
  460. */
  461. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  462. {
  463. struct atl1c_adapter *adapter = netdev_priv(netdev);
  464. struct atl1c_hw *hw = &adapter->hw;
  465. int old_mtu = netdev->mtu;
  466. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  467. /* Fast Ethernet controller doesn't support jumbo packet */
  468. if (((hw->nic_type == athr_l2c ||
  469. hw->nic_type == athr_l2c_b ||
  470. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  471. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  472. max_frame > MAX_JUMBO_FRAME_SIZE) {
  473. if (netif_msg_link(adapter))
  474. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  475. return -EINVAL;
  476. }
  477. /* set MTU */
  478. if (old_mtu != new_mtu && netif_running(netdev)) {
  479. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  480. msleep(1);
  481. netdev->mtu = new_mtu;
  482. adapter->hw.max_frame_size = new_mtu;
  483. atl1c_set_rxbufsize(adapter, netdev);
  484. atl1c_down(adapter);
  485. netdev_update_features(netdev);
  486. atl1c_up(adapter);
  487. clear_bit(__AT_RESETTING, &adapter->flags);
  488. }
  489. return 0;
  490. }
  491. /*
  492. * caller should hold mdio_lock
  493. */
  494. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  495. {
  496. struct atl1c_adapter *adapter = netdev_priv(netdev);
  497. u16 result;
  498. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  499. return result;
  500. }
  501. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  502. int reg_num, int val)
  503. {
  504. struct atl1c_adapter *adapter = netdev_priv(netdev);
  505. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  506. }
  507. static int atl1c_mii_ioctl(struct net_device *netdev,
  508. struct ifreq *ifr, int cmd)
  509. {
  510. struct atl1c_adapter *adapter = netdev_priv(netdev);
  511. struct pci_dev *pdev = adapter->pdev;
  512. struct mii_ioctl_data *data = if_mii(ifr);
  513. unsigned long flags;
  514. int retval = 0;
  515. if (!netif_running(netdev))
  516. return -EINVAL;
  517. spin_lock_irqsave(&adapter->mdio_lock, flags);
  518. switch (cmd) {
  519. case SIOCGMIIPHY:
  520. data->phy_id = 0;
  521. break;
  522. case SIOCGMIIREG:
  523. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  524. &data->val_out)) {
  525. retval = -EIO;
  526. goto out;
  527. }
  528. break;
  529. case SIOCSMIIREG:
  530. if (data->reg_num & ~(0x1F)) {
  531. retval = -EFAULT;
  532. goto out;
  533. }
  534. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  535. data->reg_num, data->val_in);
  536. if (atl1c_write_phy_reg(&adapter->hw,
  537. data->reg_num, data->val_in)) {
  538. retval = -EIO;
  539. goto out;
  540. }
  541. break;
  542. default:
  543. retval = -EOPNOTSUPP;
  544. break;
  545. }
  546. out:
  547. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  548. return retval;
  549. }
  550. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  551. {
  552. switch (cmd) {
  553. case SIOCGMIIPHY:
  554. case SIOCGMIIREG:
  555. case SIOCSMIIREG:
  556. return atl1c_mii_ioctl(netdev, ifr, cmd);
  557. default:
  558. return -EOPNOTSUPP;
  559. }
  560. }
  561. /**
  562. * atl1c_alloc_queues - Allocate memory for all rings
  563. * @adapter: board private structure to initialize
  564. *
  565. */
  566. static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
  567. {
  568. return 0;
  569. }
  570. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  571. {
  572. switch (hw->device_id) {
  573. case PCI_DEVICE_ID_ATTANSIC_L2C:
  574. hw->nic_type = athr_l2c;
  575. break;
  576. case PCI_DEVICE_ID_ATTANSIC_L1C:
  577. hw->nic_type = athr_l1c;
  578. break;
  579. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  580. hw->nic_type = athr_l2c_b;
  581. break;
  582. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  583. hw->nic_type = athr_l2c_b2;
  584. break;
  585. case PCI_DEVICE_ID_ATHEROS_L1D:
  586. hw->nic_type = athr_l1d;
  587. break;
  588. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  589. hw->nic_type = athr_l1d_2;
  590. break;
  591. default:
  592. break;
  593. }
  594. }
  595. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  596. {
  597. u32 link_ctrl_data;
  598. atl1c_set_mac_type(hw);
  599. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  600. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  601. ATL1C_TXQ_MODE_ENHANCE;
  602. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  603. ATL1C_ASPM_L1_SUPPORT;
  604. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  605. if (hw->nic_type == athr_l1c ||
  606. hw->nic_type == athr_l1d ||
  607. hw->nic_type == athr_l1d_2)
  608. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  609. return 0;
  610. }
  611. struct atl1c_platform_patch {
  612. u16 pci_did;
  613. u8 pci_revid;
  614. u16 subsystem_vid;
  615. u16 subsystem_did;
  616. u32 patch_flag;
  617. #define ATL1C_LINK_PATCH 0x1
  618. };
  619. static const struct atl1c_platform_patch plats[] = {
  620. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  621. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  622. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  623. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  624. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  625. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  626. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  627. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  628. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  629. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  630. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  631. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  632. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  633. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  634. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  635. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  636. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  637. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  638. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  639. {0},
  640. };
  641. static void atl1c_patch_assign(struct atl1c_hw *hw)
  642. {
  643. struct pci_dev *pdev = hw->adapter->pdev;
  644. u32 misc_ctrl;
  645. int i = 0;
  646. hw->msi_lnkpatch = false;
  647. while (plats[i].pci_did != 0) {
  648. if (plats[i].pci_did == hw->device_id &&
  649. plats[i].pci_revid == hw->revision_id &&
  650. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  651. plats[i].subsystem_did == hw->subsystem_id) {
  652. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  653. hw->msi_lnkpatch = true;
  654. }
  655. i++;
  656. }
  657. if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
  658. hw->revision_id == L2CB_V21) {
  659. /* config access mode */
  660. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  661. REG_PCIE_DEV_MISC_CTRL);
  662. pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
  663. misc_ctrl &= ~0x100;
  664. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  665. REG_PCIE_DEV_MISC_CTRL);
  666. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
  667. }
  668. }
  669. /**
  670. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  671. * @adapter: board private structure to initialize
  672. *
  673. * atl1c_sw_init initializes the Adapter private data structure.
  674. * Fields are initialized based on PCI device information and
  675. * OS network device settings (MTU size).
  676. */
  677. static int atl1c_sw_init(struct atl1c_adapter *adapter)
  678. {
  679. struct atl1c_hw *hw = &adapter->hw;
  680. struct pci_dev *pdev = adapter->pdev;
  681. u32 revision;
  682. adapter->wol = 0;
  683. device_set_wakeup_enable(&pdev->dev, false);
  684. adapter->link_speed = SPEED_0;
  685. adapter->link_duplex = FULL_DUPLEX;
  686. adapter->tpd_ring[0].count = 1024;
  687. adapter->rfd_ring.count = 512;
  688. hw->vendor_id = pdev->vendor;
  689. hw->device_id = pdev->device;
  690. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  691. hw->subsystem_id = pdev->subsystem_device;
  692. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
  693. hw->revision_id = revision & 0xFF;
  694. /* before link up, we assume hibernate is true */
  695. hw->hibernate = true;
  696. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  697. if (atl1c_setup_mac_funcs(hw) != 0) {
  698. dev_err(&pdev->dev, "set mac function pointers failed\n");
  699. return -1;
  700. }
  701. atl1c_patch_assign(hw);
  702. hw->intr_mask = IMR_NORMAL_MASK;
  703. hw->phy_configured = false;
  704. hw->preamble_len = 7;
  705. hw->max_frame_size = adapter->netdev->mtu;
  706. hw->autoneg_advertised = ADVERTISED_Autoneg;
  707. hw->indirect_tab = 0xE4E4E4E4;
  708. hw->base_cpu = 0;
  709. hw->ict = 50000; /* 100ms */
  710. hw->smb_timer = 200000; /* 400ms */
  711. hw->rx_imt = 200;
  712. hw->tx_imt = 1000;
  713. hw->tpd_burst = 5;
  714. hw->rfd_burst = 8;
  715. hw->dma_order = atl1c_dma_ord_out;
  716. hw->dmar_block = atl1c_dma_req_1024;
  717. if (atl1c_alloc_queues(adapter)) {
  718. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  719. return -ENOMEM;
  720. }
  721. /* TODO */
  722. atl1c_set_rxbufsize(adapter, adapter->netdev);
  723. atomic_set(&adapter->irq_sem, 1);
  724. spin_lock_init(&adapter->mdio_lock);
  725. spin_lock_init(&adapter->tx_lock);
  726. set_bit(__AT_DOWN, &adapter->flags);
  727. return 0;
  728. }
  729. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  730. struct atl1c_buffer *buffer_info)
  731. {
  732. u16 pci_driection;
  733. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  734. return;
  735. if (buffer_info->dma) {
  736. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  737. pci_driection = PCI_DMA_FROMDEVICE;
  738. else
  739. pci_driection = PCI_DMA_TODEVICE;
  740. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  741. pci_unmap_single(pdev, buffer_info->dma,
  742. buffer_info->length, pci_driection);
  743. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  744. pci_unmap_page(pdev, buffer_info->dma,
  745. buffer_info->length, pci_driection);
  746. }
  747. if (buffer_info->skb)
  748. dev_consume_skb_any(buffer_info->skb);
  749. buffer_info->dma = 0;
  750. buffer_info->skb = NULL;
  751. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  752. }
  753. /**
  754. * atl1c_clean_tx_ring - Free Tx-skb
  755. * @adapter: board private structure
  756. */
  757. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  758. enum atl1c_trans_queue type)
  759. {
  760. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  761. struct atl1c_buffer *buffer_info;
  762. struct pci_dev *pdev = adapter->pdev;
  763. u16 index, ring_count;
  764. ring_count = tpd_ring->count;
  765. for (index = 0; index < ring_count; index++) {
  766. buffer_info = &tpd_ring->buffer_info[index];
  767. atl1c_clean_buffer(pdev, buffer_info);
  768. }
  769. netdev_reset_queue(adapter->netdev);
  770. /* Zero out Tx-buffers */
  771. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  772. ring_count);
  773. atomic_set(&tpd_ring->next_to_clean, 0);
  774. tpd_ring->next_to_use = 0;
  775. }
  776. /**
  777. * atl1c_clean_rx_ring - Free rx-reservation skbs
  778. * @adapter: board private structure
  779. */
  780. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  781. {
  782. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  783. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  784. struct atl1c_buffer *buffer_info;
  785. struct pci_dev *pdev = adapter->pdev;
  786. int j;
  787. for (j = 0; j < rfd_ring->count; j++) {
  788. buffer_info = &rfd_ring->buffer_info[j];
  789. atl1c_clean_buffer(pdev, buffer_info);
  790. }
  791. /* zero out the descriptor ring */
  792. memset(rfd_ring->desc, 0, rfd_ring->size);
  793. rfd_ring->next_to_clean = 0;
  794. rfd_ring->next_to_use = 0;
  795. rrd_ring->next_to_use = 0;
  796. rrd_ring->next_to_clean = 0;
  797. }
  798. /*
  799. * Read / Write Ptr Initialize:
  800. */
  801. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  802. {
  803. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  804. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  805. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  806. struct atl1c_buffer *buffer_info;
  807. int i, j;
  808. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  809. tpd_ring[i].next_to_use = 0;
  810. atomic_set(&tpd_ring[i].next_to_clean, 0);
  811. buffer_info = tpd_ring[i].buffer_info;
  812. for (j = 0; j < tpd_ring->count; j++)
  813. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  814. ATL1C_BUFFER_FREE);
  815. }
  816. rfd_ring->next_to_use = 0;
  817. rfd_ring->next_to_clean = 0;
  818. rrd_ring->next_to_use = 0;
  819. rrd_ring->next_to_clean = 0;
  820. for (j = 0; j < rfd_ring->count; j++) {
  821. buffer_info = &rfd_ring->buffer_info[j];
  822. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  823. }
  824. }
  825. /**
  826. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  827. * @adapter: board private structure
  828. *
  829. * Free all transmit software resources
  830. */
  831. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  832. {
  833. struct pci_dev *pdev = adapter->pdev;
  834. pci_free_consistent(pdev, adapter->ring_header.size,
  835. adapter->ring_header.desc,
  836. adapter->ring_header.dma);
  837. adapter->ring_header.desc = NULL;
  838. /* Note: just free tdp_ring.buffer_info,
  839. * it contain rfd_ring.buffer_info, do not double free */
  840. if (adapter->tpd_ring[0].buffer_info) {
  841. kfree(adapter->tpd_ring[0].buffer_info);
  842. adapter->tpd_ring[0].buffer_info = NULL;
  843. }
  844. if (adapter->rx_page) {
  845. put_page(adapter->rx_page);
  846. adapter->rx_page = NULL;
  847. }
  848. }
  849. /**
  850. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  851. * @adapter: board private structure
  852. *
  853. * Return 0 on success, negative on failure
  854. */
  855. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  856. {
  857. struct pci_dev *pdev = adapter->pdev;
  858. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  859. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  860. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  861. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  862. int size;
  863. int i;
  864. int count = 0;
  865. int rx_desc_count = 0;
  866. u32 offset = 0;
  867. rrd_ring->count = rfd_ring->count;
  868. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  869. tpd_ring[i].count = tpd_ring[0].count;
  870. /* 2 tpd queue, one high priority queue,
  871. * another normal priority queue */
  872. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  873. rfd_ring->count);
  874. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  875. if (unlikely(!tpd_ring->buffer_info))
  876. goto err_nomem;
  877. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  878. tpd_ring[i].buffer_info =
  879. (tpd_ring->buffer_info + count);
  880. count += tpd_ring[i].count;
  881. }
  882. rfd_ring->buffer_info =
  883. (tpd_ring->buffer_info + count);
  884. count += rfd_ring->count;
  885. rx_desc_count += rfd_ring->count;
  886. /*
  887. * real ring DMA buffer
  888. * each ring/block may need up to 8 bytes for alignment, hence the
  889. * additional bytes tacked onto the end.
  890. */
  891. ring_header->size = size =
  892. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  893. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  894. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  895. 8 * 4;
  896. ring_header->desc = dma_zalloc_coherent(&pdev->dev, ring_header->size,
  897. &ring_header->dma, GFP_KERNEL);
  898. if (unlikely(!ring_header->desc)) {
  899. dev_err(&pdev->dev, "could not get memory for DMA buffer\n");
  900. goto err_nomem;
  901. }
  902. /* init TPD ring */
  903. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  904. offset = tpd_ring[0].dma - ring_header->dma;
  905. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  906. tpd_ring[i].dma = ring_header->dma + offset;
  907. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  908. tpd_ring[i].size =
  909. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  910. offset += roundup(tpd_ring[i].size, 8);
  911. }
  912. /* init RFD ring */
  913. rfd_ring->dma = ring_header->dma + offset;
  914. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  915. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  916. offset += roundup(rfd_ring->size, 8);
  917. /* init RRD ring */
  918. rrd_ring->dma = ring_header->dma + offset;
  919. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  920. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  921. rrd_ring->count;
  922. offset += roundup(rrd_ring->size, 8);
  923. return 0;
  924. err_nomem:
  925. kfree(tpd_ring->buffer_info);
  926. return -ENOMEM;
  927. }
  928. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  929. {
  930. struct atl1c_hw *hw = &adapter->hw;
  931. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  932. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  933. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  934. adapter->tpd_ring;
  935. /* TPD */
  936. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  937. (u32)((tpd_ring[atl1c_trans_normal].dma &
  938. AT_DMA_HI_ADDR_MASK) >> 32));
  939. /* just enable normal priority TX queue */
  940. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  941. (u32)(tpd_ring[atl1c_trans_normal].dma &
  942. AT_DMA_LO_ADDR_MASK));
  943. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  944. (u32)(tpd_ring[atl1c_trans_high].dma &
  945. AT_DMA_LO_ADDR_MASK));
  946. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  947. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  948. /* RFD */
  949. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  950. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  951. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  952. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  953. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  954. rfd_ring->count & RFD_RING_SIZE_MASK);
  955. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  956. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  957. /* RRD */
  958. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  959. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  960. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  961. (rrd_ring->count & RRD_RING_SIZE_MASK));
  962. if (hw->nic_type == athr_l2c_b) {
  963. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  964. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  965. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  966. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  967. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  968. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  969. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  970. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  971. }
  972. /* Load all of base address above */
  973. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  974. }
  975. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  976. {
  977. struct atl1c_hw *hw = &adapter->hw;
  978. int max_pay_load;
  979. u16 tx_offload_thresh;
  980. u32 txq_ctrl_data;
  981. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  982. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  983. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  984. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  985. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  986. /*
  987. * if BIOS had changed the dam-read-max-length to an invalid value,
  988. * restore it to default value
  989. */
  990. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  991. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  992. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  993. }
  994. txq_ctrl_data =
  995. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  996. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  997. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  998. }
  999. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  1000. {
  1001. struct atl1c_hw *hw = &adapter->hw;
  1002. u32 rxq_ctrl_data;
  1003. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1004. RXQ_RFD_BURST_NUM_SHIFT;
  1005. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1006. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1007. /* aspm for gigabit */
  1008. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1009. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1010. ASPM_THRUPUT_LIMIT_100M);
  1011. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1012. }
  1013. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1014. {
  1015. struct atl1c_hw *hw = &adapter->hw;
  1016. u32 dma_ctrl_data;
  1017. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1018. DMA_CTRL_RREQ_PRI_DATA |
  1019. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1020. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1021. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1022. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1023. }
  1024. /*
  1025. * Stop the mac, transmit and receive units
  1026. * hw - Struct containing variables accessed by shared code
  1027. * return : 0 or idle status (if error)
  1028. */
  1029. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1030. {
  1031. u32 data;
  1032. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1033. data &= ~RXQ_CTRL_EN;
  1034. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1035. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1036. data &= ~TXQ_CTRL_EN;
  1037. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1038. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1039. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1040. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1041. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1042. return (int)atl1c_wait_until_idle(hw,
  1043. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1044. }
  1045. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1046. {
  1047. struct atl1c_hw *hw = &adapter->hw;
  1048. u32 mac, txq, rxq;
  1049. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1050. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1051. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1052. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1053. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1054. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1055. txq |= TXQ_CTRL_EN;
  1056. rxq |= RXQ_CTRL_EN;
  1057. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1058. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1059. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1060. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1061. MAC_CTRL_HASH_ALG_CRC32;
  1062. if (hw->mac_duplex)
  1063. mac |= MAC_CTRL_DUPLX;
  1064. else
  1065. mac &= ~MAC_CTRL_DUPLX;
  1066. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1067. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1068. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1069. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1070. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1071. }
  1072. /*
  1073. * Reset the transmit and receive units; mask and clear all interrupts.
  1074. * hw - Struct containing variables accessed by shared code
  1075. * return : 0 or idle status (if error)
  1076. */
  1077. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1078. {
  1079. struct atl1c_adapter *adapter = hw->adapter;
  1080. struct pci_dev *pdev = adapter->pdev;
  1081. u32 ctrl_data = 0;
  1082. atl1c_stop_mac(hw);
  1083. /*
  1084. * Issue Soft Reset to the MAC. This will reset the chip's
  1085. * transmit, receive, DMA. It will not effect
  1086. * the current PCI configuration. The global reset bit is self-
  1087. * clearing, and should clear within a microsecond.
  1088. */
  1089. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1090. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1091. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1092. AT_WRITE_FLUSH(hw);
  1093. msleep(10);
  1094. /* Wait at least 10ms for All module to be Idle */
  1095. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1096. dev_err(&pdev->dev,
  1097. "MAC state machine can't be idle since"
  1098. " disabled for 10ms second\n");
  1099. return -1;
  1100. }
  1101. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1102. /* driver control speed/duplex */
  1103. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1104. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1105. /* clk switch setting */
  1106. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1107. switch (hw->nic_type) {
  1108. case athr_l2c_b:
  1109. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1110. SERDES_MAC_CLK_SLOWDOWN);
  1111. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1112. break;
  1113. case athr_l2c_b2:
  1114. case athr_l1d_2:
  1115. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1116. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1117. break;
  1118. default:
  1119. break;
  1120. }
  1121. return 0;
  1122. }
  1123. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1124. {
  1125. u16 ctrl_flags = hw->ctrl_flags;
  1126. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1127. atl1c_set_aspm(hw, SPEED_0);
  1128. hw->ctrl_flags = ctrl_flags;
  1129. }
  1130. /*
  1131. * Set ASPM state.
  1132. * Enable/disable L0s/L1 depend on link state.
  1133. */
  1134. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1135. {
  1136. u32 pm_ctrl_data;
  1137. u32 link_l1_timer;
  1138. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1139. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1140. PM_CTRL_ASPM_L0S_EN |
  1141. PM_CTRL_MAC_ASPM_CHK);
  1142. /* L1 timer */
  1143. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1144. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1145. link_l1_timer =
  1146. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1147. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1148. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1149. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1150. } else {
  1151. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1152. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1153. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1154. link_l1_timer = 1;
  1155. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1156. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1157. }
  1158. /* L0S/L1 enable */
  1159. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1160. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1161. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1162. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1163. /* l2cb & l1d & l2cb2 & l1d2 */
  1164. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1165. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1166. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1167. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1168. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1169. PM_CTRL_SERDES_PD_EX_L1 |
  1170. PM_CTRL_CLK_SWH_L1;
  1171. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1172. PM_CTRL_SERDES_PLL_L1_EN |
  1173. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1174. PM_CTRL_SA_DLY_EN |
  1175. PM_CTRL_HOTRST);
  1176. /* disable l0s if link down or l2cb */
  1177. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1178. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1179. } else { /* l1c */
  1180. pm_ctrl_data =
  1181. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1182. if (link_speed != SPEED_0) {
  1183. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1184. PM_CTRL_SERDES_PLL_L1_EN |
  1185. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1186. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1187. PM_CTRL_CLK_SWH_L1 |
  1188. PM_CTRL_ASPM_L0S_EN |
  1189. PM_CTRL_ASPM_L1_EN);
  1190. } else { /* link down */
  1191. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1192. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1193. PM_CTRL_SERDES_PLL_L1_EN |
  1194. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1195. PM_CTRL_ASPM_L0S_EN);
  1196. }
  1197. }
  1198. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1199. return;
  1200. }
  1201. /**
  1202. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1203. * @adapter: board private structure
  1204. *
  1205. * Configure the Tx /Rx unit of the MAC after a reset.
  1206. */
  1207. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1208. {
  1209. struct atl1c_hw *hw = &adapter->hw;
  1210. u32 master_ctrl_data = 0;
  1211. u32 intr_modrt_data;
  1212. u32 data;
  1213. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1214. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1215. MASTER_CTRL_RX_ITIMER_EN |
  1216. MASTER_CTRL_INT_RDCLR);
  1217. /* clear interrupt status */
  1218. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1219. /* Clear any WOL status */
  1220. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1221. /* set Interrupt Clear Timer
  1222. * HW will enable self to assert interrupt event to system after
  1223. * waiting x-time for software to notify it accept interrupt.
  1224. */
  1225. data = CLK_GATING_EN_ALL;
  1226. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1227. if (hw->nic_type == athr_l2c_b)
  1228. data &= ~CLK_GATING_RXMAC_EN;
  1229. } else
  1230. data = 0;
  1231. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1232. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1233. hw->ict & INT_RETRIG_TIMER_MASK);
  1234. atl1c_configure_des_ring(adapter);
  1235. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1236. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1237. IRQ_MODRT_TX_TIMER_SHIFT;
  1238. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1239. IRQ_MODRT_RX_TIMER_SHIFT;
  1240. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1241. master_ctrl_data |=
  1242. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1243. }
  1244. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1245. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1246. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1247. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1248. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1249. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1250. /* set MTU */
  1251. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1252. VLAN_HLEN + ETH_FCS_LEN);
  1253. atl1c_configure_tx(adapter);
  1254. atl1c_configure_rx(adapter);
  1255. atl1c_configure_dma(adapter);
  1256. return 0;
  1257. }
  1258. static int atl1c_configure(struct atl1c_adapter *adapter)
  1259. {
  1260. struct net_device *netdev = adapter->netdev;
  1261. int num;
  1262. atl1c_init_ring_ptrs(adapter);
  1263. atl1c_set_multi(netdev);
  1264. atl1c_restore_vlan(adapter);
  1265. num = atl1c_alloc_rx_buffer(adapter);
  1266. if (unlikely(num == 0))
  1267. return -ENOMEM;
  1268. if (atl1c_configure_mac(adapter))
  1269. return -EIO;
  1270. return 0;
  1271. }
  1272. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1273. {
  1274. u16 hw_reg_addr = 0;
  1275. unsigned long *stats_item = NULL;
  1276. u32 data;
  1277. /* update rx status */
  1278. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1279. stats_item = &adapter->hw_stats.rx_ok;
  1280. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1281. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1282. *stats_item += data;
  1283. stats_item++;
  1284. hw_reg_addr += 4;
  1285. }
  1286. /* update tx status */
  1287. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1288. stats_item = &adapter->hw_stats.tx_ok;
  1289. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1290. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1291. *stats_item += data;
  1292. stats_item++;
  1293. hw_reg_addr += 4;
  1294. }
  1295. }
  1296. /**
  1297. * atl1c_get_stats - Get System Network Statistics
  1298. * @netdev: network interface device structure
  1299. *
  1300. * Returns the address of the device statistics structure.
  1301. * The statistics are actually updated from the timer callback.
  1302. */
  1303. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1304. {
  1305. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1306. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1307. struct net_device_stats *net_stats = &netdev->stats;
  1308. atl1c_update_hw_stats(adapter);
  1309. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1310. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1311. net_stats->multicast = hw_stats->rx_mcast;
  1312. net_stats->collisions = hw_stats->tx_1_col +
  1313. hw_stats->tx_2_col +
  1314. hw_stats->tx_late_col +
  1315. hw_stats->tx_abort_col;
  1316. net_stats->rx_errors = hw_stats->rx_frag +
  1317. hw_stats->rx_fcs_err +
  1318. hw_stats->rx_len_err +
  1319. hw_stats->rx_sz_ov +
  1320. hw_stats->rx_rrd_ov +
  1321. hw_stats->rx_align_err +
  1322. hw_stats->rx_rxf_ov;
  1323. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1324. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1325. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1326. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1327. net_stats->rx_dropped = hw_stats->rx_rrd_ov;
  1328. net_stats->tx_errors = hw_stats->tx_late_col +
  1329. hw_stats->tx_abort_col +
  1330. hw_stats->tx_underrun +
  1331. hw_stats->tx_trunc;
  1332. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1333. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1334. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1335. net_stats->rx_packets = hw_stats->rx_ok + net_stats->rx_errors;
  1336. net_stats->tx_packets = hw_stats->tx_ok + net_stats->tx_errors;
  1337. return net_stats;
  1338. }
  1339. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1340. {
  1341. u16 phy_data;
  1342. spin_lock(&adapter->mdio_lock);
  1343. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1344. spin_unlock(&adapter->mdio_lock);
  1345. }
  1346. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1347. enum atl1c_trans_queue type)
  1348. {
  1349. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1350. struct atl1c_buffer *buffer_info;
  1351. struct pci_dev *pdev = adapter->pdev;
  1352. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1353. u16 hw_next_to_clean;
  1354. u16 reg;
  1355. unsigned int total_bytes = 0, total_packets = 0;
  1356. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1357. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1358. while (next_to_clean != hw_next_to_clean) {
  1359. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1360. if (buffer_info->skb) {
  1361. total_bytes += buffer_info->skb->len;
  1362. total_packets++;
  1363. }
  1364. atl1c_clean_buffer(pdev, buffer_info);
  1365. if (++next_to_clean == tpd_ring->count)
  1366. next_to_clean = 0;
  1367. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1368. }
  1369. netdev_completed_queue(adapter->netdev, total_packets, total_bytes);
  1370. if (netif_queue_stopped(adapter->netdev) &&
  1371. netif_carrier_ok(adapter->netdev)) {
  1372. netif_wake_queue(adapter->netdev);
  1373. }
  1374. return true;
  1375. }
  1376. /**
  1377. * atl1c_intr - Interrupt Handler
  1378. * @irq: interrupt number
  1379. * @data: pointer to a network interface device structure
  1380. */
  1381. static irqreturn_t atl1c_intr(int irq, void *data)
  1382. {
  1383. struct net_device *netdev = data;
  1384. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1385. struct pci_dev *pdev = adapter->pdev;
  1386. struct atl1c_hw *hw = &adapter->hw;
  1387. int max_ints = AT_MAX_INT_WORK;
  1388. int handled = IRQ_NONE;
  1389. u32 status;
  1390. u32 reg_data;
  1391. do {
  1392. AT_READ_REG(hw, REG_ISR, &reg_data);
  1393. status = reg_data & hw->intr_mask;
  1394. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1395. if (max_ints != AT_MAX_INT_WORK)
  1396. handled = IRQ_HANDLED;
  1397. break;
  1398. }
  1399. /* link event */
  1400. if (status & ISR_GPHY)
  1401. atl1c_clear_phy_int(adapter);
  1402. /* Ack ISR */
  1403. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1404. if (status & ISR_RX_PKT) {
  1405. if (likely(napi_schedule_prep(&adapter->napi))) {
  1406. hw->intr_mask &= ~ISR_RX_PKT;
  1407. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1408. __napi_schedule(&adapter->napi);
  1409. }
  1410. }
  1411. if (status & ISR_TX_PKT)
  1412. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1413. handled = IRQ_HANDLED;
  1414. /* check if PCIE PHY Link down */
  1415. if (status & ISR_ERROR) {
  1416. if (netif_msg_hw(adapter))
  1417. dev_err(&pdev->dev,
  1418. "atl1c hardware error (status = 0x%x)\n",
  1419. status & ISR_ERROR);
  1420. /* reset MAC */
  1421. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1422. schedule_work(&adapter->common_task);
  1423. return IRQ_HANDLED;
  1424. }
  1425. if (status & ISR_OVER)
  1426. if (netif_msg_intr(adapter))
  1427. dev_warn(&pdev->dev,
  1428. "TX/RX overflow (status = 0x%x)\n",
  1429. status & ISR_OVER);
  1430. /* link event */
  1431. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1432. netdev->stats.tx_carrier_errors++;
  1433. atl1c_link_chg_event(adapter);
  1434. break;
  1435. }
  1436. } while (--max_ints > 0);
  1437. /* re-enable Interrupt*/
  1438. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1439. return handled;
  1440. }
  1441. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1442. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1443. {
  1444. /*
  1445. * The pid field in RRS in not correct sometimes, so we
  1446. * cannot figure out if the packet is fragmented or not,
  1447. * so we tell the KERNEL CHECKSUM_NONE
  1448. */
  1449. skb_checksum_none_assert(skb);
  1450. }
  1451. static struct sk_buff *atl1c_alloc_skb(struct atl1c_adapter *adapter)
  1452. {
  1453. struct sk_buff *skb;
  1454. struct page *page;
  1455. if (adapter->rx_frag_size > PAGE_SIZE)
  1456. return netdev_alloc_skb(adapter->netdev,
  1457. adapter->rx_buffer_len);
  1458. page = adapter->rx_page;
  1459. if (!page) {
  1460. adapter->rx_page = page = alloc_page(GFP_ATOMIC);
  1461. if (unlikely(!page))
  1462. return NULL;
  1463. adapter->rx_page_offset = 0;
  1464. }
  1465. skb = build_skb(page_address(page) + adapter->rx_page_offset,
  1466. adapter->rx_frag_size);
  1467. if (likely(skb)) {
  1468. adapter->rx_page_offset += adapter->rx_frag_size;
  1469. if (adapter->rx_page_offset >= PAGE_SIZE)
  1470. adapter->rx_page = NULL;
  1471. else
  1472. get_page(page);
  1473. }
  1474. return skb;
  1475. }
  1476. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1477. {
  1478. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1479. struct pci_dev *pdev = adapter->pdev;
  1480. struct atl1c_buffer *buffer_info, *next_info;
  1481. struct sk_buff *skb;
  1482. void *vir_addr = NULL;
  1483. u16 num_alloc = 0;
  1484. u16 rfd_next_to_use, next_next;
  1485. struct atl1c_rx_free_desc *rfd_desc;
  1486. dma_addr_t mapping;
  1487. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1488. if (++next_next == rfd_ring->count)
  1489. next_next = 0;
  1490. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1491. next_info = &rfd_ring->buffer_info[next_next];
  1492. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1493. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1494. skb = atl1c_alloc_skb(adapter);
  1495. if (unlikely(!skb)) {
  1496. if (netif_msg_rx_err(adapter))
  1497. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1498. break;
  1499. }
  1500. /*
  1501. * Make buffer alignment 2 beyond a 16 byte boundary
  1502. * this will result in a 16 byte aligned IP header after
  1503. * the 14 byte MAC header is removed
  1504. */
  1505. vir_addr = skb->data;
  1506. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1507. buffer_info->skb = skb;
  1508. buffer_info->length = adapter->rx_buffer_len;
  1509. mapping = pci_map_single(pdev, vir_addr,
  1510. buffer_info->length,
  1511. PCI_DMA_FROMDEVICE);
  1512. if (unlikely(pci_dma_mapping_error(pdev, mapping))) {
  1513. dev_kfree_skb(skb);
  1514. buffer_info->skb = NULL;
  1515. buffer_info->length = 0;
  1516. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  1517. netif_warn(adapter, rx_err, adapter->netdev, "RX pci_map_single failed");
  1518. break;
  1519. }
  1520. buffer_info->dma = mapping;
  1521. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1522. ATL1C_PCIMAP_FROMDEVICE);
  1523. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1524. rfd_next_to_use = next_next;
  1525. if (++next_next == rfd_ring->count)
  1526. next_next = 0;
  1527. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1528. next_info = &rfd_ring->buffer_info[next_next];
  1529. num_alloc++;
  1530. }
  1531. if (num_alloc) {
  1532. /* TODO: update mailbox here */
  1533. wmb();
  1534. rfd_ring->next_to_use = rfd_next_to_use;
  1535. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1536. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1537. }
  1538. return num_alloc;
  1539. }
  1540. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1541. struct atl1c_recv_ret_status *rrs, u16 num)
  1542. {
  1543. u16 i;
  1544. /* the relationship between rrd and rfd is one map one */
  1545. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1546. rrd_ring->next_to_clean)) {
  1547. rrs->word3 &= ~RRS_RXD_UPDATED;
  1548. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1549. rrd_ring->next_to_clean = 0;
  1550. }
  1551. }
  1552. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1553. struct atl1c_recv_ret_status *rrs, u16 num)
  1554. {
  1555. u16 i;
  1556. u16 rfd_index;
  1557. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1558. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1559. RRS_RX_RFD_INDEX_MASK;
  1560. for (i = 0; i < num; i++) {
  1561. buffer_info[rfd_index].skb = NULL;
  1562. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1563. ATL1C_BUFFER_FREE);
  1564. if (++rfd_index == rfd_ring->count)
  1565. rfd_index = 0;
  1566. }
  1567. rfd_ring->next_to_clean = rfd_index;
  1568. }
  1569. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1570. int *work_done, int work_to_do)
  1571. {
  1572. u16 rfd_num, rfd_index;
  1573. u16 count = 0;
  1574. u16 length;
  1575. struct pci_dev *pdev = adapter->pdev;
  1576. struct net_device *netdev = adapter->netdev;
  1577. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1578. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1579. struct sk_buff *skb;
  1580. struct atl1c_recv_ret_status *rrs;
  1581. struct atl1c_buffer *buffer_info;
  1582. while (1) {
  1583. if (*work_done >= work_to_do)
  1584. break;
  1585. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1586. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1587. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1588. RRS_RX_RFD_CNT_MASK;
  1589. if (unlikely(rfd_num != 1))
  1590. /* TODO support mul rfd*/
  1591. if (netif_msg_rx_err(adapter))
  1592. dev_warn(&pdev->dev,
  1593. "Multi rfd not support yet!\n");
  1594. goto rrs_checked;
  1595. } else {
  1596. break;
  1597. }
  1598. rrs_checked:
  1599. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1600. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1601. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1602. if (netif_msg_rx_err(adapter))
  1603. dev_warn(&pdev->dev,
  1604. "wrong packet! rrs word3 is %x\n",
  1605. rrs->word3);
  1606. continue;
  1607. }
  1608. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1609. RRS_PKT_SIZE_MASK);
  1610. /* Good Receive */
  1611. if (likely(rfd_num == 1)) {
  1612. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1613. RRS_RX_RFD_INDEX_MASK;
  1614. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1615. pci_unmap_single(pdev, buffer_info->dma,
  1616. buffer_info->length, PCI_DMA_FROMDEVICE);
  1617. skb = buffer_info->skb;
  1618. } else {
  1619. /* TODO */
  1620. if (netif_msg_rx_err(adapter))
  1621. dev_warn(&pdev->dev,
  1622. "Multi rfd not support yet!\n");
  1623. break;
  1624. }
  1625. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1626. skb_put(skb, length - ETH_FCS_LEN);
  1627. skb->protocol = eth_type_trans(skb, netdev);
  1628. atl1c_rx_checksum(adapter, skb, rrs);
  1629. if (rrs->word3 & RRS_VLAN_INS) {
  1630. u16 vlan;
  1631. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1632. vlan = le16_to_cpu(vlan);
  1633. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
  1634. }
  1635. netif_receive_skb(skb);
  1636. (*work_done)++;
  1637. count++;
  1638. }
  1639. if (count)
  1640. atl1c_alloc_rx_buffer(adapter);
  1641. }
  1642. /**
  1643. * atl1c_clean - NAPI Rx polling callback
  1644. */
  1645. static int atl1c_clean(struct napi_struct *napi, int budget)
  1646. {
  1647. struct atl1c_adapter *adapter =
  1648. container_of(napi, struct atl1c_adapter, napi);
  1649. int work_done = 0;
  1650. /* Keep link state information with original netdev */
  1651. if (!netif_carrier_ok(adapter->netdev))
  1652. goto quit_polling;
  1653. /* just enable one RXQ */
  1654. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1655. if (work_done < budget) {
  1656. quit_polling:
  1657. napi_complete(napi);
  1658. adapter->hw.intr_mask |= ISR_RX_PKT;
  1659. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1660. }
  1661. return work_done;
  1662. }
  1663. #ifdef CONFIG_NET_POLL_CONTROLLER
  1664. /*
  1665. * Polling 'interrupt' - used by things like netconsole to send skbs
  1666. * without having to re-enable interrupts. It's not called while
  1667. * the interrupt routine is executing.
  1668. */
  1669. static void atl1c_netpoll(struct net_device *netdev)
  1670. {
  1671. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1672. disable_irq(adapter->pdev->irq);
  1673. atl1c_intr(adapter->pdev->irq, netdev);
  1674. enable_irq(adapter->pdev->irq);
  1675. }
  1676. #endif
  1677. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1678. {
  1679. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1680. u16 next_to_use = 0;
  1681. u16 next_to_clean = 0;
  1682. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1683. next_to_use = tpd_ring->next_to_use;
  1684. return (u16)(next_to_clean > next_to_use) ?
  1685. (next_to_clean - next_to_use - 1) :
  1686. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1687. }
  1688. /*
  1689. * get next usable tpd
  1690. * Note: should call atl1c_tdp_avail to make sure
  1691. * there is enough tpd to use
  1692. */
  1693. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1694. enum atl1c_trans_queue type)
  1695. {
  1696. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1697. struct atl1c_tpd_desc *tpd_desc;
  1698. u16 next_to_use = 0;
  1699. next_to_use = tpd_ring->next_to_use;
  1700. if (++tpd_ring->next_to_use == tpd_ring->count)
  1701. tpd_ring->next_to_use = 0;
  1702. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1703. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1704. return tpd_desc;
  1705. }
  1706. static struct atl1c_buffer *
  1707. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1708. {
  1709. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1710. return &tpd_ring->buffer_info[tpd -
  1711. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1712. }
  1713. /* Calculate the transmit packet descript needed*/
  1714. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1715. {
  1716. u16 tpd_req;
  1717. u16 proto_hdr_len = 0;
  1718. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1719. if (skb_is_gso(skb)) {
  1720. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1721. if (proto_hdr_len < skb_headlen(skb))
  1722. tpd_req++;
  1723. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1724. tpd_req++;
  1725. }
  1726. return tpd_req;
  1727. }
  1728. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1729. struct sk_buff *skb,
  1730. struct atl1c_tpd_desc **tpd,
  1731. enum atl1c_trans_queue type)
  1732. {
  1733. struct pci_dev *pdev = adapter->pdev;
  1734. unsigned short offload_type;
  1735. u8 hdr_len;
  1736. u32 real_len;
  1737. if (skb_is_gso(skb)) {
  1738. int err;
  1739. err = skb_cow_head(skb, 0);
  1740. if (err < 0)
  1741. return err;
  1742. offload_type = skb_shinfo(skb)->gso_type;
  1743. if (offload_type & SKB_GSO_TCPV4) {
  1744. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1745. + ntohs(ip_hdr(skb)->tot_len));
  1746. if (real_len < skb->len)
  1747. pskb_trim(skb, real_len);
  1748. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1749. if (unlikely(skb->len == hdr_len)) {
  1750. /* only xsum need */
  1751. if (netif_msg_tx_queued(adapter))
  1752. dev_warn(&pdev->dev,
  1753. "IPV4 tso with zero data??\n");
  1754. goto check_sum;
  1755. } else {
  1756. ip_hdr(skb)->check = 0;
  1757. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1758. ip_hdr(skb)->saddr,
  1759. ip_hdr(skb)->daddr,
  1760. 0, IPPROTO_TCP, 0);
  1761. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1762. }
  1763. }
  1764. if (offload_type & SKB_GSO_TCPV6) {
  1765. struct atl1c_tpd_ext_desc *etpd =
  1766. *(struct atl1c_tpd_ext_desc **)(tpd);
  1767. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1768. *tpd = atl1c_get_tpd(adapter, type);
  1769. ipv6_hdr(skb)->payload_len = 0;
  1770. /* check payload == 0 byte ? */
  1771. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1772. if (unlikely(skb->len == hdr_len)) {
  1773. /* only xsum need */
  1774. if (netif_msg_tx_queued(adapter))
  1775. dev_warn(&pdev->dev,
  1776. "IPV6 tso with zero data??\n");
  1777. goto check_sum;
  1778. } else
  1779. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1780. &ipv6_hdr(skb)->saddr,
  1781. &ipv6_hdr(skb)->daddr,
  1782. 0, IPPROTO_TCP, 0);
  1783. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1784. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1785. etpd->pkt_len = cpu_to_le32(skb->len);
  1786. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1787. }
  1788. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1789. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1790. TPD_TCPHDR_OFFSET_SHIFT;
  1791. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1792. TPD_MSS_SHIFT;
  1793. return 0;
  1794. }
  1795. check_sum:
  1796. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1797. u8 css, cso;
  1798. cso = skb_checksum_start_offset(skb);
  1799. if (unlikely(cso & 0x1)) {
  1800. if (netif_msg_tx_err(adapter))
  1801. dev_err(&adapter->pdev->dev,
  1802. "payload offset should not an event number\n");
  1803. return -1;
  1804. } else {
  1805. css = cso + skb->csum_offset;
  1806. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1807. TPD_PLOADOFFSET_SHIFT;
  1808. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1809. TPD_CCSUM_OFFSET_SHIFT;
  1810. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1811. }
  1812. }
  1813. return 0;
  1814. }
  1815. static void atl1c_tx_rollback(struct atl1c_adapter *adpt,
  1816. struct atl1c_tpd_desc *first_tpd,
  1817. enum atl1c_trans_queue type)
  1818. {
  1819. struct atl1c_tpd_ring *tpd_ring = &adpt->tpd_ring[type];
  1820. struct atl1c_buffer *buffer_info;
  1821. struct atl1c_tpd_desc *tpd;
  1822. u16 first_index, index;
  1823. first_index = first_tpd - (struct atl1c_tpd_desc *)tpd_ring->desc;
  1824. index = first_index;
  1825. while (index != tpd_ring->next_to_use) {
  1826. tpd = ATL1C_TPD_DESC(tpd_ring, index);
  1827. buffer_info = &tpd_ring->buffer_info[index];
  1828. atl1c_clean_buffer(adpt->pdev, buffer_info);
  1829. memset(tpd, 0, sizeof(struct atl1c_tpd_desc));
  1830. if (++index == tpd_ring->count)
  1831. index = 0;
  1832. }
  1833. tpd_ring->next_to_use = first_index;
  1834. }
  1835. static int atl1c_tx_map(struct atl1c_adapter *adapter,
  1836. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1837. enum atl1c_trans_queue type)
  1838. {
  1839. struct atl1c_tpd_desc *use_tpd = NULL;
  1840. struct atl1c_buffer *buffer_info = NULL;
  1841. u16 buf_len = skb_headlen(skb);
  1842. u16 map_len = 0;
  1843. u16 mapped_len = 0;
  1844. u16 hdr_len = 0;
  1845. u16 nr_frags;
  1846. u16 f;
  1847. int tso;
  1848. nr_frags = skb_shinfo(skb)->nr_frags;
  1849. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1850. if (tso) {
  1851. /* TSO */
  1852. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1853. use_tpd = tpd;
  1854. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1855. buffer_info->length = map_len;
  1856. buffer_info->dma = pci_map_single(adapter->pdev,
  1857. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1858. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1859. buffer_info->dma)))
  1860. goto err_dma;
  1861. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1862. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1863. ATL1C_PCIMAP_TODEVICE);
  1864. mapped_len += map_len;
  1865. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1866. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1867. }
  1868. if (mapped_len < buf_len) {
  1869. /* mapped_len == 0, means we should use the first tpd,
  1870. which is given by caller */
  1871. if (mapped_len == 0)
  1872. use_tpd = tpd;
  1873. else {
  1874. use_tpd = atl1c_get_tpd(adapter, type);
  1875. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1876. }
  1877. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1878. buffer_info->length = buf_len - mapped_len;
  1879. buffer_info->dma =
  1880. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1881. buffer_info->length, PCI_DMA_TODEVICE);
  1882. if (unlikely(pci_dma_mapping_error(adapter->pdev,
  1883. buffer_info->dma)))
  1884. goto err_dma;
  1885. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1886. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1887. ATL1C_PCIMAP_TODEVICE);
  1888. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1889. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1890. }
  1891. for (f = 0; f < nr_frags; f++) {
  1892. struct skb_frag_struct *frag;
  1893. frag = &skb_shinfo(skb)->frags[f];
  1894. use_tpd = atl1c_get_tpd(adapter, type);
  1895. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1896. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1897. buffer_info->length = skb_frag_size(frag);
  1898. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1899. frag, 0,
  1900. buffer_info->length,
  1901. DMA_TO_DEVICE);
  1902. if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma))
  1903. goto err_dma;
  1904. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1905. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1906. ATL1C_PCIMAP_TODEVICE);
  1907. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1908. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1909. }
  1910. /* The last tpd */
  1911. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1912. /* The last buffer info contain the skb address,
  1913. so it will be free after unmap */
  1914. buffer_info->skb = skb;
  1915. return 0;
  1916. err_dma:
  1917. buffer_info->dma = 0;
  1918. buffer_info->length = 0;
  1919. return -1;
  1920. }
  1921. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1922. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1923. {
  1924. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1925. u16 reg;
  1926. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1927. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1928. }
  1929. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1930. struct net_device *netdev)
  1931. {
  1932. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1933. unsigned long flags;
  1934. u16 tpd_req = 1;
  1935. struct atl1c_tpd_desc *tpd;
  1936. enum atl1c_trans_queue type = atl1c_trans_normal;
  1937. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1938. dev_kfree_skb_any(skb);
  1939. return NETDEV_TX_OK;
  1940. }
  1941. tpd_req = atl1c_cal_tpd_req(skb);
  1942. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1943. if (netif_msg_pktdata(adapter))
  1944. dev_info(&adapter->pdev->dev, "tx locked\n");
  1945. return NETDEV_TX_LOCKED;
  1946. }
  1947. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1948. /* no enough descriptor, just stop queue */
  1949. netif_stop_queue(netdev);
  1950. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1951. return NETDEV_TX_BUSY;
  1952. }
  1953. tpd = atl1c_get_tpd(adapter, type);
  1954. /* do TSO and check sum */
  1955. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1956. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1957. dev_kfree_skb_any(skb);
  1958. return NETDEV_TX_OK;
  1959. }
  1960. if (unlikely(skb_vlan_tag_present(skb))) {
  1961. u16 vlan = skb_vlan_tag_get(skb);
  1962. __le16 tag;
  1963. vlan = cpu_to_le16(vlan);
  1964. AT_VLAN_TO_TAG(vlan, tag);
  1965. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1966. tpd->vlan_tag = tag;
  1967. }
  1968. if (skb_network_offset(skb) != ETH_HLEN)
  1969. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1970. if (atl1c_tx_map(adapter, skb, tpd, type) < 0) {
  1971. netif_info(adapter, tx_done, adapter->netdev,
  1972. "tx-skb droppted due to dma error\n");
  1973. /* roll back tpd/buffer */
  1974. atl1c_tx_rollback(adapter, tpd, type);
  1975. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1976. dev_kfree_skb_any(skb);
  1977. } else {
  1978. netdev_sent_queue(adapter->netdev, skb->len);
  1979. atl1c_tx_queue(adapter, skb, tpd, type);
  1980. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1981. }
  1982. return NETDEV_TX_OK;
  1983. }
  1984. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1985. {
  1986. struct net_device *netdev = adapter->netdev;
  1987. free_irq(adapter->pdev->irq, netdev);
  1988. if (adapter->have_msi)
  1989. pci_disable_msi(adapter->pdev);
  1990. }
  1991. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1992. {
  1993. struct pci_dev *pdev = adapter->pdev;
  1994. struct net_device *netdev = adapter->netdev;
  1995. int flags = 0;
  1996. int err = 0;
  1997. adapter->have_msi = true;
  1998. err = pci_enable_msi(adapter->pdev);
  1999. if (err) {
  2000. if (netif_msg_ifup(adapter))
  2001. dev_err(&pdev->dev,
  2002. "Unable to allocate MSI interrupt Error: %d\n",
  2003. err);
  2004. adapter->have_msi = false;
  2005. }
  2006. if (!adapter->have_msi)
  2007. flags |= IRQF_SHARED;
  2008. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  2009. netdev->name, netdev);
  2010. if (err) {
  2011. if (netif_msg_ifup(adapter))
  2012. dev_err(&pdev->dev,
  2013. "Unable to allocate interrupt Error: %d\n",
  2014. err);
  2015. if (adapter->have_msi)
  2016. pci_disable_msi(adapter->pdev);
  2017. return err;
  2018. }
  2019. if (netif_msg_ifup(adapter))
  2020. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  2021. return err;
  2022. }
  2023. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  2024. {
  2025. /* release tx-pending skbs and reset tx/rx ring index */
  2026. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  2027. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  2028. atl1c_clean_rx_ring(adapter);
  2029. }
  2030. static int atl1c_up(struct atl1c_adapter *adapter)
  2031. {
  2032. struct net_device *netdev = adapter->netdev;
  2033. int err;
  2034. netif_carrier_off(netdev);
  2035. err = atl1c_configure(adapter);
  2036. if (unlikely(err))
  2037. goto err_up;
  2038. err = atl1c_request_irq(adapter);
  2039. if (unlikely(err))
  2040. goto err_up;
  2041. atl1c_check_link_status(adapter);
  2042. clear_bit(__AT_DOWN, &adapter->flags);
  2043. napi_enable(&adapter->napi);
  2044. atl1c_irq_enable(adapter);
  2045. netif_start_queue(netdev);
  2046. return err;
  2047. err_up:
  2048. atl1c_clean_rx_ring(adapter);
  2049. return err;
  2050. }
  2051. static void atl1c_down(struct atl1c_adapter *adapter)
  2052. {
  2053. struct net_device *netdev = adapter->netdev;
  2054. atl1c_del_timer(adapter);
  2055. adapter->work_event = 0; /* clear all event */
  2056. /* signal that we're down so the interrupt handler does not
  2057. * reschedule our watchdog timer */
  2058. set_bit(__AT_DOWN, &adapter->flags);
  2059. netif_carrier_off(netdev);
  2060. napi_disable(&adapter->napi);
  2061. atl1c_irq_disable(adapter);
  2062. atl1c_free_irq(adapter);
  2063. /* disable ASPM if device inactive */
  2064. atl1c_disable_l0s_l1(&adapter->hw);
  2065. /* reset MAC to disable all RX/TX */
  2066. atl1c_reset_mac(&adapter->hw);
  2067. msleep(1);
  2068. adapter->link_speed = SPEED_0;
  2069. adapter->link_duplex = -1;
  2070. atl1c_reset_dma_ring(adapter);
  2071. }
  2072. /**
  2073. * atl1c_open - Called when a network interface is made active
  2074. * @netdev: network interface device structure
  2075. *
  2076. * Returns 0 on success, negative value on failure
  2077. *
  2078. * The open entry point is called when a network interface is made
  2079. * active by the system (IFF_UP). At this point all resources needed
  2080. * for transmit and receive operations are allocated, the interrupt
  2081. * handler is registered with the OS, the watchdog timer is started,
  2082. * and the stack is notified that the interface is ready.
  2083. */
  2084. static int atl1c_open(struct net_device *netdev)
  2085. {
  2086. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2087. int err;
  2088. /* disallow open during test */
  2089. if (test_bit(__AT_TESTING, &adapter->flags))
  2090. return -EBUSY;
  2091. /* allocate rx/tx dma buffer & descriptors */
  2092. err = atl1c_setup_ring_resources(adapter);
  2093. if (unlikely(err))
  2094. return err;
  2095. err = atl1c_up(adapter);
  2096. if (unlikely(err))
  2097. goto err_up;
  2098. return 0;
  2099. err_up:
  2100. atl1c_free_irq(adapter);
  2101. atl1c_free_ring_resources(adapter);
  2102. atl1c_reset_mac(&adapter->hw);
  2103. return err;
  2104. }
  2105. /**
  2106. * atl1c_close - Disables a network interface
  2107. * @netdev: network interface device structure
  2108. *
  2109. * Returns 0, this is not allowed to fail
  2110. *
  2111. * The close entry point is called when an interface is de-activated
  2112. * by the OS. The hardware is still under the drivers control, but
  2113. * needs to be disabled. A global MAC reset is issued to stop the
  2114. * hardware, and all transmit and receive resources are freed.
  2115. */
  2116. static int atl1c_close(struct net_device *netdev)
  2117. {
  2118. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2119. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2120. set_bit(__AT_DOWN, &adapter->flags);
  2121. cancel_work_sync(&adapter->common_task);
  2122. atl1c_down(adapter);
  2123. atl1c_free_ring_resources(adapter);
  2124. return 0;
  2125. }
  2126. static int atl1c_suspend(struct device *dev)
  2127. {
  2128. struct pci_dev *pdev = to_pci_dev(dev);
  2129. struct net_device *netdev = pci_get_drvdata(pdev);
  2130. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2131. struct atl1c_hw *hw = &adapter->hw;
  2132. u32 wufc = adapter->wol;
  2133. atl1c_disable_l0s_l1(hw);
  2134. if (netif_running(netdev)) {
  2135. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2136. atl1c_down(adapter);
  2137. }
  2138. netif_device_detach(netdev);
  2139. if (wufc)
  2140. if (atl1c_phy_to_ps_link(hw) != 0)
  2141. dev_dbg(&pdev->dev, "phy power saving failed");
  2142. atl1c_power_saving(hw, wufc);
  2143. return 0;
  2144. }
  2145. #ifdef CONFIG_PM_SLEEP
  2146. static int atl1c_resume(struct device *dev)
  2147. {
  2148. struct pci_dev *pdev = to_pci_dev(dev);
  2149. struct net_device *netdev = pci_get_drvdata(pdev);
  2150. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2151. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2152. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2153. atl1c_phy_reset(&adapter->hw);
  2154. atl1c_reset_mac(&adapter->hw);
  2155. atl1c_phy_init(&adapter->hw);
  2156. #if 0
  2157. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2158. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2159. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2160. #endif
  2161. netif_device_attach(netdev);
  2162. if (netif_running(netdev))
  2163. atl1c_up(adapter);
  2164. return 0;
  2165. }
  2166. #endif
  2167. static void atl1c_shutdown(struct pci_dev *pdev)
  2168. {
  2169. struct net_device *netdev = pci_get_drvdata(pdev);
  2170. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2171. atl1c_suspend(&pdev->dev);
  2172. pci_wake_from_d3(pdev, adapter->wol);
  2173. pci_set_power_state(pdev, PCI_D3hot);
  2174. }
  2175. static const struct net_device_ops atl1c_netdev_ops = {
  2176. .ndo_open = atl1c_open,
  2177. .ndo_stop = atl1c_close,
  2178. .ndo_validate_addr = eth_validate_addr,
  2179. .ndo_start_xmit = atl1c_xmit_frame,
  2180. .ndo_set_mac_address = atl1c_set_mac_addr,
  2181. .ndo_set_rx_mode = atl1c_set_multi,
  2182. .ndo_change_mtu = atl1c_change_mtu,
  2183. .ndo_fix_features = atl1c_fix_features,
  2184. .ndo_set_features = atl1c_set_features,
  2185. .ndo_do_ioctl = atl1c_ioctl,
  2186. .ndo_tx_timeout = atl1c_tx_timeout,
  2187. .ndo_get_stats = atl1c_get_stats,
  2188. #ifdef CONFIG_NET_POLL_CONTROLLER
  2189. .ndo_poll_controller = atl1c_netpoll,
  2190. #endif
  2191. };
  2192. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2193. {
  2194. SET_NETDEV_DEV(netdev, &pdev->dev);
  2195. pci_set_drvdata(pdev, netdev);
  2196. netdev->netdev_ops = &atl1c_netdev_ops;
  2197. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2198. atl1c_set_ethtool_ops(netdev);
  2199. /* TODO: add when ready */
  2200. netdev->hw_features = NETIF_F_SG |
  2201. NETIF_F_HW_CSUM |
  2202. NETIF_F_HW_VLAN_CTAG_RX |
  2203. NETIF_F_TSO |
  2204. NETIF_F_TSO6;
  2205. netdev->features = netdev->hw_features |
  2206. NETIF_F_HW_VLAN_CTAG_TX;
  2207. return 0;
  2208. }
  2209. /**
  2210. * atl1c_probe - Device Initialization Routine
  2211. * @pdev: PCI device information struct
  2212. * @ent: entry in atl1c_pci_tbl
  2213. *
  2214. * Returns 0 on success, negative on failure
  2215. *
  2216. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2217. * The OS initialization, configuring of the adapter private structure,
  2218. * and a hardware reset occur.
  2219. */
  2220. static int atl1c_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2221. {
  2222. struct net_device *netdev;
  2223. struct atl1c_adapter *adapter;
  2224. static int cards_found;
  2225. int err = 0;
  2226. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2227. err = pci_enable_device_mem(pdev);
  2228. if (err) {
  2229. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2230. return err;
  2231. }
  2232. /*
  2233. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2234. * shared register for the high 32 bits, so only a single, aligned,
  2235. * 4 GB physical address range can be used at a time.
  2236. *
  2237. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2238. * worth. It is far easier to limit to 32-bit DMA than update
  2239. * various kernel subsystems to support the mechanics required by a
  2240. * fixed-high-32-bit system.
  2241. */
  2242. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2243. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2244. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2245. goto err_dma;
  2246. }
  2247. err = pci_request_regions(pdev, atl1c_driver_name);
  2248. if (err) {
  2249. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2250. goto err_pci_reg;
  2251. }
  2252. pci_set_master(pdev);
  2253. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2254. if (netdev == NULL) {
  2255. err = -ENOMEM;
  2256. goto err_alloc_etherdev;
  2257. }
  2258. err = atl1c_init_netdev(netdev, pdev);
  2259. if (err) {
  2260. dev_err(&pdev->dev, "init netdevice failed\n");
  2261. goto err_init_netdev;
  2262. }
  2263. adapter = netdev_priv(netdev);
  2264. adapter->bd_number = cards_found;
  2265. adapter->netdev = netdev;
  2266. adapter->pdev = pdev;
  2267. adapter->hw.adapter = adapter;
  2268. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2269. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2270. if (!adapter->hw.hw_addr) {
  2271. err = -EIO;
  2272. dev_err(&pdev->dev, "cannot map device registers\n");
  2273. goto err_ioremap;
  2274. }
  2275. /* init mii data */
  2276. adapter->mii.dev = netdev;
  2277. adapter->mii.mdio_read = atl1c_mdio_read;
  2278. adapter->mii.mdio_write = atl1c_mdio_write;
  2279. adapter->mii.phy_id_mask = 0x1f;
  2280. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2281. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2282. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2283. (unsigned long)adapter);
  2284. /* setup the private structure */
  2285. err = atl1c_sw_init(adapter);
  2286. if (err) {
  2287. dev_err(&pdev->dev, "net device private data init failed\n");
  2288. goto err_sw_init;
  2289. }
  2290. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2291. /* Init GPHY as early as possible due to power saving issue */
  2292. atl1c_phy_reset(&adapter->hw);
  2293. err = atl1c_reset_mac(&adapter->hw);
  2294. if (err) {
  2295. err = -EIO;
  2296. goto err_reset;
  2297. }
  2298. /* reset the controller to
  2299. * put the device in a known good starting state */
  2300. err = atl1c_phy_init(&adapter->hw);
  2301. if (err) {
  2302. err = -EIO;
  2303. goto err_reset;
  2304. }
  2305. if (atl1c_read_mac_addr(&adapter->hw)) {
  2306. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2307. netdev->addr_assign_type = NET_ADDR_RANDOM;
  2308. }
  2309. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2310. if (netif_msg_probe(adapter))
  2311. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2312. adapter->hw.mac_addr);
  2313. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2314. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2315. adapter->work_event = 0;
  2316. err = register_netdev(netdev);
  2317. if (err) {
  2318. dev_err(&pdev->dev, "register netdevice failed\n");
  2319. goto err_register;
  2320. }
  2321. if (netif_msg_probe(adapter))
  2322. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2323. cards_found++;
  2324. return 0;
  2325. err_reset:
  2326. err_register:
  2327. err_sw_init:
  2328. iounmap(adapter->hw.hw_addr);
  2329. err_init_netdev:
  2330. err_ioremap:
  2331. free_netdev(netdev);
  2332. err_alloc_etherdev:
  2333. pci_release_regions(pdev);
  2334. err_pci_reg:
  2335. err_dma:
  2336. pci_disable_device(pdev);
  2337. return err;
  2338. }
  2339. /**
  2340. * atl1c_remove - Device Removal Routine
  2341. * @pdev: PCI device information struct
  2342. *
  2343. * atl1c_remove is called by the PCI subsystem to alert the driver
  2344. * that it should release a PCI device. The could be caused by a
  2345. * Hot-Plug event, or because the driver is going to be removed from
  2346. * memory.
  2347. */
  2348. static void atl1c_remove(struct pci_dev *pdev)
  2349. {
  2350. struct net_device *netdev = pci_get_drvdata(pdev);
  2351. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2352. unregister_netdev(netdev);
  2353. /* restore permanent address */
  2354. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2355. atl1c_phy_disable(&adapter->hw);
  2356. iounmap(adapter->hw.hw_addr);
  2357. pci_release_regions(pdev);
  2358. pci_disable_device(pdev);
  2359. free_netdev(netdev);
  2360. }
  2361. /**
  2362. * atl1c_io_error_detected - called when PCI error is detected
  2363. * @pdev: Pointer to PCI device
  2364. * @state: The current pci connection state
  2365. *
  2366. * This function is called after a PCI bus error affecting
  2367. * this device has been detected.
  2368. */
  2369. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2370. pci_channel_state_t state)
  2371. {
  2372. struct net_device *netdev = pci_get_drvdata(pdev);
  2373. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2374. netif_device_detach(netdev);
  2375. if (state == pci_channel_io_perm_failure)
  2376. return PCI_ERS_RESULT_DISCONNECT;
  2377. if (netif_running(netdev))
  2378. atl1c_down(adapter);
  2379. pci_disable_device(pdev);
  2380. /* Request a slot slot reset. */
  2381. return PCI_ERS_RESULT_NEED_RESET;
  2382. }
  2383. /**
  2384. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2385. * @pdev: Pointer to PCI device
  2386. *
  2387. * Restart the card from scratch, as if from a cold-boot. Implementation
  2388. * resembles the first-half of the e1000_resume routine.
  2389. */
  2390. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2391. {
  2392. struct net_device *netdev = pci_get_drvdata(pdev);
  2393. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2394. if (pci_enable_device(pdev)) {
  2395. if (netif_msg_hw(adapter))
  2396. dev_err(&pdev->dev,
  2397. "Cannot re-enable PCI device after reset\n");
  2398. return PCI_ERS_RESULT_DISCONNECT;
  2399. }
  2400. pci_set_master(pdev);
  2401. pci_enable_wake(pdev, PCI_D3hot, 0);
  2402. pci_enable_wake(pdev, PCI_D3cold, 0);
  2403. atl1c_reset_mac(&adapter->hw);
  2404. return PCI_ERS_RESULT_RECOVERED;
  2405. }
  2406. /**
  2407. * atl1c_io_resume - called when traffic can start flowing again.
  2408. * @pdev: Pointer to PCI device
  2409. *
  2410. * This callback is called when the error recovery driver tells us that
  2411. * its OK to resume normal operation. Implementation resembles the
  2412. * second-half of the atl1c_resume routine.
  2413. */
  2414. static void atl1c_io_resume(struct pci_dev *pdev)
  2415. {
  2416. struct net_device *netdev = pci_get_drvdata(pdev);
  2417. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2418. if (netif_running(netdev)) {
  2419. if (atl1c_up(adapter)) {
  2420. if (netif_msg_hw(adapter))
  2421. dev_err(&pdev->dev,
  2422. "Cannot bring device back up after reset\n");
  2423. return;
  2424. }
  2425. }
  2426. netif_device_attach(netdev);
  2427. }
  2428. static const struct pci_error_handlers atl1c_err_handler = {
  2429. .error_detected = atl1c_io_error_detected,
  2430. .slot_reset = atl1c_io_slot_reset,
  2431. .resume = atl1c_io_resume,
  2432. };
  2433. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2434. static struct pci_driver atl1c_driver = {
  2435. .name = atl1c_driver_name,
  2436. .id_table = atl1c_pci_tbl,
  2437. .probe = atl1c_probe,
  2438. .remove = atl1c_remove,
  2439. .shutdown = atl1c_shutdown,
  2440. .err_handler = &atl1c_err_handler,
  2441. .driver.pm = &atl1c_pm_ops,
  2442. };
  2443. module_pci_driver(atl1c_driver);