mv88e6060.c 6.4 KB

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  1. /*
  2. * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
  3. * Copyright (c) 2008-2009 Marvell Semiconductor
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/jiffies.h>
  12. #include <linux/list.h>
  13. #include <linux/module.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/phy.h>
  16. #include <net/dsa.h>
  17. #include "mv88e6060.h"
  18. static int reg_read(struct dsa_switch *ds, int addr, int reg)
  19. {
  20. struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  21. if (bus == NULL)
  22. return -EINVAL;
  23. return mdiobus_read_nested(bus, ds->pd->sw_addr + addr, reg);
  24. }
  25. #define REG_READ(addr, reg) \
  26. ({ \
  27. int __ret; \
  28. \
  29. __ret = reg_read(ds, addr, reg); \
  30. if (__ret < 0) \
  31. return __ret; \
  32. __ret; \
  33. })
  34. static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
  35. {
  36. struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
  37. if (bus == NULL)
  38. return -EINVAL;
  39. return mdiobus_write_nested(bus, ds->pd->sw_addr + addr, reg, val);
  40. }
  41. #define REG_WRITE(addr, reg, val) \
  42. ({ \
  43. int __ret; \
  44. \
  45. __ret = reg_write(ds, addr, reg, val); \
  46. if (__ret < 0) \
  47. return __ret; \
  48. })
  49. static char *mv88e6060_probe(struct device *host_dev, int sw_addr)
  50. {
  51. struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  52. int ret;
  53. if (bus == NULL)
  54. return NULL;
  55. ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
  56. if (ret >= 0) {
  57. if (ret == PORT_SWITCH_ID_6060)
  58. return "Marvell 88E6060 (A0)";
  59. if (ret == PORT_SWITCH_ID_6060_R1 ||
  60. ret == PORT_SWITCH_ID_6060_R2)
  61. return "Marvell 88E6060 (B0)";
  62. if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
  63. return "Marvell 88E6060";
  64. }
  65. return NULL;
  66. }
  67. static int mv88e6060_switch_reset(struct dsa_switch *ds)
  68. {
  69. int i;
  70. int ret;
  71. unsigned long timeout;
  72. /* Set all ports to the disabled state. */
  73. for (i = 0; i < MV88E6060_PORTS; i++) {
  74. ret = REG_READ(REG_PORT(i), PORT_CONTROL);
  75. REG_WRITE(REG_PORT(i), PORT_CONTROL,
  76. ret & ~PORT_CONTROL_STATE_MASK);
  77. }
  78. /* Wait for transmit queues to drain. */
  79. usleep_range(2000, 4000);
  80. /* Reset the switch. */
  81. REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
  82. GLOBAL_ATU_CONTROL_SWRESET |
  83. GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
  84. GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
  85. /* Wait up to one second for reset to complete. */
  86. timeout = jiffies + 1 * HZ;
  87. while (time_before(jiffies, timeout)) {
  88. ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
  89. if (ret & GLOBAL_STATUS_INIT_READY)
  90. break;
  91. usleep_range(1000, 2000);
  92. }
  93. if (time_after(jiffies, timeout))
  94. return -ETIMEDOUT;
  95. return 0;
  96. }
  97. static int mv88e6060_setup_global(struct dsa_switch *ds)
  98. {
  99. /* Disable discarding of frames with excessive collisions,
  100. * set the maximum frame size to 1536 bytes, and mask all
  101. * interrupt sources.
  102. */
  103. REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
  104. /* Enable automatic address learning, set the address
  105. * database size to 1024 entries, and set the default aging
  106. * time to 5 minutes.
  107. */
  108. REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
  109. GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
  110. GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
  111. return 0;
  112. }
  113. static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
  114. {
  115. int addr = REG_PORT(p);
  116. /* Do not force flow control, disable Ingress and Egress
  117. * Header tagging, disable VLAN tunneling, and set the port
  118. * state to Forwarding. Additionally, if this is the CPU
  119. * port, enable Ingress and Egress Trailer tagging mode.
  120. */
  121. REG_WRITE(addr, PORT_CONTROL,
  122. dsa_is_cpu_port(ds, p) ?
  123. PORT_CONTROL_TRAILER |
  124. PORT_CONTROL_INGRESS_MODE |
  125. PORT_CONTROL_STATE_FORWARDING :
  126. PORT_CONTROL_STATE_FORWARDING);
  127. /* Port based VLAN map: give each port its own address
  128. * database, allow the CPU port to talk to each of the 'real'
  129. * ports, and allow each of the 'real' ports to only talk to
  130. * the CPU port.
  131. */
  132. REG_WRITE(addr, PORT_VLAN_MAP,
  133. ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
  134. (dsa_is_cpu_port(ds, p) ?
  135. ds->phys_port_mask :
  136. BIT(ds->dst->cpu_port)));
  137. /* Port Association Vector: when learning source addresses
  138. * of packets, add the address to the address database using
  139. * a port bitmap that has only the bit for this port set and
  140. * the other bits clear.
  141. */
  142. REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
  143. return 0;
  144. }
  145. static int mv88e6060_setup(struct dsa_switch *ds)
  146. {
  147. int i;
  148. int ret;
  149. ret = mv88e6060_switch_reset(ds);
  150. if (ret < 0)
  151. return ret;
  152. /* @@@ initialise atu */
  153. ret = mv88e6060_setup_global(ds);
  154. if (ret < 0)
  155. return ret;
  156. for (i = 0; i < MV88E6060_PORTS; i++) {
  157. ret = mv88e6060_setup_port(ds, i);
  158. if (ret < 0)
  159. return ret;
  160. }
  161. return 0;
  162. }
  163. static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
  164. {
  165. /* Use the same MAC Address as FD Pause frames for all ports */
  166. REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 9) | addr[1]);
  167. REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
  168. REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
  169. return 0;
  170. }
  171. static int mv88e6060_port_to_phy_addr(int port)
  172. {
  173. if (port >= 0 && port < MV88E6060_PORTS)
  174. return port;
  175. return -1;
  176. }
  177. static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
  178. {
  179. int addr;
  180. addr = mv88e6060_port_to_phy_addr(port);
  181. if (addr == -1)
  182. return 0xffff;
  183. return reg_read(ds, addr, regnum);
  184. }
  185. static int
  186. mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  187. {
  188. int addr;
  189. addr = mv88e6060_port_to_phy_addr(port);
  190. if (addr == -1)
  191. return 0xffff;
  192. return reg_write(ds, addr, regnum, val);
  193. }
  194. static struct dsa_switch_driver mv88e6060_switch_driver = {
  195. .tag_protocol = DSA_TAG_PROTO_TRAILER,
  196. .probe = mv88e6060_probe,
  197. .setup = mv88e6060_setup,
  198. .set_addr = mv88e6060_set_addr,
  199. .phy_read = mv88e6060_phy_read,
  200. .phy_write = mv88e6060_phy_write,
  201. };
  202. static int __init mv88e6060_init(void)
  203. {
  204. register_switch_driver(&mv88e6060_switch_driver);
  205. return 0;
  206. }
  207. module_init(mv88e6060_init);
  208. static void __exit mv88e6060_cleanup(void)
  209. {
  210. unregister_switch_driver(&mv88e6060_switch_driver);
  211. }
  212. module_exit(mv88e6060_cleanup);
  213. MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
  214. MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
  215. MODULE_LICENSE("GPL");
  216. MODULE_ALIAS("platform:mv88e6060");