bcm_sf2.h 5.0 KB

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  1. /*
  2. * Broadcom Starfighter2 private context
  3. *
  4. * Copyright (C) 2014, Broadcom Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #ifndef __BCM_SF2_H
  12. #define __BCM_SF2_H
  13. #include <linux/platform_device.h>
  14. #include <linux/kernel.h>
  15. #include <linux/io.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mutex.h>
  18. #include <linux/mii.h>
  19. #include <linux/ethtool.h>
  20. #include <linux/types.h>
  21. #include <linux/bitops.h>
  22. #include <net/dsa.h>
  23. #include "bcm_sf2_regs.h"
  24. struct bcm_sf2_hw_params {
  25. u16 top_rev;
  26. u16 core_rev;
  27. u16 gphy_rev;
  28. u32 num_gphy;
  29. u8 num_acb_queue;
  30. u8 num_rgmii;
  31. u8 num_ports;
  32. u8 fcb_pause_override:1;
  33. u8 acb_packets_inflight:1;
  34. };
  35. #define BCM_SF2_REGS_NAME {\
  36. "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
  37. }
  38. #define BCM_SF2_REGS_NUM 6
  39. struct bcm_sf2_port_status {
  40. unsigned int link;
  41. struct ethtool_eee eee;
  42. u32 vlan_ctl_mask;
  43. struct net_device *bridge_dev;
  44. };
  45. struct bcm_sf2_arl_entry {
  46. u8 port;
  47. u8 mac[ETH_ALEN];
  48. u16 vid;
  49. u8 is_valid:1;
  50. u8 is_age:1;
  51. u8 is_static:1;
  52. };
  53. static inline void bcm_sf2_mac_from_u64(u64 src, u8 *dst)
  54. {
  55. unsigned int i;
  56. for (i = 0; i < ETH_ALEN; i++)
  57. dst[ETH_ALEN - 1 - i] = (src >> (8 * i)) & 0xff;
  58. }
  59. static inline u64 bcm_sf2_mac_to_u64(const u8 *src)
  60. {
  61. unsigned int i;
  62. u64 dst = 0;
  63. for (i = 0; i < ETH_ALEN; i++)
  64. dst |= (u64)src[ETH_ALEN - 1 - i] << (8 * i);
  65. return dst;
  66. }
  67. static inline void bcm_sf2_arl_to_entry(struct bcm_sf2_arl_entry *ent,
  68. u64 mac_vid, u32 fwd_entry)
  69. {
  70. memset(ent, 0, sizeof(*ent));
  71. ent->port = fwd_entry & PORTID_MASK;
  72. ent->is_valid = !!(fwd_entry & ARL_VALID);
  73. ent->is_age = !!(fwd_entry & ARL_AGE);
  74. ent->is_static = !!(fwd_entry & ARL_STATIC);
  75. bcm_sf2_mac_from_u64(mac_vid, ent->mac);
  76. ent->vid = mac_vid >> VID_SHIFT;
  77. }
  78. static inline void bcm_sf2_arl_from_entry(u64 *mac_vid, u32 *fwd_entry,
  79. const struct bcm_sf2_arl_entry *ent)
  80. {
  81. *mac_vid = bcm_sf2_mac_to_u64(ent->mac);
  82. *mac_vid |= (u64)(ent->vid & VID_MASK) << VID_SHIFT;
  83. *fwd_entry = ent->port & PORTID_MASK;
  84. if (ent->is_valid)
  85. *fwd_entry |= ARL_VALID;
  86. if (ent->is_static)
  87. *fwd_entry |= ARL_STATIC;
  88. if (ent->is_age)
  89. *fwd_entry |= ARL_AGE;
  90. }
  91. struct bcm_sf2_priv {
  92. /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
  93. void __iomem *core;
  94. void __iomem *reg;
  95. void __iomem *intrl2_0;
  96. void __iomem *intrl2_1;
  97. void __iomem *fcb;
  98. void __iomem *acb;
  99. /* spinlock protecting access to the indirect registers */
  100. spinlock_t indir_lock;
  101. int irq0;
  102. int irq1;
  103. u32 irq0_stat;
  104. u32 irq0_mask;
  105. u32 irq1_stat;
  106. u32 irq1_mask;
  107. /* Mutex protecting access to the MIB counters */
  108. struct mutex stats_mutex;
  109. struct bcm_sf2_hw_params hw_params;
  110. struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
  111. /* Mask of ports enabled for Wake-on-LAN */
  112. u32 wol_ports_mask;
  113. /* MoCA port location */
  114. int moca_port;
  115. /* Bitmask of ports having an integrated PHY */
  116. unsigned int int_phy_mask;
  117. };
  118. struct bcm_sf2_hw_stats {
  119. const char *string;
  120. u16 reg;
  121. u8 sizeof_stat;
  122. };
  123. #define SF2_IO_MACRO(name) \
  124. static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
  125. { \
  126. return __raw_readl(priv->name + off); \
  127. } \
  128. static inline void name##_writel(struct bcm_sf2_priv *priv, \
  129. u32 val, u32 off) \
  130. { \
  131. __raw_writel(val, priv->name + off); \
  132. } \
  133. /* Accesses to 64-bits register requires us to latch the hi/lo pairs
  134. * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
  135. * spinlock is automatically grabbed and released to provide relative
  136. * atomiticy with latched reads/writes.
  137. */
  138. #define SF2_IO64_MACRO(name) \
  139. static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
  140. { \
  141. u32 indir, dir; \
  142. spin_lock(&priv->indir_lock); \
  143. dir = __raw_readl(priv->name + off); \
  144. indir = reg_readl(priv, REG_DIR_DATA_READ); \
  145. spin_unlock(&priv->indir_lock); \
  146. return (u64)indir << 32 | dir; \
  147. } \
  148. static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
  149. u32 off) \
  150. { \
  151. spin_lock(&priv->indir_lock); \
  152. reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
  153. __raw_writel(lower_32_bits(val), priv->name + off); \
  154. spin_unlock(&priv->indir_lock); \
  155. }
  156. #define SWITCH_INTR_L2(which) \
  157. static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
  158. u32 mask) \
  159. { \
  160. intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
  161. priv->irq##which##_mask &= ~(mask); \
  162. } \
  163. static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
  164. u32 mask) \
  165. { \
  166. intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
  167. priv->irq##which##_mask |= (mask); \
  168. } \
  169. SF2_IO_MACRO(core);
  170. SF2_IO_MACRO(reg);
  171. SF2_IO64_MACRO(core);
  172. SF2_IO_MACRO(intrl2_0);
  173. SF2_IO_MACRO(intrl2_1);
  174. SF2_IO_MACRO(fcb);
  175. SF2_IO_MACRO(acb);
  176. SWITCH_INTR_L2(0);
  177. SWITCH_INTR_L2(1);
  178. #endif /* __BCM_SF2_H */