scif_dma.c 53 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970
  1. /*
  2. * Intel MIC Platform Software Stack (MPSS)
  3. *
  4. * Copyright(c) 2015 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * Intel SCIF driver.
  16. *
  17. */
  18. #include "scif_main.h"
  19. #include "scif_map.h"
  20. /*
  21. * struct scif_dma_comp_cb - SCIF DMA completion callback
  22. *
  23. * @dma_completion_func: DMA completion callback
  24. * @cb_cookie: DMA completion callback cookie
  25. * @temp_buf: Temporary buffer
  26. * @temp_buf_to_free: Temporary buffer to be freed
  27. * @is_cache: Is a kmem_cache allocated buffer
  28. * @dst_offset: Destination registration offset
  29. * @dst_window: Destination registration window
  30. * @len: Length of the temp buffer
  31. * @temp_phys: DMA address of the temp buffer
  32. * @sdev: The SCIF device
  33. * @header_padding: padding for cache line alignment
  34. */
  35. struct scif_dma_comp_cb {
  36. void (*dma_completion_func)(void *cookie);
  37. void *cb_cookie;
  38. u8 *temp_buf;
  39. u8 *temp_buf_to_free;
  40. bool is_cache;
  41. s64 dst_offset;
  42. struct scif_window *dst_window;
  43. size_t len;
  44. dma_addr_t temp_phys;
  45. struct scif_dev *sdev;
  46. int header_padding;
  47. };
  48. /**
  49. * struct scif_copy_work - Work for DMA copy
  50. *
  51. * @src_offset: Starting source offset
  52. * @dst_offset: Starting destination offset
  53. * @src_window: Starting src registered window
  54. * @dst_window: Starting dst registered window
  55. * @loopback: true if this is a loopback DMA transfer
  56. * @len: Length of the transfer
  57. * @comp_cb: DMA copy completion callback
  58. * @remote_dev: The remote SCIF peer device
  59. * @fence_type: polling or interrupt based
  60. * @ordered: is this a tail byte ordered DMA transfer
  61. */
  62. struct scif_copy_work {
  63. s64 src_offset;
  64. s64 dst_offset;
  65. struct scif_window *src_window;
  66. struct scif_window *dst_window;
  67. int loopback;
  68. size_t len;
  69. struct scif_dma_comp_cb *comp_cb;
  70. struct scif_dev *remote_dev;
  71. int fence_type;
  72. bool ordered;
  73. };
  74. /**
  75. * scif_reserve_dma_chan:
  76. * @ep: Endpoint Descriptor.
  77. *
  78. * This routine reserves a DMA channel for a particular
  79. * endpoint. All DMA transfers for an endpoint are always
  80. * programmed on the same DMA channel.
  81. */
  82. int scif_reserve_dma_chan(struct scif_endpt *ep)
  83. {
  84. int err = 0;
  85. struct scif_dev *scifdev;
  86. struct scif_hw_dev *sdev;
  87. struct dma_chan *chan;
  88. /* Loopback DMAs are not supported on the management node */
  89. if (!scif_info.nodeid && scifdev_self(ep->remote_dev))
  90. return 0;
  91. if (scif_info.nodeid)
  92. scifdev = &scif_dev[0];
  93. else
  94. scifdev = ep->remote_dev;
  95. sdev = scifdev->sdev;
  96. if (!sdev->num_dma_ch)
  97. return -ENODEV;
  98. chan = sdev->dma_ch[scifdev->dma_ch_idx];
  99. scifdev->dma_ch_idx = (scifdev->dma_ch_idx + 1) % sdev->num_dma_ch;
  100. mutex_lock(&ep->rma_info.rma_lock);
  101. ep->rma_info.dma_chan = chan;
  102. mutex_unlock(&ep->rma_info.rma_lock);
  103. return err;
  104. }
  105. #ifdef CONFIG_MMU_NOTIFIER
  106. /**
  107. * scif_rma_destroy_tcw:
  108. *
  109. * This routine destroys temporary cached windows
  110. */
  111. static
  112. void __scif_rma_destroy_tcw(struct scif_mmu_notif *mmn,
  113. struct scif_endpt *ep,
  114. u64 start, u64 len)
  115. {
  116. struct list_head *item, *tmp;
  117. struct scif_window *window;
  118. u64 start_va, end_va;
  119. u64 end = start + len;
  120. if (end <= start)
  121. return;
  122. list_for_each_safe(item, tmp, &mmn->tc_reg_list) {
  123. window = list_entry(item, struct scif_window, list);
  124. ep = (struct scif_endpt *)window->ep;
  125. if (!len)
  126. break;
  127. start_va = window->va_for_temp;
  128. end_va = start_va + (window->nr_pages << PAGE_SHIFT);
  129. if (start < start_va && end <= start_va)
  130. break;
  131. if (start >= end_va)
  132. continue;
  133. __scif_rma_destroy_tcw_helper(window);
  134. }
  135. }
  136. static void scif_rma_destroy_tcw(struct scif_mmu_notif *mmn, u64 start, u64 len)
  137. {
  138. struct scif_endpt *ep = mmn->ep;
  139. spin_lock(&ep->rma_info.tc_lock);
  140. __scif_rma_destroy_tcw(mmn, ep, start, len);
  141. spin_unlock(&ep->rma_info.tc_lock);
  142. }
  143. static void scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  144. {
  145. struct list_head *item, *tmp;
  146. struct scif_mmu_notif *mmn;
  147. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  148. mmn = list_entry(item, struct scif_mmu_notif, list);
  149. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  150. }
  151. }
  152. static void __scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  153. {
  154. struct list_head *item, *tmp;
  155. struct scif_mmu_notif *mmn;
  156. spin_lock(&ep->rma_info.tc_lock);
  157. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  158. mmn = list_entry(item, struct scif_mmu_notif, list);
  159. __scif_rma_destroy_tcw(mmn, ep, 0, ULONG_MAX);
  160. }
  161. spin_unlock(&ep->rma_info.tc_lock);
  162. }
  163. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  164. {
  165. if ((cur_bytes >> PAGE_SHIFT) > scif_info.rma_tc_limit)
  166. return false;
  167. if ((atomic_read(&ep->rma_info.tcw_total_pages)
  168. + (cur_bytes >> PAGE_SHIFT)) >
  169. scif_info.rma_tc_limit) {
  170. dev_info(scif_info.mdev.this_device,
  171. "%s %d total=%d, current=%zu reached max\n",
  172. __func__, __LINE__,
  173. atomic_read(&ep->rma_info.tcw_total_pages),
  174. (1 + (cur_bytes >> PAGE_SHIFT)));
  175. scif_rma_destroy_tcw_invalid();
  176. __scif_rma_destroy_tcw_ep(ep);
  177. }
  178. return true;
  179. }
  180. static void scif_mmu_notifier_release(struct mmu_notifier *mn,
  181. struct mm_struct *mm)
  182. {
  183. struct scif_mmu_notif *mmn;
  184. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  185. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  186. schedule_work(&scif_info.misc_work);
  187. }
  188. static void scif_mmu_notifier_invalidate_page(struct mmu_notifier *mn,
  189. struct mm_struct *mm,
  190. unsigned long address)
  191. {
  192. struct scif_mmu_notif *mmn;
  193. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  194. scif_rma_destroy_tcw(mmn, address, PAGE_SIZE);
  195. }
  196. static void scif_mmu_notifier_invalidate_range_start(struct mmu_notifier *mn,
  197. struct mm_struct *mm,
  198. unsigned long start,
  199. unsigned long end)
  200. {
  201. struct scif_mmu_notif *mmn;
  202. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  203. scif_rma_destroy_tcw(mmn, start, end - start);
  204. }
  205. static void scif_mmu_notifier_invalidate_range_end(struct mmu_notifier *mn,
  206. struct mm_struct *mm,
  207. unsigned long start,
  208. unsigned long end)
  209. {
  210. /*
  211. * Nothing to do here, everything needed was done in
  212. * invalidate_range_start.
  213. */
  214. }
  215. static const struct mmu_notifier_ops scif_mmu_notifier_ops = {
  216. .release = scif_mmu_notifier_release,
  217. .clear_flush_young = NULL,
  218. .invalidate_page = scif_mmu_notifier_invalidate_page,
  219. .invalidate_range_start = scif_mmu_notifier_invalidate_range_start,
  220. .invalidate_range_end = scif_mmu_notifier_invalidate_range_end};
  221. static void scif_ep_unregister_mmu_notifier(struct scif_endpt *ep)
  222. {
  223. struct scif_endpt_rma_info *rma = &ep->rma_info;
  224. struct scif_mmu_notif *mmn = NULL;
  225. struct list_head *item, *tmp;
  226. mutex_lock(&ep->rma_info.mmn_lock);
  227. list_for_each_safe(item, tmp, &rma->mmn_list) {
  228. mmn = list_entry(item, struct scif_mmu_notif, list);
  229. mmu_notifier_unregister(&mmn->ep_mmu_notifier, mmn->mm);
  230. list_del(item);
  231. kfree(mmn);
  232. }
  233. mutex_unlock(&ep->rma_info.mmn_lock);
  234. }
  235. static void scif_init_mmu_notifier(struct scif_mmu_notif *mmn,
  236. struct mm_struct *mm, struct scif_endpt *ep)
  237. {
  238. mmn->ep = ep;
  239. mmn->mm = mm;
  240. mmn->ep_mmu_notifier.ops = &scif_mmu_notifier_ops;
  241. INIT_LIST_HEAD(&mmn->list);
  242. INIT_LIST_HEAD(&mmn->tc_reg_list);
  243. }
  244. static struct scif_mmu_notif *
  245. scif_find_mmu_notifier(struct mm_struct *mm, struct scif_endpt_rma_info *rma)
  246. {
  247. struct scif_mmu_notif *mmn;
  248. list_for_each_entry(mmn, &rma->mmn_list, list)
  249. if (mmn->mm == mm)
  250. return mmn;
  251. return NULL;
  252. }
  253. static struct scif_mmu_notif *
  254. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  255. {
  256. struct scif_mmu_notif *mmn
  257. = kzalloc(sizeof(*mmn), GFP_KERNEL);
  258. if (!mmn)
  259. return ERR_PTR(-ENOMEM);
  260. scif_init_mmu_notifier(mmn, current->mm, ep);
  261. if (mmu_notifier_register(&mmn->ep_mmu_notifier, current->mm)) {
  262. kfree(mmn);
  263. return ERR_PTR(-EBUSY);
  264. }
  265. list_add(&mmn->list, &ep->rma_info.mmn_list);
  266. return mmn;
  267. }
  268. /*
  269. * Called from the misc thread to destroy temporary cached windows and
  270. * unregister the MMU notifier for the SCIF endpoint.
  271. */
  272. void scif_mmu_notif_handler(struct work_struct *work)
  273. {
  274. struct list_head *pos, *tmpq;
  275. struct scif_endpt *ep;
  276. restart:
  277. scif_rma_destroy_tcw_invalid();
  278. spin_lock(&scif_info.rmalock);
  279. list_for_each_safe(pos, tmpq, &scif_info.mmu_notif_cleanup) {
  280. ep = list_entry(pos, struct scif_endpt, mmu_list);
  281. list_del(&ep->mmu_list);
  282. spin_unlock(&scif_info.rmalock);
  283. scif_rma_destroy_tcw_ep(ep);
  284. scif_ep_unregister_mmu_notifier(ep);
  285. goto restart;
  286. }
  287. spin_unlock(&scif_info.rmalock);
  288. }
  289. static bool scif_is_set_reg_cache(int flags)
  290. {
  291. return !!(flags & SCIF_RMA_USECACHE);
  292. }
  293. #else
  294. static struct scif_mmu_notif *
  295. scif_find_mmu_notifier(struct mm_struct *mm,
  296. struct scif_endpt_rma_info *rma)
  297. {
  298. return NULL;
  299. }
  300. static struct scif_mmu_notif *
  301. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  302. {
  303. return NULL;
  304. }
  305. void scif_mmu_notif_handler(struct work_struct *work)
  306. {
  307. }
  308. static bool scif_is_set_reg_cache(int flags)
  309. {
  310. return false;
  311. }
  312. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  313. {
  314. return false;
  315. }
  316. #endif
  317. /**
  318. * scif_register_temp:
  319. * @epd: End Point Descriptor.
  320. * @addr: virtual address to/from which to copy
  321. * @len: length of range to copy
  322. * @out_offset: computed offset returned by reference.
  323. * @out_window: allocated registered window returned by reference.
  324. *
  325. * Create a temporary registered window. The peer will not know about this
  326. * window. This API is used for scif_vreadfrom()/scif_vwriteto() API's.
  327. */
  328. static int
  329. scif_register_temp(scif_epd_t epd, unsigned long addr, size_t len, int prot,
  330. off_t *out_offset, struct scif_window **out_window)
  331. {
  332. struct scif_endpt *ep = (struct scif_endpt *)epd;
  333. int err;
  334. scif_pinned_pages_t pinned_pages;
  335. size_t aligned_len;
  336. aligned_len = ALIGN(len, PAGE_SIZE);
  337. err = __scif_pin_pages((void *)(addr & PAGE_MASK),
  338. aligned_len, &prot, 0, &pinned_pages);
  339. if (err)
  340. return err;
  341. pinned_pages->prot = prot;
  342. /* Compute the offset for this registration */
  343. err = scif_get_window_offset(ep, 0, 0,
  344. aligned_len >> PAGE_SHIFT,
  345. (s64 *)out_offset);
  346. if (err)
  347. goto error_unpin;
  348. /* Allocate and prepare self registration window */
  349. *out_window = scif_create_window(ep, aligned_len >> PAGE_SHIFT,
  350. *out_offset, true);
  351. if (!*out_window) {
  352. scif_free_window_offset(ep, NULL, *out_offset);
  353. err = -ENOMEM;
  354. goto error_unpin;
  355. }
  356. (*out_window)->pinned_pages = pinned_pages;
  357. (*out_window)->nr_pages = pinned_pages->nr_pages;
  358. (*out_window)->prot = pinned_pages->prot;
  359. (*out_window)->va_for_temp = addr & PAGE_MASK;
  360. err = scif_map_window(ep->remote_dev, *out_window);
  361. if (err) {
  362. /* Something went wrong! Rollback */
  363. scif_destroy_window(ep, *out_window);
  364. *out_window = NULL;
  365. } else {
  366. *out_offset |= (addr - (*out_window)->va_for_temp);
  367. }
  368. return err;
  369. error_unpin:
  370. if (err)
  371. dev_err(&ep->remote_dev->sdev->dev,
  372. "%s %d err %d\n", __func__, __LINE__, err);
  373. scif_unpin_pages(pinned_pages);
  374. return err;
  375. }
  376. #define SCIF_DMA_TO (3 * HZ)
  377. /*
  378. * scif_sync_dma - Program a DMA without an interrupt descriptor
  379. *
  380. * @dev - The address of the pointer to the device instance used
  381. * for DMA registration.
  382. * @chan - DMA channel to be used.
  383. * @sync_wait: Wait for DMA to complete?
  384. *
  385. * Return 0 on success and -errno on error.
  386. */
  387. static int scif_sync_dma(struct scif_hw_dev *sdev, struct dma_chan *chan,
  388. bool sync_wait)
  389. {
  390. int err = 0;
  391. struct dma_async_tx_descriptor *tx = NULL;
  392. enum dma_ctrl_flags flags = DMA_PREP_FENCE;
  393. dma_cookie_t cookie;
  394. struct dma_device *ddev;
  395. if (!chan) {
  396. err = -EIO;
  397. dev_err(&sdev->dev, "%s %d err %d\n",
  398. __func__, __LINE__, err);
  399. return err;
  400. }
  401. ddev = chan->device;
  402. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  403. if (!tx) {
  404. err = -ENOMEM;
  405. dev_err(&sdev->dev, "%s %d err %d\n",
  406. __func__, __LINE__, err);
  407. goto release;
  408. }
  409. cookie = tx->tx_submit(tx);
  410. if (dma_submit_error(cookie)) {
  411. err = -ENOMEM;
  412. dev_err(&sdev->dev, "%s %d err %d\n",
  413. __func__, __LINE__, err);
  414. goto release;
  415. }
  416. if (!sync_wait) {
  417. dma_async_issue_pending(chan);
  418. } else {
  419. if (dma_sync_wait(chan, cookie) == DMA_COMPLETE) {
  420. err = 0;
  421. } else {
  422. err = -EIO;
  423. dev_err(&sdev->dev, "%s %d err %d\n",
  424. __func__, __LINE__, err);
  425. }
  426. }
  427. release:
  428. return err;
  429. }
  430. static void scif_dma_callback(void *arg)
  431. {
  432. struct completion *done = (struct completion *)arg;
  433. complete(done);
  434. }
  435. #define SCIF_DMA_SYNC_WAIT true
  436. #define SCIF_DMA_POLL BIT(0)
  437. #define SCIF_DMA_INTR BIT(1)
  438. /*
  439. * scif_async_dma - Program a DMA with an interrupt descriptor
  440. *
  441. * @dev - The address of the pointer to the device instance used
  442. * for DMA registration.
  443. * @chan - DMA channel to be used.
  444. * Return 0 on success and -errno on error.
  445. */
  446. static int scif_async_dma(struct scif_hw_dev *sdev, struct dma_chan *chan)
  447. {
  448. int err = 0;
  449. struct dma_device *ddev;
  450. struct dma_async_tx_descriptor *tx = NULL;
  451. enum dma_ctrl_flags flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
  452. DECLARE_COMPLETION_ONSTACK(done_wait);
  453. dma_cookie_t cookie;
  454. enum dma_status status;
  455. if (!chan) {
  456. err = -EIO;
  457. dev_err(&sdev->dev, "%s %d err %d\n",
  458. __func__, __LINE__, err);
  459. return err;
  460. }
  461. ddev = chan->device;
  462. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  463. if (!tx) {
  464. err = -ENOMEM;
  465. dev_err(&sdev->dev, "%s %d err %d\n",
  466. __func__, __LINE__, err);
  467. goto release;
  468. }
  469. reinit_completion(&done_wait);
  470. tx->callback = scif_dma_callback;
  471. tx->callback_param = &done_wait;
  472. cookie = tx->tx_submit(tx);
  473. if (dma_submit_error(cookie)) {
  474. err = -ENOMEM;
  475. dev_err(&sdev->dev, "%s %d err %d\n",
  476. __func__, __LINE__, err);
  477. goto release;
  478. }
  479. dma_async_issue_pending(chan);
  480. err = wait_for_completion_timeout(&done_wait, SCIF_DMA_TO);
  481. if (!err) {
  482. err = -EIO;
  483. dev_err(&sdev->dev, "%s %d err %d\n",
  484. __func__, __LINE__, err);
  485. goto release;
  486. }
  487. err = 0;
  488. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  489. if (status != DMA_COMPLETE) {
  490. err = -EIO;
  491. dev_err(&sdev->dev, "%s %d err %d\n",
  492. __func__, __LINE__, err);
  493. goto release;
  494. }
  495. release:
  496. return err;
  497. }
  498. /*
  499. * scif_drain_dma_poll - Drain all outstanding DMA operations for a particular
  500. * DMA channel via polling.
  501. *
  502. * @sdev - The SCIF device
  503. * @chan - DMA channel
  504. * Return 0 on success and -errno on error.
  505. */
  506. static int scif_drain_dma_poll(struct scif_hw_dev *sdev, struct dma_chan *chan)
  507. {
  508. if (!chan)
  509. return -EINVAL;
  510. return scif_sync_dma(sdev, chan, SCIF_DMA_SYNC_WAIT);
  511. }
  512. /*
  513. * scif_drain_dma_intr - Drain all outstanding DMA operations for a particular
  514. * DMA channel via interrupt based blocking wait.
  515. *
  516. * @sdev - The SCIF device
  517. * @chan - DMA channel
  518. * Return 0 on success and -errno on error.
  519. */
  520. int scif_drain_dma_intr(struct scif_hw_dev *sdev, struct dma_chan *chan)
  521. {
  522. if (!chan)
  523. return -EINVAL;
  524. return scif_async_dma(sdev, chan);
  525. }
  526. /**
  527. * scif_rma_destroy_windows:
  528. *
  529. * This routine destroys all windows queued for cleanup
  530. */
  531. void scif_rma_destroy_windows(void)
  532. {
  533. struct list_head *item, *tmp;
  534. struct scif_window *window;
  535. struct scif_endpt *ep;
  536. struct dma_chan *chan;
  537. might_sleep();
  538. restart:
  539. spin_lock(&scif_info.rmalock);
  540. list_for_each_safe(item, tmp, &scif_info.rma) {
  541. window = list_entry(item, struct scif_window,
  542. list);
  543. ep = (struct scif_endpt *)window->ep;
  544. chan = ep->rma_info.dma_chan;
  545. list_del_init(&window->list);
  546. spin_unlock(&scif_info.rmalock);
  547. if (!chan || !scifdev_alive(ep) ||
  548. !scif_drain_dma_intr(ep->remote_dev->sdev,
  549. ep->rma_info.dma_chan))
  550. /* Remove window from global list */
  551. window->unreg_state = OP_COMPLETED;
  552. else
  553. dev_warn(&ep->remote_dev->sdev->dev,
  554. "DMA engine hung?\n");
  555. if (window->unreg_state == OP_COMPLETED) {
  556. if (window->type == SCIF_WINDOW_SELF)
  557. scif_destroy_window(ep, window);
  558. else
  559. scif_destroy_remote_window(window);
  560. atomic_dec(&ep->rma_info.tw_refcount);
  561. }
  562. goto restart;
  563. }
  564. spin_unlock(&scif_info.rmalock);
  565. }
  566. /**
  567. * scif_rma_destroy_tcw:
  568. *
  569. * This routine destroys temporary cached registered windows
  570. * which have been queued for cleanup.
  571. */
  572. void scif_rma_destroy_tcw_invalid(void)
  573. {
  574. struct list_head *item, *tmp;
  575. struct scif_window *window;
  576. struct scif_endpt *ep;
  577. struct dma_chan *chan;
  578. might_sleep();
  579. restart:
  580. spin_lock(&scif_info.rmalock);
  581. list_for_each_safe(item, tmp, &scif_info.rma_tc) {
  582. window = list_entry(item, struct scif_window, list);
  583. ep = (struct scif_endpt *)window->ep;
  584. chan = ep->rma_info.dma_chan;
  585. list_del_init(&window->list);
  586. spin_unlock(&scif_info.rmalock);
  587. mutex_lock(&ep->rma_info.rma_lock);
  588. if (!chan || !scifdev_alive(ep) ||
  589. !scif_drain_dma_intr(ep->remote_dev->sdev,
  590. ep->rma_info.dma_chan)) {
  591. atomic_sub(window->nr_pages,
  592. &ep->rma_info.tcw_total_pages);
  593. scif_destroy_window(ep, window);
  594. atomic_dec(&ep->rma_info.tcw_refcount);
  595. } else {
  596. dev_warn(&ep->remote_dev->sdev->dev,
  597. "DMA engine hung?\n");
  598. }
  599. mutex_unlock(&ep->rma_info.rma_lock);
  600. goto restart;
  601. }
  602. spin_unlock(&scif_info.rmalock);
  603. }
  604. static inline
  605. void *_get_local_va(off_t off, struct scif_window *window, size_t len)
  606. {
  607. int page_nr = (off - window->offset) >> PAGE_SHIFT;
  608. off_t page_off = off & ~PAGE_MASK;
  609. void *va = NULL;
  610. if (window->type == SCIF_WINDOW_SELF) {
  611. struct page **pages = window->pinned_pages->pages;
  612. va = page_address(pages[page_nr]) + page_off;
  613. }
  614. return va;
  615. }
  616. static inline
  617. void *ioremap_remote(off_t off, struct scif_window *window,
  618. size_t len, struct scif_dev *dev,
  619. struct scif_window_iter *iter)
  620. {
  621. dma_addr_t phys = scif_off_to_dma_addr(window, off, NULL, iter);
  622. /*
  623. * If the DMA address is not card relative then we need the DMA
  624. * addresses to be an offset into the bar. The aperture base was already
  625. * added so subtract it here since scif_ioremap is going to add it again
  626. */
  627. if (!scifdev_self(dev) && window->type == SCIF_WINDOW_PEER &&
  628. dev->sdev->aper && !dev->sdev->card_rel_da)
  629. phys = phys - dev->sdev->aper->pa;
  630. return scif_ioremap(phys, len, dev);
  631. }
  632. static inline void
  633. iounmap_remote(void *virt, size_t size, struct scif_copy_work *work)
  634. {
  635. scif_iounmap(virt, size, work->remote_dev);
  636. }
  637. /*
  638. * Takes care of ordering issue caused by
  639. * 1. Hardware: Only in the case of cpu copy from mgmt node to card
  640. * because of WC memory.
  641. * 2. Software: If memcpy reorders copy instructions for optimization.
  642. * This could happen at both mgmt node and card.
  643. */
  644. static inline void
  645. scif_ordered_memcpy_toio(char *dst, const char *src, size_t count)
  646. {
  647. if (!count)
  648. return;
  649. memcpy_toio((void __iomem __force *)dst, src, --count);
  650. /* Order the last byte with the previous stores */
  651. wmb();
  652. *(dst + count) = *(src + count);
  653. }
  654. static inline void scif_unaligned_cpy_toio(char *dst, const char *src,
  655. size_t count, bool ordered)
  656. {
  657. if (ordered)
  658. scif_ordered_memcpy_toio(dst, src, count);
  659. else
  660. memcpy_toio((void __iomem __force *)dst, src, count);
  661. }
  662. static inline
  663. void scif_ordered_memcpy_fromio(char *dst, const char *src, size_t count)
  664. {
  665. if (!count)
  666. return;
  667. memcpy_fromio(dst, (void __iomem __force *)src, --count);
  668. /* Order the last byte with the previous loads */
  669. rmb();
  670. *(dst + count) = *(src + count);
  671. }
  672. static inline void scif_unaligned_cpy_fromio(char *dst, const char *src,
  673. size_t count, bool ordered)
  674. {
  675. if (ordered)
  676. scif_ordered_memcpy_fromio(dst, src, count);
  677. else
  678. memcpy_fromio(dst, (void __iomem __force *)src, count);
  679. }
  680. #define SCIF_RMA_ERROR_CODE (~(dma_addr_t)0x0)
  681. /*
  682. * scif_off_to_dma_addr:
  683. * Obtain the dma_addr given the window and the offset.
  684. * @window: Registered window.
  685. * @off: Window offset.
  686. * @nr_bytes: Return the number of contiguous bytes till next DMA addr index.
  687. * @index: Return the index of the dma_addr array found.
  688. * @start_off: start offset of index of the dma addr array found.
  689. * The nr_bytes provides the callee an estimate of the maximum possible
  690. * DMA xfer possible while the index/start_off provide faster lookups
  691. * for the next iteration.
  692. */
  693. dma_addr_t scif_off_to_dma_addr(struct scif_window *window, s64 off,
  694. size_t *nr_bytes, struct scif_window_iter *iter)
  695. {
  696. int i, page_nr;
  697. s64 start, end;
  698. off_t page_off;
  699. if (window->nr_pages == window->nr_contig_chunks) {
  700. page_nr = (off - window->offset) >> PAGE_SHIFT;
  701. page_off = off & ~PAGE_MASK;
  702. if (nr_bytes)
  703. *nr_bytes = PAGE_SIZE - page_off;
  704. return window->dma_addr[page_nr] | page_off;
  705. }
  706. if (iter) {
  707. i = iter->index;
  708. start = iter->offset;
  709. } else {
  710. i = 0;
  711. start = window->offset;
  712. }
  713. for (; i < window->nr_contig_chunks; i++) {
  714. end = start + (window->num_pages[i] << PAGE_SHIFT);
  715. if (off >= start && off < end) {
  716. if (iter) {
  717. iter->index = i;
  718. iter->offset = start;
  719. }
  720. if (nr_bytes)
  721. *nr_bytes = end - off;
  722. return (window->dma_addr[i] + (off - start));
  723. }
  724. start += (window->num_pages[i] << PAGE_SHIFT);
  725. }
  726. dev_err(scif_info.mdev.this_device,
  727. "%s %d BUG. Addr not found? window %p off 0x%llx\n",
  728. __func__, __LINE__, window, off);
  729. return SCIF_RMA_ERROR_CODE;
  730. }
  731. /*
  732. * Copy between rma window and temporary buffer
  733. */
  734. static void scif_rma_local_cpu_copy(s64 offset, struct scif_window *window,
  735. u8 *temp, size_t rem_len, bool to_temp)
  736. {
  737. void *window_virt;
  738. size_t loop_len;
  739. int offset_in_page;
  740. s64 end_offset;
  741. offset_in_page = offset & ~PAGE_MASK;
  742. loop_len = PAGE_SIZE - offset_in_page;
  743. if (rem_len < loop_len)
  744. loop_len = rem_len;
  745. window_virt = _get_local_va(offset, window, loop_len);
  746. if (!window_virt)
  747. return;
  748. if (to_temp)
  749. memcpy(temp, window_virt, loop_len);
  750. else
  751. memcpy(window_virt, temp, loop_len);
  752. offset += loop_len;
  753. temp += loop_len;
  754. rem_len -= loop_len;
  755. end_offset = window->offset +
  756. (window->nr_pages << PAGE_SHIFT);
  757. while (rem_len) {
  758. if (offset == end_offset) {
  759. window = list_next_entry(window, list);
  760. end_offset = window->offset +
  761. (window->nr_pages << PAGE_SHIFT);
  762. }
  763. loop_len = min(PAGE_SIZE, rem_len);
  764. window_virt = _get_local_va(offset, window, loop_len);
  765. if (!window_virt)
  766. return;
  767. if (to_temp)
  768. memcpy(temp, window_virt, loop_len);
  769. else
  770. memcpy(window_virt, temp, loop_len);
  771. offset += loop_len;
  772. temp += loop_len;
  773. rem_len -= loop_len;
  774. }
  775. }
  776. /**
  777. * scif_rma_completion_cb:
  778. * @data: RMA cookie
  779. *
  780. * RMA interrupt completion callback.
  781. */
  782. static void scif_rma_completion_cb(void *data)
  783. {
  784. struct scif_dma_comp_cb *comp_cb = data;
  785. /* Free DMA Completion CB. */
  786. if (comp_cb->dst_window)
  787. scif_rma_local_cpu_copy(comp_cb->dst_offset,
  788. comp_cb->dst_window,
  789. comp_cb->temp_buf +
  790. comp_cb->header_padding,
  791. comp_cb->len, false);
  792. scif_unmap_single(comp_cb->temp_phys, comp_cb->sdev,
  793. SCIF_KMEM_UNALIGNED_BUF_SIZE);
  794. if (comp_cb->is_cache)
  795. kmem_cache_free(unaligned_cache,
  796. comp_cb->temp_buf_to_free);
  797. else
  798. kfree(comp_cb->temp_buf_to_free);
  799. }
  800. /* Copies between temporary buffer and offsets provided in work */
  801. static int
  802. scif_rma_list_dma_copy_unaligned(struct scif_copy_work *work,
  803. u8 *temp, struct dma_chan *chan,
  804. bool src_local)
  805. {
  806. struct scif_dma_comp_cb *comp_cb = work->comp_cb;
  807. dma_addr_t window_dma_addr, temp_dma_addr;
  808. dma_addr_t temp_phys = comp_cb->temp_phys;
  809. size_t loop_len, nr_contig_bytes = 0, remaining_len = work->len;
  810. int offset_in_ca, ret = 0;
  811. s64 end_offset, offset;
  812. struct scif_window *window;
  813. void *window_virt_addr;
  814. size_t tail_len;
  815. struct dma_async_tx_descriptor *tx;
  816. struct dma_device *dev = chan->device;
  817. dma_cookie_t cookie;
  818. if (src_local) {
  819. offset = work->dst_offset;
  820. window = work->dst_window;
  821. } else {
  822. offset = work->src_offset;
  823. window = work->src_window;
  824. }
  825. offset_in_ca = offset & (L1_CACHE_BYTES - 1);
  826. if (offset_in_ca) {
  827. loop_len = L1_CACHE_BYTES - offset_in_ca;
  828. loop_len = min(loop_len, remaining_len);
  829. window_virt_addr = ioremap_remote(offset, window,
  830. loop_len,
  831. work->remote_dev,
  832. NULL);
  833. if (!window_virt_addr)
  834. return -ENOMEM;
  835. if (src_local)
  836. scif_unaligned_cpy_toio(window_virt_addr, temp,
  837. loop_len,
  838. work->ordered &&
  839. !(remaining_len - loop_len));
  840. else
  841. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  842. loop_len, work->ordered &&
  843. !(remaining_len - loop_len));
  844. iounmap_remote(window_virt_addr, loop_len, work);
  845. offset += loop_len;
  846. temp += loop_len;
  847. temp_phys += loop_len;
  848. remaining_len -= loop_len;
  849. }
  850. offset_in_ca = offset & ~PAGE_MASK;
  851. end_offset = window->offset +
  852. (window->nr_pages << PAGE_SHIFT);
  853. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  854. remaining_len -= tail_len;
  855. while (remaining_len) {
  856. if (offset == end_offset) {
  857. window = list_next_entry(window, list);
  858. end_offset = window->offset +
  859. (window->nr_pages << PAGE_SHIFT);
  860. }
  861. if (scif_is_mgmt_node())
  862. temp_dma_addr = temp_phys;
  863. else
  864. /* Fix if we ever enable IOMMU on the card */
  865. temp_dma_addr = (dma_addr_t)virt_to_phys(temp);
  866. window_dma_addr = scif_off_to_dma_addr(window, offset,
  867. &nr_contig_bytes,
  868. NULL);
  869. loop_len = min(nr_contig_bytes, remaining_len);
  870. if (src_local) {
  871. if (work->ordered && !tail_len &&
  872. !(remaining_len - loop_len) &&
  873. loop_len != L1_CACHE_BYTES) {
  874. /*
  875. * Break up the last chunk of the transfer into
  876. * two steps. if there is no tail to guarantee
  877. * DMA ordering. SCIF_DMA_POLLING inserts
  878. * a status update descriptor in step 1 which
  879. * acts as a double sided synchronization fence
  880. * for the DMA engine to ensure that the last
  881. * cache line in step 2 is updated last.
  882. */
  883. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  884. tx =
  885. dev->device_prep_dma_memcpy(chan,
  886. window_dma_addr,
  887. temp_dma_addr,
  888. loop_len -
  889. L1_CACHE_BYTES,
  890. DMA_PREP_FENCE);
  891. if (!tx) {
  892. ret = -ENOMEM;
  893. goto err;
  894. }
  895. cookie = tx->tx_submit(tx);
  896. if (dma_submit_error(cookie)) {
  897. ret = -ENOMEM;
  898. goto err;
  899. }
  900. dma_async_issue_pending(chan);
  901. offset += (loop_len - L1_CACHE_BYTES);
  902. temp_dma_addr += (loop_len - L1_CACHE_BYTES);
  903. window_dma_addr += (loop_len - L1_CACHE_BYTES);
  904. remaining_len -= (loop_len - L1_CACHE_BYTES);
  905. loop_len = remaining_len;
  906. /* Step 2) DMA: L1_CACHE_BYTES */
  907. tx =
  908. dev->device_prep_dma_memcpy(chan,
  909. window_dma_addr,
  910. temp_dma_addr,
  911. loop_len, 0);
  912. if (!tx) {
  913. ret = -ENOMEM;
  914. goto err;
  915. }
  916. cookie = tx->tx_submit(tx);
  917. if (dma_submit_error(cookie)) {
  918. ret = -ENOMEM;
  919. goto err;
  920. }
  921. dma_async_issue_pending(chan);
  922. } else {
  923. tx =
  924. dev->device_prep_dma_memcpy(chan,
  925. window_dma_addr,
  926. temp_dma_addr,
  927. loop_len, 0);
  928. if (!tx) {
  929. ret = -ENOMEM;
  930. goto err;
  931. }
  932. cookie = tx->tx_submit(tx);
  933. if (dma_submit_error(cookie)) {
  934. ret = -ENOMEM;
  935. goto err;
  936. }
  937. dma_async_issue_pending(chan);
  938. }
  939. } else {
  940. tx = dev->device_prep_dma_memcpy(chan, temp_dma_addr,
  941. window_dma_addr, loop_len, 0);
  942. if (!tx) {
  943. ret = -ENOMEM;
  944. goto err;
  945. }
  946. cookie = tx->tx_submit(tx);
  947. if (dma_submit_error(cookie)) {
  948. ret = -ENOMEM;
  949. goto err;
  950. }
  951. dma_async_issue_pending(chan);
  952. }
  953. if (ret < 0)
  954. goto err;
  955. offset += loop_len;
  956. temp += loop_len;
  957. temp_phys += loop_len;
  958. remaining_len -= loop_len;
  959. offset_in_ca = 0;
  960. }
  961. if (tail_len) {
  962. if (offset == end_offset) {
  963. window = list_next_entry(window, list);
  964. end_offset = window->offset +
  965. (window->nr_pages << PAGE_SHIFT);
  966. }
  967. window_virt_addr = ioremap_remote(offset, window, tail_len,
  968. work->remote_dev,
  969. NULL);
  970. if (!window_virt_addr)
  971. return -ENOMEM;
  972. /*
  973. * The CPU copy for the tail bytes must be initiated only once
  974. * previous DMA transfers for this endpoint have completed
  975. * to guarantee ordering.
  976. */
  977. if (work->ordered) {
  978. struct scif_dev *rdev = work->remote_dev;
  979. ret = scif_drain_dma_intr(rdev->sdev, chan);
  980. if (ret)
  981. return ret;
  982. }
  983. if (src_local)
  984. scif_unaligned_cpy_toio(window_virt_addr, temp,
  985. tail_len, work->ordered);
  986. else
  987. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  988. tail_len, work->ordered);
  989. iounmap_remote(window_virt_addr, tail_len, work);
  990. }
  991. tx = dev->device_prep_dma_memcpy(chan, 0, 0, 0, DMA_PREP_INTERRUPT);
  992. if (!tx) {
  993. ret = -ENOMEM;
  994. return ret;
  995. }
  996. tx->callback = &scif_rma_completion_cb;
  997. tx->callback_param = comp_cb;
  998. cookie = tx->tx_submit(tx);
  999. if (dma_submit_error(cookie)) {
  1000. ret = -ENOMEM;
  1001. return ret;
  1002. }
  1003. dma_async_issue_pending(chan);
  1004. return 0;
  1005. err:
  1006. dev_err(scif_info.mdev.this_device,
  1007. "%s %d Desc Prog Failed ret %d\n",
  1008. __func__, __LINE__, ret);
  1009. return ret;
  1010. }
  1011. /*
  1012. * _scif_rma_list_dma_copy_aligned:
  1013. *
  1014. * Traverse all the windows and perform DMA copy.
  1015. */
  1016. static int _scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1017. struct dma_chan *chan)
  1018. {
  1019. dma_addr_t src_dma_addr, dst_dma_addr;
  1020. size_t loop_len, remaining_len, src_contig_bytes = 0;
  1021. size_t dst_contig_bytes = 0;
  1022. struct scif_window_iter src_win_iter;
  1023. struct scif_window_iter dst_win_iter;
  1024. s64 end_src_offset, end_dst_offset;
  1025. struct scif_window *src_window = work->src_window;
  1026. struct scif_window *dst_window = work->dst_window;
  1027. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1028. int ret = 0;
  1029. struct dma_async_tx_descriptor *tx;
  1030. struct dma_device *dev = chan->device;
  1031. dma_cookie_t cookie;
  1032. remaining_len = work->len;
  1033. scif_init_window_iter(src_window, &src_win_iter);
  1034. scif_init_window_iter(dst_window, &dst_win_iter);
  1035. end_src_offset = src_window->offset +
  1036. (src_window->nr_pages << PAGE_SHIFT);
  1037. end_dst_offset = dst_window->offset +
  1038. (dst_window->nr_pages << PAGE_SHIFT);
  1039. while (remaining_len) {
  1040. if (src_offset == end_src_offset) {
  1041. src_window = list_next_entry(src_window, list);
  1042. end_src_offset = src_window->offset +
  1043. (src_window->nr_pages << PAGE_SHIFT);
  1044. scif_init_window_iter(src_window, &src_win_iter);
  1045. }
  1046. if (dst_offset == end_dst_offset) {
  1047. dst_window = list_next_entry(dst_window, list);
  1048. end_dst_offset = dst_window->offset +
  1049. (dst_window->nr_pages << PAGE_SHIFT);
  1050. scif_init_window_iter(dst_window, &dst_win_iter);
  1051. }
  1052. /* compute dma addresses for transfer */
  1053. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1054. &src_contig_bytes,
  1055. &src_win_iter);
  1056. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1057. &dst_contig_bytes,
  1058. &dst_win_iter);
  1059. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1060. loop_len = min(loop_len, remaining_len);
  1061. if (work->ordered && !(remaining_len - loop_len)) {
  1062. /*
  1063. * Break up the last chunk of the transfer into two
  1064. * steps to ensure that the last byte in step 2 is
  1065. * updated last.
  1066. */
  1067. /* Step 1) DMA: Body Length - 1 */
  1068. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1069. src_dma_addr,
  1070. loop_len - 1,
  1071. DMA_PREP_FENCE);
  1072. if (!tx) {
  1073. ret = -ENOMEM;
  1074. goto err;
  1075. }
  1076. cookie = tx->tx_submit(tx);
  1077. if (dma_submit_error(cookie)) {
  1078. ret = -ENOMEM;
  1079. goto err;
  1080. }
  1081. src_offset += (loop_len - 1);
  1082. dst_offset += (loop_len - 1);
  1083. src_dma_addr += (loop_len - 1);
  1084. dst_dma_addr += (loop_len - 1);
  1085. remaining_len -= (loop_len - 1);
  1086. loop_len = remaining_len;
  1087. /* Step 2) DMA: 1 BYTES */
  1088. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1089. src_dma_addr, loop_len, 0);
  1090. if (!tx) {
  1091. ret = -ENOMEM;
  1092. goto err;
  1093. }
  1094. cookie = tx->tx_submit(tx);
  1095. if (dma_submit_error(cookie)) {
  1096. ret = -ENOMEM;
  1097. goto err;
  1098. }
  1099. dma_async_issue_pending(chan);
  1100. } else {
  1101. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1102. src_dma_addr, loop_len, 0);
  1103. if (!tx) {
  1104. ret = -ENOMEM;
  1105. goto err;
  1106. }
  1107. cookie = tx->tx_submit(tx);
  1108. if (dma_submit_error(cookie)) {
  1109. ret = -ENOMEM;
  1110. goto err;
  1111. }
  1112. }
  1113. src_offset += loop_len;
  1114. dst_offset += loop_len;
  1115. remaining_len -= loop_len;
  1116. }
  1117. return ret;
  1118. err:
  1119. dev_err(scif_info.mdev.this_device,
  1120. "%s %d Desc Prog Failed ret %d\n",
  1121. __func__, __LINE__, ret);
  1122. return ret;
  1123. }
  1124. /*
  1125. * scif_rma_list_dma_copy_aligned:
  1126. *
  1127. * Traverse all the windows and perform DMA copy.
  1128. */
  1129. static int scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1130. struct dma_chan *chan)
  1131. {
  1132. dma_addr_t src_dma_addr, dst_dma_addr;
  1133. size_t loop_len, remaining_len, tail_len, src_contig_bytes = 0;
  1134. size_t dst_contig_bytes = 0;
  1135. int src_cache_off;
  1136. s64 end_src_offset, end_dst_offset;
  1137. struct scif_window_iter src_win_iter;
  1138. struct scif_window_iter dst_win_iter;
  1139. void *src_virt, *dst_virt;
  1140. struct scif_window *src_window = work->src_window;
  1141. struct scif_window *dst_window = work->dst_window;
  1142. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1143. int ret = 0;
  1144. struct dma_async_tx_descriptor *tx;
  1145. struct dma_device *dev = chan->device;
  1146. dma_cookie_t cookie;
  1147. remaining_len = work->len;
  1148. scif_init_window_iter(src_window, &src_win_iter);
  1149. scif_init_window_iter(dst_window, &dst_win_iter);
  1150. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1151. if (src_cache_off != 0) {
  1152. /* Head */
  1153. loop_len = L1_CACHE_BYTES - src_cache_off;
  1154. loop_len = min(loop_len, remaining_len);
  1155. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1156. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1157. if (src_window->type == SCIF_WINDOW_SELF)
  1158. src_virt = _get_local_va(src_offset, src_window,
  1159. loop_len);
  1160. else
  1161. src_virt = ioremap_remote(src_offset, src_window,
  1162. loop_len,
  1163. work->remote_dev, NULL);
  1164. if (!src_virt)
  1165. return -ENOMEM;
  1166. if (dst_window->type == SCIF_WINDOW_SELF)
  1167. dst_virt = _get_local_va(dst_offset, dst_window,
  1168. loop_len);
  1169. else
  1170. dst_virt = ioremap_remote(dst_offset, dst_window,
  1171. loop_len,
  1172. work->remote_dev, NULL);
  1173. if (!dst_virt) {
  1174. if (src_window->type != SCIF_WINDOW_SELF)
  1175. iounmap_remote(src_virt, loop_len, work);
  1176. return -ENOMEM;
  1177. }
  1178. if (src_window->type == SCIF_WINDOW_SELF)
  1179. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1180. remaining_len == loop_len ?
  1181. work->ordered : false);
  1182. else
  1183. scif_unaligned_cpy_fromio(dst_virt, src_virt, loop_len,
  1184. remaining_len == loop_len ?
  1185. work->ordered : false);
  1186. if (src_window->type != SCIF_WINDOW_SELF)
  1187. iounmap_remote(src_virt, loop_len, work);
  1188. if (dst_window->type != SCIF_WINDOW_SELF)
  1189. iounmap_remote(dst_virt, loop_len, work);
  1190. src_offset += loop_len;
  1191. dst_offset += loop_len;
  1192. remaining_len -= loop_len;
  1193. }
  1194. end_src_offset = src_window->offset +
  1195. (src_window->nr_pages << PAGE_SHIFT);
  1196. end_dst_offset = dst_window->offset +
  1197. (dst_window->nr_pages << PAGE_SHIFT);
  1198. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  1199. remaining_len -= tail_len;
  1200. while (remaining_len) {
  1201. if (src_offset == end_src_offset) {
  1202. src_window = list_next_entry(src_window, list);
  1203. end_src_offset = src_window->offset +
  1204. (src_window->nr_pages << PAGE_SHIFT);
  1205. scif_init_window_iter(src_window, &src_win_iter);
  1206. }
  1207. if (dst_offset == end_dst_offset) {
  1208. dst_window = list_next_entry(dst_window, list);
  1209. end_dst_offset = dst_window->offset +
  1210. (dst_window->nr_pages << PAGE_SHIFT);
  1211. scif_init_window_iter(dst_window, &dst_win_iter);
  1212. }
  1213. /* compute dma addresses for transfer */
  1214. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1215. &src_contig_bytes,
  1216. &src_win_iter);
  1217. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1218. &dst_contig_bytes,
  1219. &dst_win_iter);
  1220. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1221. loop_len = min(loop_len, remaining_len);
  1222. if (work->ordered && !tail_len &&
  1223. !(remaining_len - loop_len)) {
  1224. /*
  1225. * Break up the last chunk of the transfer into two
  1226. * steps. if there is no tail to gurantee DMA ordering.
  1227. * Passing SCIF_DMA_POLLING inserts a status update
  1228. * descriptor in step 1 which acts as a double sided
  1229. * synchronization fence for the DMA engine to ensure
  1230. * that the last cache line in step 2 is updated last.
  1231. */
  1232. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  1233. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1234. src_dma_addr,
  1235. loop_len -
  1236. L1_CACHE_BYTES,
  1237. DMA_PREP_FENCE);
  1238. if (!tx) {
  1239. ret = -ENOMEM;
  1240. goto err;
  1241. }
  1242. cookie = tx->tx_submit(tx);
  1243. if (dma_submit_error(cookie)) {
  1244. ret = -ENOMEM;
  1245. goto err;
  1246. }
  1247. dma_async_issue_pending(chan);
  1248. src_offset += (loop_len - L1_CACHE_BYTES);
  1249. dst_offset += (loop_len - L1_CACHE_BYTES);
  1250. src_dma_addr += (loop_len - L1_CACHE_BYTES);
  1251. dst_dma_addr += (loop_len - L1_CACHE_BYTES);
  1252. remaining_len -= (loop_len - L1_CACHE_BYTES);
  1253. loop_len = remaining_len;
  1254. /* Step 2) DMA: L1_CACHE_BYTES */
  1255. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1256. src_dma_addr,
  1257. loop_len, 0);
  1258. if (!tx) {
  1259. ret = -ENOMEM;
  1260. goto err;
  1261. }
  1262. cookie = tx->tx_submit(tx);
  1263. if (dma_submit_error(cookie)) {
  1264. ret = -ENOMEM;
  1265. goto err;
  1266. }
  1267. dma_async_issue_pending(chan);
  1268. } else {
  1269. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1270. src_dma_addr,
  1271. loop_len, 0);
  1272. if (!tx) {
  1273. ret = -ENOMEM;
  1274. goto err;
  1275. }
  1276. cookie = tx->tx_submit(tx);
  1277. if (dma_submit_error(cookie)) {
  1278. ret = -ENOMEM;
  1279. goto err;
  1280. }
  1281. dma_async_issue_pending(chan);
  1282. }
  1283. src_offset += loop_len;
  1284. dst_offset += loop_len;
  1285. remaining_len -= loop_len;
  1286. }
  1287. remaining_len = tail_len;
  1288. if (remaining_len) {
  1289. loop_len = remaining_len;
  1290. if (src_offset == end_src_offset)
  1291. src_window = list_next_entry(src_window, list);
  1292. if (dst_offset == end_dst_offset)
  1293. dst_window = list_next_entry(dst_window, list);
  1294. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1295. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1296. /*
  1297. * The CPU copy for the tail bytes must be initiated only once
  1298. * previous DMA transfers for this endpoint have completed to
  1299. * guarantee ordering.
  1300. */
  1301. if (work->ordered) {
  1302. struct scif_dev *rdev = work->remote_dev;
  1303. ret = scif_drain_dma_poll(rdev->sdev, chan);
  1304. if (ret)
  1305. return ret;
  1306. }
  1307. if (src_window->type == SCIF_WINDOW_SELF)
  1308. src_virt = _get_local_va(src_offset, src_window,
  1309. loop_len);
  1310. else
  1311. src_virt = ioremap_remote(src_offset, src_window,
  1312. loop_len,
  1313. work->remote_dev, NULL);
  1314. if (!src_virt)
  1315. return -ENOMEM;
  1316. if (dst_window->type == SCIF_WINDOW_SELF)
  1317. dst_virt = _get_local_va(dst_offset, dst_window,
  1318. loop_len);
  1319. else
  1320. dst_virt = ioremap_remote(dst_offset, dst_window,
  1321. loop_len,
  1322. work->remote_dev, NULL);
  1323. if (!dst_virt) {
  1324. if (src_window->type != SCIF_WINDOW_SELF)
  1325. iounmap_remote(src_virt, loop_len, work);
  1326. return -ENOMEM;
  1327. }
  1328. if (src_window->type == SCIF_WINDOW_SELF)
  1329. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1330. work->ordered);
  1331. else
  1332. scif_unaligned_cpy_fromio(dst_virt, src_virt,
  1333. loop_len, work->ordered);
  1334. if (src_window->type != SCIF_WINDOW_SELF)
  1335. iounmap_remote(src_virt, loop_len, work);
  1336. if (dst_window->type != SCIF_WINDOW_SELF)
  1337. iounmap_remote(dst_virt, loop_len, work);
  1338. remaining_len -= loop_len;
  1339. }
  1340. return ret;
  1341. err:
  1342. dev_err(scif_info.mdev.this_device,
  1343. "%s %d Desc Prog Failed ret %d\n",
  1344. __func__, __LINE__, ret);
  1345. return ret;
  1346. }
  1347. /*
  1348. * scif_rma_list_cpu_copy:
  1349. *
  1350. * Traverse all the windows and perform CPU copy.
  1351. */
  1352. static int scif_rma_list_cpu_copy(struct scif_copy_work *work)
  1353. {
  1354. void *src_virt, *dst_virt;
  1355. size_t loop_len, remaining_len;
  1356. int src_page_off, dst_page_off;
  1357. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1358. struct scif_window *src_window = work->src_window;
  1359. struct scif_window *dst_window = work->dst_window;
  1360. s64 end_src_offset, end_dst_offset;
  1361. int ret = 0;
  1362. struct scif_window_iter src_win_iter;
  1363. struct scif_window_iter dst_win_iter;
  1364. remaining_len = work->len;
  1365. scif_init_window_iter(src_window, &src_win_iter);
  1366. scif_init_window_iter(dst_window, &dst_win_iter);
  1367. while (remaining_len) {
  1368. src_page_off = src_offset & ~PAGE_MASK;
  1369. dst_page_off = dst_offset & ~PAGE_MASK;
  1370. loop_len = min(PAGE_SIZE -
  1371. max(src_page_off, dst_page_off),
  1372. remaining_len);
  1373. if (src_window->type == SCIF_WINDOW_SELF)
  1374. src_virt = _get_local_va(src_offset, src_window,
  1375. loop_len);
  1376. else
  1377. src_virt = ioremap_remote(src_offset, src_window,
  1378. loop_len,
  1379. work->remote_dev,
  1380. &src_win_iter);
  1381. if (!src_virt) {
  1382. ret = -ENOMEM;
  1383. goto error;
  1384. }
  1385. if (dst_window->type == SCIF_WINDOW_SELF)
  1386. dst_virt = _get_local_va(dst_offset, dst_window,
  1387. loop_len);
  1388. else
  1389. dst_virt = ioremap_remote(dst_offset, dst_window,
  1390. loop_len,
  1391. work->remote_dev,
  1392. &dst_win_iter);
  1393. if (!dst_virt) {
  1394. if (src_window->type == SCIF_WINDOW_PEER)
  1395. iounmap_remote(src_virt, loop_len, work);
  1396. ret = -ENOMEM;
  1397. goto error;
  1398. }
  1399. if (work->loopback) {
  1400. memcpy(dst_virt, src_virt, loop_len);
  1401. } else {
  1402. if (src_window->type == SCIF_WINDOW_SELF)
  1403. memcpy_toio((void __iomem __force *)dst_virt,
  1404. src_virt, loop_len);
  1405. else
  1406. memcpy_fromio(dst_virt,
  1407. (void __iomem __force *)src_virt,
  1408. loop_len);
  1409. }
  1410. if (src_window->type == SCIF_WINDOW_PEER)
  1411. iounmap_remote(src_virt, loop_len, work);
  1412. if (dst_window->type == SCIF_WINDOW_PEER)
  1413. iounmap_remote(dst_virt, loop_len, work);
  1414. src_offset += loop_len;
  1415. dst_offset += loop_len;
  1416. remaining_len -= loop_len;
  1417. if (remaining_len) {
  1418. end_src_offset = src_window->offset +
  1419. (src_window->nr_pages << PAGE_SHIFT);
  1420. end_dst_offset = dst_window->offset +
  1421. (dst_window->nr_pages << PAGE_SHIFT);
  1422. if (src_offset == end_src_offset) {
  1423. src_window = list_next_entry(src_window, list);
  1424. scif_init_window_iter(src_window,
  1425. &src_win_iter);
  1426. }
  1427. if (dst_offset == end_dst_offset) {
  1428. dst_window = list_next_entry(dst_window, list);
  1429. scif_init_window_iter(dst_window,
  1430. &dst_win_iter);
  1431. }
  1432. }
  1433. }
  1434. error:
  1435. return ret;
  1436. }
  1437. static int scif_rma_list_dma_copy_wrapper(struct scif_endpt *epd,
  1438. struct scif_copy_work *work,
  1439. struct dma_chan *chan, off_t loffset)
  1440. {
  1441. int src_cache_off, dst_cache_off;
  1442. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1443. u8 *temp = NULL;
  1444. bool src_local = true, dst_local = false;
  1445. struct scif_dma_comp_cb *comp_cb;
  1446. dma_addr_t src_dma_addr, dst_dma_addr;
  1447. int err;
  1448. if (is_dma_copy_aligned(chan->device, 1, 1, 1))
  1449. return _scif_rma_list_dma_copy_aligned(work, chan);
  1450. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1451. dst_cache_off = dst_offset & (L1_CACHE_BYTES - 1);
  1452. if (dst_cache_off == src_cache_off)
  1453. return scif_rma_list_dma_copy_aligned(work, chan);
  1454. if (work->loopback)
  1455. return scif_rma_list_cpu_copy(work);
  1456. src_dma_addr = __scif_off_to_dma_addr(work->src_window, src_offset);
  1457. dst_dma_addr = __scif_off_to_dma_addr(work->dst_window, dst_offset);
  1458. src_local = work->src_window->type == SCIF_WINDOW_SELF;
  1459. dst_local = work->dst_window->type == SCIF_WINDOW_SELF;
  1460. dst_local = dst_local;
  1461. /* Allocate dma_completion cb */
  1462. comp_cb = kzalloc(sizeof(*comp_cb), GFP_KERNEL);
  1463. if (!comp_cb)
  1464. goto error;
  1465. work->comp_cb = comp_cb;
  1466. comp_cb->cb_cookie = comp_cb;
  1467. comp_cb->dma_completion_func = &scif_rma_completion_cb;
  1468. if (work->len + (L1_CACHE_BYTES << 1) < SCIF_KMEM_UNALIGNED_BUF_SIZE) {
  1469. comp_cb->is_cache = false;
  1470. /* Allocate padding bytes to align to a cache line */
  1471. temp = kmalloc(work->len + (L1_CACHE_BYTES << 1),
  1472. GFP_KERNEL);
  1473. if (!temp)
  1474. goto free_comp_cb;
  1475. comp_cb->temp_buf_to_free = temp;
  1476. /* kmalloc(..) does not guarantee cache line alignment */
  1477. if (!IS_ALIGNED((u64)temp, L1_CACHE_BYTES))
  1478. temp = PTR_ALIGN(temp, L1_CACHE_BYTES);
  1479. } else {
  1480. comp_cb->is_cache = true;
  1481. temp = kmem_cache_alloc(unaligned_cache, GFP_KERNEL);
  1482. if (!temp)
  1483. goto free_comp_cb;
  1484. comp_cb->temp_buf_to_free = temp;
  1485. }
  1486. if (src_local) {
  1487. temp += dst_cache_off;
  1488. scif_rma_local_cpu_copy(work->src_offset, work->src_window,
  1489. temp, work->len, true);
  1490. } else {
  1491. comp_cb->dst_window = work->dst_window;
  1492. comp_cb->dst_offset = work->dst_offset;
  1493. work->src_offset = work->src_offset - src_cache_off;
  1494. comp_cb->len = work->len;
  1495. work->len = ALIGN(work->len + src_cache_off, L1_CACHE_BYTES);
  1496. comp_cb->header_padding = src_cache_off;
  1497. }
  1498. comp_cb->temp_buf = temp;
  1499. err = scif_map_single(&comp_cb->temp_phys, temp,
  1500. work->remote_dev, SCIF_KMEM_UNALIGNED_BUF_SIZE);
  1501. if (err)
  1502. goto free_temp_buf;
  1503. comp_cb->sdev = work->remote_dev;
  1504. if (scif_rma_list_dma_copy_unaligned(work, temp, chan, src_local) < 0)
  1505. goto free_temp_buf;
  1506. if (!src_local)
  1507. work->fence_type = SCIF_DMA_INTR;
  1508. return 0;
  1509. free_temp_buf:
  1510. if (comp_cb->is_cache)
  1511. kmem_cache_free(unaligned_cache, comp_cb->temp_buf_to_free);
  1512. else
  1513. kfree(comp_cb->temp_buf_to_free);
  1514. free_comp_cb:
  1515. kfree(comp_cb);
  1516. error:
  1517. return -ENOMEM;
  1518. }
  1519. /**
  1520. * scif_rma_copy:
  1521. * @epd: end point descriptor.
  1522. * @loffset: offset in local registered address space to/from which to copy
  1523. * @addr: user virtual address to/from which to copy
  1524. * @len: length of range to copy
  1525. * @roffset: offset in remote registered address space to/from which to copy
  1526. * @flags: flags
  1527. * @dir: LOCAL->REMOTE or vice versa.
  1528. * @last_chunk: true if this is the last chunk of a larger transfer
  1529. *
  1530. * Validate parameters, check if src/dst registered ranges requested for copy
  1531. * are valid and initiate either CPU or DMA copy.
  1532. */
  1533. static int scif_rma_copy(scif_epd_t epd, off_t loffset, unsigned long addr,
  1534. size_t len, off_t roffset, int flags,
  1535. enum scif_rma_dir dir, bool last_chunk)
  1536. {
  1537. struct scif_endpt *ep = (struct scif_endpt *)epd;
  1538. struct scif_rma_req remote_req;
  1539. struct scif_rma_req req;
  1540. struct scif_window *local_window = NULL;
  1541. struct scif_window *remote_window = NULL;
  1542. struct scif_copy_work copy_work;
  1543. bool loopback;
  1544. int err = 0;
  1545. struct dma_chan *chan;
  1546. struct scif_mmu_notif *mmn = NULL;
  1547. bool cache = false;
  1548. struct device *spdev;
  1549. err = scif_verify_epd(ep);
  1550. if (err)
  1551. return err;
  1552. if (flags && !(flags & (SCIF_RMA_USECPU | SCIF_RMA_USECACHE |
  1553. SCIF_RMA_SYNC | SCIF_RMA_ORDERED)))
  1554. return -EINVAL;
  1555. loopback = scifdev_self(ep->remote_dev) ? true : false;
  1556. copy_work.fence_type = ((flags & SCIF_RMA_SYNC) && last_chunk) ?
  1557. SCIF_DMA_POLL : 0;
  1558. copy_work.ordered = !!((flags & SCIF_RMA_ORDERED) && last_chunk);
  1559. /* Use CPU for Mgmt node <-> Mgmt node copies */
  1560. if (loopback && scif_is_mgmt_node()) {
  1561. flags |= SCIF_RMA_USECPU;
  1562. copy_work.fence_type = 0x0;
  1563. }
  1564. cache = scif_is_set_reg_cache(flags);
  1565. remote_req.out_window = &remote_window;
  1566. remote_req.offset = roffset;
  1567. remote_req.nr_bytes = len;
  1568. /*
  1569. * If transfer is from local to remote then the remote window
  1570. * must be writeable and vice versa.
  1571. */
  1572. remote_req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_WRITE : VM_READ;
  1573. remote_req.type = SCIF_WINDOW_PARTIAL;
  1574. remote_req.head = &ep->rma_info.remote_reg_list;
  1575. spdev = scif_get_peer_dev(ep->remote_dev);
  1576. if (IS_ERR(spdev)) {
  1577. err = PTR_ERR(spdev);
  1578. return err;
  1579. }
  1580. if (addr && cache) {
  1581. mutex_lock(&ep->rma_info.mmn_lock);
  1582. mmn = scif_find_mmu_notifier(current->mm, &ep->rma_info);
  1583. if (!mmn)
  1584. mmn = scif_add_mmu_notifier(current->mm, ep);
  1585. mutex_unlock(&ep->rma_info.mmn_lock);
  1586. if (IS_ERR(mmn)) {
  1587. scif_put_peer_dev(spdev);
  1588. return PTR_ERR(mmn);
  1589. }
  1590. cache = cache && !scif_rma_tc_can_cache(ep, len);
  1591. }
  1592. mutex_lock(&ep->rma_info.rma_lock);
  1593. if (addr) {
  1594. req.out_window = &local_window;
  1595. req.nr_bytes = ALIGN(len + (addr & ~PAGE_MASK),
  1596. PAGE_SIZE);
  1597. req.va_for_temp = addr & PAGE_MASK;
  1598. req.prot = (dir == SCIF_LOCAL_TO_REMOTE ?
  1599. VM_READ : VM_WRITE | VM_READ);
  1600. /* Does a valid local window exist? */
  1601. if (mmn) {
  1602. spin_lock(&ep->rma_info.tc_lock);
  1603. req.head = &mmn->tc_reg_list;
  1604. err = scif_query_tcw(ep, &req);
  1605. spin_unlock(&ep->rma_info.tc_lock);
  1606. }
  1607. if (!mmn || err) {
  1608. err = scif_register_temp(epd, req.va_for_temp,
  1609. req.nr_bytes, req.prot,
  1610. &loffset, &local_window);
  1611. if (err) {
  1612. mutex_unlock(&ep->rma_info.rma_lock);
  1613. goto error;
  1614. }
  1615. if (!cache)
  1616. goto skip_cache;
  1617. atomic_inc(&ep->rma_info.tcw_refcount);
  1618. atomic_add_return(local_window->nr_pages,
  1619. &ep->rma_info.tcw_total_pages);
  1620. if (mmn) {
  1621. spin_lock(&ep->rma_info.tc_lock);
  1622. scif_insert_tcw(local_window,
  1623. &mmn->tc_reg_list);
  1624. spin_unlock(&ep->rma_info.tc_lock);
  1625. }
  1626. }
  1627. skip_cache:
  1628. loffset = local_window->offset +
  1629. (addr - local_window->va_for_temp);
  1630. } else {
  1631. req.out_window = &local_window;
  1632. req.offset = loffset;
  1633. /*
  1634. * If transfer is from local to remote then the self window
  1635. * must be readable and vice versa.
  1636. */
  1637. req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_READ : VM_WRITE;
  1638. req.nr_bytes = len;
  1639. req.type = SCIF_WINDOW_PARTIAL;
  1640. req.head = &ep->rma_info.reg_list;
  1641. /* Does a valid local window exist? */
  1642. err = scif_query_window(&req);
  1643. if (err) {
  1644. mutex_unlock(&ep->rma_info.rma_lock);
  1645. goto error;
  1646. }
  1647. }
  1648. /* Does a valid remote window exist? */
  1649. err = scif_query_window(&remote_req);
  1650. if (err) {
  1651. mutex_unlock(&ep->rma_info.rma_lock);
  1652. goto error;
  1653. }
  1654. /*
  1655. * Prepare copy_work for submitting work to the DMA kernel thread
  1656. * or CPU copy routine.
  1657. */
  1658. copy_work.len = len;
  1659. copy_work.loopback = loopback;
  1660. copy_work.remote_dev = ep->remote_dev;
  1661. if (dir == SCIF_LOCAL_TO_REMOTE) {
  1662. copy_work.src_offset = loffset;
  1663. copy_work.src_window = local_window;
  1664. copy_work.dst_offset = roffset;
  1665. copy_work.dst_window = remote_window;
  1666. } else {
  1667. copy_work.src_offset = roffset;
  1668. copy_work.src_window = remote_window;
  1669. copy_work.dst_offset = loffset;
  1670. copy_work.dst_window = local_window;
  1671. }
  1672. if (flags & SCIF_RMA_USECPU) {
  1673. scif_rma_list_cpu_copy(&copy_work);
  1674. } else {
  1675. chan = ep->rma_info.dma_chan;
  1676. err = scif_rma_list_dma_copy_wrapper(epd, &copy_work,
  1677. chan, loffset);
  1678. }
  1679. if (addr && !cache)
  1680. atomic_inc(&ep->rma_info.tw_refcount);
  1681. mutex_unlock(&ep->rma_info.rma_lock);
  1682. if (last_chunk) {
  1683. struct scif_dev *rdev = ep->remote_dev;
  1684. if (copy_work.fence_type == SCIF_DMA_POLL)
  1685. err = scif_drain_dma_poll(rdev->sdev,
  1686. ep->rma_info.dma_chan);
  1687. else if (copy_work.fence_type == SCIF_DMA_INTR)
  1688. err = scif_drain_dma_intr(rdev->sdev,
  1689. ep->rma_info.dma_chan);
  1690. }
  1691. if (addr && !cache)
  1692. scif_queue_for_cleanup(local_window, &scif_info.rma);
  1693. scif_put_peer_dev(spdev);
  1694. return err;
  1695. error:
  1696. if (err) {
  1697. if (addr && local_window && !cache)
  1698. scif_destroy_window(ep, local_window);
  1699. dev_err(scif_info.mdev.this_device,
  1700. "%s %d err %d len 0x%lx\n",
  1701. __func__, __LINE__, err, len);
  1702. }
  1703. scif_put_peer_dev(spdev);
  1704. return err;
  1705. }
  1706. int scif_readfrom(scif_epd_t epd, off_t loffset, size_t len,
  1707. off_t roffset, int flags)
  1708. {
  1709. int err;
  1710. dev_dbg(scif_info.mdev.this_device,
  1711. "SCIFAPI readfrom: ep %p loffset 0x%lx len 0x%lx offset 0x%lx flags 0x%x\n",
  1712. epd, loffset, len, roffset, flags);
  1713. if (scif_unaligned(loffset, roffset)) {
  1714. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1715. err = scif_rma_copy(epd, loffset, 0x0,
  1716. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1717. roffset, flags,
  1718. SCIF_REMOTE_TO_LOCAL, false);
  1719. if (err)
  1720. goto readfrom_err;
  1721. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1722. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1723. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1724. }
  1725. }
  1726. err = scif_rma_copy(epd, loffset, 0x0, len,
  1727. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1728. readfrom_err:
  1729. return err;
  1730. }
  1731. EXPORT_SYMBOL_GPL(scif_readfrom);
  1732. int scif_writeto(scif_epd_t epd, off_t loffset, size_t len,
  1733. off_t roffset, int flags)
  1734. {
  1735. int err;
  1736. dev_dbg(scif_info.mdev.this_device,
  1737. "SCIFAPI writeto: ep %p loffset 0x%lx len 0x%lx roffset 0x%lx flags 0x%x\n",
  1738. epd, loffset, len, roffset, flags);
  1739. if (scif_unaligned(loffset, roffset)) {
  1740. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1741. err = scif_rma_copy(epd, loffset, 0x0,
  1742. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1743. roffset, flags,
  1744. SCIF_LOCAL_TO_REMOTE, false);
  1745. if (err)
  1746. goto writeto_err;
  1747. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1748. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1749. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1750. }
  1751. }
  1752. err = scif_rma_copy(epd, loffset, 0x0, len,
  1753. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1754. writeto_err:
  1755. return err;
  1756. }
  1757. EXPORT_SYMBOL_GPL(scif_writeto);
  1758. int scif_vreadfrom(scif_epd_t epd, void *addr, size_t len,
  1759. off_t roffset, int flags)
  1760. {
  1761. int err;
  1762. dev_dbg(scif_info.mdev.this_device,
  1763. "SCIFAPI vreadfrom: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1764. epd, addr, len, roffset, flags);
  1765. if (scif_unaligned((off_t __force)addr, roffset)) {
  1766. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1767. flags &= ~SCIF_RMA_USECACHE;
  1768. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1769. err = scif_rma_copy(epd, 0, (u64)addr,
  1770. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1771. roffset, flags,
  1772. SCIF_REMOTE_TO_LOCAL, false);
  1773. if (err)
  1774. goto vreadfrom_err;
  1775. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1776. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1777. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1778. }
  1779. }
  1780. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1781. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1782. vreadfrom_err:
  1783. return err;
  1784. }
  1785. EXPORT_SYMBOL_GPL(scif_vreadfrom);
  1786. int scif_vwriteto(scif_epd_t epd, void *addr, size_t len,
  1787. off_t roffset, int flags)
  1788. {
  1789. int err;
  1790. dev_dbg(scif_info.mdev.this_device,
  1791. "SCIFAPI vwriteto: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1792. epd, addr, len, roffset, flags);
  1793. if (scif_unaligned((off_t __force)addr, roffset)) {
  1794. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1795. flags &= ~SCIF_RMA_USECACHE;
  1796. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1797. err = scif_rma_copy(epd, 0, (u64)addr,
  1798. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1799. roffset, flags,
  1800. SCIF_LOCAL_TO_REMOTE, false);
  1801. if (err)
  1802. goto vwriteto_err;
  1803. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1804. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1805. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1806. }
  1807. }
  1808. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1809. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1810. vwriteto_err:
  1811. return err;
  1812. }
  1813. EXPORT_SYMBOL_GPL(scif_vwriteto);