pci-me.c 12 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2003-2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/kernel.h>
  19. #include <linux/device.h>
  20. #include <linux/fs.h>
  21. #include <linux/errno.h>
  22. #include <linux/types.h>
  23. #include <linux/fcntl.h>
  24. #include <linux/pci.h>
  25. #include <linux/poll.h>
  26. #include <linux/ioctl.h>
  27. #include <linux/cdev.h>
  28. #include <linux/sched.h>
  29. #include <linux/uuid.h>
  30. #include <linux/compat.h>
  31. #include <linux/jiffies.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/pm_domain.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/mei.h>
  36. #include "mei_dev.h"
  37. #include "client.h"
  38. #include "hw-me-regs.h"
  39. #include "hw-me.h"
  40. /* mei_pci_tbl - PCI Device ID Table */
  41. static const struct pci_device_id mei_me_pci_tbl[] = {
  42. {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
  43. {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
  44. {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
  45. {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
  46. {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
  47. {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
  48. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
  49. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
  50. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
  51. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
  52. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
  53. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
  54. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
  55. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
  56. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
  57. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
  58. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
  59. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
  60. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
  61. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
  62. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
  63. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
  64. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
  65. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
  66. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
  67. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
  68. {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
  69. {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
  70. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
  71. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
  72. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
  73. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
  74. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
  75. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
  76. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
  77. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
  78. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
  79. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
  80. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
  81. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_cfg)},
  82. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_cfg)},
  83. {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
  84. {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},
  85. /* required last entry */
  86. {0, }
  87. };
  88. MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
  89. #ifdef CONFIG_PM
  90. static inline void mei_me_set_pm_domain(struct mei_device *dev);
  91. static inline void mei_me_unset_pm_domain(struct mei_device *dev);
  92. #else
  93. static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
  94. static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
  95. #endif /* CONFIG_PM */
  96. /**
  97. * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
  98. *
  99. * @pdev: PCI device structure
  100. * @cfg: per generation config
  101. *
  102. * Return: true if ME Interface is valid, false otherwise
  103. */
  104. static bool mei_me_quirk_probe(struct pci_dev *pdev,
  105. const struct mei_cfg *cfg)
  106. {
  107. if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
  108. dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
  109. return false;
  110. }
  111. return true;
  112. }
  113. /**
  114. * mei_me_probe - Device Initialization Routine
  115. *
  116. * @pdev: PCI device structure
  117. * @ent: entry in kcs_pci_tbl
  118. *
  119. * Return: 0 on success, <0 on failure.
  120. */
  121. static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  122. {
  123. const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
  124. struct mei_device *dev;
  125. struct mei_me_hw *hw;
  126. unsigned int irqflags;
  127. int err;
  128. if (!mei_me_quirk_probe(pdev, cfg))
  129. return -ENODEV;
  130. /* enable pci dev */
  131. err = pci_enable_device(pdev);
  132. if (err) {
  133. dev_err(&pdev->dev, "failed to enable pci device.\n");
  134. goto end;
  135. }
  136. /* set PCI host mastering */
  137. pci_set_master(pdev);
  138. /* pci request regions for mei driver */
  139. err = pci_request_regions(pdev, KBUILD_MODNAME);
  140. if (err) {
  141. dev_err(&pdev->dev, "failed to get pci regions.\n");
  142. goto disable_device;
  143. }
  144. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
  145. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  146. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  147. if (err)
  148. err = dma_set_coherent_mask(&pdev->dev,
  149. DMA_BIT_MASK(32));
  150. }
  151. if (err) {
  152. dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
  153. goto release_regions;
  154. }
  155. /* allocates and initializes the mei dev structure */
  156. dev = mei_me_dev_init(pdev, cfg);
  157. if (!dev) {
  158. err = -ENOMEM;
  159. goto release_regions;
  160. }
  161. hw = to_me_hw(dev);
  162. /* mapping IO device memory */
  163. hw->mem_addr = pci_iomap(pdev, 0, 0);
  164. if (!hw->mem_addr) {
  165. dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
  166. err = -ENOMEM;
  167. goto free_device;
  168. }
  169. pci_enable_msi(pdev);
  170. /* request and enable interrupt */
  171. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  172. err = request_threaded_irq(pdev->irq,
  173. mei_me_irq_quick_handler,
  174. mei_me_irq_thread_handler,
  175. irqflags, KBUILD_MODNAME, dev);
  176. if (err) {
  177. dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
  178. pdev->irq);
  179. goto disable_msi;
  180. }
  181. if (mei_start(dev)) {
  182. dev_err(&pdev->dev, "init hw failure.\n");
  183. err = -ENODEV;
  184. goto release_irq;
  185. }
  186. pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
  187. pm_runtime_use_autosuspend(&pdev->dev);
  188. err = mei_register(dev, &pdev->dev);
  189. if (err)
  190. goto stop;
  191. pci_set_drvdata(pdev, dev);
  192. schedule_delayed_work(&dev->timer_work, HZ);
  193. /*
  194. * For not wake-able HW runtime pm framework
  195. * can't be used on pci device level.
  196. * Use domain runtime pm callbacks instead.
  197. */
  198. if (!pci_dev_run_wake(pdev))
  199. mei_me_set_pm_domain(dev);
  200. if (mei_pg_is_enabled(dev))
  201. pm_runtime_put_noidle(&pdev->dev);
  202. dev_dbg(&pdev->dev, "initialization successful.\n");
  203. return 0;
  204. stop:
  205. mei_stop(dev);
  206. release_irq:
  207. mei_cancel_work(dev);
  208. mei_disable_interrupts(dev);
  209. free_irq(pdev->irq, dev);
  210. disable_msi:
  211. pci_disable_msi(pdev);
  212. pci_iounmap(pdev, hw->mem_addr);
  213. free_device:
  214. kfree(dev);
  215. release_regions:
  216. pci_release_regions(pdev);
  217. disable_device:
  218. pci_disable_device(pdev);
  219. end:
  220. dev_err(&pdev->dev, "initialization failed.\n");
  221. return err;
  222. }
  223. /**
  224. * mei_me_remove - Device Removal Routine
  225. *
  226. * @pdev: PCI device structure
  227. *
  228. * mei_remove is called by the PCI subsystem to alert the driver
  229. * that it should release a PCI device.
  230. */
  231. static void mei_me_remove(struct pci_dev *pdev)
  232. {
  233. struct mei_device *dev;
  234. struct mei_me_hw *hw;
  235. dev = pci_get_drvdata(pdev);
  236. if (!dev)
  237. return;
  238. if (mei_pg_is_enabled(dev))
  239. pm_runtime_get_noresume(&pdev->dev);
  240. hw = to_me_hw(dev);
  241. dev_dbg(&pdev->dev, "stop\n");
  242. mei_stop(dev);
  243. if (!pci_dev_run_wake(pdev))
  244. mei_me_unset_pm_domain(dev);
  245. /* disable interrupts */
  246. mei_disable_interrupts(dev);
  247. free_irq(pdev->irq, dev);
  248. pci_disable_msi(pdev);
  249. if (hw->mem_addr)
  250. pci_iounmap(pdev, hw->mem_addr);
  251. mei_deregister(dev);
  252. kfree(dev);
  253. pci_release_regions(pdev);
  254. pci_disable_device(pdev);
  255. }
  256. #ifdef CONFIG_PM_SLEEP
  257. static int mei_me_pci_suspend(struct device *device)
  258. {
  259. struct pci_dev *pdev = to_pci_dev(device);
  260. struct mei_device *dev = pci_get_drvdata(pdev);
  261. if (!dev)
  262. return -ENODEV;
  263. dev_dbg(&pdev->dev, "suspend\n");
  264. mei_stop(dev);
  265. mei_disable_interrupts(dev);
  266. free_irq(pdev->irq, dev);
  267. pci_disable_msi(pdev);
  268. return 0;
  269. }
  270. static int mei_me_pci_resume(struct device *device)
  271. {
  272. struct pci_dev *pdev = to_pci_dev(device);
  273. struct mei_device *dev;
  274. unsigned int irqflags;
  275. int err;
  276. dev = pci_get_drvdata(pdev);
  277. if (!dev)
  278. return -ENODEV;
  279. pci_enable_msi(pdev);
  280. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  281. /* request and enable interrupt */
  282. err = request_threaded_irq(pdev->irq,
  283. mei_me_irq_quick_handler,
  284. mei_me_irq_thread_handler,
  285. irqflags, KBUILD_MODNAME, dev);
  286. if (err) {
  287. dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
  288. pdev->irq);
  289. return err;
  290. }
  291. err = mei_restart(dev);
  292. if (err)
  293. return err;
  294. /* Start timer if stopped in suspend */
  295. schedule_delayed_work(&dev->timer_work, HZ);
  296. return 0;
  297. }
  298. #endif /* CONFIG_PM_SLEEP */
  299. #ifdef CONFIG_PM
  300. static int mei_me_pm_runtime_idle(struct device *device)
  301. {
  302. struct pci_dev *pdev = to_pci_dev(device);
  303. struct mei_device *dev;
  304. dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
  305. dev = pci_get_drvdata(pdev);
  306. if (!dev)
  307. return -ENODEV;
  308. if (mei_write_is_idle(dev))
  309. pm_runtime_autosuspend(device);
  310. return -EBUSY;
  311. }
  312. static int mei_me_pm_runtime_suspend(struct device *device)
  313. {
  314. struct pci_dev *pdev = to_pci_dev(device);
  315. struct mei_device *dev;
  316. int ret;
  317. dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
  318. dev = pci_get_drvdata(pdev);
  319. if (!dev)
  320. return -ENODEV;
  321. mutex_lock(&dev->device_lock);
  322. if (mei_write_is_idle(dev))
  323. ret = mei_me_pg_enter_sync(dev);
  324. else
  325. ret = -EAGAIN;
  326. mutex_unlock(&dev->device_lock);
  327. dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
  328. return ret;
  329. }
  330. static int mei_me_pm_runtime_resume(struct device *device)
  331. {
  332. struct pci_dev *pdev = to_pci_dev(device);
  333. struct mei_device *dev;
  334. int ret;
  335. dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
  336. dev = pci_get_drvdata(pdev);
  337. if (!dev)
  338. return -ENODEV;
  339. mutex_lock(&dev->device_lock);
  340. ret = mei_me_pg_exit_sync(dev);
  341. mutex_unlock(&dev->device_lock);
  342. dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
  343. return ret;
  344. }
  345. /**
  346. * mei_me_set_pm_domain - fill and set pm domain structure for device
  347. *
  348. * @dev: mei_device
  349. */
  350. static inline void mei_me_set_pm_domain(struct mei_device *dev)
  351. {
  352. struct pci_dev *pdev = to_pci_dev(dev->dev);
  353. if (pdev->dev.bus && pdev->dev.bus->pm) {
  354. dev->pg_domain.ops = *pdev->dev.bus->pm;
  355. dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
  356. dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
  357. dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
  358. dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
  359. }
  360. }
  361. /**
  362. * mei_me_unset_pm_domain - clean pm domain structure for device
  363. *
  364. * @dev: mei_device
  365. */
  366. static inline void mei_me_unset_pm_domain(struct mei_device *dev)
  367. {
  368. /* stop using pm callbacks if any */
  369. dev_pm_domain_set(dev->dev, NULL);
  370. }
  371. static const struct dev_pm_ops mei_me_pm_ops = {
  372. SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
  373. mei_me_pci_resume)
  374. SET_RUNTIME_PM_OPS(
  375. mei_me_pm_runtime_suspend,
  376. mei_me_pm_runtime_resume,
  377. mei_me_pm_runtime_idle)
  378. };
  379. #define MEI_ME_PM_OPS (&mei_me_pm_ops)
  380. #else
  381. #define MEI_ME_PM_OPS NULL
  382. #endif /* CONFIG_PM */
  383. /*
  384. * PCI driver structure
  385. */
  386. static struct pci_driver mei_me_driver = {
  387. .name = KBUILD_MODNAME,
  388. .id_table = mei_me_pci_tbl,
  389. .probe = mei_me_probe,
  390. .remove = mei_me_remove,
  391. .shutdown = mei_me_remove,
  392. .driver.pm = MEI_ME_PM_OPS,
  393. };
  394. module_pci_driver(mei_me_driver);
  395. MODULE_AUTHOR("Intel Corporation");
  396. MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
  397. MODULE_LICENSE("GPL v2");