coresight-etb10.c 20 KB

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  1. /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  2. *
  3. * Description: CoreSight Embedded Trace Buffer driver
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 and
  7. * only version 2 as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <asm/local.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/types.h>
  18. #include <linux/device.h>
  19. #include <linux/io.h>
  20. #include <linux/err.h>
  21. #include <linux/fs.h>
  22. #include <linux/miscdevice.h>
  23. #include <linux/uaccess.h>
  24. #include <linux/slab.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/seq_file.h>
  28. #include <linux/coresight.h>
  29. #include <linux/amba/bus.h>
  30. #include <linux/clk.h>
  31. #include <linux/circ_buf.h>
  32. #include <linux/mm.h>
  33. #include <linux/perf_event.h>
  34. #include <asm/local.h>
  35. #include "coresight-priv.h"
  36. #define ETB_RAM_DEPTH_REG 0x004
  37. #define ETB_STATUS_REG 0x00c
  38. #define ETB_RAM_READ_DATA_REG 0x010
  39. #define ETB_RAM_READ_POINTER 0x014
  40. #define ETB_RAM_WRITE_POINTER 0x018
  41. #define ETB_TRG 0x01c
  42. #define ETB_CTL_REG 0x020
  43. #define ETB_RWD_REG 0x024
  44. #define ETB_FFSR 0x300
  45. #define ETB_FFCR 0x304
  46. #define ETB_ITMISCOP0 0xee0
  47. #define ETB_ITTRFLINACK 0xee4
  48. #define ETB_ITTRFLIN 0xee8
  49. #define ETB_ITATBDATA0 0xeeC
  50. #define ETB_ITATBCTR2 0xef0
  51. #define ETB_ITATBCTR1 0xef4
  52. #define ETB_ITATBCTR0 0xef8
  53. /* register description */
  54. /* STS - 0x00C */
  55. #define ETB_STATUS_RAM_FULL BIT(0)
  56. /* CTL - 0x020 */
  57. #define ETB_CTL_CAPT_EN BIT(0)
  58. /* FFCR - 0x304 */
  59. #define ETB_FFCR_EN_FTC BIT(0)
  60. #define ETB_FFCR_FON_MAN BIT(6)
  61. #define ETB_FFCR_STOP_FI BIT(12)
  62. #define ETB_FFCR_STOP_TRIGGER BIT(13)
  63. #define ETB_FFCR_BIT 6
  64. #define ETB_FFSR_BIT 1
  65. #define ETB_FRAME_SIZE_WORDS 4
  66. /**
  67. * struct cs_buffer - keep track of a recording session' specifics
  68. * @cur: index of the current buffer
  69. * @nr_pages: max number of pages granted to us
  70. * @offset: offset within the current buffer
  71. * @data_size: how much we collected in this run
  72. * @lost: other than zero if we had a HW buffer wrap around
  73. * @snapshot: is this run in snapshot mode
  74. * @data_pages: a handle the ring buffer
  75. */
  76. struct cs_buffers {
  77. unsigned int cur;
  78. unsigned int nr_pages;
  79. unsigned long offset;
  80. local_t data_size;
  81. local_t lost;
  82. bool snapshot;
  83. void **data_pages;
  84. };
  85. /**
  86. * struct etb_drvdata - specifics associated to an ETB component
  87. * @base: memory mapped base address for this component.
  88. * @dev: the device entity associated to this component.
  89. * @atclk: optional clock for the core parts of the ETB.
  90. * @csdev: component vitals needed by the framework.
  91. * @miscdev: specifics to handle "/dev/xyz.etb" entry.
  92. * @spinlock: only one at a time pls.
  93. * @reading: synchronise user space access to etb buffer.
  94. * @mode: this ETB is being used.
  95. * @buf: area of memory where ETB buffer content gets sent.
  96. * @buffer_depth: size of @buf.
  97. * @trigger_cntr: amount of words to store after a trigger.
  98. */
  99. struct etb_drvdata {
  100. void __iomem *base;
  101. struct device *dev;
  102. struct clk *atclk;
  103. struct coresight_device *csdev;
  104. struct miscdevice miscdev;
  105. spinlock_t spinlock;
  106. local_t reading;
  107. local_t mode;
  108. u8 *buf;
  109. u32 buffer_depth;
  110. u32 trigger_cntr;
  111. };
  112. static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
  113. {
  114. u32 depth = 0;
  115. pm_runtime_get_sync(drvdata->dev);
  116. /* RO registers don't need locking */
  117. depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
  118. pm_runtime_put(drvdata->dev);
  119. return depth;
  120. }
  121. static void etb_enable_hw(struct etb_drvdata *drvdata)
  122. {
  123. int i;
  124. u32 depth;
  125. CS_UNLOCK(drvdata->base);
  126. depth = drvdata->buffer_depth;
  127. /* reset write RAM pointer address */
  128. writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
  129. /* clear entire RAM buffer */
  130. for (i = 0; i < depth; i++)
  131. writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
  132. /* reset write RAM pointer address */
  133. writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
  134. /* reset read RAM pointer address */
  135. writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
  136. writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
  137. writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
  138. drvdata->base + ETB_FFCR);
  139. /* ETB trace capture enable */
  140. writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
  141. CS_LOCK(drvdata->base);
  142. }
  143. static int etb_enable(struct coresight_device *csdev, u32 mode)
  144. {
  145. u32 val;
  146. unsigned long flags;
  147. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  148. val = local_cmpxchg(&drvdata->mode,
  149. CS_MODE_DISABLED, mode);
  150. /*
  151. * When accessing from Perf, a HW buffer can be handled
  152. * by a single trace entity. In sysFS mode many tracers
  153. * can be logging to the same HW buffer.
  154. */
  155. if (val == CS_MODE_PERF)
  156. return -EBUSY;
  157. /* Nothing to do, the tracer is already enabled. */
  158. if (val == CS_MODE_SYSFS)
  159. goto out;
  160. spin_lock_irqsave(&drvdata->spinlock, flags);
  161. etb_enable_hw(drvdata);
  162. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  163. out:
  164. dev_info(drvdata->dev, "ETB enabled\n");
  165. return 0;
  166. }
  167. static void etb_disable_hw(struct etb_drvdata *drvdata)
  168. {
  169. u32 ffcr;
  170. CS_UNLOCK(drvdata->base);
  171. ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
  172. /* stop formatter when a stop has completed */
  173. ffcr |= ETB_FFCR_STOP_FI;
  174. writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
  175. /* manually generate a flush of the system */
  176. ffcr |= ETB_FFCR_FON_MAN;
  177. writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
  178. if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
  179. dev_err(drvdata->dev,
  180. "timeout observed when probing at offset %#x\n",
  181. ETB_FFCR);
  182. }
  183. /* disable trace capture */
  184. writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
  185. if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
  186. dev_err(drvdata->dev,
  187. "timeout observed when probing at offset %#x\n",
  188. ETB_FFCR);
  189. }
  190. CS_LOCK(drvdata->base);
  191. }
  192. static void etb_dump_hw(struct etb_drvdata *drvdata)
  193. {
  194. int i;
  195. u8 *buf_ptr;
  196. u32 read_data, depth;
  197. u32 read_ptr, write_ptr;
  198. u32 frame_off, frame_endoff;
  199. CS_UNLOCK(drvdata->base);
  200. read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
  201. write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
  202. frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
  203. frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
  204. if (frame_off) {
  205. dev_err(drvdata->dev,
  206. "write_ptr: %lu not aligned to formatter frame size\n",
  207. (unsigned long)write_ptr);
  208. dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
  209. (unsigned long)frame_off, (unsigned long)frame_endoff);
  210. write_ptr += frame_endoff;
  211. }
  212. if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
  213. & ETB_STATUS_RAM_FULL) == 0)
  214. writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
  215. else
  216. writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
  217. depth = drvdata->buffer_depth;
  218. buf_ptr = drvdata->buf;
  219. for (i = 0; i < depth; i++) {
  220. read_data = readl_relaxed(drvdata->base +
  221. ETB_RAM_READ_DATA_REG);
  222. *buf_ptr++ = read_data >> 0;
  223. *buf_ptr++ = read_data >> 8;
  224. *buf_ptr++ = read_data >> 16;
  225. *buf_ptr++ = read_data >> 24;
  226. }
  227. if (frame_off) {
  228. buf_ptr -= (frame_endoff * 4);
  229. for (i = 0; i < frame_endoff; i++) {
  230. *buf_ptr++ = 0x0;
  231. *buf_ptr++ = 0x0;
  232. *buf_ptr++ = 0x0;
  233. *buf_ptr++ = 0x0;
  234. }
  235. }
  236. writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
  237. CS_LOCK(drvdata->base);
  238. }
  239. static void etb_disable(struct coresight_device *csdev)
  240. {
  241. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  242. unsigned long flags;
  243. spin_lock_irqsave(&drvdata->spinlock, flags);
  244. etb_disable_hw(drvdata);
  245. etb_dump_hw(drvdata);
  246. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  247. local_set(&drvdata->mode, CS_MODE_DISABLED);
  248. dev_info(drvdata->dev, "ETB disabled\n");
  249. }
  250. static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
  251. void **pages, int nr_pages, bool overwrite)
  252. {
  253. int node;
  254. struct cs_buffers *buf;
  255. if (cpu == -1)
  256. cpu = smp_processor_id();
  257. node = cpu_to_node(cpu);
  258. buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
  259. if (!buf)
  260. return NULL;
  261. buf->snapshot = overwrite;
  262. buf->nr_pages = nr_pages;
  263. buf->data_pages = pages;
  264. return buf;
  265. }
  266. static void etb_free_buffer(void *config)
  267. {
  268. struct cs_buffers *buf = config;
  269. kfree(buf);
  270. }
  271. static int etb_set_buffer(struct coresight_device *csdev,
  272. struct perf_output_handle *handle,
  273. void *sink_config)
  274. {
  275. int ret = 0;
  276. unsigned long head;
  277. struct cs_buffers *buf = sink_config;
  278. /* wrap head around to the amount of space we have */
  279. head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
  280. /* find the page to write to */
  281. buf->cur = head / PAGE_SIZE;
  282. /* and offset within that page */
  283. buf->offset = head % PAGE_SIZE;
  284. local_set(&buf->data_size, 0);
  285. return ret;
  286. }
  287. static unsigned long etb_reset_buffer(struct coresight_device *csdev,
  288. struct perf_output_handle *handle,
  289. void *sink_config, bool *lost)
  290. {
  291. unsigned long size = 0;
  292. struct cs_buffers *buf = sink_config;
  293. if (buf) {
  294. /*
  295. * In snapshot mode ->data_size holds the new address of the
  296. * ring buffer's head. The size itself is the whole address
  297. * range since we want the latest information.
  298. */
  299. if (buf->snapshot)
  300. handle->head = local_xchg(&buf->data_size,
  301. buf->nr_pages << PAGE_SHIFT);
  302. /*
  303. * Tell the tracer PMU how much we got in this run and if
  304. * something went wrong along the way. Nobody else can use
  305. * this cs_buffers instance until we are done. As such
  306. * resetting parameters here and squaring off with the ring
  307. * buffer API in the tracer PMU is fine.
  308. */
  309. *lost = !!local_xchg(&buf->lost, 0);
  310. size = local_xchg(&buf->data_size, 0);
  311. }
  312. return size;
  313. }
  314. static void etb_update_buffer(struct coresight_device *csdev,
  315. struct perf_output_handle *handle,
  316. void *sink_config)
  317. {
  318. int i, cur;
  319. u8 *buf_ptr;
  320. u32 read_ptr, write_ptr, capacity;
  321. u32 status, read_data, to_read;
  322. unsigned long offset;
  323. struct cs_buffers *buf = sink_config;
  324. struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  325. if (!buf)
  326. return;
  327. capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
  328. CS_UNLOCK(drvdata->base);
  329. etb_disable_hw(drvdata);
  330. /* unit is in words, not bytes */
  331. read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
  332. write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
  333. /*
  334. * Entries should be aligned to the frame size. If they are not
  335. * go back to the last alignement point to give decoding tools a
  336. * chance to fix things.
  337. */
  338. if (write_ptr % ETB_FRAME_SIZE_WORDS) {
  339. dev_err(drvdata->dev,
  340. "write_ptr: %lu not aligned to formatter frame size\n",
  341. (unsigned long)write_ptr);
  342. write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
  343. local_inc(&buf->lost);
  344. }
  345. /*
  346. * Get a hold of the status register and see if a wrap around
  347. * has occurred. If so adjust things accordingly. Otherwise
  348. * start at the beginning and go until the write pointer has
  349. * been reached.
  350. */
  351. status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
  352. if (status & ETB_STATUS_RAM_FULL) {
  353. local_inc(&buf->lost);
  354. to_read = capacity;
  355. read_ptr = write_ptr;
  356. } else {
  357. to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
  358. to_read *= ETB_FRAME_SIZE_WORDS;
  359. }
  360. /*
  361. * Make sure we don't overwrite data that hasn't been consumed yet.
  362. * It is entirely possible that the HW buffer has more data than the
  363. * ring buffer can currently handle. If so adjust the start address
  364. * to take only the last traces.
  365. *
  366. * In snapshot mode we are looking to get the latest traces only and as
  367. * such, we don't care about not overwriting data that hasn't been
  368. * processed by user space.
  369. */
  370. if (!buf->snapshot && to_read > handle->size) {
  371. u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
  372. /* The new read pointer must be frame size aligned */
  373. to_read -= handle->size & mask;
  374. /*
  375. * Move the RAM read pointer up, keeping in mind that
  376. * everything is in frame size units.
  377. */
  378. read_ptr = (write_ptr + drvdata->buffer_depth) -
  379. to_read / ETB_FRAME_SIZE_WORDS;
  380. /* Wrap around if need be*/
  381. read_ptr &= ~(drvdata->buffer_depth - 1);
  382. /* let the decoder know we've skipped ahead */
  383. local_inc(&buf->lost);
  384. }
  385. /* finally tell HW where we want to start reading from */
  386. writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
  387. cur = buf->cur;
  388. offset = buf->offset;
  389. for (i = 0; i < to_read; i += 4) {
  390. buf_ptr = buf->data_pages[cur] + offset;
  391. read_data = readl_relaxed(drvdata->base +
  392. ETB_RAM_READ_DATA_REG);
  393. *buf_ptr++ = read_data >> 0;
  394. *buf_ptr++ = read_data >> 8;
  395. *buf_ptr++ = read_data >> 16;
  396. *buf_ptr++ = read_data >> 24;
  397. offset += 4;
  398. if (offset >= PAGE_SIZE) {
  399. offset = 0;
  400. cur++;
  401. /* wrap around at the end of the buffer */
  402. cur &= buf->nr_pages - 1;
  403. }
  404. }
  405. /* reset ETB buffer for next run */
  406. writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
  407. writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
  408. /*
  409. * In snapshot mode all we have to do is communicate to
  410. * perf_aux_output_end() the address of the current head. In full
  411. * trace mode the same function expects a size to move rb->aux_head
  412. * forward.
  413. */
  414. if (buf->snapshot)
  415. local_set(&buf->data_size, (cur * PAGE_SIZE) + offset);
  416. else
  417. local_add(to_read, &buf->data_size);
  418. etb_enable_hw(drvdata);
  419. CS_LOCK(drvdata->base);
  420. }
  421. static const struct coresight_ops_sink etb_sink_ops = {
  422. .enable = etb_enable,
  423. .disable = etb_disable,
  424. .alloc_buffer = etb_alloc_buffer,
  425. .free_buffer = etb_free_buffer,
  426. .set_buffer = etb_set_buffer,
  427. .reset_buffer = etb_reset_buffer,
  428. .update_buffer = etb_update_buffer,
  429. };
  430. static const struct coresight_ops etb_cs_ops = {
  431. .sink_ops = &etb_sink_ops,
  432. };
  433. static void etb_dump(struct etb_drvdata *drvdata)
  434. {
  435. unsigned long flags;
  436. spin_lock_irqsave(&drvdata->spinlock, flags);
  437. if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
  438. etb_disable_hw(drvdata);
  439. etb_dump_hw(drvdata);
  440. etb_enable_hw(drvdata);
  441. }
  442. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  443. dev_info(drvdata->dev, "ETB dumped\n");
  444. }
  445. static int etb_open(struct inode *inode, struct file *file)
  446. {
  447. struct etb_drvdata *drvdata = container_of(file->private_data,
  448. struct etb_drvdata, miscdev);
  449. if (local_cmpxchg(&drvdata->reading, 0, 1))
  450. return -EBUSY;
  451. dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
  452. return 0;
  453. }
  454. static ssize_t etb_read(struct file *file, char __user *data,
  455. size_t len, loff_t *ppos)
  456. {
  457. u32 depth;
  458. struct etb_drvdata *drvdata = container_of(file->private_data,
  459. struct etb_drvdata, miscdev);
  460. etb_dump(drvdata);
  461. depth = drvdata->buffer_depth;
  462. if (*ppos + len > depth * 4)
  463. len = depth * 4 - *ppos;
  464. if (copy_to_user(data, drvdata->buf + *ppos, len)) {
  465. dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
  466. return -EFAULT;
  467. }
  468. *ppos += len;
  469. dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
  470. __func__, len, (int)(depth * 4 - *ppos));
  471. return len;
  472. }
  473. static int etb_release(struct inode *inode, struct file *file)
  474. {
  475. struct etb_drvdata *drvdata = container_of(file->private_data,
  476. struct etb_drvdata, miscdev);
  477. local_set(&drvdata->reading, 0);
  478. dev_dbg(drvdata->dev, "%s: released\n", __func__);
  479. return 0;
  480. }
  481. static const struct file_operations etb_fops = {
  482. .owner = THIS_MODULE,
  483. .open = etb_open,
  484. .read = etb_read,
  485. .release = etb_release,
  486. .llseek = no_llseek,
  487. };
  488. static ssize_t status_show(struct device *dev,
  489. struct device_attribute *attr, char *buf)
  490. {
  491. unsigned long flags;
  492. u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
  493. u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
  494. struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
  495. pm_runtime_get_sync(drvdata->dev);
  496. spin_lock_irqsave(&drvdata->spinlock, flags);
  497. CS_UNLOCK(drvdata->base);
  498. etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
  499. etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
  500. etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
  501. etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
  502. etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
  503. etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
  504. etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
  505. etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
  506. CS_LOCK(drvdata->base);
  507. spin_unlock_irqrestore(&drvdata->spinlock, flags);
  508. pm_runtime_put(drvdata->dev);
  509. return sprintf(buf,
  510. "Depth:\t\t0x%x\n"
  511. "Status:\t\t0x%x\n"
  512. "RAM read ptr:\t0x%x\n"
  513. "RAM wrt ptr:\t0x%x\n"
  514. "Trigger cnt:\t0x%x\n"
  515. "Control:\t0x%x\n"
  516. "Flush status:\t0x%x\n"
  517. "Flush ctrl:\t0x%x\n",
  518. etb_rdr, etb_sr, etb_rrp, etb_rwp,
  519. etb_trg, etb_cr, etb_ffsr, etb_ffcr);
  520. return -EINVAL;
  521. }
  522. static DEVICE_ATTR_RO(status);
  523. static ssize_t trigger_cntr_show(struct device *dev,
  524. struct device_attribute *attr, char *buf)
  525. {
  526. struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
  527. unsigned long val = drvdata->trigger_cntr;
  528. return sprintf(buf, "%#lx\n", val);
  529. }
  530. static ssize_t trigger_cntr_store(struct device *dev,
  531. struct device_attribute *attr,
  532. const char *buf, size_t size)
  533. {
  534. int ret;
  535. unsigned long val;
  536. struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
  537. ret = kstrtoul(buf, 16, &val);
  538. if (ret)
  539. return ret;
  540. drvdata->trigger_cntr = val;
  541. return size;
  542. }
  543. static DEVICE_ATTR_RW(trigger_cntr);
  544. static struct attribute *coresight_etb_attrs[] = {
  545. &dev_attr_trigger_cntr.attr,
  546. &dev_attr_status.attr,
  547. NULL,
  548. };
  549. ATTRIBUTE_GROUPS(coresight_etb);
  550. static int etb_probe(struct amba_device *adev, const struct amba_id *id)
  551. {
  552. int ret;
  553. void __iomem *base;
  554. struct device *dev = &adev->dev;
  555. struct coresight_platform_data *pdata = NULL;
  556. struct etb_drvdata *drvdata;
  557. struct resource *res = &adev->res;
  558. struct coresight_desc *desc;
  559. struct device_node *np = adev->dev.of_node;
  560. if (np) {
  561. pdata = of_get_coresight_platform_data(dev, np);
  562. if (IS_ERR(pdata))
  563. return PTR_ERR(pdata);
  564. adev->dev.platform_data = pdata;
  565. }
  566. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  567. if (!drvdata)
  568. return -ENOMEM;
  569. drvdata->dev = &adev->dev;
  570. drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
  571. if (!IS_ERR(drvdata->atclk)) {
  572. ret = clk_prepare_enable(drvdata->atclk);
  573. if (ret)
  574. return ret;
  575. }
  576. dev_set_drvdata(dev, drvdata);
  577. /* validity for the resource is already checked by the AMBA core */
  578. base = devm_ioremap_resource(dev, res);
  579. if (IS_ERR(base))
  580. return PTR_ERR(base);
  581. drvdata->base = base;
  582. spin_lock_init(&drvdata->spinlock);
  583. drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
  584. pm_runtime_put(&adev->dev);
  585. if (drvdata->buffer_depth & 0x80000000)
  586. return -EINVAL;
  587. drvdata->buf = devm_kzalloc(dev,
  588. drvdata->buffer_depth * 4, GFP_KERNEL);
  589. if (!drvdata->buf) {
  590. dev_err(dev, "Failed to allocate %u bytes for buffer data\n",
  591. drvdata->buffer_depth * 4);
  592. return -ENOMEM;
  593. }
  594. desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
  595. if (!desc)
  596. return -ENOMEM;
  597. desc->type = CORESIGHT_DEV_TYPE_SINK;
  598. desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
  599. desc->ops = &etb_cs_ops;
  600. desc->pdata = pdata;
  601. desc->dev = dev;
  602. desc->groups = coresight_etb_groups;
  603. drvdata->csdev = coresight_register(desc);
  604. if (IS_ERR(drvdata->csdev))
  605. return PTR_ERR(drvdata->csdev);
  606. drvdata->miscdev.name = pdata->name;
  607. drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
  608. drvdata->miscdev.fops = &etb_fops;
  609. ret = misc_register(&drvdata->miscdev);
  610. if (ret)
  611. goto err_misc_register;
  612. dev_info(dev, "ETB initialized\n");
  613. return 0;
  614. err_misc_register:
  615. coresight_unregister(drvdata->csdev);
  616. return ret;
  617. }
  618. #ifdef CONFIG_PM
  619. static int etb_runtime_suspend(struct device *dev)
  620. {
  621. struct etb_drvdata *drvdata = dev_get_drvdata(dev);
  622. if (drvdata && !IS_ERR(drvdata->atclk))
  623. clk_disable_unprepare(drvdata->atclk);
  624. return 0;
  625. }
  626. static int etb_runtime_resume(struct device *dev)
  627. {
  628. struct etb_drvdata *drvdata = dev_get_drvdata(dev);
  629. if (drvdata && !IS_ERR(drvdata->atclk))
  630. clk_prepare_enable(drvdata->atclk);
  631. return 0;
  632. }
  633. #endif
  634. static const struct dev_pm_ops etb_dev_pm_ops = {
  635. SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
  636. };
  637. static struct amba_id etb_ids[] = {
  638. {
  639. .id = 0x0003b907,
  640. .mask = 0x0003ffff,
  641. },
  642. { 0, 0},
  643. };
  644. static struct amba_driver etb_driver = {
  645. .drv = {
  646. .name = "coresight-etb10",
  647. .owner = THIS_MODULE,
  648. .pm = &etb_dev_pm_ops,
  649. .suppress_bind_attrs = true,
  650. },
  651. .probe = etb_probe,
  652. .id_table = etb_ids,
  653. };
  654. builtin_amba_driver(etb_driver);