sti_hdmi.c 36 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  4. * License terms: GNU General Public License (GPL), version 2
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/debugfs.h>
  9. #include <linux/hdmi.h>
  10. #include <linux/module.h>
  11. #include <linux/of_gpio.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/reset.h>
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic_helper.h>
  16. #include <drm/drm_crtc_helper.h>
  17. #include <drm/drm_edid.h>
  18. #include "sti_hdmi.h"
  19. #include "sti_hdmi_tx3g4c28phy.h"
  20. #include "sti_hdmi_tx3g0c55phy.h"
  21. #include "sti_vtg.h"
  22. #define HDMI_CFG 0x0000
  23. #define HDMI_INT_EN 0x0004
  24. #define HDMI_INT_STA 0x0008
  25. #define HDMI_INT_CLR 0x000C
  26. #define HDMI_STA 0x0010
  27. #define HDMI_ACTIVE_VID_XMIN 0x0100
  28. #define HDMI_ACTIVE_VID_XMAX 0x0104
  29. #define HDMI_ACTIVE_VID_YMIN 0x0108
  30. #define HDMI_ACTIVE_VID_YMAX 0x010C
  31. #define HDMI_DFLT_CHL0_DAT 0x0110
  32. #define HDMI_DFLT_CHL1_DAT 0x0114
  33. #define HDMI_DFLT_CHL2_DAT 0x0118
  34. #define HDMI_SW_DI_1_HEAD_WORD 0x0210
  35. #define HDMI_SW_DI_1_PKT_WORD0 0x0214
  36. #define HDMI_SW_DI_1_PKT_WORD1 0x0218
  37. #define HDMI_SW_DI_1_PKT_WORD2 0x021C
  38. #define HDMI_SW_DI_1_PKT_WORD3 0x0220
  39. #define HDMI_SW_DI_1_PKT_WORD4 0x0224
  40. #define HDMI_SW_DI_1_PKT_WORD5 0x0228
  41. #define HDMI_SW_DI_1_PKT_WORD6 0x022C
  42. #define HDMI_SW_DI_CFG 0x0230
  43. #define HDMI_SW_DI_2_HEAD_WORD 0x0600
  44. #define HDMI_SW_DI_2_PKT_WORD0 0x0604
  45. #define HDMI_SW_DI_2_PKT_WORD1 0x0608
  46. #define HDMI_SW_DI_2_PKT_WORD2 0x060C
  47. #define HDMI_SW_DI_2_PKT_WORD3 0x0610
  48. #define HDMI_SW_DI_2_PKT_WORD4 0x0614
  49. #define HDMI_SW_DI_2_PKT_WORD5 0x0618
  50. #define HDMI_SW_DI_2_PKT_WORD6 0x061C
  51. #define HDMI_SW_DI_3_HEAD_WORD 0x0620
  52. #define HDMI_SW_DI_3_PKT_WORD0 0x0624
  53. #define HDMI_SW_DI_3_PKT_WORD1 0x0628
  54. #define HDMI_SW_DI_3_PKT_WORD2 0x062C
  55. #define HDMI_SW_DI_3_PKT_WORD3 0x0630
  56. #define HDMI_SW_DI_3_PKT_WORD4 0x0634
  57. #define HDMI_SW_DI_3_PKT_WORD5 0x0638
  58. #define HDMI_SW_DI_3_PKT_WORD6 0x063C
  59. #define HDMI_IFRAME_SLOT_AVI 1
  60. #define HDMI_IFRAME_SLOT_AUDIO 2
  61. #define HDMI_IFRAME_SLOT_VENDOR 3
  62. #define XCAT(prefix, x, suffix) prefix ## x ## suffix
  63. #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  64. #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  65. #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  66. #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  67. #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  68. #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  69. #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  70. #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  71. #define HDMI_SW_DI_MAX_WORD 7
  72. #define HDMI_IFRAME_DISABLED 0x0
  73. #define HDMI_IFRAME_SINGLE_SHOT 0x1
  74. #define HDMI_IFRAME_FIELD 0x2
  75. #define HDMI_IFRAME_FRAME 0x3
  76. #define HDMI_IFRAME_MASK 0x3
  77. #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
  78. #define HDMI_CFG_DEVICE_EN BIT(0)
  79. #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
  80. #define HDMI_CFG_HDCP_EN BIT(2)
  81. #define HDMI_CFG_ESS_NOT_OESS BIT(3)
  82. #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
  83. #define HDMI_CFG_SINK_TERM_DET_EN BIT(5)
  84. #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
  85. #define HDMI_CFG_422_EN BIT(8)
  86. #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
  87. #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
  88. #define HDMI_CFG_SW_RST_EN BIT(31)
  89. #define HDMI_INT_GLOBAL BIT(0)
  90. #define HDMI_INT_SW_RST BIT(1)
  91. #define HDMI_INT_PIX_CAP BIT(3)
  92. #define HDMI_INT_HOT_PLUG BIT(4)
  93. #define HDMI_INT_DLL_LCK BIT(5)
  94. #define HDMI_INT_NEW_FRAME BIT(6)
  95. #define HDMI_INT_GENCTRL_PKT BIT(7)
  96. #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
  97. #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
  98. | HDMI_INT_DLL_LCK \
  99. | HDMI_INT_HOT_PLUG \
  100. | HDMI_INT_GLOBAL)
  101. #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
  102. | HDMI_INT_GENCTRL_PKT \
  103. | HDMI_INT_NEW_FRAME \
  104. | HDMI_INT_DLL_LCK \
  105. | HDMI_INT_HOT_PLUG \
  106. | HDMI_INT_PIX_CAP \
  107. | HDMI_INT_SW_RST \
  108. | HDMI_INT_GLOBAL)
  109. #define HDMI_STA_SW_RST BIT(1)
  110. #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
  111. #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
  112. #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
  113. struct sti_hdmi_connector {
  114. struct drm_connector drm_connector;
  115. struct drm_encoder *encoder;
  116. struct sti_hdmi *hdmi;
  117. struct drm_property *colorspace_property;
  118. struct drm_property *hdmi_mode_property;
  119. };
  120. #define to_sti_hdmi_connector(x) \
  121. container_of(x, struct sti_hdmi_connector, drm_connector)
  122. u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
  123. {
  124. return readl(hdmi->regs + offset);
  125. }
  126. void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
  127. {
  128. writel(val, hdmi->regs + offset);
  129. }
  130. /**
  131. * HDMI interrupt handler threaded
  132. *
  133. * @irq: irq number
  134. * @arg: connector structure
  135. */
  136. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  137. {
  138. struct sti_hdmi *hdmi = arg;
  139. /* Hot plug/unplug IRQ */
  140. if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
  141. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  142. if (hdmi->drm_dev)
  143. drm_helper_hpd_irq_event(hdmi->drm_dev);
  144. }
  145. /* Sw reset and PLL lock are exclusive so we can use the same
  146. * event to signal them
  147. */
  148. if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
  149. hdmi->event_received = true;
  150. wake_up_interruptible(&hdmi->wait_event);
  151. }
  152. return IRQ_HANDLED;
  153. }
  154. /**
  155. * HDMI interrupt handler
  156. *
  157. * @irq: irq number
  158. * @arg: connector structure
  159. */
  160. static irqreturn_t hdmi_irq(int irq, void *arg)
  161. {
  162. struct sti_hdmi *hdmi = arg;
  163. /* read interrupt status */
  164. hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
  165. /* clear interrupt status */
  166. hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
  167. /* force sync bus write */
  168. hdmi_read(hdmi, HDMI_INT_STA);
  169. return IRQ_WAKE_THREAD;
  170. }
  171. /**
  172. * Set hdmi active area depending on the drm display mode selected
  173. *
  174. * @hdmi: pointer on the hdmi internal structure
  175. */
  176. static void hdmi_active_area(struct sti_hdmi *hdmi)
  177. {
  178. u32 xmin, xmax;
  179. u32 ymin, ymax;
  180. xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
  181. xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
  182. ymin = sti_vtg_get_line_number(hdmi->mode, 0);
  183. ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
  184. hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
  185. hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
  186. hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
  187. hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
  188. }
  189. /**
  190. * Overall hdmi configuration
  191. *
  192. * @hdmi: pointer on the hdmi internal structure
  193. */
  194. static void hdmi_config(struct sti_hdmi *hdmi)
  195. {
  196. u32 conf;
  197. DRM_DEBUG_DRIVER("\n");
  198. /* Clear overrun and underrun fifo */
  199. conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
  200. /* Select encryption type and the framing mode */
  201. conf |= HDMI_CFG_ESS_NOT_OESS;
  202. if (hdmi->hdmi_mode == HDMI_MODE_HDMI)
  203. conf |= HDMI_CFG_HDMI_NOT_DVI;
  204. /* Enable sink term detection */
  205. conf |= HDMI_CFG_SINK_TERM_DET_EN;
  206. /* Set Hsync polarity */
  207. if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
  208. DRM_DEBUG_DRIVER("H Sync Negative\n");
  209. conf |= HDMI_CFG_H_SYNC_POL_NEG;
  210. }
  211. /* Set Vsync polarity */
  212. if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
  213. DRM_DEBUG_DRIVER("V Sync Negative\n");
  214. conf |= HDMI_CFG_V_SYNC_POL_NEG;
  215. }
  216. /* Enable HDMI */
  217. conf |= HDMI_CFG_DEVICE_EN;
  218. hdmi_write(hdmi, conf, HDMI_CFG);
  219. }
  220. /*
  221. * Helper to reset info frame
  222. *
  223. * @hdmi: pointer on the hdmi internal structure
  224. * @slot: infoframe to reset
  225. */
  226. static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
  227. u32 slot)
  228. {
  229. u32 val, i;
  230. u32 head_offset, pack_offset;
  231. switch (slot) {
  232. case HDMI_IFRAME_SLOT_AVI:
  233. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
  234. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
  235. break;
  236. case HDMI_IFRAME_SLOT_AUDIO:
  237. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
  238. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
  239. break;
  240. case HDMI_IFRAME_SLOT_VENDOR:
  241. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
  242. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
  243. break;
  244. default:
  245. DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
  246. return;
  247. }
  248. /* Disable transmission for the selected slot */
  249. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  250. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
  251. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  252. /* Reset info frame registers */
  253. hdmi_write(hdmi, 0x0, head_offset);
  254. for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
  255. hdmi_write(hdmi, 0x0, pack_offset + i);
  256. }
  257. /**
  258. * Helper to concatenate infoframe in 32 bits word
  259. *
  260. * @ptr: pointer on the hdmi internal structure
  261. * @data: infoframe to write
  262. * @size: size to write
  263. */
  264. static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
  265. {
  266. unsigned long value = 0;
  267. size_t i;
  268. for (i = size; i > 0; i--)
  269. value = (value << 8) | ptr[i - 1];
  270. return value;
  271. }
  272. /**
  273. * Helper to write info frame
  274. *
  275. * @hdmi: pointer on the hdmi internal structure
  276. * @data: infoframe to write
  277. * @size: size to write
  278. */
  279. static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
  280. const u8 *data,
  281. size_t size)
  282. {
  283. const u8 *ptr = data;
  284. u32 val, slot, mode, i;
  285. u32 head_offset, pack_offset;
  286. switch (*ptr) {
  287. case HDMI_INFOFRAME_TYPE_AVI:
  288. slot = HDMI_IFRAME_SLOT_AVI;
  289. mode = HDMI_IFRAME_FIELD;
  290. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
  291. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
  292. break;
  293. case HDMI_INFOFRAME_TYPE_AUDIO:
  294. slot = HDMI_IFRAME_SLOT_AUDIO;
  295. mode = HDMI_IFRAME_FRAME;
  296. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
  297. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
  298. break;
  299. case HDMI_INFOFRAME_TYPE_VENDOR:
  300. slot = HDMI_IFRAME_SLOT_VENDOR;
  301. mode = HDMI_IFRAME_FRAME;
  302. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
  303. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
  304. break;
  305. default:
  306. DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
  307. return;
  308. }
  309. /* Disable transmission slot for updated infoframe */
  310. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  311. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
  312. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  313. val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
  314. val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
  315. val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
  316. writel(val, hdmi->regs + head_offset);
  317. /*
  318. * Each subpack contains 4 bytes
  319. * The First Bytes of the first subpacket must contain the checksum
  320. * Packet size is increase by one.
  321. */
  322. size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
  323. for (i = 0; i < size; i += sizeof(u32)) {
  324. size_t num;
  325. num = min_t(size_t, size - i, sizeof(u32));
  326. val = hdmi_infoframe_subpack(ptr, num);
  327. ptr += sizeof(u32);
  328. writel(val, hdmi->regs + pack_offset + i);
  329. }
  330. /* Enable transmission slot for updated infoframe */
  331. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  332. val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
  333. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  334. }
  335. /**
  336. * Prepare and configure the AVI infoframe
  337. *
  338. * AVI infoframe are transmitted at least once per two video field and
  339. * contains information about HDMI transmission mode such as color space,
  340. * colorimetry, ...
  341. *
  342. * @hdmi: pointer on the hdmi internal structure
  343. *
  344. * Return negative value if error occurs
  345. */
  346. static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
  347. {
  348. struct drm_display_mode *mode = &hdmi->mode;
  349. struct hdmi_avi_infoframe infoframe;
  350. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  351. int ret;
  352. DRM_DEBUG_DRIVER("\n");
  353. ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode);
  354. if (ret < 0) {
  355. DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
  356. return ret;
  357. }
  358. /* fixed infoframe configuration not linked to the mode */
  359. infoframe.colorspace = hdmi->colorspace;
  360. infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  361. infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
  362. ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  363. if (ret < 0) {
  364. DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
  365. return ret;
  366. }
  367. hdmi_infoframe_write_infopack(hdmi, buffer, ret);
  368. return 0;
  369. }
  370. /**
  371. * Prepare and configure the AUDIO infoframe
  372. *
  373. * AUDIO infoframe are transmitted once per frame and
  374. * contains information about HDMI transmission mode such as audio codec,
  375. * sample size, ...
  376. *
  377. * @hdmi: pointer on the hdmi internal structure
  378. *
  379. * Return negative value if error occurs
  380. */
  381. static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
  382. {
  383. struct hdmi_audio_infoframe infofame;
  384. u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
  385. int ret;
  386. ret = hdmi_audio_infoframe_init(&infofame);
  387. if (ret < 0) {
  388. DRM_ERROR("failed to setup audio infoframe: %d\n", ret);
  389. return ret;
  390. }
  391. infofame.channels = 2;
  392. ret = hdmi_audio_infoframe_pack(&infofame, buffer, sizeof(buffer));
  393. if (ret < 0) {
  394. DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
  395. return ret;
  396. }
  397. hdmi_infoframe_write_infopack(hdmi, buffer, ret);
  398. return 0;
  399. }
  400. /*
  401. * Prepare and configure the VS infoframe
  402. *
  403. * Vendor Specific infoframe are transmitted once per frame and
  404. * contains vendor specific information.
  405. *
  406. * @hdmi: pointer on the hdmi internal structure
  407. *
  408. * Return negative value if error occurs
  409. */
  410. #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
  411. static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
  412. {
  413. struct drm_display_mode *mode = &hdmi->mode;
  414. struct hdmi_vendor_infoframe infoframe;
  415. u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
  416. int ret;
  417. DRM_DEBUG_DRIVER("\n");
  418. ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, mode);
  419. if (ret < 0) {
  420. /*
  421. * Going into that statement does not means vendor infoframe
  422. * fails. It just informed us that vendor infoframe is not
  423. * needed for the selected mode. Only 4k or stereoscopic 3D
  424. * mode requires vendor infoframe. So just simply return 0.
  425. */
  426. return 0;
  427. }
  428. ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  429. if (ret < 0) {
  430. DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
  431. return ret;
  432. }
  433. hdmi_infoframe_write_infopack(hdmi, buffer, ret);
  434. return 0;
  435. }
  436. /**
  437. * Software reset of the hdmi subsystem
  438. *
  439. * @hdmi: pointer on the hdmi internal structure
  440. *
  441. */
  442. #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
  443. static void hdmi_swreset(struct sti_hdmi *hdmi)
  444. {
  445. u32 val;
  446. DRM_DEBUG_DRIVER("\n");
  447. /* Enable hdmi_audio clock only during hdmi reset */
  448. if (clk_prepare_enable(hdmi->clk_audio))
  449. DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
  450. /* Sw reset */
  451. hdmi->event_received = false;
  452. val = hdmi_read(hdmi, HDMI_CFG);
  453. val |= HDMI_CFG_SW_RST_EN;
  454. hdmi_write(hdmi, val, HDMI_CFG);
  455. /* Wait reset completed */
  456. wait_event_interruptible_timeout(hdmi->wait_event,
  457. hdmi->event_received == true,
  458. msecs_to_jiffies
  459. (HDMI_TIMEOUT_SWRESET));
  460. /*
  461. * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
  462. * set to '1' and clk_audio is running.
  463. */
  464. if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
  465. DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
  466. val = hdmi_read(hdmi, HDMI_CFG);
  467. val &= ~HDMI_CFG_SW_RST_EN;
  468. hdmi_write(hdmi, val, HDMI_CFG);
  469. /* Disable hdmi_audio clock. Not used anymore for drm purpose */
  470. clk_disable_unprepare(hdmi->clk_audio);
  471. }
  472. #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
  473. #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
  474. #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \
  475. hdmi_read(hdmi, reg))
  476. #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
  477. static void hdmi_dbg_cfg(struct seq_file *s, int val)
  478. {
  479. int tmp;
  480. seq_puts(s, "\t");
  481. tmp = val & HDMI_CFG_HDMI_NOT_DVI;
  482. DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
  483. seq_puts(s, "\t\t\t\t\t");
  484. tmp = val & HDMI_CFG_HDCP_EN;
  485. DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
  486. seq_puts(s, "\t\t\t\t\t");
  487. tmp = val & HDMI_CFG_ESS_NOT_OESS;
  488. DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
  489. seq_puts(s, "\t\t\t\t\t");
  490. tmp = val & HDMI_CFG_SINK_TERM_DET_EN;
  491. DBGFS_PRINT_STR("Sink term detection:", tmp ? "enable" : "disable");
  492. seq_puts(s, "\t\t\t\t\t");
  493. tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
  494. DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
  495. seq_puts(s, "\t\t\t\t\t");
  496. tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
  497. DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
  498. seq_puts(s, "\t\t\t\t\t");
  499. tmp = val & HDMI_CFG_422_EN;
  500. DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
  501. }
  502. static void hdmi_dbg_sta(struct seq_file *s, int val)
  503. {
  504. int tmp;
  505. seq_puts(s, "\t");
  506. tmp = (val & HDMI_STA_DLL_LCK);
  507. DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
  508. seq_puts(s, "\t\t\t\t\t");
  509. tmp = (val & HDMI_STA_HOT_PLUG);
  510. DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
  511. }
  512. static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
  513. {
  514. int tmp;
  515. char *const en_di[] = {"no transmission",
  516. "single transmission",
  517. "once every field",
  518. "once every frame"};
  519. seq_puts(s, "\t");
  520. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
  521. DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
  522. seq_puts(s, "\t\t\t\t\t");
  523. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
  524. DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
  525. seq_puts(s, "\t\t\t\t\t");
  526. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
  527. DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
  528. seq_puts(s, "\t\t\t\t\t");
  529. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
  530. DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
  531. seq_puts(s, "\t\t\t\t\t");
  532. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
  533. DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
  534. seq_puts(s, "\t\t\t\t\t");
  535. tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
  536. DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
  537. }
  538. static int hdmi_dbg_show(struct seq_file *s, void *data)
  539. {
  540. struct drm_info_node *node = s->private;
  541. struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
  542. struct drm_device *dev = node->minor->dev;
  543. int ret;
  544. ret = mutex_lock_interruptible(&dev->struct_mutex);
  545. if (ret)
  546. return ret;
  547. seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
  548. DBGFS_DUMP("\n", HDMI_CFG);
  549. hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
  550. DBGFS_DUMP("", HDMI_INT_EN);
  551. DBGFS_DUMP("\n", HDMI_STA);
  552. hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
  553. DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
  554. seq_puts(s, "\t");
  555. DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
  556. DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
  557. seq_puts(s, "\t");
  558. DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
  559. DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
  560. seq_puts(s, "\t");
  561. DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
  562. DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
  563. seq_puts(s, "\t");
  564. DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
  565. DBGFS_DUMP("", HDMI_SW_DI_CFG);
  566. hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
  567. seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
  568. HDMI_IFRAME_SLOT_AVI);
  569. DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
  570. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
  571. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
  572. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
  573. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
  574. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
  575. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
  576. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
  577. seq_puts(s, "\n");
  578. seq_printf(s, "\n AUDIO Infoframe (Data Island slot N=%d):",
  579. HDMI_IFRAME_SLOT_AUDIO);
  580. DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
  581. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
  582. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
  583. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
  584. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
  585. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
  586. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
  587. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
  588. seq_puts(s, "\n");
  589. seq_printf(s, "\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
  590. HDMI_IFRAME_SLOT_VENDOR);
  591. DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
  592. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
  593. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
  594. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
  595. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
  596. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
  597. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
  598. DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
  599. seq_puts(s, "\n");
  600. mutex_unlock(&dev->struct_mutex);
  601. return 0;
  602. }
  603. static struct drm_info_list hdmi_debugfs_files[] = {
  604. { "hdmi", hdmi_dbg_show, 0, NULL },
  605. };
  606. static void hdmi_debugfs_exit(struct sti_hdmi *hdmi, struct drm_minor *minor)
  607. {
  608. drm_debugfs_remove_files(hdmi_debugfs_files,
  609. ARRAY_SIZE(hdmi_debugfs_files),
  610. minor);
  611. }
  612. static int hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
  613. {
  614. unsigned int i;
  615. for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
  616. hdmi_debugfs_files[i].data = hdmi;
  617. return drm_debugfs_create_files(hdmi_debugfs_files,
  618. ARRAY_SIZE(hdmi_debugfs_files),
  619. minor->debugfs_root, minor);
  620. }
  621. static void sti_hdmi_disable(struct drm_bridge *bridge)
  622. {
  623. struct sti_hdmi *hdmi = bridge->driver_private;
  624. u32 val = hdmi_read(hdmi, HDMI_CFG);
  625. if (!hdmi->enabled)
  626. return;
  627. DRM_DEBUG_DRIVER("\n");
  628. /* Disable HDMI */
  629. val &= ~HDMI_CFG_DEVICE_EN;
  630. hdmi_write(hdmi, val, HDMI_CFG);
  631. hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
  632. /* Stop the phy */
  633. hdmi->phy_ops->stop(hdmi);
  634. /* Reset info frame transmission */
  635. hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
  636. hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
  637. hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
  638. /* Set the default channel data to be a dark red */
  639. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
  640. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
  641. hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
  642. /* Disable/unprepare hdmi clock */
  643. clk_disable_unprepare(hdmi->clk_phy);
  644. clk_disable_unprepare(hdmi->clk_tmds);
  645. clk_disable_unprepare(hdmi->clk_pix);
  646. hdmi->enabled = false;
  647. }
  648. static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
  649. {
  650. struct sti_hdmi *hdmi = bridge->driver_private;
  651. DRM_DEBUG_DRIVER("\n");
  652. if (hdmi->enabled)
  653. return;
  654. /* Prepare/enable clocks */
  655. if (clk_prepare_enable(hdmi->clk_pix))
  656. DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
  657. if (clk_prepare_enable(hdmi->clk_tmds))
  658. DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
  659. if (clk_prepare_enable(hdmi->clk_phy))
  660. DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
  661. hdmi->enabled = true;
  662. /* Program hdmi serializer and start phy */
  663. if (!hdmi->phy_ops->start(hdmi)) {
  664. DRM_ERROR("Unable to start hdmi phy\n");
  665. return;
  666. }
  667. /* Program hdmi active area */
  668. hdmi_active_area(hdmi);
  669. /* Enable working interrupts */
  670. hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
  671. /* Program hdmi config */
  672. hdmi_config(hdmi);
  673. /* Program AVI infoframe */
  674. if (hdmi_avi_infoframe_config(hdmi))
  675. DRM_ERROR("Unable to configure AVI infoframe\n");
  676. /* Program AUDIO infoframe */
  677. if (hdmi_audio_infoframe_config(hdmi))
  678. DRM_ERROR("Unable to configure AUDIO infoframe\n");
  679. /* Program VS infoframe */
  680. if (hdmi_vendor_infoframe_config(hdmi))
  681. DRM_ERROR("Unable to configure VS infoframe\n");
  682. /* Sw reset */
  683. hdmi_swreset(hdmi);
  684. }
  685. static void sti_hdmi_set_mode(struct drm_bridge *bridge,
  686. struct drm_display_mode *mode,
  687. struct drm_display_mode *adjusted_mode)
  688. {
  689. struct sti_hdmi *hdmi = bridge->driver_private;
  690. int ret;
  691. DRM_DEBUG_DRIVER("\n");
  692. /* Copy the drm display mode in the connector local structure */
  693. memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
  694. /* Update clock framerate according to the selected mode */
  695. ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
  696. if (ret < 0) {
  697. DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
  698. mode->clock * 1000);
  699. return;
  700. }
  701. ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
  702. if (ret < 0) {
  703. DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
  704. mode->clock * 1000);
  705. return;
  706. }
  707. }
  708. static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
  709. {
  710. /* do nothing */
  711. }
  712. static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
  713. .pre_enable = sti_hdmi_pre_enable,
  714. .enable = sti_hdmi_bridge_nope,
  715. .disable = sti_hdmi_disable,
  716. .post_disable = sti_hdmi_bridge_nope,
  717. .mode_set = sti_hdmi_set_mode,
  718. };
  719. static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
  720. {
  721. struct sti_hdmi_connector *hdmi_connector
  722. = to_sti_hdmi_connector(connector);
  723. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  724. struct edid *edid;
  725. int count;
  726. DRM_DEBUG_DRIVER("\n");
  727. edid = drm_get_edid(connector, hdmi->ddc_adapt);
  728. if (!edid)
  729. goto fail;
  730. count = drm_add_edid_modes(connector, edid);
  731. drm_mode_connector_update_edid_property(connector, edid);
  732. kfree(edid);
  733. return count;
  734. fail:
  735. DRM_ERROR("Can't read HDMI EDID\n");
  736. return 0;
  737. }
  738. #define CLK_TOLERANCE_HZ 50
  739. static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
  740. struct drm_display_mode *mode)
  741. {
  742. int target = mode->clock * 1000;
  743. int target_min = target - CLK_TOLERANCE_HZ;
  744. int target_max = target + CLK_TOLERANCE_HZ;
  745. int result;
  746. struct sti_hdmi_connector *hdmi_connector
  747. = to_sti_hdmi_connector(connector);
  748. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  749. result = clk_round_rate(hdmi->clk_pix, target);
  750. DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
  751. target, result);
  752. if ((result < target_min) || (result > target_max)) {
  753. DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
  754. return MODE_BAD;
  755. }
  756. return MODE_OK;
  757. }
  758. struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
  759. {
  760. struct sti_hdmi_connector *hdmi_connector
  761. = to_sti_hdmi_connector(connector);
  762. /* Best encoder is the one associated during connector creation */
  763. return hdmi_connector->encoder;
  764. }
  765. static const
  766. struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
  767. .get_modes = sti_hdmi_connector_get_modes,
  768. .mode_valid = sti_hdmi_connector_mode_valid,
  769. .best_encoder = sti_hdmi_best_encoder,
  770. };
  771. /* get detection status of display device */
  772. static enum drm_connector_status
  773. sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
  774. {
  775. struct sti_hdmi_connector *hdmi_connector
  776. = to_sti_hdmi_connector(connector);
  777. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  778. DRM_DEBUG_DRIVER("\n");
  779. if (hdmi->hpd) {
  780. DRM_DEBUG_DRIVER("hdmi cable connected\n");
  781. return connector_status_connected;
  782. }
  783. DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
  784. return connector_status_disconnected;
  785. }
  786. static void sti_hdmi_connector_destroy(struct drm_connector *connector)
  787. {
  788. struct sti_hdmi_connector *hdmi_connector
  789. = to_sti_hdmi_connector(connector);
  790. drm_connector_unregister(connector);
  791. drm_connector_cleanup(connector);
  792. kfree(hdmi_connector);
  793. }
  794. static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
  795. struct drm_connector *connector)
  796. {
  797. struct sti_hdmi_connector *hdmi_connector
  798. = to_sti_hdmi_connector(connector);
  799. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  800. struct drm_property *prop;
  801. /* colorspace property */
  802. hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
  803. prop = drm_property_create_enum(drm_dev, 0, "colorspace",
  804. colorspace_mode_names,
  805. ARRAY_SIZE(colorspace_mode_names));
  806. if (!prop) {
  807. DRM_ERROR("fails to create colorspace property\n");
  808. return;
  809. }
  810. hdmi_connector->colorspace_property = prop;
  811. drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
  812. /* hdmi_mode property */
  813. hdmi->hdmi_mode = DEFAULT_HDMI_MODE;
  814. prop = drm_property_create_enum(drm_dev, 0, "hdmi_mode",
  815. hdmi_mode_names,
  816. ARRAY_SIZE(hdmi_mode_names));
  817. if (!prop) {
  818. DRM_ERROR("fails to create colorspace property\n");
  819. return;
  820. }
  821. hdmi_connector->hdmi_mode_property = prop;
  822. drm_object_attach_property(&connector->base, prop, hdmi->hdmi_mode);
  823. }
  824. static int
  825. sti_hdmi_connector_set_property(struct drm_connector *connector,
  826. struct drm_connector_state *state,
  827. struct drm_property *property,
  828. uint64_t val)
  829. {
  830. struct sti_hdmi_connector *hdmi_connector
  831. = to_sti_hdmi_connector(connector);
  832. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  833. if (property == hdmi_connector->colorspace_property) {
  834. hdmi->colorspace = val;
  835. return 0;
  836. }
  837. if (property == hdmi_connector->hdmi_mode_property) {
  838. hdmi->hdmi_mode = val;
  839. return 0;
  840. }
  841. DRM_ERROR("failed to set hdmi connector property\n");
  842. return -EINVAL;
  843. }
  844. static int
  845. sti_hdmi_connector_get_property(struct drm_connector *connector,
  846. const struct drm_connector_state *state,
  847. struct drm_property *property,
  848. uint64_t *val)
  849. {
  850. struct sti_hdmi_connector *hdmi_connector
  851. = to_sti_hdmi_connector(connector);
  852. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  853. if (property == hdmi_connector->colorspace_property) {
  854. *val = hdmi->colorspace;
  855. return 0;
  856. }
  857. if (property == hdmi_connector->hdmi_mode_property) {
  858. *val = hdmi->hdmi_mode;
  859. return 0;
  860. }
  861. DRM_ERROR("failed to get hdmi connector property\n");
  862. return -EINVAL;
  863. }
  864. static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
  865. .dpms = drm_atomic_helper_connector_dpms,
  866. .fill_modes = drm_helper_probe_single_connector_modes,
  867. .detect = sti_hdmi_connector_detect,
  868. .destroy = sti_hdmi_connector_destroy,
  869. .reset = drm_atomic_helper_connector_reset,
  870. .set_property = drm_atomic_helper_connector_set_property,
  871. .atomic_set_property = sti_hdmi_connector_set_property,
  872. .atomic_get_property = sti_hdmi_connector_get_property,
  873. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  874. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  875. };
  876. static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
  877. {
  878. struct drm_encoder *encoder;
  879. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  880. if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
  881. return encoder;
  882. }
  883. return NULL;
  884. }
  885. static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
  886. {
  887. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  888. struct drm_device *drm_dev = data;
  889. struct drm_encoder *encoder;
  890. struct sti_hdmi_connector *connector;
  891. struct drm_connector *drm_connector;
  892. struct drm_bridge *bridge;
  893. int err;
  894. /* Set the drm device handle */
  895. hdmi->drm_dev = drm_dev;
  896. encoder = sti_hdmi_find_encoder(drm_dev);
  897. if (!encoder)
  898. return -EINVAL;
  899. connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
  900. if (!connector)
  901. return -EINVAL;
  902. connector->hdmi = hdmi;
  903. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  904. if (!bridge)
  905. return -EINVAL;
  906. bridge->driver_private = hdmi;
  907. bridge->funcs = &sti_hdmi_bridge_funcs;
  908. drm_bridge_attach(drm_dev, bridge);
  909. encoder->bridge = bridge;
  910. connector->encoder = encoder;
  911. drm_connector = (struct drm_connector *)connector;
  912. drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
  913. drm_connector_init(drm_dev, drm_connector,
  914. &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
  915. drm_connector_helper_add(drm_connector,
  916. &sti_hdmi_connector_helper_funcs);
  917. /* initialise property */
  918. sti_hdmi_connector_init_property(drm_dev, drm_connector);
  919. err = drm_connector_register(drm_connector);
  920. if (err)
  921. goto err_connector;
  922. err = drm_mode_connector_attach_encoder(drm_connector, encoder);
  923. if (err) {
  924. DRM_ERROR("Failed to attach a connector to a encoder\n");
  925. goto err_sysfs;
  926. }
  927. /* Enable default interrupts */
  928. hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
  929. if (hdmi_debugfs_init(hdmi, drm_dev->primary))
  930. DRM_ERROR("HDMI debugfs setup failed\n");
  931. return 0;
  932. err_sysfs:
  933. drm_connector_unregister(drm_connector);
  934. err_connector:
  935. drm_connector_cleanup(drm_connector);
  936. return -EINVAL;
  937. }
  938. static void sti_hdmi_unbind(struct device *dev,
  939. struct device *master, void *data)
  940. {
  941. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  942. struct drm_device *drm_dev = data;
  943. hdmi_debugfs_exit(hdmi, drm_dev->primary);
  944. }
  945. static const struct component_ops sti_hdmi_ops = {
  946. .bind = sti_hdmi_bind,
  947. .unbind = sti_hdmi_unbind,
  948. };
  949. static const struct of_device_id hdmi_of_match[] = {
  950. {
  951. .compatible = "st,stih416-hdmi",
  952. .data = &tx3g0c55phy_ops,
  953. }, {
  954. .compatible = "st,stih407-hdmi",
  955. .data = &tx3g4c28phy_ops,
  956. }, {
  957. /* end node */
  958. }
  959. };
  960. MODULE_DEVICE_TABLE(of, hdmi_of_match);
  961. static int sti_hdmi_probe(struct platform_device *pdev)
  962. {
  963. struct device *dev = &pdev->dev;
  964. struct sti_hdmi *hdmi;
  965. struct device_node *np = dev->of_node;
  966. struct resource *res;
  967. struct device_node *ddc;
  968. int ret;
  969. DRM_INFO("%s\n", __func__);
  970. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  971. if (!hdmi)
  972. return -ENOMEM;
  973. ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
  974. if (ddc) {
  975. hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
  976. of_node_put(ddc);
  977. if (!hdmi->ddc_adapt)
  978. return -EPROBE_DEFER;
  979. }
  980. hdmi->dev = pdev->dev;
  981. /* Get resources */
  982. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
  983. if (!res) {
  984. DRM_ERROR("Invalid hdmi resource\n");
  985. ret = -ENOMEM;
  986. goto release_adapter;
  987. }
  988. hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  989. if (!hdmi->regs) {
  990. ret = -ENOMEM;
  991. goto release_adapter;
  992. }
  993. if (of_device_is_compatible(np, "st,stih416-hdmi")) {
  994. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  995. "syscfg");
  996. if (!res) {
  997. DRM_ERROR("Invalid syscfg resource\n");
  998. ret = -ENOMEM;
  999. goto release_adapter;
  1000. }
  1001. hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
  1002. resource_size(res));
  1003. if (!hdmi->syscfg) {
  1004. ret = -ENOMEM;
  1005. goto release_adapter;
  1006. }
  1007. }
  1008. hdmi->phy_ops = (struct hdmi_phy_ops *)
  1009. of_match_node(hdmi_of_match, np)->data;
  1010. /* Get clock resources */
  1011. hdmi->clk_pix = devm_clk_get(dev, "pix");
  1012. if (IS_ERR(hdmi->clk_pix)) {
  1013. DRM_ERROR("Cannot get hdmi_pix clock\n");
  1014. ret = PTR_ERR(hdmi->clk_pix);
  1015. goto release_adapter;
  1016. }
  1017. hdmi->clk_tmds = devm_clk_get(dev, "tmds");
  1018. if (IS_ERR(hdmi->clk_tmds)) {
  1019. DRM_ERROR("Cannot get hdmi_tmds clock\n");
  1020. ret = PTR_ERR(hdmi->clk_tmds);
  1021. goto release_adapter;
  1022. }
  1023. hdmi->clk_phy = devm_clk_get(dev, "phy");
  1024. if (IS_ERR(hdmi->clk_phy)) {
  1025. DRM_ERROR("Cannot get hdmi_phy clock\n");
  1026. ret = PTR_ERR(hdmi->clk_phy);
  1027. goto release_adapter;
  1028. }
  1029. hdmi->clk_audio = devm_clk_get(dev, "audio");
  1030. if (IS_ERR(hdmi->clk_audio)) {
  1031. DRM_ERROR("Cannot get hdmi_audio clock\n");
  1032. ret = PTR_ERR(hdmi->clk_audio);
  1033. goto release_adapter;
  1034. }
  1035. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  1036. init_waitqueue_head(&hdmi->wait_event);
  1037. hdmi->irq = platform_get_irq_byname(pdev, "irq");
  1038. ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
  1039. hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
  1040. if (ret) {
  1041. DRM_ERROR("Failed to register HDMI interrupt\n");
  1042. goto release_adapter;
  1043. }
  1044. hdmi->reset = devm_reset_control_get(dev, "hdmi");
  1045. /* Take hdmi out of reset */
  1046. if (!IS_ERR(hdmi->reset))
  1047. reset_control_deassert(hdmi->reset);
  1048. platform_set_drvdata(pdev, hdmi);
  1049. return component_add(&pdev->dev, &sti_hdmi_ops);
  1050. release_adapter:
  1051. i2c_put_adapter(hdmi->ddc_adapt);
  1052. return ret;
  1053. }
  1054. static int sti_hdmi_remove(struct platform_device *pdev)
  1055. {
  1056. struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
  1057. i2c_put_adapter(hdmi->ddc_adapt);
  1058. component_del(&pdev->dev, &sti_hdmi_ops);
  1059. return 0;
  1060. }
  1061. struct platform_driver sti_hdmi_driver = {
  1062. .driver = {
  1063. .name = "sti-hdmi",
  1064. .owner = THIS_MODULE,
  1065. .of_match_table = hdmi_of_match,
  1066. },
  1067. .probe = sti_hdmi_probe,
  1068. .remove = sti_hdmi_remove,
  1069. };
  1070. MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
  1071. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  1072. MODULE_LICENSE("GPL");