adreno_device.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2013-2014 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "adreno_gpu.h"
  20. #define ANY_ID 0xff
  21. bool hang_debug = false;
  22. MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  23. module_param_named(hang_debug, hang_debug, bool, 0600);
  24. struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
  25. struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
  26. static const struct adreno_info gpulist[] = {
  27. {
  28. .rev = ADRENO_REV(3, 0, 5, ANY_ID),
  29. .revn = 305,
  30. .name = "A305",
  31. .pm4fw = "a300_pm4.fw",
  32. .pfpfw = "a300_pfp.fw",
  33. .gmem = SZ_256K,
  34. .init = a3xx_gpu_init,
  35. }, {
  36. .rev = ADRENO_REV(3, 0, 6, 0),
  37. .revn = 307, /* because a305c is revn==306 */
  38. .name = "A306",
  39. .pm4fw = "a300_pm4.fw",
  40. .pfpfw = "a300_pfp.fw",
  41. .gmem = SZ_128K,
  42. .init = a3xx_gpu_init,
  43. }, {
  44. .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  45. .revn = 320,
  46. .name = "A320",
  47. .pm4fw = "a300_pm4.fw",
  48. .pfpfw = "a300_pfp.fw",
  49. .gmem = SZ_512K,
  50. .init = a3xx_gpu_init,
  51. }, {
  52. .rev = ADRENO_REV(3, 3, 0, ANY_ID),
  53. .revn = 330,
  54. .name = "A330",
  55. .pm4fw = "a330_pm4.fw",
  56. .pfpfw = "a330_pfp.fw",
  57. .gmem = SZ_1M,
  58. .init = a3xx_gpu_init,
  59. }, {
  60. .rev = ADRENO_REV(4, 2, 0, ANY_ID),
  61. .revn = 420,
  62. .name = "A420",
  63. .pm4fw = "a420_pm4.fw",
  64. .pfpfw = "a420_pfp.fw",
  65. .gmem = (SZ_1M + SZ_512K),
  66. .init = a4xx_gpu_init,
  67. }, {
  68. .rev = ADRENO_REV(4, 3, 0, ANY_ID),
  69. .revn = 430,
  70. .name = "A430",
  71. .pm4fw = "a420_pm4.fw",
  72. .pfpfw = "a420_pfp.fw",
  73. .gmem = (SZ_1M + SZ_512K),
  74. .init = a4xx_gpu_init,
  75. },
  76. };
  77. MODULE_FIRMWARE("a300_pm4.fw");
  78. MODULE_FIRMWARE("a300_pfp.fw");
  79. MODULE_FIRMWARE("a330_pm4.fw");
  80. MODULE_FIRMWARE("a330_pfp.fw");
  81. MODULE_FIRMWARE("a420_pm4.fw");
  82. MODULE_FIRMWARE("a420_pfp.fw");
  83. static inline bool _rev_match(uint8_t entry, uint8_t id)
  84. {
  85. return (entry == ANY_ID) || (entry == id);
  86. }
  87. const struct adreno_info *adreno_info(struct adreno_rev rev)
  88. {
  89. int i;
  90. /* identify gpu: */
  91. for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
  92. const struct adreno_info *info = &gpulist[i];
  93. if (_rev_match(info->rev.core, rev.core) &&
  94. _rev_match(info->rev.major, rev.major) &&
  95. _rev_match(info->rev.minor, rev.minor) &&
  96. _rev_match(info->rev.patchid, rev.patchid))
  97. return info;
  98. }
  99. return NULL;
  100. }
  101. struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
  102. {
  103. struct msm_drm_private *priv = dev->dev_private;
  104. struct platform_device *pdev = priv->gpu_pdev;
  105. struct adreno_platform_config *config;
  106. struct adreno_rev rev;
  107. const struct adreno_info *info;
  108. struct msm_gpu *gpu = NULL;
  109. if (!pdev) {
  110. dev_err(dev->dev, "no adreno device\n");
  111. return NULL;
  112. }
  113. config = pdev->dev.platform_data;
  114. rev = config->rev;
  115. info = adreno_info(config->rev);
  116. if (!info) {
  117. dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
  118. rev.core, rev.major, rev.minor, rev.patchid);
  119. return NULL;
  120. }
  121. DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
  122. rev.minor, rev.patchid);
  123. gpu = info->init(dev);
  124. if (IS_ERR(gpu)) {
  125. dev_warn(dev->dev, "failed to load adreno gpu\n");
  126. gpu = NULL;
  127. /* not fatal */
  128. }
  129. if (gpu) {
  130. int ret;
  131. mutex_lock(&dev->struct_mutex);
  132. gpu->funcs->pm_resume(gpu);
  133. mutex_unlock(&dev->struct_mutex);
  134. ret = gpu->funcs->hw_init(gpu);
  135. if (ret) {
  136. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  137. gpu->funcs->destroy(gpu);
  138. gpu = NULL;
  139. } else {
  140. /* give inactive pm a chance to kick in: */
  141. msm_gpu_retire(gpu);
  142. }
  143. }
  144. return gpu;
  145. }
  146. static void set_gpu_pdev(struct drm_device *dev,
  147. struct platform_device *pdev)
  148. {
  149. struct msm_drm_private *priv = dev->dev_private;
  150. priv->gpu_pdev = pdev;
  151. }
  152. static int adreno_bind(struct device *dev, struct device *master, void *data)
  153. {
  154. static struct adreno_platform_config config = {};
  155. struct device_node *child, *node = dev->of_node;
  156. u32 val;
  157. int ret;
  158. ret = of_property_read_u32(node, "qcom,chipid", &val);
  159. if (ret) {
  160. dev_err(dev, "could not find chipid: %d\n", ret);
  161. return ret;
  162. }
  163. config.rev = ADRENO_REV((val >> 24) & 0xff,
  164. (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
  165. /* find clock rates: */
  166. config.fast_rate = 0;
  167. config.slow_rate = ~0;
  168. for_each_child_of_node(node, child) {
  169. if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
  170. struct device_node *pwrlvl;
  171. for_each_child_of_node(child, pwrlvl) {
  172. ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
  173. if (ret) {
  174. dev_err(dev, "could not find gpu-freq: %d\n", ret);
  175. return ret;
  176. }
  177. config.fast_rate = max(config.fast_rate, val);
  178. config.slow_rate = min(config.slow_rate, val);
  179. }
  180. }
  181. }
  182. if (!config.fast_rate) {
  183. dev_err(dev, "could not find clk rates\n");
  184. return -ENXIO;
  185. }
  186. dev->platform_data = &config;
  187. set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
  188. return 0;
  189. }
  190. static void adreno_unbind(struct device *dev, struct device *master,
  191. void *data)
  192. {
  193. set_gpu_pdev(dev_get_drvdata(master), NULL);
  194. }
  195. static const struct component_ops a3xx_ops = {
  196. .bind = adreno_bind,
  197. .unbind = adreno_unbind,
  198. };
  199. static int adreno_probe(struct platform_device *pdev)
  200. {
  201. return component_add(&pdev->dev, &a3xx_ops);
  202. }
  203. static int adreno_remove(struct platform_device *pdev)
  204. {
  205. component_del(&pdev->dev, &a3xx_ops);
  206. return 0;
  207. }
  208. static const struct of_device_id dt_match[] = {
  209. { .compatible = "qcom,adreno-3xx" },
  210. /* for backwards compat w/ downstream kgsl DT files: */
  211. { .compatible = "qcom,kgsl-3d0" },
  212. {}
  213. };
  214. static struct platform_driver adreno_driver = {
  215. .probe = adreno_probe,
  216. .remove = adreno_remove,
  217. .driver = {
  218. .name = "adreno",
  219. .of_match_table = dt_match,
  220. },
  221. };
  222. void __init adreno_register(void)
  223. {
  224. platform_driver_register(&adreno_driver);
  225. }
  226. void __exit adreno_unregister(void)
  227. {
  228. platform_driver_unregister(&adreno_driver);
  229. }