gpio-tc3589x.c 8.2 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License, version 2
  5. * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include <linux/gpio.h>
  13. #include <linux/of.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mfd/tc3589x.h>
  16. /*
  17. * These registers are modified under the irq bus lock and cached to avoid
  18. * unnecessary writes in bus_sync_unlock.
  19. */
  20. enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
  21. #define CACHE_NR_REGS 4
  22. #define CACHE_NR_BANKS 3
  23. struct tc3589x_gpio {
  24. struct gpio_chip chip;
  25. struct tc3589x *tc3589x;
  26. struct device *dev;
  27. struct mutex irq_lock;
  28. /* Caches of interrupt control registers for bus_lock */
  29. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  30. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  31. };
  32. static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
  33. {
  34. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  35. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  36. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  37. u8 mask = 1 << (offset % 8);
  38. int ret;
  39. ret = tc3589x_reg_read(tc3589x, reg);
  40. if (ret < 0)
  41. return ret;
  42. return !!(ret & mask);
  43. }
  44. static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  45. {
  46. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  47. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  48. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  49. unsigned pos = offset % 8;
  50. u8 data[] = {!!val << pos, 1 << pos};
  51. tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
  52. }
  53. static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
  54. unsigned offset, int val)
  55. {
  56. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  57. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  58. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  59. unsigned pos = offset % 8;
  60. tc3589x_gpio_set(chip, offset, val);
  61. return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
  62. }
  63. static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
  64. unsigned offset)
  65. {
  66. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  67. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  68. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  69. unsigned pos = offset % 8;
  70. return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
  71. }
  72. static struct gpio_chip template_chip = {
  73. .label = "tc3589x",
  74. .owner = THIS_MODULE,
  75. .direction_input = tc3589x_gpio_direction_input,
  76. .get = tc3589x_gpio_get,
  77. .direction_output = tc3589x_gpio_direction_output,
  78. .set = tc3589x_gpio_set,
  79. .can_sleep = true,
  80. };
  81. static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  82. {
  83. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  84. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  85. int offset = d->hwirq;
  86. int regoffset = offset / 8;
  87. int mask = 1 << (offset % 8);
  88. if (type == IRQ_TYPE_EDGE_BOTH) {
  89. tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
  90. return 0;
  91. }
  92. tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
  93. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  94. tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
  95. else
  96. tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
  97. if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  98. tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
  99. else
  100. tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
  101. return 0;
  102. }
  103. static void tc3589x_gpio_irq_lock(struct irq_data *d)
  104. {
  105. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  106. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  107. mutex_lock(&tc3589x_gpio->irq_lock);
  108. }
  109. static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
  110. {
  111. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  112. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  113. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  114. static const u8 regmap[] = {
  115. [REG_IBE] = TC3589x_GPIOIBE0,
  116. [REG_IEV] = TC3589x_GPIOIEV0,
  117. [REG_IS] = TC3589x_GPIOIS0,
  118. [REG_IE] = TC3589x_GPIOIE0,
  119. };
  120. int i, j;
  121. for (i = 0; i < CACHE_NR_REGS; i++) {
  122. for (j = 0; j < CACHE_NR_BANKS; j++) {
  123. u8 old = tc3589x_gpio->oldregs[i][j];
  124. u8 new = tc3589x_gpio->regs[i][j];
  125. if (new == old)
  126. continue;
  127. tc3589x_gpio->oldregs[i][j] = new;
  128. tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
  129. }
  130. }
  131. mutex_unlock(&tc3589x_gpio->irq_lock);
  132. }
  133. static void tc3589x_gpio_irq_mask(struct irq_data *d)
  134. {
  135. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  136. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  137. int offset = d->hwirq;
  138. int regoffset = offset / 8;
  139. int mask = 1 << (offset % 8);
  140. tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
  141. }
  142. static void tc3589x_gpio_irq_unmask(struct irq_data *d)
  143. {
  144. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  145. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  146. int offset = d->hwirq;
  147. int regoffset = offset / 8;
  148. int mask = 1 << (offset % 8);
  149. tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
  150. }
  151. static struct irq_chip tc3589x_gpio_irq_chip = {
  152. .name = "tc3589x-gpio",
  153. .irq_bus_lock = tc3589x_gpio_irq_lock,
  154. .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
  155. .irq_mask = tc3589x_gpio_irq_mask,
  156. .irq_unmask = tc3589x_gpio_irq_unmask,
  157. .irq_set_type = tc3589x_gpio_irq_set_type,
  158. };
  159. static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
  160. {
  161. struct tc3589x_gpio *tc3589x_gpio = dev;
  162. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  163. u8 status[CACHE_NR_BANKS];
  164. int ret;
  165. int i;
  166. ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
  167. ARRAY_SIZE(status), status);
  168. if (ret < 0)
  169. return IRQ_NONE;
  170. for (i = 0; i < ARRAY_SIZE(status); i++) {
  171. unsigned int stat = status[i];
  172. if (!stat)
  173. continue;
  174. while (stat) {
  175. int bit = __ffs(stat);
  176. int line = i * 8 + bit;
  177. int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
  178. line);
  179. handle_nested_irq(irq);
  180. stat &= ~(1 << bit);
  181. }
  182. tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
  183. }
  184. return IRQ_HANDLED;
  185. }
  186. static int tc3589x_gpio_probe(struct platform_device *pdev)
  187. {
  188. struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
  189. struct device_node *np = pdev->dev.of_node;
  190. struct tc3589x_gpio *tc3589x_gpio;
  191. int ret;
  192. int irq;
  193. if (!np) {
  194. dev_err(&pdev->dev, "No Device Tree node found\n");
  195. return -EINVAL;
  196. }
  197. irq = platform_get_irq(pdev, 0);
  198. if (irq < 0)
  199. return irq;
  200. tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
  201. GFP_KERNEL);
  202. if (!tc3589x_gpio)
  203. return -ENOMEM;
  204. mutex_init(&tc3589x_gpio->irq_lock);
  205. tc3589x_gpio->dev = &pdev->dev;
  206. tc3589x_gpio->tc3589x = tc3589x;
  207. tc3589x_gpio->chip = template_chip;
  208. tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
  209. tc3589x_gpio->chip.parent = &pdev->dev;
  210. tc3589x_gpio->chip.base = -1;
  211. tc3589x_gpio->chip.of_node = np;
  212. /* Bring the GPIO module out of reset */
  213. ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
  214. TC3589x_RSTCTRL_GPIRST, 0);
  215. if (ret < 0)
  216. return ret;
  217. ret = devm_request_threaded_irq(&pdev->dev,
  218. irq, NULL, tc3589x_gpio_irq,
  219. IRQF_ONESHOT, "tc3589x-gpio",
  220. tc3589x_gpio);
  221. if (ret) {
  222. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  223. return ret;
  224. }
  225. ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
  226. tc3589x_gpio);
  227. if (ret) {
  228. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  229. return ret;
  230. }
  231. ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
  232. &tc3589x_gpio_irq_chip,
  233. 0,
  234. handle_simple_irq,
  235. IRQ_TYPE_NONE);
  236. if (ret) {
  237. dev_err(&pdev->dev,
  238. "could not connect irqchip to gpiochip\n");
  239. return ret;
  240. }
  241. gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
  242. &tc3589x_gpio_irq_chip,
  243. irq,
  244. NULL);
  245. platform_set_drvdata(pdev, tc3589x_gpio);
  246. return 0;
  247. }
  248. static struct platform_driver tc3589x_gpio_driver = {
  249. .driver.name = "tc3589x-gpio",
  250. .driver.owner = THIS_MODULE,
  251. .probe = tc3589x_gpio_probe,
  252. };
  253. static int __init tc3589x_gpio_init(void)
  254. {
  255. return platform_driver_register(&tc3589x_gpio_driver);
  256. }
  257. subsys_initcall(tc3589x_gpio_init);
  258. static void __exit tc3589x_gpio_exit(void)
  259. {
  260. platform_driver_unregister(&tc3589x_gpio_driver);
  261. }
  262. module_exit(tc3589x_gpio_exit);
  263. MODULE_LICENSE("GPL v2");
  264. MODULE_DESCRIPTION("TC3589x GPIO driver");
  265. MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");