gpio-pca953x.c 21 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/acpi.h>
  22. #define PCA953X_INPUT 0
  23. #define PCA953X_OUTPUT 1
  24. #define PCA953X_INVERT 2
  25. #define PCA953X_DIRECTION 3
  26. #define REG_ADDR_AI 0x80
  27. #define PCA957X_IN 0
  28. #define PCA957X_INVRT 1
  29. #define PCA957X_BKEN 2
  30. #define PCA957X_PUPD 3
  31. #define PCA957X_CFG 4
  32. #define PCA957X_OUT 5
  33. #define PCA957X_MSK 6
  34. #define PCA957X_INTS 7
  35. #define PCA_GPIO_MASK 0x00FF
  36. #define PCA_INT 0x0100
  37. #define PCA953X_TYPE 0x1000
  38. #define PCA957X_TYPE 0x2000
  39. #define PCA_TYPE_MASK 0xF000
  40. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  41. static const struct i2c_device_id pca953x_id[] = {
  42. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  43. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  44. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  45. { "pca9536", 4 | PCA953X_TYPE, },
  46. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  47. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9556", 8 | PCA953X_TYPE, },
  52. { "pca9557", 8 | PCA953X_TYPE, },
  53. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  54. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  55. { "pca9698", 40 | PCA953X_TYPE, },
  56. { "max7310", 8 | PCA953X_TYPE, },
  57. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  59. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  60. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  61. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  62. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  64. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  65. { "xra1202", 8 | PCA953X_TYPE },
  66. { }
  67. };
  68. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  69. static const struct acpi_device_id pca953x_acpi_ids[] = {
  70. { "INT3491", 16 | PCA953X_TYPE | PCA_INT, },
  71. { }
  72. };
  73. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  74. #define MAX_BANK 5
  75. #define BANK_SZ 8
  76. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  77. struct pca953x_chip {
  78. unsigned gpio_start;
  79. u8 reg_output[MAX_BANK];
  80. u8 reg_direction[MAX_BANK];
  81. struct mutex i2c_lock;
  82. #ifdef CONFIG_GPIO_PCA953X_IRQ
  83. struct mutex irq_lock;
  84. u8 irq_mask[MAX_BANK];
  85. u8 irq_stat[MAX_BANK];
  86. u8 irq_trig_raise[MAX_BANK];
  87. u8 irq_trig_fall[MAX_BANK];
  88. #endif
  89. struct i2c_client *client;
  90. struct gpio_chip gpio_chip;
  91. const char *const *names;
  92. int chip_type;
  93. unsigned long driver_data;
  94. };
  95. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  96. int off)
  97. {
  98. int ret;
  99. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  100. int offset = off / BANK_SZ;
  101. ret = i2c_smbus_read_byte_data(chip->client,
  102. (reg << bank_shift) + offset);
  103. *val = ret;
  104. if (ret < 0) {
  105. dev_err(&chip->client->dev, "failed reading register\n");
  106. return ret;
  107. }
  108. return 0;
  109. }
  110. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  111. int off)
  112. {
  113. int ret = 0;
  114. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  115. int offset = off / BANK_SZ;
  116. ret = i2c_smbus_write_byte_data(chip->client,
  117. (reg << bank_shift) + offset, val);
  118. if (ret < 0) {
  119. dev_err(&chip->client->dev, "failed writing register\n");
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  125. {
  126. int ret = 0;
  127. if (chip->gpio_chip.ngpio <= 8)
  128. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  129. else if (chip->gpio_chip.ngpio >= 24) {
  130. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  131. ret = i2c_smbus_write_i2c_block_data(chip->client,
  132. (reg << bank_shift) | REG_ADDR_AI,
  133. NBANK(chip), val);
  134. } else {
  135. switch (chip->chip_type) {
  136. case PCA953X_TYPE:
  137. ret = i2c_smbus_write_word_data(chip->client,
  138. reg << 1, (u16) *val);
  139. break;
  140. case PCA957X_TYPE:
  141. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  142. val[0]);
  143. if (ret < 0)
  144. break;
  145. ret = i2c_smbus_write_byte_data(chip->client,
  146. (reg << 1) + 1,
  147. val[1]);
  148. break;
  149. }
  150. }
  151. if (ret < 0) {
  152. dev_err(&chip->client->dev, "failed writing register\n");
  153. return ret;
  154. }
  155. return 0;
  156. }
  157. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  158. {
  159. int ret;
  160. if (chip->gpio_chip.ngpio <= 8) {
  161. ret = i2c_smbus_read_byte_data(chip->client, reg);
  162. *val = ret;
  163. } else if (chip->gpio_chip.ngpio >= 24) {
  164. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  165. ret = i2c_smbus_read_i2c_block_data(chip->client,
  166. (reg << bank_shift) | REG_ADDR_AI,
  167. NBANK(chip), val);
  168. } else {
  169. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  170. val[0] = (u16)ret & 0xFF;
  171. val[1] = (u16)ret >> 8;
  172. }
  173. if (ret < 0) {
  174. dev_err(&chip->client->dev, "failed reading register\n");
  175. return ret;
  176. }
  177. return 0;
  178. }
  179. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  180. {
  181. struct pca953x_chip *chip = gpiochip_get_data(gc);
  182. u8 reg_val;
  183. int ret, offset = 0;
  184. mutex_lock(&chip->i2c_lock);
  185. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  186. switch (chip->chip_type) {
  187. case PCA953X_TYPE:
  188. offset = PCA953X_DIRECTION;
  189. break;
  190. case PCA957X_TYPE:
  191. offset = PCA957X_CFG;
  192. break;
  193. }
  194. ret = pca953x_write_single(chip, offset, reg_val, off);
  195. if (ret)
  196. goto exit;
  197. chip->reg_direction[off / BANK_SZ] = reg_val;
  198. ret = 0;
  199. exit:
  200. mutex_unlock(&chip->i2c_lock);
  201. return ret;
  202. }
  203. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  204. unsigned off, int val)
  205. {
  206. struct pca953x_chip *chip = gpiochip_get_data(gc);
  207. u8 reg_val;
  208. int ret, offset = 0;
  209. mutex_lock(&chip->i2c_lock);
  210. /* set output level */
  211. if (val)
  212. reg_val = chip->reg_output[off / BANK_SZ]
  213. | (1u << (off % BANK_SZ));
  214. else
  215. reg_val = chip->reg_output[off / BANK_SZ]
  216. & ~(1u << (off % BANK_SZ));
  217. switch (chip->chip_type) {
  218. case PCA953X_TYPE:
  219. offset = PCA953X_OUTPUT;
  220. break;
  221. case PCA957X_TYPE:
  222. offset = PCA957X_OUT;
  223. break;
  224. }
  225. ret = pca953x_write_single(chip, offset, reg_val, off);
  226. if (ret)
  227. goto exit;
  228. chip->reg_output[off / BANK_SZ] = reg_val;
  229. /* then direction */
  230. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  231. switch (chip->chip_type) {
  232. case PCA953X_TYPE:
  233. offset = PCA953X_DIRECTION;
  234. break;
  235. case PCA957X_TYPE:
  236. offset = PCA957X_CFG;
  237. break;
  238. }
  239. ret = pca953x_write_single(chip, offset, reg_val, off);
  240. if (ret)
  241. goto exit;
  242. chip->reg_direction[off / BANK_SZ] = reg_val;
  243. ret = 0;
  244. exit:
  245. mutex_unlock(&chip->i2c_lock);
  246. return ret;
  247. }
  248. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  249. {
  250. struct pca953x_chip *chip = gpiochip_get_data(gc);
  251. u32 reg_val;
  252. int ret, offset = 0;
  253. mutex_lock(&chip->i2c_lock);
  254. switch (chip->chip_type) {
  255. case PCA953X_TYPE:
  256. offset = PCA953X_INPUT;
  257. break;
  258. case PCA957X_TYPE:
  259. offset = PCA957X_IN;
  260. break;
  261. }
  262. ret = pca953x_read_single(chip, offset, &reg_val, off);
  263. mutex_unlock(&chip->i2c_lock);
  264. if (ret < 0) {
  265. /* NOTE: diagnostic already emitted; that's all we should
  266. * do unless gpio_*_value_cansleep() calls become different
  267. * from their nonsleeping siblings (and report faults).
  268. */
  269. return 0;
  270. }
  271. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  272. }
  273. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  274. {
  275. struct pca953x_chip *chip = gpiochip_get_data(gc);
  276. u8 reg_val;
  277. int ret, offset = 0;
  278. mutex_lock(&chip->i2c_lock);
  279. if (val)
  280. reg_val = chip->reg_output[off / BANK_SZ]
  281. | (1u << (off % BANK_SZ));
  282. else
  283. reg_val = chip->reg_output[off / BANK_SZ]
  284. & ~(1u << (off % BANK_SZ));
  285. switch (chip->chip_type) {
  286. case PCA953X_TYPE:
  287. offset = PCA953X_OUTPUT;
  288. break;
  289. case PCA957X_TYPE:
  290. offset = PCA957X_OUT;
  291. break;
  292. }
  293. ret = pca953x_write_single(chip, offset, reg_val, off);
  294. if (ret)
  295. goto exit;
  296. chip->reg_output[off / BANK_SZ] = reg_val;
  297. exit:
  298. mutex_unlock(&chip->i2c_lock);
  299. }
  300. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  301. unsigned long *mask, unsigned long *bits)
  302. {
  303. struct pca953x_chip *chip = gpiochip_get_data(gc);
  304. u8 reg_val[MAX_BANK];
  305. int ret, offset = 0;
  306. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  307. int bank;
  308. switch (chip->chip_type) {
  309. case PCA953X_TYPE:
  310. offset = PCA953X_OUTPUT;
  311. break;
  312. case PCA957X_TYPE:
  313. offset = PCA957X_OUT;
  314. break;
  315. }
  316. memcpy(reg_val, chip->reg_output, NBANK(chip));
  317. mutex_lock(&chip->i2c_lock);
  318. for(bank=0; bank<NBANK(chip); bank++) {
  319. unsigned bankmask = mask[bank / sizeof(*mask)] >>
  320. ((bank % sizeof(*mask)) * 8);
  321. if(bankmask) {
  322. unsigned bankval = bits[bank / sizeof(*bits)] >>
  323. ((bank % sizeof(*bits)) * 8);
  324. reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
  325. }
  326. }
  327. ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
  328. if (ret)
  329. goto exit;
  330. memcpy(chip->reg_output, reg_val, NBANK(chip));
  331. exit:
  332. mutex_unlock(&chip->i2c_lock);
  333. }
  334. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  335. {
  336. struct gpio_chip *gc;
  337. gc = &chip->gpio_chip;
  338. gc->direction_input = pca953x_gpio_direction_input;
  339. gc->direction_output = pca953x_gpio_direction_output;
  340. gc->get = pca953x_gpio_get_value;
  341. gc->set = pca953x_gpio_set_value;
  342. gc->set_multiple = pca953x_gpio_set_multiple;
  343. gc->can_sleep = true;
  344. gc->base = chip->gpio_start;
  345. gc->ngpio = gpios;
  346. gc->label = chip->client->name;
  347. gc->parent = &chip->client->dev;
  348. gc->owner = THIS_MODULE;
  349. gc->names = chip->names;
  350. }
  351. #ifdef CONFIG_GPIO_PCA953X_IRQ
  352. static void pca953x_irq_mask(struct irq_data *d)
  353. {
  354. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  355. struct pca953x_chip *chip = gpiochip_get_data(gc);
  356. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  357. }
  358. static void pca953x_irq_unmask(struct irq_data *d)
  359. {
  360. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  361. struct pca953x_chip *chip = gpiochip_get_data(gc);
  362. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  363. }
  364. static void pca953x_irq_bus_lock(struct irq_data *d)
  365. {
  366. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  367. struct pca953x_chip *chip = gpiochip_get_data(gc);
  368. mutex_lock(&chip->irq_lock);
  369. }
  370. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  371. {
  372. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  373. struct pca953x_chip *chip = gpiochip_get_data(gc);
  374. u8 new_irqs;
  375. int level, i;
  376. /* Look for any newly setup interrupt */
  377. for (i = 0; i < NBANK(chip); i++) {
  378. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  379. new_irqs &= ~chip->reg_direction[i];
  380. while (new_irqs) {
  381. level = __ffs(new_irqs);
  382. pca953x_gpio_direction_input(&chip->gpio_chip,
  383. level + (BANK_SZ * i));
  384. new_irqs &= ~(1 << level);
  385. }
  386. }
  387. mutex_unlock(&chip->irq_lock);
  388. }
  389. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  390. {
  391. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  392. struct pca953x_chip *chip = gpiochip_get_data(gc);
  393. int bank_nb = d->hwirq / BANK_SZ;
  394. u8 mask = 1 << (d->hwirq % BANK_SZ);
  395. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  396. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  397. d->irq, type);
  398. return -EINVAL;
  399. }
  400. if (type & IRQ_TYPE_EDGE_FALLING)
  401. chip->irq_trig_fall[bank_nb] |= mask;
  402. else
  403. chip->irq_trig_fall[bank_nb] &= ~mask;
  404. if (type & IRQ_TYPE_EDGE_RISING)
  405. chip->irq_trig_raise[bank_nb] |= mask;
  406. else
  407. chip->irq_trig_raise[bank_nb] &= ~mask;
  408. return 0;
  409. }
  410. static struct irq_chip pca953x_irq_chip = {
  411. .name = "pca953x",
  412. .irq_mask = pca953x_irq_mask,
  413. .irq_unmask = pca953x_irq_unmask,
  414. .irq_bus_lock = pca953x_irq_bus_lock,
  415. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  416. .irq_set_type = pca953x_irq_set_type,
  417. };
  418. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  419. {
  420. u8 cur_stat[MAX_BANK];
  421. u8 old_stat[MAX_BANK];
  422. bool pending_seen = false;
  423. bool trigger_seen = false;
  424. u8 trigger[MAX_BANK];
  425. int ret, i, offset = 0;
  426. switch (chip->chip_type) {
  427. case PCA953X_TYPE:
  428. offset = PCA953X_INPUT;
  429. break;
  430. case PCA957X_TYPE:
  431. offset = PCA957X_IN;
  432. break;
  433. }
  434. ret = pca953x_read_regs(chip, offset, cur_stat);
  435. if (ret)
  436. return false;
  437. /* Remove output pins from the equation */
  438. for (i = 0; i < NBANK(chip); i++)
  439. cur_stat[i] &= chip->reg_direction[i];
  440. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  441. for (i = 0; i < NBANK(chip); i++) {
  442. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  443. if (trigger[i])
  444. trigger_seen = true;
  445. }
  446. if (!trigger_seen)
  447. return false;
  448. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  449. for (i = 0; i < NBANK(chip); i++) {
  450. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  451. (cur_stat[i] & chip->irq_trig_raise[i]);
  452. pending[i] &= trigger[i];
  453. if (pending[i])
  454. pending_seen = true;
  455. }
  456. return pending_seen;
  457. }
  458. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  459. {
  460. struct pca953x_chip *chip = devid;
  461. u8 pending[MAX_BANK];
  462. u8 level;
  463. unsigned nhandled = 0;
  464. int i;
  465. if (!pca953x_irq_pending(chip, pending))
  466. return IRQ_NONE;
  467. for (i = 0; i < NBANK(chip); i++) {
  468. while (pending[i]) {
  469. level = __ffs(pending[i]);
  470. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  471. level + (BANK_SZ * i)));
  472. pending[i] &= ~(1 << level);
  473. nhandled++;
  474. }
  475. }
  476. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  477. }
  478. static int pca953x_irq_setup(struct pca953x_chip *chip,
  479. int irq_base)
  480. {
  481. struct i2c_client *client = chip->client;
  482. int ret, i, offset = 0;
  483. if (client->irq && irq_base != -1
  484. && (chip->driver_data & PCA_INT)) {
  485. switch (chip->chip_type) {
  486. case PCA953X_TYPE:
  487. offset = PCA953X_INPUT;
  488. break;
  489. case PCA957X_TYPE:
  490. offset = PCA957X_IN;
  491. break;
  492. }
  493. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  494. if (ret)
  495. return ret;
  496. /*
  497. * There is no way to know which GPIO line generated the
  498. * interrupt. We have to rely on the previous read for
  499. * this purpose.
  500. */
  501. for (i = 0; i < NBANK(chip); i++)
  502. chip->irq_stat[i] &= chip->reg_direction[i];
  503. mutex_init(&chip->irq_lock);
  504. ret = devm_request_threaded_irq(&client->dev,
  505. client->irq,
  506. NULL,
  507. pca953x_irq_handler,
  508. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  509. IRQF_SHARED,
  510. dev_name(&client->dev), chip);
  511. if (ret) {
  512. dev_err(&client->dev, "failed to request irq %d\n",
  513. client->irq);
  514. return ret;
  515. }
  516. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  517. &pca953x_irq_chip,
  518. irq_base,
  519. handle_simple_irq,
  520. IRQ_TYPE_NONE);
  521. if (ret) {
  522. dev_err(&client->dev,
  523. "could not connect irqchip to gpiochip\n");
  524. return ret;
  525. }
  526. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  527. &pca953x_irq_chip,
  528. client->irq, NULL);
  529. }
  530. return 0;
  531. }
  532. #else /* CONFIG_GPIO_PCA953X_IRQ */
  533. static int pca953x_irq_setup(struct pca953x_chip *chip,
  534. int irq_base)
  535. {
  536. struct i2c_client *client = chip->client;
  537. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  538. dev_warn(&client->dev, "interrupt support not compiled in\n");
  539. return 0;
  540. }
  541. #endif
  542. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  543. {
  544. int ret;
  545. u8 val[MAX_BANK];
  546. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  547. if (ret)
  548. goto out;
  549. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  550. chip->reg_direction);
  551. if (ret)
  552. goto out;
  553. /* set platform specific polarity inversion */
  554. if (invert)
  555. memset(val, 0xFF, NBANK(chip));
  556. else
  557. memset(val, 0, NBANK(chip));
  558. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  559. out:
  560. return ret;
  561. }
  562. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  563. {
  564. int ret;
  565. u8 val[MAX_BANK];
  566. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  567. if (ret)
  568. goto out;
  569. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  570. if (ret)
  571. goto out;
  572. /* set platform specific polarity inversion */
  573. if (invert)
  574. memset(val, 0xFF, NBANK(chip));
  575. else
  576. memset(val, 0, NBANK(chip));
  577. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  578. if (ret)
  579. goto out;
  580. /* To enable register 6, 7 to control pull up and pull down */
  581. memset(val, 0x02, NBANK(chip));
  582. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  583. if (ret)
  584. goto out;
  585. return 0;
  586. out:
  587. return ret;
  588. }
  589. static const struct of_device_id pca953x_dt_ids[];
  590. static int pca953x_probe(struct i2c_client *client,
  591. const struct i2c_device_id *id)
  592. {
  593. struct pca953x_platform_data *pdata;
  594. struct pca953x_chip *chip;
  595. int irq_base = 0;
  596. int ret;
  597. u32 invert = 0;
  598. chip = devm_kzalloc(&client->dev,
  599. sizeof(struct pca953x_chip), GFP_KERNEL);
  600. if (chip == NULL)
  601. return -ENOMEM;
  602. pdata = dev_get_platdata(&client->dev);
  603. if (pdata) {
  604. irq_base = pdata->irq_base;
  605. chip->gpio_start = pdata->gpio_base;
  606. invert = pdata->invert;
  607. chip->names = pdata->names;
  608. } else {
  609. chip->gpio_start = -1;
  610. irq_base = 0;
  611. }
  612. chip->client = client;
  613. if (id) {
  614. chip->driver_data = id->driver_data;
  615. } else {
  616. const struct acpi_device_id *id;
  617. const struct of_device_id *match;
  618. match = of_match_device(pca953x_dt_ids, &client->dev);
  619. if (match) {
  620. chip->driver_data = (int)(uintptr_t)match->data;
  621. } else {
  622. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  623. if (!id)
  624. return -ENODEV;
  625. chip->driver_data = id->driver_data;
  626. }
  627. }
  628. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  629. mutex_init(&chip->i2c_lock);
  630. /* initialize cached registers from their original values.
  631. * we can't share this chip with another i2c master.
  632. */
  633. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  634. if (chip->chip_type == PCA953X_TYPE)
  635. ret = device_pca953x_init(chip, invert);
  636. else
  637. ret = device_pca957x_init(chip, invert);
  638. if (ret)
  639. return ret;
  640. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  641. if (ret)
  642. return ret;
  643. ret = pca953x_irq_setup(chip, irq_base);
  644. if (ret)
  645. return ret;
  646. if (pdata && pdata->setup) {
  647. ret = pdata->setup(client, chip->gpio_chip.base,
  648. chip->gpio_chip.ngpio, pdata->context);
  649. if (ret < 0)
  650. dev_warn(&client->dev, "setup failed, %d\n", ret);
  651. }
  652. i2c_set_clientdata(client, chip);
  653. return 0;
  654. }
  655. static int pca953x_remove(struct i2c_client *client)
  656. {
  657. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  658. struct pca953x_chip *chip = i2c_get_clientdata(client);
  659. int ret = 0;
  660. if (pdata && pdata->teardown) {
  661. ret = pdata->teardown(client, chip->gpio_chip.base,
  662. chip->gpio_chip.ngpio, pdata->context);
  663. if (ret < 0) {
  664. dev_err(&client->dev, "%s failed, %d\n",
  665. "teardown", ret);
  666. return ret;
  667. }
  668. }
  669. return 0;
  670. }
  671. /* convenience to stop overlong match-table lines */
  672. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  673. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  674. static const struct of_device_id pca953x_dt_ids[] = {
  675. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  676. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  677. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  678. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  679. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  680. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  681. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  682. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  683. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  684. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  685. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  686. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  687. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  688. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  689. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  690. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  691. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  692. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  693. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  694. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  695. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  696. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  697. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  698. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  699. { }
  700. };
  701. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  702. static struct i2c_driver pca953x_driver = {
  703. .driver = {
  704. .name = "pca953x",
  705. .of_match_table = pca953x_dt_ids,
  706. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  707. },
  708. .probe = pca953x_probe,
  709. .remove = pca953x_remove,
  710. .id_table = pca953x_id,
  711. };
  712. static int __init pca953x_init(void)
  713. {
  714. return i2c_add_driver(&pca953x_driver);
  715. }
  716. /* register after i2c postcore initcall and before
  717. * subsys initcalls that may rely on these GPIOs
  718. */
  719. subsys_initcall(pca953x_init);
  720. static void __exit pca953x_exit(void)
  721. {
  722. i2c_del_driver(&pca953x_driver);
  723. }
  724. module_exit(pca953x_exit);
  725. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  726. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  727. MODULE_LICENSE("GPL");