gpio-mcp23s08.c 25 KB

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  1. /*
  2. * MCP23S08 SPI/I2C GPIO gpio expander driver
  3. *
  4. * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
  5. * supported.
  6. * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
  7. * interrupts is also supported.
  8. * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
  9. * also capable of generating interrupts, but the linux driver does not
  10. * support that yet.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/device.h>
  14. #include <linux/mutex.h>
  15. #include <linux/module.h>
  16. #include <linux/gpio.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/mcp23s08.h>
  20. #include <linux/slab.h>
  21. #include <asm/byteorder.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/of_device.h>
  25. /**
  26. * MCP types supported by driver
  27. */
  28. #define MCP_TYPE_S08 0
  29. #define MCP_TYPE_S17 1
  30. #define MCP_TYPE_008 2
  31. #define MCP_TYPE_017 3
  32. #define MCP_TYPE_S18 4
  33. /* Registers are all 8 bits wide.
  34. *
  35. * The mcp23s17 has twice as many bits, and can be configured to work
  36. * with either 16 bit registers or with two adjacent 8 bit banks.
  37. */
  38. #define MCP_IODIR 0x00 /* init/reset: all ones */
  39. #define MCP_IPOL 0x01
  40. #define MCP_GPINTEN 0x02
  41. #define MCP_DEFVAL 0x03
  42. #define MCP_INTCON 0x04
  43. #define MCP_IOCON 0x05
  44. # define IOCON_MIRROR (1 << 6)
  45. # define IOCON_SEQOP (1 << 5)
  46. # define IOCON_HAEN (1 << 3)
  47. # define IOCON_ODR (1 << 2)
  48. # define IOCON_INTPOL (1 << 1)
  49. # define IOCON_INTCC (1)
  50. #define MCP_GPPU 0x06
  51. #define MCP_INTF 0x07
  52. #define MCP_INTCAP 0x08
  53. #define MCP_GPIO 0x09
  54. #define MCP_OLAT 0x0a
  55. struct mcp23s08;
  56. struct mcp23s08_ops {
  57. int (*read)(struct mcp23s08 *mcp, unsigned reg);
  58. int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
  59. int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
  60. u16 *vals, unsigned n);
  61. };
  62. struct mcp23s08 {
  63. u8 addr;
  64. bool irq_active_high;
  65. u16 cache[11];
  66. u16 irq_rise;
  67. u16 irq_fall;
  68. int irq;
  69. bool irq_controller;
  70. /* lock protects the cached values */
  71. struct mutex lock;
  72. struct mutex irq_lock;
  73. struct irq_domain *irq_domain;
  74. struct gpio_chip chip;
  75. const struct mcp23s08_ops *ops;
  76. void *data; /* ops specific data */
  77. };
  78. /* A given spi_device can represent up to eight mcp23sxx chips
  79. * sharing the same chipselect but using different addresses
  80. * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
  81. * Driver data holds all the per-chip data.
  82. */
  83. struct mcp23s08_driver_data {
  84. unsigned ngpio;
  85. struct mcp23s08 *mcp[8];
  86. struct mcp23s08 chip[];
  87. };
  88. /* This lock class tells lockdep that GPIO irqs are in a different
  89. * category than their parents, so it won't report false recursion.
  90. */
  91. static struct lock_class_key gpio_lock_class;
  92. /*----------------------------------------------------------------------*/
  93. #if IS_ENABLED(CONFIG_I2C)
  94. static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
  95. {
  96. return i2c_smbus_read_byte_data(mcp->data, reg);
  97. }
  98. static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  99. {
  100. return i2c_smbus_write_byte_data(mcp->data, reg, val);
  101. }
  102. static int
  103. mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  104. {
  105. while (n--) {
  106. int ret = mcp23008_read(mcp, reg++);
  107. if (ret < 0)
  108. return ret;
  109. *vals++ = ret;
  110. }
  111. return 0;
  112. }
  113. static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
  114. {
  115. return i2c_smbus_read_word_data(mcp->data, reg << 1);
  116. }
  117. static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  118. {
  119. return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
  120. }
  121. static int
  122. mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  123. {
  124. while (n--) {
  125. int ret = mcp23017_read(mcp, reg++);
  126. if (ret < 0)
  127. return ret;
  128. *vals++ = ret;
  129. }
  130. return 0;
  131. }
  132. static const struct mcp23s08_ops mcp23008_ops = {
  133. .read = mcp23008_read,
  134. .write = mcp23008_write,
  135. .read_regs = mcp23008_read_regs,
  136. };
  137. static const struct mcp23s08_ops mcp23017_ops = {
  138. .read = mcp23017_read,
  139. .write = mcp23017_write,
  140. .read_regs = mcp23017_read_regs,
  141. };
  142. #endif /* CONFIG_I2C */
  143. /*----------------------------------------------------------------------*/
  144. #ifdef CONFIG_SPI_MASTER
  145. static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
  146. {
  147. u8 tx[2], rx[1];
  148. int status;
  149. tx[0] = mcp->addr | 0x01;
  150. tx[1] = reg;
  151. status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
  152. return (status < 0) ? status : rx[0];
  153. }
  154. static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  155. {
  156. u8 tx[3];
  157. tx[0] = mcp->addr;
  158. tx[1] = reg;
  159. tx[2] = val;
  160. return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
  161. }
  162. static int
  163. mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  164. {
  165. u8 tx[2], *tmp;
  166. int status;
  167. if ((n + reg) > sizeof(mcp->cache))
  168. return -EINVAL;
  169. tx[0] = mcp->addr | 0x01;
  170. tx[1] = reg;
  171. tmp = (u8 *)vals;
  172. status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
  173. if (status >= 0) {
  174. while (n--)
  175. vals[n] = tmp[n]; /* expand to 16bit */
  176. }
  177. return status;
  178. }
  179. static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
  180. {
  181. u8 tx[2], rx[2];
  182. int status;
  183. tx[0] = mcp->addr | 0x01;
  184. tx[1] = reg << 1;
  185. status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
  186. return (status < 0) ? status : (rx[0] | (rx[1] << 8));
  187. }
  188. static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  189. {
  190. u8 tx[4];
  191. tx[0] = mcp->addr;
  192. tx[1] = reg << 1;
  193. tx[2] = val;
  194. tx[3] = val >> 8;
  195. return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
  196. }
  197. static int
  198. mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  199. {
  200. u8 tx[2];
  201. int status;
  202. if ((n + reg) > sizeof(mcp->cache))
  203. return -EINVAL;
  204. tx[0] = mcp->addr | 0x01;
  205. tx[1] = reg << 1;
  206. status = spi_write_then_read(mcp->data, tx, sizeof(tx),
  207. (u8 *)vals, n * 2);
  208. if (status >= 0) {
  209. while (n--)
  210. vals[n] = __le16_to_cpu((__le16)vals[n]);
  211. }
  212. return status;
  213. }
  214. static const struct mcp23s08_ops mcp23s08_ops = {
  215. .read = mcp23s08_read,
  216. .write = mcp23s08_write,
  217. .read_regs = mcp23s08_read_regs,
  218. };
  219. static const struct mcp23s08_ops mcp23s17_ops = {
  220. .read = mcp23s17_read,
  221. .write = mcp23s17_write,
  222. .read_regs = mcp23s17_read_regs,
  223. };
  224. #endif /* CONFIG_SPI_MASTER */
  225. /*----------------------------------------------------------------------*/
  226. static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
  227. {
  228. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  229. int status;
  230. mutex_lock(&mcp->lock);
  231. mcp->cache[MCP_IODIR] |= (1 << offset);
  232. status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
  233. mutex_unlock(&mcp->lock);
  234. return status;
  235. }
  236. static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
  237. {
  238. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  239. int status;
  240. mutex_lock(&mcp->lock);
  241. /* REVISIT reading this clears any IRQ ... */
  242. status = mcp->ops->read(mcp, MCP_GPIO);
  243. if (status < 0)
  244. status = 0;
  245. else {
  246. mcp->cache[MCP_GPIO] = status;
  247. status = !!(status & (1 << offset));
  248. }
  249. mutex_unlock(&mcp->lock);
  250. return status;
  251. }
  252. static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
  253. {
  254. unsigned olat = mcp->cache[MCP_OLAT];
  255. if (value)
  256. olat |= mask;
  257. else
  258. olat &= ~mask;
  259. mcp->cache[MCP_OLAT] = olat;
  260. return mcp->ops->write(mcp, MCP_OLAT, olat);
  261. }
  262. static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
  263. {
  264. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  265. unsigned mask = 1 << offset;
  266. mutex_lock(&mcp->lock);
  267. __mcp23s08_set(mcp, mask, value);
  268. mutex_unlock(&mcp->lock);
  269. }
  270. static int
  271. mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  272. {
  273. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  274. unsigned mask = 1 << offset;
  275. int status;
  276. mutex_lock(&mcp->lock);
  277. status = __mcp23s08_set(mcp, mask, value);
  278. if (status == 0) {
  279. mcp->cache[MCP_IODIR] &= ~mask;
  280. status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
  281. }
  282. mutex_unlock(&mcp->lock);
  283. return status;
  284. }
  285. /*----------------------------------------------------------------------*/
  286. static irqreturn_t mcp23s08_irq(int irq, void *data)
  287. {
  288. struct mcp23s08 *mcp = data;
  289. int intcap, intf, i;
  290. unsigned int child_irq;
  291. mutex_lock(&mcp->lock);
  292. intf = mcp->ops->read(mcp, MCP_INTF);
  293. if (intf < 0) {
  294. mutex_unlock(&mcp->lock);
  295. return IRQ_HANDLED;
  296. }
  297. mcp->cache[MCP_INTF] = intf;
  298. intcap = mcp->ops->read(mcp, MCP_INTCAP);
  299. if (intcap < 0) {
  300. mutex_unlock(&mcp->lock);
  301. return IRQ_HANDLED;
  302. }
  303. mcp->cache[MCP_INTCAP] = intcap;
  304. mutex_unlock(&mcp->lock);
  305. for (i = 0; i < mcp->chip.ngpio; i++) {
  306. if ((BIT(i) & mcp->cache[MCP_INTF]) &&
  307. ((BIT(i) & intcap & mcp->irq_rise) ||
  308. (mcp->irq_fall & ~intcap & BIT(i)))) {
  309. child_irq = irq_find_mapping(mcp->irq_domain, i);
  310. handle_nested_irq(child_irq);
  311. }
  312. }
  313. return IRQ_HANDLED;
  314. }
  315. static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  316. {
  317. struct mcp23s08 *mcp = gpiochip_get_data(chip);
  318. return irq_find_mapping(mcp->irq_domain, offset);
  319. }
  320. static void mcp23s08_irq_mask(struct irq_data *data)
  321. {
  322. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  323. unsigned int pos = data->hwirq;
  324. mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
  325. }
  326. static void mcp23s08_irq_unmask(struct irq_data *data)
  327. {
  328. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  329. unsigned int pos = data->hwirq;
  330. mcp->cache[MCP_GPINTEN] |= BIT(pos);
  331. }
  332. static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
  333. {
  334. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  335. unsigned int pos = data->hwirq;
  336. int status = 0;
  337. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  338. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  339. mcp->irq_rise |= BIT(pos);
  340. mcp->irq_fall |= BIT(pos);
  341. } else if (type & IRQ_TYPE_EDGE_RISING) {
  342. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  343. mcp->irq_rise |= BIT(pos);
  344. mcp->irq_fall &= ~BIT(pos);
  345. } else if (type & IRQ_TYPE_EDGE_FALLING) {
  346. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  347. mcp->irq_rise &= ~BIT(pos);
  348. mcp->irq_fall |= BIT(pos);
  349. } else
  350. return -EINVAL;
  351. return status;
  352. }
  353. static void mcp23s08_irq_bus_lock(struct irq_data *data)
  354. {
  355. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  356. mutex_lock(&mcp->irq_lock);
  357. }
  358. static void mcp23s08_irq_bus_unlock(struct irq_data *data)
  359. {
  360. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  361. mutex_lock(&mcp->lock);
  362. mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
  363. mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
  364. mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
  365. mutex_unlock(&mcp->lock);
  366. mutex_unlock(&mcp->irq_lock);
  367. }
  368. static int mcp23s08_irq_reqres(struct irq_data *data)
  369. {
  370. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  371. if (gpiochip_lock_as_irq(&mcp->chip, data->hwirq)) {
  372. dev_err(mcp->chip.parent,
  373. "unable to lock HW IRQ %lu for IRQ usage\n",
  374. data->hwirq);
  375. return -EINVAL;
  376. }
  377. return 0;
  378. }
  379. static void mcp23s08_irq_relres(struct irq_data *data)
  380. {
  381. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  382. gpiochip_unlock_as_irq(&mcp->chip, data->hwirq);
  383. }
  384. static struct irq_chip mcp23s08_irq_chip = {
  385. .name = "gpio-mcp23xxx",
  386. .irq_mask = mcp23s08_irq_mask,
  387. .irq_unmask = mcp23s08_irq_unmask,
  388. .irq_set_type = mcp23s08_irq_set_type,
  389. .irq_bus_lock = mcp23s08_irq_bus_lock,
  390. .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
  391. .irq_request_resources = mcp23s08_irq_reqres,
  392. .irq_release_resources = mcp23s08_irq_relres,
  393. };
  394. static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
  395. {
  396. struct gpio_chip *chip = &mcp->chip;
  397. int err, irq, j;
  398. unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
  399. mutex_init(&mcp->irq_lock);
  400. mcp->irq_domain = irq_domain_add_linear(chip->parent->of_node,
  401. chip->ngpio,
  402. &irq_domain_simple_ops, mcp);
  403. if (!mcp->irq_domain)
  404. return -ENODEV;
  405. if (mcp->irq_active_high)
  406. irqflags |= IRQF_TRIGGER_HIGH;
  407. else
  408. irqflags |= IRQF_TRIGGER_LOW;
  409. err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
  410. mcp23s08_irq,
  411. irqflags, dev_name(chip->parent), mcp);
  412. if (err != 0) {
  413. dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
  414. mcp->irq, err);
  415. return err;
  416. }
  417. chip->to_irq = mcp23s08_gpio_to_irq;
  418. for (j = 0; j < mcp->chip.ngpio; j++) {
  419. irq = irq_create_mapping(mcp->irq_domain, j);
  420. irq_set_lockdep_class(irq, &gpio_lock_class);
  421. irq_set_chip_data(irq, mcp);
  422. irq_set_chip(irq, &mcp23s08_irq_chip);
  423. irq_set_nested_thread(irq, true);
  424. irq_set_noprobe(irq);
  425. }
  426. return 0;
  427. }
  428. static void mcp23s08_irq_teardown(struct mcp23s08 *mcp)
  429. {
  430. unsigned int irq, i;
  431. for (i = 0; i < mcp->chip.ngpio; i++) {
  432. irq = irq_find_mapping(mcp->irq_domain, i);
  433. if (irq > 0)
  434. irq_dispose_mapping(irq);
  435. }
  436. irq_domain_remove(mcp->irq_domain);
  437. }
  438. /*----------------------------------------------------------------------*/
  439. #ifdef CONFIG_DEBUG_FS
  440. #include <linux/seq_file.h>
  441. /*
  442. * This shows more info than the generic gpio dump code:
  443. * pullups, deglitching, open drain drive.
  444. */
  445. static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  446. {
  447. struct mcp23s08 *mcp;
  448. char bank;
  449. int t;
  450. unsigned mask;
  451. mcp = gpiochip_get_data(chip);
  452. /* NOTE: we only handle one bank for now ... */
  453. bank = '0' + ((mcp->addr >> 1) & 0x7);
  454. mutex_lock(&mcp->lock);
  455. t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
  456. if (t < 0) {
  457. seq_printf(s, " I/O ERROR %d\n", t);
  458. goto done;
  459. }
  460. for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
  461. const char *label;
  462. label = gpiochip_is_requested(chip, t);
  463. if (!label)
  464. continue;
  465. seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
  466. chip->base + t, bank, t, label,
  467. (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
  468. (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
  469. (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
  470. /* NOTE: ignoring the irq-related registers */
  471. seq_puts(s, "\n");
  472. }
  473. done:
  474. mutex_unlock(&mcp->lock);
  475. }
  476. #else
  477. #define mcp23s08_dbg_show NULL
  478. #endif
  479. /*----------------------------------------------------------------------*/
  480. static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
  481. void *data, unsigned addr, unsigned type,
  482. struct mcp23s08_platform_data *pdata, int cs)
  483. {
  484. int status;
  485. bool mirror = false;
  486. mutex_init(&mcp->lock);
  487. mcp->data = data;
  488. mcp->addr = addr;
  489. mcp->irq_active_high = false;
  490. mcp->chip.direction_input = mcp23s08_direction_input;
  491. mcp->chip.get = mcp23s08_get;
  492. mcp->chip.direction_output = mcp23s08_direction_output;
  493. mcp->chip.set = mcp23s08_set;
  494. mcp->chip.dbg_show = mcp23s08_dbg_show;
  495. #ifdef CONFIG_OF
  496. mcp->chip.of_gpio_n_cells = 2;
  497. mcp->chip.of_node = dev->of_node;
  498. #endif
  499. switch (type) {
  500. #ifdef CONFIG_SPI_MASTER
  501. case MCP_TYPE_S08:
  502. mcp->ops = &mcp23s08_ops;
  503. mcp->chip.ngpio = 8;
  504. mcp->chip.label = "mcp23s08";
  505. break;
  506. case MCP_TYPE_S17:
  507. mcp->ops = &mcp23s17_ops;
  508. mcp->chip.ngpio = 16;
  509. mcp->chip.label = "mcp23s17";
  510. break;
  511. case MCP_TYPE_S18:
  512. mcp->ops = &mcp23s17_ops;
  513. mcp->chip.ngpio = 16;
  514. mcp->chip.label = "mcp23s18";
  515. break;
  516. #endif /* CONFIG_SPI_MASTER */
  517. #if IS_ENABLED(CONFIG_I2C)
  518. case MCP_TYPE_008:
  519. mcp->ops = &mcp23008_ops;
  520. mcp->chip.ngpio = 8;
  521. mcp->chip.label = "mcp23008";
  522. break;
  523. case MCP_TYPE_017:
  524. mcp->ops = &mcp23017_ops;
  525. mcp->chip.ngpio = 16;
  526. mcp->chip.label = "mcp23017";
  527. break;
  528. #endif /* CONFIG_I2C */
  529. default:
  530. dev_err(dev, "invalid device type (%d)\n", type);
  531. return -EINVAL;
  532. }
  533. mcp->chip.base = pdata->base;
  534. mcp->chip.can_sleep = true;
  535. mcp->chip.parent = dev;
  536. mcp->chip.owner = THIS_MODULE;
  537. /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
  538. * and MCP_IOCON.HAEN = 1, so we work with all chips.
  539. */
  540. status = mcp->ops->read(mcp, MCP_IOCON);
  541. if (status < 0)
  542. goto fail;
  543. mcp->irq_controller = pdata->irq_controller;
  544. if (mcp->irq && mcp->irq_controller) {
  545. mcp->irq_active_high =
  546. of_property_read_bool(mcp->chip.parent->of_node,
  547. "microchip,irq-active-high");
  548. mirror = pdata->mirror;
  549. }
  550. if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
  551. mcp->irq_active_high) {
  552. /* mcp23s17 has IOCON twice, make sure they are in sync */
  553. status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
  554. status |= IOCON_HAEN | (IOCON_HAEN << 8);
  555. if (mcp->irq_active_high)
  556. status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
  557. else
  558. status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
  559. if (mirror)
  560. status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
  561. if (type == MCP_TYPE_S18)
  562. status |= IOCON_INTCC | (IOCON_INTCC << 8);
  563. status = mcp->ops->write(mcp, MCP_IOCON, status);
  564. if (status < 0)
  565. goto fail;
  566. }
  567. /* configure ~100K pullups */
  568. status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
  569. if (status < 0)
  570. goto fail;
  571. status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
  572. if (status < 0)
  573. goto fail;
  574. /* disable inverter on input */
  575. if (mcp->cache[MCP_IPOL] != 0) {
  576. mcp->cache[MCP_IPOL] = 0;
  577. status = mcp->ops->write(mcp, MCP_IPOL, 0);
  578. if (status < 0)
  579. goto fail;
  580. }
  581. /* disable irqs */
  582. if (mcp->cache[MCP_GPINTEN] != 0) {
  583. mcp->cache[MCP_GPINTEN] = 0;
  584. status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
  585. if (status < 0)
  586. goto fail;
  587. }
  588. status = gpiochip_add_data(&mcp->chip, mcp);
  589. if (status < 0)
  590. goto fail;
  591. if (mcp->irq && mcp->irq_controller) {
  592. status = mcp23s08_irq_setup(mcp);
  593. if (status) {
  594. mcp23s08_irq_teardown(mcp);
  595. goto fail;
  596. }
  597. }
  598. fail:
  599. if (status < 0)
  600. dev_dbg(dev, "can't setup chip %d, --> %d\n",
  601. addr, status);
  602. return status;
  603. }
  604. /*----------------------------------------------------------------------*/
  605. #ifdef CONFIG_OF
  606. #ifdef CONFIG_SPI_MASTER
  607. static const struct of_device_id mcp23s08_spi_of_match[] = {
  608. {
  609. .compatible = "microchip,mcp23s08",
  610. .data = (void *) MCP_TYPE_S08,
  611. },
  612. {
  613. .compatible = "microchip,mcp23s17",
  614. .data = (void *) MCP_TYPE_S17,
  615. },
  616. {
  617. .compatible = "microchip,mcp23s18",
  618. .data = (void *) MCP_TYPE_S18,
  619. },
  620. /* NOTE: The use of the mcp prefix is deprecated and will be removed. */
  621. {
  622. .compatible = "mcp,mcp23s08",
  623. .data = (void *) MCP_TYPE_S08,
  624. },
  625. {
  626. .compatible = "mcp,mcp23s17",
  627. .data = (void *) MCP_TYPE_S17,
  628. },
  629. { },
  630. };
  631. MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
  632. #endif
  633. #if IS_ENABLED(CONFIG_I2C)
  634. static const struct of_device_id mcp23s08_i2c_of_match[] = {
  635. {
  636. .compatible = "microchip,mcp23008",
  637. .data = (void *) MCP_TYPE_008,
  638. },
  639. {
  640. .compatible = "microchip,mcp23017",
  641. .data = (void *) MCP_TYPE_017,
  642. },
  643. /* NOTE: The use of the mcp prefix is deprecated and will be removed. */
  644. {
  645. .compatible = "mcp,mcp23008",
  646. .data = (void *) MCP_TYPE_008,
  647. },
  648. {
  649. .compatible = "mcp,mcp23017",
  650. .data = (void *) MCP_TYPE_017,
  651. },
  652. { },
  653. };
  654. MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
  655. #endif
  656. #endif /* CONFIG_OF */
  657. #if IS_ENABLED(CONFIG_I2C)
  658. static int mcp230xx_probe(struct i2c_client *client,
  659. const struct i2c_device_id *id)
  660. {
  661. struct mcp23s08_platform_data *pdata, local_pdata;
  662. struct mcp23s08 *mcp;
  663. int status;
  664. const struct of_device_id *match;
  665. match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
  666. &client->dev);
  667. if (match) {
  668. pdata = &local_pdata;
  669. pdata->base = -1;
  670. pdata->chip[0].pullups = 0;
  671. pdata->irq_controller = of_property_read_bool(
  672. client->dev.of_node,
  673. "interrupt-controller");
  674. pdata->mirror = of_property_read_bool(client->dev.of_node,
  675. "microchip,irq-mirror");
  676. client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
  677. } else {
  678. pdata = dev_get_platdata(&client->dev);
  679. if (!pdata) {
  680. pdata = devm_kzalloc(&client->dev,
  681. sizeof(struct mcp23s08_platform_data),
  682. GFP_KERNEL);
  683. if (!pdata)
  684. return -ENOMEM;
  685. pdata->base = -1;
  686. }
  687. }
  688. mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
  689. if (!mcp)
  690. return -ENOMEM;
  691. mcp->irq = client->irq;
  692. status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
  693. id->driver_data, pdata, 0);
  694. if (status)
  695. goto fail;
  696. i2c_set_clientdata(client, mcp);
  697. return 0;
  698. fail:
  699. kfree(mcp);
  700. return status;
  701. }
  702. static int mcp230xx_remove(struct i2c_client *client)
  703. {
  704. struct mcp23s08 *mcp = i2c_get_clientdata(client);
  705. if (client->irq && mcp->irq_controller)
  706. mcp23s08_irq_teardown(mcp);
  707. gpiochip_remove(&mcp->chip);
  708. kfree(mcp);
  709. return 0;
  710. }
  711. static const struct i2c_device_id mcp230xx_id[] = {
  712. { "mcp23008", MCP_TYPE_008 },
  713. { "mcp23017", MCP_TYPE_017 },
  714. { },
  715. };
  716. MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
  717. static struct i2c_driver mcp230xx_driver = {
  718. .driver = {
  719. .name = "mcp230xx",
  720. .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
  721. },
  722. .probe = mcp230xx_probe,
  723. .remove = mcp230xx_remove,
  724. .id_table = mcp230xx_id,
  725. };
  726. static int __init mcp23s08_i2c_init(void)
  727. {
  728. return i2c_add_driver(&mcp230xx_driver);
  729. }
  730. static void mcp23s08_i2c_exit(void)
  731. {
  732. i2c_del_driver(&mcp230xx_driver);
  733. }
  734. #else
  735. static int __init mcp23s08_i2c_init(void) { return 0; }
  736. static void mcp23s08_i2c_exit(void) { }
  737. #endif /* CONFIG_I2C */
  738. /*----------------------------------------------------------------------*/
  739. #ifdef CONFIG_SPI_MASTER
  740. static int mcp23s08_probe(struct spi_device *spi)
  741. {
  742. struct mcp23s08_platform_data *pdata, local_pdata;
  743. unsigned addr;
  744. int chips = 0;
  745. struct mcp23s08_driver_data *data;
  746. int status, type;
  747. unsigned ngpio = 0;
  748. const struct of_device_id *match;
  749. u32 spi_present_mask = 0;
  750. match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
  751. if (match) {
  752. type = (int)(uintptr_t)match->data;
  753. status = of_property_read_u32(spi->dev.of_node,
  754. "microchip,spi-present-mask", &spi_present_mask);
  755. if (status) {
  756. status = of_property_read_u32(spi->dev.of_node,
  757. "mcp,spi-present-mask", &spi_present_mask);
  758. if (status) {
  759. dev_err(&spi->dev,
  760. "DT has no spi-present-mask\n");
  761. return -ENODEV;
  762. }
  763. }
  764. if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
  765. dev_err(&spi->dev, "invalid spi-present-mask\n");
  766. return -ENODEV;
  767. }
  768. pdata = &local_pdata;
  769. pdata->base = -1;
  770. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  771. pdata->chip[addr].pullups = 0;
  772. if (spi_present_mask & (1 << addr))
  773. chips++;
  774. }
  775. pdata->irq_controller = of_property_read_bool(
  776. spi->dev.of_node,
  777. "interrupt-controller");
  778. pdata->mirror = of_property_read_bool(spi->dev.of_node,
  779. "microchip,irq-mirror");
  780. } else {
  781. type = spi_get_device_id(spi)->driver_data;
  782. pdata = dev_get_platdata(&spi->dev);
  783. if (!pdata) {
  784. pdata = devm_kzalloc(&spi->dev,
  785. sizeof(struct mcp23s08_platform_data),
  786. GFP_KERNEL);
  787. pdata->base = -1;
  788. }
  789. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  790. if (!pdata->chip[addr].is_present)
  791. continue;
  792. chips++;
  793. if ((type == MCP_TYPE_S08) && (addr > 3)) {
  794. dev_err(&spi->dev,
  795. "mcp23s08 only supports address 0..3\n");
  796. return -EINVAL;
  797. }
  798. spi_present_mask |= 1 << addr;
  799. }
  800. }
  801. if (!chips)
  802. return -ENODEV;
  803. data = devm_kzalloc(&spi->dev,
  804. sizeof(*data) + chips * sizeof(struct mcp23s08),
  805. GFP_KERNEL);
  806. if (!data)
  807. return -ENOMEM;
  808. spi_set_drvdata(spi, data);
  809. spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
  810. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  811. if (!(spi_present_mask & (1 << addr)))
  812. continue;
  813. chips--;
  814. data->mcp[addr] = &data->chip[chips];
  815. data->mcp[addr]->irq = spi->irq;
  816. status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
  817. 0x40 | (addr << 1), type, pdata,
  818. addr);
  819. if (status < 0)
  820. goto fail;
  821. if (pdata->base != -1)
  822. pdata->base += data->mcp[addr]->chip.ngpio;
  823. ngpio += data->mcp[addr]->chip.ngpio;
  824. }
  825. data->ngpio = ngpio;
  826. /* NOTE: these chips have a relatively sane IRQ framework, with
  827. * per-signal masking and level/edge triggering. It's not yet
  828. * handled here...
  829. */
  830. return 0;
  831. fail:
  832. for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
  833. if (!data->mcp[addr])
  834. continue;
  835. gpiochip_remove(&data->mcp[addr]->chip);
  836. }
  837. return status;
  838. }
  839. static int mcp23s08_remove(struct spi_device *spi)
  840. {
  841. struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
  842. unsigned addr;
  843. for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
  844. if (!data->mcp[addr])
  845. continue;
  846. if (spi->irq && data->mcp[addr]->irq_controller)
  847. mcp23s08_irq_teardown(data->mcp[addr]);
  848. gpiochip_remove(&data->mcp[addr]->chip);
  849. }
  850. return 0;
  851. }
  852. static const struct spi_device_id mcp23s08_ids[] = {
  853. { "mcp23s08", MCP_TYPE_S08 },
  854. { "mcp23s17", MCP_TYPE_S17 },
  855. { "mcp23s18", MCP_TYPE_S18 },
  856. { },
  857. };
  858. MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
  859. static struct spi_driver mcp23s08_driver = {
  860. .probe = mcp23s08_probe,
  861. .remove = mcp23s08_remove,
  862. .id_table = mcp23s08_ids,
  863. .driver = {
  864. .name = "mcp23s08",
  865. .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
  866. },
  867. };
  868. static int __init mcp23s08_spi_init(void)
  869. {
  870. return spi_register_driver(&mcp23s08_driver);
  871. }
  872. static void mcp23s08_spi_exit(void)
  873. {
  874. spi_unregister_driver(&mcp23s08_driver);
  875. }
  876. #else
  877. static int __init mcp23s08_spi_init(void) { return 0; }
  878. static void mcp23s08_spi_exit(void) { }
  879. #endif /* CONFIG_SPI_MASTER */
  880. /*----------------------------------------------------------------------*/
  881. static int __init mcp23s08_init(void)
  882. {
  883. int ret;
  884. ret = mcp23s08_spi_init();
  885. if (ret)
  886. goto spi_fail;
  887. ret = mcp23s08_i2c_init();
  888. if (ret)
  889. goto i2c_fail;
  890. return 0;
  891. i2c_fail:
  892. mcp23s08_spi_exit();
  893. spi_fail:
  894. return ret;
  895. }
  896. /* register after spi/i2c postcore initcall and before
  897. * subsys initcalls that may rely on these GPIOs
  898. */
  899. subsys_initcall(mcp23s08_init);
  900. static void __exit mcp23s08_exit(void)
  901. {
  902. mcp23s08_spi_exit();
  903. mcp23s08_i2c_exit();
  904. }
  905. module_exit(mcp23s08_exit);
  906. MODULE_LICENSE("GPL");