gpio-amdpt.c 6.6 KB

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  1. /*
  2. * AMD Promontory GPIO driver
  3. *
  4. * Copyright (C) 2015 ASMedia Technology Inc.
  5. * Author: YD Tseng <yd_tseng@asmedia.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/gpio/driver.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/acpi.h>
  16. #include <linux/platform_device.h>
  17. #define PT_TOTAL_GPIO 8
  18. /* PCI-E MMIO register offsets */
  19. #define PT_DIRECTION_REG 0x00
  20. #define PT_INPUTDATA_REG 0x04
  21. #define PT_OUTPUTDATA_REG 0x08
  22. #define PT_CLOCKRATE_REG 0x0C
  23. #define PT_SYNC_REG 0x28
  24. struct pt_gpio_chip {
  25. struct gpio_chip gc;
  26. void __iomem *reg_base;
  27. spinlock_t lock;
  28. };
  29. static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
  30. {
  31. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  32. unsigned long flags;
  33. u32 using_pins;
  34. dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);
  35. spin_lock_irqsave(&pt_gpio->lock, flags);
  36. using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
  37. if (using_pins & BIT(offset)) {
  38. dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",
  39. offset);
  40. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  41. return -EINVAL;
  42. }
  43. writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
  44. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  45. return 0;
  46. }
  47. static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
  48. {
  49. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  50. unsigned long flags;
  51. u32 using_pins;
  52. spin_lock_irqsave(&pt_gpio->lock, flags);
  53. using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
  54. using_pins &= ~BIT(offset);
  55. writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
  56. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  57. dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);
  58. }
  59. static void pt_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
  60. {
  61. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  62. unsigned long flags;
  63. u32 data;
  64. dev_dbg(gc->parent, "pt_gpio_set_value offset=%x, value=%x\n",
  65. offset, value);
  66. spin_lock_irqsave(&pt_gpio->lock, flags);
  67. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  68. data &= ~BIT(offset);
  69. if (value)
  70. data |= BIT(offset);
  71. writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  72. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  73. }
  74. static int pt_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  75. {
  76. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  77. unsigned long flags;
  78. u32 data;
  79. spin_lock_irqsave(&pt_gpio->lock, flags);
  80. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  81. /* configure as output */
  82. if (data & BIT(offset))
  83. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  84. else /* configure as input */
  85. data = readl(pt_gpio->reg_base + PT_INPUTDATA_REG);
  86. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  87. data >>= offset;
  88. data &= 1;
  89. dev_dbg(gc->parent, "pt_gpio_get_value offset=%x, value=%x\n",
  90. offset, data);
  91. return data;
  92. }
  93. static int pt_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  94. {
  95. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  96. unsigned long flags;
  97. u32 data;
  98. dev_dbg(gc->parent, "pt_gpio_dirction_input offset=%x\n", offset);
  99. spin_lock_irqsave(&pt_gpio->lock, flags);
  100. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  101. data &= ~BIT(offset);
  102. writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
  103. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  104. return 0;
  105. }
  106. static int pt_gpio_direction_output(struct gpio_chip *gc,
  107. unsigned offset, int value)
  108. {
  109. struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
  110. unsigned long flags;
  111. u32 data;
  112. dev_dbg(gc->parent, "pt_gpio_direction_output offset=%x, value=%x\n",
  113. offset, value);
  114. spin_lock_irqsave(&pt_gpio->lock, flags);
  115. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  116. if (value)
  117. data |= BIT(offset);
  118. else
  119. data &= ~BIT(offset);
  120. writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  121. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  122. data |= BIT(offset);
  123. writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
  124. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  125. return 0;
  126. }
  127. static int pt_gpio_probe(struct platform_device *pdev)
  128. {
  129. struct device *dev = &pdev->dev;
  130. struct acpi_device *acpi_dev;
  131. acpi_handle handle = ACPI_HANDLE(dev);
  132. struct pt_gpio_chip *pt_gpio;
  133. struct resource *res_mem;
  134. int ret = 0;
  135. if (acpi_bus_get_device(handle, &acpi_dev)) {
  136. dev_err(dev, "PT GPIO device node not found\n");
  137. return -ENODEV;
  138. }
  139. pt_gpio = devm_kzalloc(dev, sizeof(struct pt_gpio_chip), GFP_KERNEL);
  140. if (!pt_gpio)
  141. return -ENOMEM;
  142. res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  143. if (!res_mem) {
  144. dev_err(&pdev->dev, "Failed to get MMIO resource for PT GPIO.\n");
  145. return -EINVAL;
  146. }
  147. pt_gpio->reg_base = devm_ioremap_resource(dev, res_mem);
  148. if (IS_ERR(pt_gpio->reg_base)) {
  149. dev_err(&pdev->dev, "Failed to map MMIO resource for PT GPIO.\n");
  150. return PTR_ERR(pt_gpio->reg_base);
  151. }
  152. spin_lock_init(&pt_gpio->lock);
  153. pt_gpio->gc.label = pdev->name;
  154. pt_gpio->gc.owner = THIS_MODULE;
  155. pt_gpio->gc.parent = dev;
  156. pt_gpio->gc.request = pt_gpio_request;
  157. pt_gpio->gc.free = pt_gpio_free;
  158. pt_gpio->gc.direction_input = pt_gpio_direction_input;
  159. pt_gpio->gc.direction_output = pt_gpio_direction_output;
  160. pt_gpio->gc.get = pt_gpio_get_value;
  161. pt_gpio->gc.set = pt_gpio_set_value;
  162. pt_gpio->gc.base = -1;
  163. pt_gpio->gc.ngpio = PT_TOTAL_GPIO;
  164. #if defined(CONFIG_OF_GPIO)
  165. pt_gpio->gc.of_node = pdev->dev.of_node;
  166. #endif
  167. ret = gpiochip_add_data(&pt_gpio->gc, pt_gpio);
  168. if (ret) {
  169. dev_err(&pdev->dev, "Failed to register GPIO lib\n");
  170. return ret;
  171. }
  172. platform_set_drvdata(pdev, pt_gpio);
  173. /* initialize register setting */
  174. writel(0, pt_gpio->reg_base + PT_SYNC_REG);
  175. writel(0, pt_gpio->reg_base + PT_CLOCKRATE_REG);
  176. dev_dbg(&pdev->dev, "PT GPIO driver loaded\n");
  177. return ret;
  178. }
  179. static int pt_gpio_remove(struct platform_device *pdev)
  180. {
  181. struct pt_gpio_chip *pt_gpio = platform_get_drvdata(pdev);
  182. gpiochip_remove(&pt_gpio->gc);
  183. return 0;
  184. }
  185. static const struct acpi_device_id pt_gpio_acpi_match[] = {
  186. { "AMDF030", 0 },
  187. { },
  188. };
  189. MODULE_DEVICE_TABLE(acpi, pt_gpio_acpi_match);
  190. static struct platform_driver pt_gpio_driver = {
  191. .driver = {
  192. .name = "pt-gpio",
  193. .acpi_match_table = ACPI_PTR(pt_gpio_acpi_match),
  194. },
  195. .probe = pt_gpio_probe,
  196. .remove = pt_gpio_remove,
  197. };
  198. module_platform_driver(pt_gpio_driver);
  199. MODULE_LICENSE("GPL");
  200. MODULE_AUTHOR("YD Tseng <yd_tseng@asmedia.com.tw>");
  201. MODULE_DESCRIPTION("AMD Promontory GPIO Driver");