clk-gate.c 4.2 KB

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  1. /*
  2. * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
  3. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * Gated clock implementation
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/module.h>
  13. #include <linux/slab.h>
  14. #include <linux/io.h>
  15. #include <linux/err.h>
  16. #include <linux/string.h>
  17. /**
  18. * DOC: basic gatable clock which can gate and ungate it's ouput
  19. *
  20. * Traits of this clock:
  21. * prepare - clk_(un)prepare only ensures parent is (un)prepared
  22. * enable - clk_enable and clk_disable are functional & control gating
  23. * rate - inherits rate from parent. No clk_set_rate support
  24. * parent - fixed parent. No clk_set_parent support
  25. */
  26. /*
  27. * It works on following logic:
  28. *
  29. * For enabling clock, enable = 1
  30. * set2dis = 1 -> clear bit -> set = 0
  31. * set2dis = 0 -> set bit -> set = 1
  32. *
  33. * For disabling clock, enable = 0
  34. * set2dis = 1 -> set bit -> set = 1
  35. * set2dis = 0 -> clear bit -> set = 0
  36. *
  37. * So, result is always: enable xor set2dis.
  38. */
  39. static void clk_gate_endisable(struct clk_hw *hw, int enable)
  40. {
  41. struct clk_gate *gate = to_clk_gate(hw);
  42. int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
  43. unsigned long uninitialized_var(flags);
  44. u32 reg;
  45. set ^= enable;
  46. if (gate->lock)
  47. spin_lock_irqsave(gate->lock, flags);
  48. else
  49. __acquire(gate->lock);
  50. if (gate->flags & CLK_GATE_HIWORD_MASK) {
  51. reg = BIT(gate->bit_idx + 16);
  52. if (set)
  53. reg |= BIT(gate->bit_idx);
  54. } else {
  55. reg = clk_readl(gate->reg);
  56. if (set)
  57. reg |= BIT(gate->bit_idx);
  58. else
  59. reg &= ~BIT(gate->bit_idx);
  60. }
  61. clk_writel(reg, gate->reg);
  62. if (gate->lock)
  63. spin_unlock_irqrestore(gate->lock, flags);
  64. else
  65. __release(gate->lock);
  66. }
  67. static int clk_gate_enable(struct clk_hw *hw)
  68. {
  69. clk_gate_endisable(hw, 1);
  70. return 0;
  71. }
  72. static void clk_gate_disable(struct clk_hw *hw)
  73. {
  74. clk_gate_endisable(hw, 0);
  75. }
  76. static int clk_gate_is_enabled(struct clk_hw *hw)
  77. {
  78. u32 reg;
  79. struct clk_gate *gate = to_clk_gate(hw);
  80. reg = clk_readl(gate->reg);
  81. /* if a set bit disables this clk, flip it before masking */
  82. if (gate->flags & CLK_GATE_SET_TO_DISABLE)
  83. reg ^= BIT(gate->bit_idx);
  84. reg &= BIT(gate->bit_idx);
  85. return reg ? 1 : 0;
  86. }
  87. const struct clk_ops clk_gate_ops = {
  88. .enable = clk_gate_enable,
  89. .disable = clk_gate_disable,
  90. .is_enabled = clk_gate_is_enabled,
  91. };
  92. EXPORT_SYMBOL_GPL(clk_gate_ops);
  93. /**
  94. * clk_register_gate - register a gate clock with the clock framework
  95. * @dev: device that is registering this clock
  96. * @name: name of this clock
  97. * @parent_name: name of this clock's parent
  98. * @flags: framework-specific flags for this clock
  99. * @reg: register address to control gating of this clock
  100. * @bit_idx: which bit in the register controls gating of this clock
  101. * @clk_gate_flags: gate-specific flags for this clock
  102. * @lock: shared register lock for this clock
  103. */
  104. struct clk *clk_register_gate(struct device *dev, const char *name,
  105. const char *parent_name, unsigned long flags,
  106. void __iomem *reg, u8 bit_idx,
  107. u8 clk_gate_flags, spinlock_t *lock)
  108. {
  109. struct clk_gate *gate;
  110. struct clk *clk;
  111. struct clk_init_data init;
  112. if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
  113. if (bit_idx > 15) {
  114. pr_err("gate bit exceeds LOWORD field\n");
  115. return ERR_PTR(-EINVAL);
  116. }
  117. }
  118. /* allocate the gate */
  119. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  120. if (!gate)
  121. return ERR_PTR(-ENOMEM);
  122. init.name = name;
  123. init.ops = &clk_gate_ops;
  124. init.flags = flags | CLK_IS_BASIC;
  125. init.parent_names = (parent_name ? &parent_name: NULL);
  126. init.num_parents = (parent_name ? 1 : 0);
  127. /* struct clk_gate assignments */
  128. gate->reg = reg;
  129. gate->bit_idx = bit_idx;
  130. gate->flags = clk_gate_flags;
  131. gate->lock = lock;
  132. gate->hw.init = &init;
  133. clk = clk_register(dev, &gate->hw);
  134. if (IS_ERR(clk))
  135. kfree(gate);
  136. return clk;
  137. }
  138. EXPORT_SYMBOL_GPL(clk_register_gate);
  139. void clk_unregister_gate(struct clk *clk)
  140. {
  141. struct clk_gate *gate;
  142. struct clk_hw *hw;
  143. hw = __clk_get_hw(clk);
  144. if (!hw)
  145. return;
  146. gate = to_clk_gate(hw);
  147. clk_unregister(clk);
  148. kfree(gate);
  149. }
  150. EXPORT_SYMBOL_GPL(clk_unregister_gate);