vc4_irq.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210
  1. /*
  2. * Copyright © 2014 Broadcom
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. */
  23. /** DOC: Interrupt management for the V3D engine.
  24. *
  25. * We have an interrupt status register (V3D_INTCTL) which reports
  26. * interrupts, and where writing 1 bits clears those interrupts.
  27. * There are also a pair of interrupt registers
  28. * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
  29. * disables that specific interrupt, and 0s written are ignored
  30. * (reading either one returns the set of enabled interrupts).
  31. *
  32. * When we take a render frame interrupt, we need to wake the
  33. * processes waiting for some frame to be done, and get the next frame
  34. * submitted ASAP (so the hardware doesn't sit idle when there's work
  35. * to do).
  36. *
  37. * When we take the binner out of memory interrupt, we need to
  38. * allocate some new memory and pass it to the binner so that the
  39. * current job can make progress.
  40. */
  41. #include "vc4_drv.h"
  42. #include "vc4_regs.h"
  43. #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
  44. V3D_INT_FRDONE)
  45. DECLARE_WAIT_QUEUE_HEAD(render_wait);
  46. static void
  47. vc4_overflow_mem_work(struct work_struct *work)
  48. {
  49. struct vc4_dev *vc4 =
  50. container_of(work, struct vc4_dev, overflow_mem_work);
  51. struct drm_device *dev = vc4->dev;
  52. struct vc4_bo *bo;
  53. bo = vc4_bo_create(dev, 256 * 1024, true);
  54. if (!bo) {
  55. DRM_ERROR("Couldn't allocate binner overflow mem\n");
  56. return;
  57. }
  58. /* If there's a job executing currently, then our previous
  59. * overflow allocation is getting used in that job and we need
  60. * to queue it to be released when the job is done. But if no
  61. * job is executing at all, then we can free the old overflow
  62. * object direcctly.
  63. *
  64. * No lock necessary for this pointer since we're the only
  65. * ones that update the pointer, and our workqueue won't
  66. * reenter.
  67. */
  68. if (vc4->overflow_mem) {
  69. struct vc4_exec_info *current_exec;
  70. unsigned long irqflags;
  71. spin_lock_irqsave(&vc4->job_lock, irqflags);
  72. current_exec = vc4_first_job(vc4);
  73. if (current_exec) {
  74. vc4->overflow_mem->seqno = vc4->finished_seqno + 1;
  75. list_add_tail(&vc4->overflow_mem->unref_head,
  76. &current_exec->unref_list);
  77. vc4->overflow_mem = NULL;
  78. }
  79. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  80. }
  81. if (vc4->overflow_mem)
  82. drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
  83. vc4->overflow_mem = bo;
  84. V3D_WRITE(V3D_BPOA, bo->base.paddr);
  85. V3D_WRITE(V3D_BPOS, bo->base.base.size);
  86. V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
  87. V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
  88. }
  89. static void
  90. vc4_irq_finish_job(struct drm_device *dev)
  91. {
  92. struct vc4_dev *vc4 = to_vc4_dev(dev);
  93. struct vc4_exec_info *exec = vc4_first_job(vc4);
  94. if (!exec)
  95. return;
  96. vc4->finished_seqno++;
  97. list_move_tail(&exec->head, &vc4->job_done_list);
  98. vc4_submit_next_job(dev);
  99. wake_up_all(&vc4->job_wait_queue);
  100. schedule_work(&vc4->job_done_work);
  101. }
  102. irqreturn_t
  103. vc4_irq(int irq, void *arg)
  104. {
  105. struct drm_device *dev = arg;
  106. struct vc4_dev *vc4 = to_vc4_dev(dev);
  107. uint32_t intctl;
  108. irqreturn_t status = IRQ_NONE;
  109. barrier();
  110. intctl = V3D_READ(V3D_INTCTL);
  111. /* Acknowledge the interrupts we're handling here. The render
  112. * frame done interrupt will be cleared, while OUTOMEM will
  113. * stay high until the underlying cause is cleared.
  114. */
  115. V3D_WRITE(V3D_INTCTL, intctl);
  116. if (intctl & V3D_INT_OUTOMEM) {
  117. /* Disable OUTOMEM until the work is done. */
  118. V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
  119. schedule_work(&vc4->overflow_mem_work);
  120. status = IRQ_HANDLED;
  121. }
  122. if (intctl & V3D_INT_FRDONE) {
  123. spin_lock(&vc4->job_lock);
  124. vc4_irq_finish_job(dev);
  125. spin_unlock(&vc4->job_lock);
  126. status = IRQ_HANDLED;
  127. }
  128. return status;
  129. }
  130. void
  131. vc4_irq_preinstall(struct drm_device *dev)
  132. {
  133. struct vc4_dev *vc4 = to_vc4_dev(dev);
  134. init_waitqueue_head(&vc4->job_wait_queue);
  135. INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
  136. /* Clear any pending interrupts someone might have left around
  137. * for us.
  138. */
  139. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  140. }
  141. int
  142. vc4_irq_postinstall(struct drm_device *dev)
  143. {
  144. struct vc4_dev *vc4 = to_vc4_dev(dev);
  145. /* Enable both the render done and out of memory interrupts. */
  146. V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
  147. return 0;
  148. }
  149. void
  150. vc4_irq_uninstall(struct drm_device *dev)
  151. {
  152. struct vc4_dev *vc4 = to_vc4_dev(dev);
  153. /* Disable sending interrupts for our driver's IRQs. */
  154. V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
  155. /* Clear any pending interrupts we might have left. */
  156. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  157. cancel_work_sync(&vc4->overflow_mem_work);
  158. }
  159. /** Reinitializes interrupt registers when a GPU reset is performed. */
  160. void vc4_irq_reset(struct drm_device *dev)
  161. {
  162. struct vc4_dev *vc4 = to_vc4_dev(dev);
  163. unsigned long irqflags;
  164. /* Acknowledge any stale IRQs. */
  165. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  166. /*
  167. * Turn all our interrupts on. Binner out of memory is the
  168. * only one we expect to trigger at this point, since we've
  169. * just come from poweron and haven't supplied any overflow
  170. * memory yet.
  171. */
  172. V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
  173. spin_lock_irqsave(&vc4->job_lock, irqflags);
  174. vc4_irq_finish_job(dev);
  175. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  176. }