atmel_hlcdc_plane.c 21 KB

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  1. /*
  2. * Copyright (C) 2014 Free Electrons
  3. * Copyright (C) 2014 Atmel
  4. *
  5. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "atmel_hlcdc_dc.h"
  20. #define SUBPIXEL_MASK 0xffff
  21. static uint32_t rgb_formats[] = {
  22. DRM_FORMAT_XRGB4444,
  23. DRM_FORMAT_ARGB4444,
  24. DRM_FORMAT_RGBA4444,
  25. DRM_FORMAT_ARGB1555,
  26. DRM_FORMAT_RGB565,
  27. DRM_FORMAT_RGB888,
  28. DRM_FORMAT_XRGB8888,
  29. DRM_FORMAT_ARGB8888,
  30. DRM_FORMAT_RGBA8888,
  31. };
  32. struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats = {
  33. .formats = rgb_formats,
  34. .nformats = ARRAY_SIZE(rgb_formats),
  35. };
  36. static uint32_t rgb_and_yuv_formats[] = {
  37. DRM_FORMAT_XRGB4444,
  38. DRM_FORMAT_ARGB4444,
  39. DRM_FORMAT_RGBA4444,
  40. DRM_FORMAT_ARGB1555,
  41. DRM_FORMAT_RGB565,
  42. DRM_FORMAT_RGB888,
  43. DRM_FORMAT_XRGB8888,
  44. DRM_FORMAT_ARGB8888,
  45. DRM_FORMAT_RGBA8888,
  46. DRM_FORMAT_AYUV,
  47. DRM_FORMAT_YUYV,
  48. DRM_FORMAT_UYVY,
  49. DRM_FORMAT_YVYU,
  50. DRM_FORMAT_VYUY,
  51. DRM_FORMAT_NV21,
  52. DRM_FORMAT_NV61,
  53. DRM_FORMAT_YUV422,
  54. DRM_FORMAT_YUV420,
  55. };
  56. struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats = {
  57. .formats = rgb_and_yuv_formats,
  58. .nformats = ARRAY_SIZE(rgb_and_yuv_formats),
  59. };
  60. static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode)
  61. {
  62. switch (format) {
  63. case DRM_FORMAT_XRGB4444:
  64. *mode = ATMEL_HLCDC_XRGB4444_MODE;
  65. break;
  66. case DRM_FORMAT_ARGB4444:
  67. *mode = ATMEL_HLCDC_ARGB4444_MODE;
  68. break;
  69. case DRM_FORMAT_RGBA4444:
  70. *mode = ATMEL_HLCDC_RGBA4444_MODE;
  71. break;
  72. case DRM_FORMAT_RGB565:
  73. *mode = ATMEL_HLCDC_RGB565_MODE;
  74. break;
  75. case DRM_FORMAT_RGB888:
  76. *mode = ATMEL_HLCDC_RGB888_MODE;
  77. break;
  78. case DRM_FORMAT_ARGB1555:
  79. *mode = ATMEL_HLCDC_ARGB1555_MODE;
  80. break;
  81. case DRM_FORMAT_XRGB8888:
  82. *mode = ATMEL_HLCDC_XRGB8888_MODE;
  83. break;
  84. case DRM_FORMAT_ARGB8888:
  85. *mode = ATMEL_HLCDC_ARGB8888_MODE;
  86. break;
  87. case DRM_FORMAT_RGBA8888:
  88. *mode = ATMEL_HLCDC_RGBA8888_MODE;
  89. break;
  90. case DRM_FORMAT_AYUV:
  91. *mode = ATMEL_HLCDC_AYUV_MODE;
  92. break;
  93. case DRM_FORMAT_YUYV:
  94. *mode = ATMEL_HLCDC_YUYV_MODE;
  95. break;
  96. case DRM_FORMAT_UYVY:
  97. *mode = ATMEL_HLCDC_UYVY_MODE;
  98. break;
  99. case DRM_FORMAT_YVYU:
  100. *mode = ATMEL_HLCDC_YVYU_MODE;
  101. break;
  102. case DRM_FORMAT_VYUY:
  103. *mode = ATMEL_HLCDC_VYUY_MODE;
  104. break;
  105. case DRM_FORMAT_NV21:
  106. *mode = ATMEL_HLCDC_NV21_MODE;
  107. break;
  108. case DRM_FORMAT_NV61:
  109. *mode = ATMEL_HLCDC_NV61_MODE;
  110. break;
  111. case DRM_FORMAT_YUV420:
  112. *mode = ATMEL_HLCDC_YUV420_MODE;
  113. break;
  114. case DRM_FORMAT_YUV422:
  115. *mode = ATMEL_HLCDC_YUV422_MODE;
  116. break;
  117. default:
  118. return -ENOTSUPP;
  119. }
  120. return 0;
  121. }
  122. static bool atmel_hlcdc_format_embedds_alpha(u32 format)
  123. {
  124. int i;
  125. for (i = 0; i < sizeof(format); i++) {
  126. char tmp = (format >> (8 * i)) & 0xff;
  127. if (tmp == 'A')
  128. return true;
  129. }
  130. return false;
  131. }
  132. static u32 heo_downscaling_xcoef[] = {
  133. 0x11343311,
  134. 0x000000f7,
  135. 0x1635300c,
  136. 0x000000f9,
  137. 0x1b362c08,
  138. 0x000000fb,
  139. 0x1f372804,
  140. 0x000000fe,
  141. 0x24382400,
  142. 0x00000000,
  143. 0x28371ffe,
  144. 0x00000004,
  145. 0x2c361bfb,
  146. 0x00000008,
  147. 0x303516f9,
  148. 0x0000000c,
  149. };
  150. static u32 heo_downscaling_ycoef[] = {
  151. 0x00123737,
  152. 0x00173732,
  153. 0x001b382d,
  154. 0x001f3928,
  155. 0x00243824,
  156. 0x0028391f,
  157. 0x002d381b,
  158. 0x00323717,
  159. };
  160. static u32 heo_upscaling_xcoef[] = {
  161. 0xf74949f7,
  162. 0x00000000,
  163. 0xf55f33fb,
  164. 0x000000fe,
  165. 0xf5701efe,
  166. 0x000000ff,
  167. 0xf87c0dff,
  168. 0x00000000,
  169. 0x00800000,
  170. 0x00000000,
  171. 0x0d7cf800,
  172. 0x000000ff,
  173. 0x1e70f5ff,
  174. 0x000000fe,
  175. 0x335ff5fe,
  176. 0x000000fb,
  177. };
  178. static u32 heo_upscaling_ycoef[] = {
  179. 0x00004040,
  180. 0x00075920,
  181. 0x00056f0c,
  182. 0x00027b03,
  183. 0x00008000,
  184. 0x00037b02,
  185. 0x000c6f05,
  186. 0x00205907,
  187. };
  188. static void
  189. atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
  190. struct atmel_hlcdc_plane_update_req *req)
  191. {
  192. const struct atmel_hlcdc_layer_cfg_layout *layout =
  193. &plane->layer.desc->layout;
  194. if (layout->size)
  195. atmel_hlcdc_layer_update_cfg(&plane->layer,
  196. layout->size,
  197. 0xffffffff,
  198. (req->crtc_w - 1) |
  199. ((req->crtc_h - 1) << 16));
  200. if (layout->memsize)
  201. atmel_hlcdc_layer_update_cfg(&plane->layer,
  202. layout->memsize,
  203. 0xffffffff,
  204. (req->src_w - 1) |
  205. ((req->src_h - 1) << 16));
  206. if (layout->pos)
  207. atmel_hlcdc_layer_update_cfg(&plane->layer,
  208. layout->pos,
  209. 0xffffffff,
  210. req->crtc_x |
  211. (req->crtc_y << 16));
  212. /* TODO: rework the rescaling part */
  213. if (req->crtc_w != req->src_w || req->crtc_h != req->src_h) {
  214. u32 factor_reg = 0;
  215. if (req->crtc_w != req->src_w) {
  216. int i;
  217. u32 factor;
  218. u32 *coeff_tab = heo_upscaling_xcoef;
  219. u32 max_memsize;
  220. if (req->crtc_w < req->src_w)
  221. coeff_tab = heo_downscaling_xcoef;
  222. for (i = 0; i < ARRAY_SIZE(heo_upscaling_xcoef); i++)
  223. atmel_hlcdc_layer_update_cfg(&plane->layer,
  224. 17 + i,
  225. 0xffffffff,
  226. coeff_tab[i]);
  227. factor = ((8 * 256 * req->src_w) - (256 * 4)) /
  228. req->crtc_w;
  229. factor++;
  230. max_memsize = ((factor * req->crtc_w) + (256 * 4)) /
  231. 2048;
  232. if (max_memsize > req->src_w)
  233. factor--;
  234. factor_reg |= factor | 0x80000000;
  235. }
  236. if (req->crtc_h != req->src_h) {
  237. int i;
  238. u32 factor;
  239. u32 *coeff_tab = heo_upscaling_ycoef;
  240. u32 max_memsize;
  241. if (req->crtc_w < req->src_w)
  242. coeff_tab = heo_downscaling_ycoef;
  243. for (i = 0; i < ARRAY_SIZE(heo_upscaling_ycoef); i++)
  244. atmel_hlcdc_layer_update_cfg(&plane->layer,
  245. 33 + i,
  246. 0xffffffff,
  247. coeff_tab[i]);
  248. factor = ((8 * 256 * req->src_w) - (256 * 4)) /
  249. req->crtc_w;
  250. factor++;
  251. max_memsize = ((factor * req->crtc_w) + (256 * 4)) /
  252. 2048;
  253. if (max_memsize > req->src_w)
  254. factor--;
  255. factor_reg |= (factor << 16) | 0x80000000;
  256. }
  257. atmel_hlcdc_layer_update_cfg(&plane->layer, 13, 0xffffffff,
  258. factor_reg);
  259. }
  260. }
  261. static void
  262. atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
  263. struct atmel_hlcdc_plane_update_req *req)
  264. {
  265. const struct atmel_hlcdc_layer_cfg_layout *layout =
  266. &plane->layer.desc->layout;
  267. unsigned int cfg = ATMEL_HLCDC_LAYER_DMA;
  268. if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
  269. cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
  270. ATMEL_HLCDC_LAYER_ITER;
  271. if (atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format))
  272. cfg |= ATMEL_HLCDC_LAYER_LAEN;
  273. else
  274. cfg |= ATMEL_HLCDC_LAYER_GAEN;
  275. }
  276. atmel_hlcdc_layer_update_cfg(&plane->layer,
  277. ATMEL_HLCDC_LAYER_DMA_CFG_ID,
  278. ATMEL_HLCDC_LAYER_DMA_BLEN_MASK,
  279. ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16);
  280. atmel_hlcdc_layer_update_cfg(&plane->layer, layout->general_config,
  281. ATMEL_HLCDC_LAYER_ITER2BL |
  282. ATMEL_HLCDC_LAYER_ITER |
  283. ATMEL_HLCDC_LAYER_GAEN |
  284. ATMEL_HLCDC_LAYER_LAEN |
  285. ATMEL_HLCDC_LAYER_OVR |
  286. ATMEL_HLCDC_LAYER_DMA, cfg);
  287. }
  288. static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
  289. struct atmel_hlcdc_plane_update_req *req)
  290. {
  291. u32 cfg;
  292. int ret;
  293. ret = atmel_hlcdc_format_to_plane_mode(req->fb->pixel_format, &cfg);
  294. if (ret)
  295. return;
  296. if ((req->fb->pixel_format == DRM_FORMAT_YUV422 ||
  297. req->fb->pixel_format == DRM_FORMAT_NV61) &&
  298. (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))))
  299. cfg |= ATMEL_HLCDC_YUV422ROT;
  300. atmel_hlcdc_layer_update_cfg(&plane->layer,
  301. ATMEL_HLCDC_LAYER_FORMAT_CFG_ID,
  302. 0xffffffff,
  303. cfg);
  304. /*
  305. * Rotation optimization is not working on RGB888 (rotation is still
  306. * working but without any optimization).
  307. */
  308. if (req->fb->pixel_format == DRM_FORMAT_RGB888)
  309. cfg = ATMEL_HLCDC_LAYER_DMA_ROTDIS;
  310. else
  311. cfg = 0;
  312. atmel_hlcdc_layer_update_cfg(&plane->layer,
  313. ATMEL_HLCDC_LAYER_DMA_CFG_ID,
  314. ATMEL_HLCDC_LAYER_DMA_ROTDIS, cfg);
  315. }
  316. static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
  317. struct atmel_hlcdc_plane_update_req *req)
  318. {
  319. struct atmel_hlcdc_layer *layer = &plane->layer;
  320. const struct atmel_hlcdc_layer_cfg_layout *layout =
  321. &layer->desc->layout;
  322. int i;
  323. atmel_hlcdc_layer_update_set_fb(&plane->layer, req->fb, req->offsets);
  324. for (i = 0; i < req->nplanes; i++) {
  325. if (layout->xstride[i]) {
  326. atmel_hlcdc_layer_update_cfg(&plane->layer,
  327. layout->xstride[i],
  328. 0xffffffff,
  329. req->xstride[i]);
  330. }
  331. if (layout->pstride[i]) {
  332. atmel_hlcdc_layer_update_cfg(&plane->layer,
  333. layout->pstride[i],
  334. 0xffffffff,
  335. req->pstride[i]);
  336. }
  337. }
  338. }
  339. static int atmel_hlcdc_plane_check_update_req(struct drm_plane *p,
  340. struct atmel_hlcdc_plane_update_req *req,
  341. const struct drm_display_mode *mode)
  342. {
  343. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  344. const struct atmel_hlcdc_layer_cfg_layout *layout =
  345. &plane->layer.desc->layout;
  346. if (!layout->size &&
  347. (mode->hdisplay != req->crtc_w ||
  348. mode->vdisplay != req->crtc_h))
  349. return -EINVAL;
  350. if (plane->layer.desc->max_height &&
  351. req->crtc_h > plane->layer.desc->max_height)
  352. return -EINVAL;
  353. if (plane->layer.desc->max_width &&
  354. req->crtc_w > plane->layer.desc->max_width)
  355. return -EINVAL;
  356. if ((req->crtc_h != req->src_h || req->crtc_w != req->src_w) &&
  357. (!layout->memsize ||
  358. atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format)))
  359. return -EINVAL;
  360. if (req->crtc_x < 0 || req->crtc_y < 0)
  361. return -EINVAL;
  362. if (req->crtc_w + req->crtc_x > mode->hdisplay ||
  363. req->crtc_h + req->crtc_y > mode->vdisplay)
  364. return -EINVAL;
  365. return 0;
  366. }
  367. int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p,
  368. struct atmel_hlcdc_plane_update_req *req,
  369. const struct drm_display_mode *mode)
  370. {
  371. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  372. unsigned int patched_crtc_w;
  373. unsigned int patched_crtc_h;
  374. unsigned int patched_src_w;
  375. unsigned int patched_src_h;
  376. unsigned int tmp;
  377. int x_offset = 0;
  378. int y_offset = 0;
  379. int hsub = 1;
  380. int vsub = 1;
  381. int i;
  382. if ((req->src_x | req->src_y | req->src_w | req->src_h) &
  383. SUBPIXEL_MASK)
  384. return -EINVAL;
  385. req->src_x >>= 16;
  386. req->src_y >>= 16;
  387. req->src_w >>= 16;
  388. req->src_h >>= 16;
  389. req->nplanes = drm_format_num_planes(req->fb->pixel_format);
  390. if (req->nplanes > ATMEL_HLCDC_MAX_PLANES)
  391. return -EINVAL;
  392. /*
  393. * Swap width and size in case of 90 or 270 degrees rotation
  394. */
  395. if (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) {
  396. tmp = req->crtc_w;
  397. req->crtc_w = req->crtc_h;
  398. req->crtc_h = tmp;
  399. tmp = req->src_w;
  400. req->src_w = req->src_h;
  401. req->src_h = tmp;
  402. }
  403. if (req->crtc_x + req->crtc_w > mode->hdisplay)
  404. patched_crtc_w = mode->hdisplay - req->crtc_x;
  405. else
  406. patched_crtc_w = req->crtc_w;
  407. if (req->crtc_x < 0) {
  408. patched_crtc_w += req->crtc_x;
  409. x_offset = -req->crtc_x;
  410. req->crtc_x = 0;
  411. }
  412. if (req->crtc_y + req->crtc_h > mode->vdisplay)
  413. patched_crtc_h = mode->vdisplay - req->crtc_y;
  414. else
  415. patched_crtc_h = req->crtc_h;
  416. if (req->crtc_y < 0) {
  417. patched_crtc_h += req->crtc_y;
  418. y_offset = -req->crtc_y;
  419. req->crtc_y = 0;
  420. }
  421. patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * req->src_w,
  422. req->crtc_w);
  423. patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * req->src_h,
  424. req->crtc_h);
  425. hsub = drm_format_horz_chroma_subsampling(req->fb->pixel_format);
  426. vsub = drm_format_vert_chroma_subsampling(req->fb->pixel_format);
  427. for (i = 0; i < req->nplanes; i++) {
  428. unsigned int offset = 0;
  429. int xdiv = i ? hsub : 1;
  430. int ydiv = i ? vsub : 1;
  431. req->bpp[i] = drm_format_plane_cpp(req->fb->pixel_format, i);
  432. if (!req->bpp[i])
  433. return -EINVAL;
  434. switch (plane->rotation & 0xf) {
  435. case BIT(DRM_ROTATE_90):
  436. offset = ((y_offset + req->src_y + patched_src_w - 1) /
  437. ydiv) * req->fb->pitches[i];
  438. offset += ((x_offset + req->src_x) / xdiv) *
  439. req->bpp[i];
  440. req->xstride[i] = ((patched_src_w - 1) / ydiv) *
  441. req->fb->pitches[i];
  442. req->pstride[i] = -req->fb->pitches[i] - req->bpp[i];
  443. break;
  444. case BIT(DRM_ROTATE_180):
  445. offset = ((y_offset + req->src_y + patched_src_h - 1) /
  446. ydiv) * req->fb->pitches[i];
  447. offset += ((x_offset + req->src_x + patched_src_w - 1) /
  448. xdiv) * req->bpp[i];
  449. req->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) *
  450. req->bpp[i]) - req->fb->pitches[i];
  451. req->pstride[i] = -2 * req->bpp[i];
  452. break;
  453. case BIT(DRM_ROTATE_270):
  454. offset = ((y_offset + req->src_y) / ydiv) *
  455. req->fb->pitches[i];
  456. offset += ((x_offset + req->src_x + patched_src_h - 1) /
  457. xdiv) * req->bpp[i];
  458. req->xstride[i] = -(((patched_src_w - 1) / ydiv) *
  459. req->fb->pitches[i]) -
  460. (2 * req->bpp[i]);
  461. req->pstride[i] = req->fb->pitches[i] - req->bpp[i];
  462. break;
  463. case BIT(DRM_ROTATE_0):
  464. default:
  465. offset = ((y_offset + req->src_y) / ydiv) *
  466. req->fb->pitches[i];
  467. offset += ((x_offset + req->src_x) / xdiv) *
  468. req->bpp[i];
  469. req->xstride[i] = req->fb->pitches[i] -
  470. ((patched_src_w / xdiv) *
  471. req->bpp[i]);
  472. req->pstride[i] = 0;
  473. break;
  474. }
  475. req->offsets[i] = offset + req->fb->offsets[i];
  476. }
  477. req->src_w = patched_src_w;
  478. req->src_h = patched_src_h;
  479. req->crtc_w = patched_crtc_w;
  480. req->crtc_h = patched_crtc_h;
  481. return atmel_hlcdc_plane_check_update_req(p, req, mode);
  482. }
  483. int atmel_hlcdc_plane_apply_update_req(struct drm_plane *p,
  484. struct atmel_hlcdc_plane_update_req *req)
  485. {
  486. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  487. int ret;
  488. ret = atmel_hlcdc_layer_update_start(&plane->layer);
  489. if (ret)
  490. return ret;
  491. atmel_hlcdc_plane_update_pos_and_size(plane, req);
  492. atmel_hlcdc_plane_update_general_settings(plane, req);
  493. atmel_hlcdc_plane_update_format(plane, req);
  494. atmel_hlcdc_plane_update_buffers(plane, req);
  495. atmel_hlcdc_layer_update_commit(&plane->layer);
  496. return 0;
  497. }
  498. int atmel_hlcdc_plane_update_with_mode(struct drm_plane *p,
  499. struct drm_crtc *crtc,
  500. struct drm_framebuffer *fb,
  501. int crtc_x, int crtc_y,
  502. unsigned int crtc_w,
  503. unsigned int crtc_h,
  504. uint32_t src_x, uint32_t src_y,
  505. uint32_t src_w, uint32_t src_h,
  506. const struct drm_display_mode *mode)
  507. {
  508. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  509. struct atmel_hlcdc_plane_update_req req;
  510. int ret = 0;
  511. memset(&req, 0, sizeof(req));
  512. req.crtc_x = crtc_x;
  513. req.crtc_y = crtc_y;
  514. req.crtc_w = crtc_w;
  515. req.crtc_h = crtc_h;
  516. req.src_x = src_x;
  517. req.src_y = src_y;
  518. req.src_w = src_w;
  519. req.src_h = src_h;
  520. req.fb = fb;
  521. ret = atmel_hlcdc_plane_prepare_update_req(&plane->base, &req, mode);
  522. if (ret)
  523. return ret;
  524. if (!req.crtc_h || !req.crtc_w)
  525. return atmel_hlcdc_layer_disable(&plane->layer);
  526. return atmel_hlcdc_plane_apply_update_req(&plane->base, &req);
  527. }
  528. static int atmel_hlcdc_plane_update(struct drm_plane *p,
  529. struct drm_crtc *crtc,
  530. struct drm_framebuffer *fb,
  531. int crtc_x, int crtc_y,
  532. unsigned int crtc_w, unsigned int crtc_h,
  533. uint32_t src_x, uint32_t src_y,
  534. uint32_t src_w, uint32_t src_h)
  535. {
  536. return atmel_hlcdc_plane_update_with_mode(p, crtc, fb, crtc_x, crtc_y,
  537. crtc_w, crtc_h, src_x, src_y,
  538. src_w, src_h, &crtc->hwmode);
  539. }
  540. static int atmel_hlcdc_plane_disable(struct drm_plane *p)
  541. {
  542. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  543. return atmel_hlcdc_layer_disable(&plane->layer);
  544. }
  545. static void atmel_hlcdc_plane_destroy(struct drm_plane *p)
  546. {
  547. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  548. if (plane->base.fb)
  549. drm_framebuffer_unreference(plane->base.fb);
  550. atmel_hlcdc_layer_cleanup(p->dev, &plane->layer);
  551. drm_plane_cleanup(p);
  552. devm_kfree(p->dev->dev, plane);
  553. }
  554. static int atmel_hlcdc_plane_set_alpha(struct atmel_hlcdc_plane *plane,
  555. u8 alpha)
  556. {
  557. atmel_hlcdc_layer_update_start(&plane->layer);
  558. atmel_hlcdc_layer_update_cfg(&plane->layer,
  559. plane->layer.desc->layout.general_config,
  560. ATMEL_HLCDC_LAYER_GA_MASK,
  561. alpha << ATMEL_HLCDC_LAYER_GA_SHIFT);
  562. atmel_hlcdc_layer_update_commit(&plane->layer);
  563. return 0;
  564. }
  565. static int atmel_hlcdc_plane_set_rotation(struct atmel_hlcdc_plane *plane,
  566. unsigned int rotation)
  567. {
  568. plane->rotation = rotation;
  569. return 0;
  570. }
  571. static int atmel_hlcdc_plane_set_property(struct drm_plane *p,
  572. struct drm_property *property,
  573. uint64_t value)
  574. {
  575. struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
  576. struct atmel_hlcdc_plane_properties *props = plane->properties;
  577. if (property == props->alpha)
  578. atmel_hlcdc_plane_set_alpha(plane, value);
  579. else if (property == props->rotation)
  580. atmel_hlcdc_plane_set_rotation(plane, value);
  581. else
  582. return -EINVAL;
  583. return 0;
  584. }
  585. static void atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane,
  586. const struct atmel_hlcdc_layer_desc *desc,
  587. struct atmel_hlcdc_plane_properties *props)
  588. {
  589. struct regmap *regmap = plane->layer.hlcdc->regmap;
  590. if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
  591. desc->type == ATMEL_HLCDC_CURSOR_LAYER) {
  592. drm_object_attach_property(&plane->base.base,
  593. props->alpha, 255);
  594. /* Set default alpha value */
  595. regmap_update_bits(regmap,
  596. desc->regs_offset +
  597. ATMEL_HLCDC_LAYER_GENERAL_CFG(&plane->layer),
  598. ATMEL_HLCDC_LAYER_GA_MASK,
  599. ATMEL_HLCDC_LAYER_GA_MASK);
  600. }
  601. if (desc->layout.xstride && desc->layout.pstride)
  602. drm_object_attach_property(&plane->base.base,
  603. props->rotation,
  604. BIT(DRM_ROTATE_0));
  605. if (desc->layout.csc) {
  606. /*
  607. * TODO: decare a "yuv-to-rgb-conv-factors" property to let
  608. * userspace modify these factors (using a BLOB property ?).
  609. */
  610. regmap_write(regmap,
  611. desc->regs_offset +
  612. ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 0),
  613. 0x4c900091);
  614. regmap_write(regmap,
  615. desc->regs_offset +
  616. ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 1),
  617. 0x7a5f5090);
  618. regmap_write(regmap,
  619. desc->regs_offset +
  620. ATMEL_HLCDC_LAYER_CSC_CFG(&plane->layer, 2),
  621. 0x40040890);
  622. }
  623. }
  624. static struct drm_plane_funcs layer_plane_funcs = {
  625. .update_plane = atmel_hlcdc_plane_update,
  626. .disable_plane = atmel_hlcdc_plane_disable,
  627. .set_property = atmel_hlcdc_plane_set_property,
  628. .destroy = atmel_hlcdc_plane_destroy,
  629. };
  630. static struct atmel_hlcdc_plane *
  631. atmel_hlcdc_plane_create(struct drm_device *dev,
  632. const struct atmel_hlcdc_layer_desc *desc,
  633. struct atmel_hlcdc_plane_properties *props)
  634. {
  635. struct atmel_hlcdc_plane *plane;
  636. enum drm_plane_type type;
  637. int ret;
  638. plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
  639. if (!plane)
  640. return ERR_PTR(-ENOMEM);
  641. ret = atmel_hlcdc_layer_init(dev, &plane->layer, desc);
  642. if (ret)
  643. return ERR_PTR(ret);
  644. if (desc->type == ATMEL_HLCDC_BASE_LAYER)
  645. type = DRM_PLANE_TYPE_PRIMARY;
  646. else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER)
  647. type = DRM_PLANE_TYPE_CURSOR;
  648. else
  649. type = DRM_PLANE_TYPE_OVERLAY;
  650. ret = drm_universal_plane_init(dev, &plane->base, 0,
  651. &layer_plane_funcs,
  652. desc->formats->formats,
  653. desc->formats->nformats, type);
  654. if (ret)
  655. return ERR_PTR(ret);
  656. /* Set default property values*/
  657. atmel_hlcdc_plane_init_properties(plane, desc, props);
  658. return plane;
  659. }
  660. static struct atmel_hlcdc_plane_properties *
  661. atmel_hlcdc_plane_create_properties(struct drm_device *dev)
  662. {
  663. struct atmel_hlcdc_plane_properties *props;
  664. props = devm_kzalloc(dev->dev, sizeof(*props), GFP_KERNEL);
  665. if (!props)
  666. return ERR_PTR(-ENOMEM);
  667. props->alpha = drm_property_create_range(dev, 0, "alpha", 0, 255);
  668. if (!props->alpha)
  669. return ERR_PTR(-ENOMEM);
  670. props->rotation = drm_mode_create_rotation_property(dev,
  671. BIT(DRM_ROTATE_0) |
  672. BIT(DRM_ROTATE_90) |
  673. BIT(DRM_ROTATE_180) |
  674. BIT(DRM_ROTATE_270));
  675. if (!props->rotation)
  676. return ERR_PTR(-ENOMEM);
  677. return props;
  678. }
  679. struct atmel_hlcdc_planes *
  680. atmel_hlcdc_create_planes(struct drm_device *dev)
  681. {
  682. struct atmel_hlcdc_dc *dc = dev->dev_private;
  683. struct atmel_hlcdc_plane_properties *props;
  684. struct atmel_hlcdc_planes *planes;
  685. const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;
  686. int nlayers = dc->desc->nlayers;
  687. int i;
  688. planes = devm_kzalloc(dev->dev, sizeof(*planes), GFP_KERNEL);
  689. if (!planes)
  690. return ERR_PTR(-ENOMEM);
  691. for (i = 0; i < nlayers; i++) {
  692. if (descs[i].type == ATMEL_HLCDC_OVERLAY_LAYER)
  693. planes->noverlays++;
  694. }
  695. if (planes->noverlays) {
  696. planes->overlays = devm_kzalloc(dev->dev,
  697. planes->noverlays *
  698. sizeof(*planes->overlays),
  699. GFP_KERNEL);
  700. if (!planes->overlays)
  701. return ERR_PTR(-ENOMEM);
  702. }
  703. props = atmel_hlcdc_plane_create_properties(dev);
  704. if (IS_ERR(props))
  705. return ERR_CAST(props);
  706. planes->noverlays = 0;
  707. for (i = 0; i < nlayers; i++) {
  708. struct atmel_hlcdc_plane *plane;
  709. if (descs[i].type == ATMEL_HLCDC_PP_LAYER)
  710. continue;
  711. plane = atmel_hlcdc_plane_create(dev, &descs[i], props);
  712. if (IS_ERR(plane))
  713. return ERR_CAST(plane);
  714. plane->properties = props;
  715. switch (descs[i].type) {
  716. case ATMEL_HLCDC_BASE_LAYER:
  717. if (planes->primary)
  718. return ERR_PTR(-EINVAL);
  719. planes->primary = plane;
  720. break;
  721. case ATMEL_HLCDC_OVERLAY_LAYER:
  722. planes->overlays[planes->noverlays++] = plane;
  723. break;
  724. case ATMEL_HLCDC_CURSOR_LAYER:
  725. if (planes->cursor)
  726. return ERR_PTR(-EINVAL);
  727. planes->cursor = plane;
  728. break;
  729. default:
  730. break;
  731. }
  732. }
  733. return planes;
  734. }