atmel_hlcdc_crtc.c 11 KB

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  1. /*
  2. * Copyright (C) 2014 Traphandler
  3. * Copyright (C) 2014 Free Electrons
  4. *
  5. * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
  6. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published by
  10. * the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/pm.h>
  22. #include <linux/pm_runtime.h>
  23. #include <drm/drm_crtc.h>
  24. #include <drm/drm_crtc_helper.h>
  25. #include <drm/drmP.h>
  26. #include <video/videomode.h>
  27. #include "atmel_hlcdc_dc.h"
  28. /**
  29. * Atmel HLCDC CRTC structure
  30. *
  31. * @base: base DRM CRTC structure
  32. * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
  33. * @event: pointer to the current page flip event
  34. * @id: CRTC id (returned by drm_crtc_index)
  35. * @dpms: DPMS mode
  36. */
  37. struct atmel_hlcdc_crtc {
  38. struct drm_crtc base;
  39. struct atmel_hlcdc_dc *dc;
  40. struct drm_pending_vblank_event *event;
  41. int id;
  42. int dpms;
  43. };
  44. static inline struct atmel_hlcdc_crtc *
  45. drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
  46. {
  47. return container_of(crtc, struct atmel_hlcdc_crtc, base);
  48. }
  49. static void atmel_hlcdc_crtc_dpms(struct drm_crtc *c, int mode)
  50. {
  51. struct drm_device *dev = c->dev;
  52. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  53. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  54. unsigned int status;
  55. if (mode != DRM_MODE_DPMS_ON)
  56. mode = DRM_MODE_DPMS_OFF;
  57. if (crtc->dpms == mode)
  58. return;
  59. pm_runtime_get_sync(dev->dev);
  60. if (mode != DRM_MODE_DPMS_ON) {
  61. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
  62. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  63. (status & ATMEL_HLCDC_DISP))
  64. cpu_relax();
  65. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
  66. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  67. (status & ATMEL_HLCDC_SYNC))
  68. cpu_relax();
  69. regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
  70. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  71. (status & ATMEL_HLCDC_PIXEL_CLK))
  72. cpu_relax();
  73. clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
  74. pm_runtime_allow(dev->dev);
  75. } else {
  76. pm_runtime_forbid(dev->dev);
  77. clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
  78. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
  79. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  80. !(status & ATMEL_HLCDC_PIXEL_CLK))
  81. cpu_relax();
  82. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
  83. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  84. !(status & ATMEL_HLCDC_SYNC))
  85. cpu_relax();
  86. regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
  87. while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
  88. !(status & ATMEL_HLCDC_DISP))
  89. cpu_relax();
  90. }
  91. pm_runtime_put_sync(dev->dev);
  92. crtc->dpms = mode;
  93. }
  94. static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
  95. struct drm_display_mode *mode,
  96. struct drm_display_mode *adj,
  97. int x, int y,
  98. struct drm_framebuffer *old_fb)
  99. {
  100. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  101. struct regmap *regmap = crtc->dc->hlcdc->regmap;
  102. struct drm_plane *plane = c->primary;
  103. struct drm_framebuffer *fb;
  104. unsigned long mode_rate;
  105. struct videomode vm;
  106. unsigned long prate;
  107. unsigned int cfg;
  108. int div;
  109. if (atmel_hlcdc_dc_mode_valid(crtc->dc, adj) != MODE_OK)
  110. return -EINVAL;
  111. vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
  112. vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
  113. vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
  114. vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
  115. vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
  116. vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
  117. regmap_write(regmap, ATMEL_HLCDC_CFG(1),
  118. (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));
  119. regmap_write(regmap, ATMEL_HLCDC_CFG(2),
  120. (vm.vfront_porch - 1) | (vm.vback_porch << 16));
  121. regmap_write(regmap, ATMEL_HLCDC_CFG(3),
  122. (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));
  123. regmap_write(regmap, ATMEL_HLCDC_CFG(4),
  124. (adj->crtc_hdisplay - 1) |
  125. ((adj->crtc_vdisplay - 1) << 16));
  126. cfg = ATMEL_HLCDC_CLKPOL;
  127. prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
  128. mode_rate = mode->crtc_clock * 1000;
  129. if ((prate / 2) < mode_rate) {
  130. prate *= 2;
  131. cfg |= ATMEL_HLCDC_CLKSEL;
  132. }
  133. div = DIV_ROUND_UP(prate, mode_rate);
  134. if (div < 2)
  135. div = 2;
  136. cfg |= ATMEL_HLCDC_CLKDIV(div);
  137. regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0),
  138. ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK |
  139. ATMEL_HLCDC_CLKPOL, cfg);
  140. cfg = 0;
  141. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  142. cfg |= ATMEL_HLCDC_VSPOL;
  143. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  144. cfg |= ATMEL_HLCDC_HSPOL;
  145. regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
  146. ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
  147. ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
  148. ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
  149. ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
  150. ATMEL_HLCDC_GUARDTIME_MASK,
  151. cfg);
  152. fb = plane->fb;
  153. plane->fb = old_fb;
  154. return atmel_hlcdc_plane_update_with_mode(plane, c, fb, 0, 0,
  155. adj->hdisplay, adj->vdisplay,
  156. x << 16, y << 16,
  157. adj->hdisplay << 16,
  158. adj->vdisplay << 16,
  159. adj);
  160. }
  161. int atmel_hlcdc_crtc_mode_set_base(struct drm_crtc *c, int x, int y,
  162. struct drm_framebuffer *old_fb)
  163. {
  164. struct drm_plane *plane = c->primary;
  165. struct drm_framebuffer *fb = plane->fb;
  166. struct drm_display_mode *mode = &c->hwmode;
  167. plane->fb = old_fb;
  168. return plane->funcs->update_plane(plane, c, fb,
  169. 0, 0,
  170. mode->hdisplay,
  171. mode->vdisplay,
  172. x << 16, y << 16,
  173. mode->hdisplay << 16,
  174. mode->vdisplay << 16);
  175. }
  176. static void atmel_hlcdc_crtc_prepare(struct drm_crtc *crtc)
  177. {
  178. atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  179. }
  180. static void atmel_hlcdc_crtc_commit(struct drm_crtc *crtc)
  181. {
  182. atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  183. }
  184. static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
  185. const struct drm_display_mode *mode,
  186. struct drm_display_mode *adjusted_mode)
  187. {
  188. return true;
  189. }
  190. static void atmel_hlcdc_crtc_disable(struct drm_crtc *crtc)
  191. {
  192. struct drm_plane *plane;
  193. atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  194. crtc->primary->funcs->disable_plane(crtc->primary);
  195. drm_for_each_legacy_plane(plane, &crtc->dev->mode_config.plane_list) {
  196. if (plane->crtc != crtc)
  197. continue;
  198. plane->funcs->disable_plane(crtc->primary);
  199. plane->crtc = NULL;
  200. }
  201. }
  202. static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
  203. .mode_fixup = atmel_hlcdc_crtc_mode_fixup,
  204. .dpms = atmel_hlcdc_crtc_dpms,
  205. .mode_set = atmel_hlcdc_crtc_mode_set,
  206. .mode_set_base = atmel_hlcdc_crtc_mode_set_base,
  207. .prepare = atmel_hlcdc_crtc_prepare,
  208. .commit = atmel_hlcdc_crtc_commit,
  209. .disable = atmel_hlcdc_crtc_disable,
  210. };
  211. static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
  212. {
  213. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  214. drm_crtc_cleanup(c);
  215. kfree(crtc);
  216. }
  217. void atmel_hlcdc_crtc_cancel_page_flip(struct drm_crtc *c,
  218. struct drm_file *file)
  219. {
  220. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  221. struct drm_pending_vblank_event *event;
  222. struct drm_device *dev = c->dev;
  223. unsigned long flags;
  224. spin_lock_irqsave(&dev->event_lock, flags);
  225. event = crtc->event;
  226. if (event && event->base.file_priv == file) {
  227. event->base.destroy(&event->base);
  228. drm_vblank_put(dev, crtc->id);
  229. crtc->event = NULL;
  230. }
  231. spin_unlock_irqrestore(&dev->event_lock, flags);
  232. }
  233. static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
  234. {
  235. struct drm_device *dev = crtc->base.dev;
  236. unsigned long flags;
  237. spin_lock_irqsave(&dev->event_lock, flags);
  238. if (crtc->event) {
  239. drm_send_vblank_event(dev, crtc->id, crtc->event);
  240. drm_vblank_put(dev, crtc->id);
  241. crtc->event = NULL;
  242. }
  243. spin_unlock_irqrestore(&dev->event_lock, flags);
  244. }
  245. void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
  246. {
  247. drm_handle_vblank(c->dev, 0);
  248. atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
  249. }
  250. static int atmel_hlcdc_crtc_page_flip(struct drm_crtc *c,
  251. struct drm_framebuffer *fb,
  252. struct drm_pending_vblank_event *event,
  253. uint32_t page_flip_flags)
  254. {
  255. struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  256. struct atmel_hlcdc_plane_update_req req;
  257. struct drm_plane *plane = c->primary;
  258. struct drm_device *dev = c->dev;
  259. unsigned long flags;
  260. int ret = 0;
  261. spin_lock_irqsave(&dev->event_lock, flags);
  262. if (crtc->event)
  263. ret = -EBUSY;
  264. spin_unlock_irqrestore(&dev->event_lock, flags);
  265. if (ret)
  266. return ret;
  267. memset(&req, 0, sizeof(req));
  268. req.crtc_x = 0;
  269. req.crtc_y = 0;
  270. req.crtc_h = c->mode.crtc_vdisplay;
  271. req.crtc_w = c->mode.crtc_hdisplay;
  272. req.src_x = c->x << 16;
  273. req.src_y = c->y << 16;
  274. req.src_w = req.crtc_w << 16;
  275. req.src_h = req.crtc_h << 16;
  276. req.fb = fb;
  277. ret = atmel_hlcdc_plane_prepare_update_req(plane, &req, &c->hwmode);
  278. if (ret)
  279. return ret;
  280. if (event) {
  281. drm_vblank_get(c->dev, crtc->id);
  282. spin_lock_irqsave(&dev->event_lock, flags);
  283. crtc->event = event;
  284. spin_unlock_irqrestore(&dev->event_lock, flags);
  285. }
  286. ret = atmel_hlcdc_plane_apply_update_req(plane, &req);
  287. if (ret)
  288. crtc->event = NULL;
  289. else
  290. plane->fb = fb;
  291. return ret;
  292. }
  293. static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
  294. .page_flip = atmel_hlcdc_crtc_page_flip,
  295. .set_config = drm_crtc_helper_set_config,
  296. .destroy = atmel_hlcdc_crtc_destroy,
  297. };
  298. int atmel_hlcdc_crtc_create(struct drm_device *dev)
  299. {
  300. struct atmel_hlcdc_dc *dc = dev->dev_private;
  301. struct atmel_hlcdc_planes *planes = dc->planes;
  302. struct atmel_hlcdc_crtc *crtc;
  303. int ret;
  304. int i;
  305. crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
  306. if (!crtc)
  307. return -ENOMEM;
  308. crtc->dpms = DRM_MODE_DPMS_OFF;
  309. crtc->dc = dc;
  310. ret = drm_crtc_init_with_planes(dev, &crtc->base,
  311. &planes->primary->base,
  312. planes->cursor ? &planes->cursor->base : NULL,
  313. &atmel_hlcdc_crtc_funcs);
  314. if (ret < 0)
  315. goto fail;
  316. crtc->id = drm_crtc_index(&crtc->base);
  317. if (planes->cursor)
  318. planes->cursor->base.possible_crtcs = 1 << crtc->id;
  319. for (i = 0; i < planes->noverlays; i++)
  320. planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;
  321. drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
  322. dc->crtc = &crtc->base;
  323. return 0;
  324. fail:
  325. atmel_hlcdc_crtc_destroy(&crtc->base);
  326. return ret;
  327. }