hda_intel.c 61 KB

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  1. /*
  2. *
  3. * hda_intel.c - Implementation of primary alsa driver code base
  4. * for Intel HD Audio.
  5. *
  6. * Copyright(c) 2004 Intel Corporation. All rights reserved.
  7. *
  8. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9. * PeiSen Hou <pshou@realtek.com.tw>
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the Free
  13. * Software Foundation; either version 2 of the License, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program; if not, write to the Free Software Foundation, Inc., 59
  23. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  24. *
  25. * CONTACTS:
  26. *
  27. * Matt Jared matt.jared@intel.com
  28. * Andy Kopp andy.kopp@intel.com
  29. * Dan Kogan dan.d.kogan@intel.com
  30. *
  31. * CHANGES:
  32. *
  33. * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
  34. *
  35. */
  36. #include <linux/delay.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/dma-mapping.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/init.h>
  43. #include <linux/slab.h>
  44. #include <linux/pci.h>
  45. #include <linux/mutex.h>
  46. #include <linux/io.h>
  47. #include <linux/pm_runtime.h>
  48. #include <linux/clocksource.h>
  49. #include <linux/time.h>
  50. #include <linux/completion.h>
  51. #ifdef CONFIG_X86
  52. /* for snoop control */
  53. #include <asm/pgtable.h>
  54. #include <asm/cacheflush.h>
  55. #endif
  56. #include <sound/core.h>
  57. #include <sound/initval.h>
  58. #include <linux/vgaarb.h>
  59. #include <linux/vga_switcheroo.h>
  60. #include <linux/firmware.h>
  61. #include "hda_codec.h"
  62. #include "hda_controller.h"
  63. #include "hda_intel.h"
  64. /* position fix mode */
  65. enum {
  66. POS_FIX_AUTO,
  67. POS_FIX_LPIB,
  68. POS_FIX_POSBUF,
  69. POS_FIX_VIACOMBO,
  70. POS_FIX_COMBO,
  71. };
  72. /* Defines for ATI HD Audio support in SB450 south bridge */
  73. #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
  74. #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
  75. /* Defines for Nvidia HDA support */
  76. #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
  77. #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
  78. #define NVIDIA_HDA_ISTRM_COH 0x4d
  79. #define NVIDIA_HDA_OSTRM_COH 0x4c
  80. #define NVIDIA_HDA_ENABLE_COHBIT 0x01
  81. /* Defines for Intel SCH HDA snoop control */
  82. #define INTEL_SCH_HDA_DEVC 0x78
  83. #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
  84. /* Define IN stream 0 FIFO size offset in VIA controller */
  85. #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  86. /* Define VIA HD Audio Device ID*/
  87. #define VIA_HDAC_DEVICE_ID 0x3288
  88. /* max number of SDs */
  89. /* ICH, ATI and VIA have 4 playback and 4 capture */
  90. #define ICH6_NUM_CAPTURE 4
  91. #define ICH6_NUM_PLAYBACK 4
  92. /* ULI has 6 playback and 5 capture */
  93. #define ULI_NUM_CAPTURE 5
  94. #define ULI_NUM_PLAYBACK 6
  95. /* ATI HDMI may have up to 8 playbacks and 0 capture */
  96. #define ATIHDMI_NUM_CAPTURE 0
  97. #define ATIHDMI_NUM_PLAYBACK 8
  98. /* TERA has 4 playback and 3 capture */
  99. #define TERA_NUM_CAPTURE 3
  100. #define TERA_NUM_PLAYBACK 4
  101. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  102. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  103. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  104. static char *model[SNDRV_CARDS];
  105. static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  106. static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  107. static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  108. static int probe_only[SNDRV_CARDS];
  109. static int jackpoll_ms[SNDRV_CARDS];
  110. static bool single_cmd;
  111. static int enable_msi = -1;
  112. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  113. static char *patch[SNDRV_CARDS];
  114. #endif
  115. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  116. static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  117. CONFIG_SND_HDA_INPUT_BEEP_MODE};
  118. #endif
  119. module_param_array(index, int, NULL, 0444);
  120. MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  121. module_param_array(id, charp, NULL, 0444);
  122. MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  123. module_param_array(enable, bool, NULL, 0444);
  124. MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  125. module_param_array(model, charp, NULL, 0444);
  126. MODULE_PARM_DESC(model, "Use the given board model.");
  127. module_param_array(position_fix, int, NULL, 0444);
  128. MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  129. "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  130. module_param_array(bdl_pos_adj, int, NULL, 0644);
  131. MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  132. module_param_array(probe_mask, int, NULL, 0444);
  133. MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  134. module_param_array(probe_only, int, NULL, 0444);
  135. MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  136. module_param_array(jackpoll_ms, int, NULL, 0444);
  137. MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
  138. module_param(single_cmd, bool, 0444);
  139. MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  140. "(for debugging only).");
  141. module_param(enable_msi, bint, 0444);
  142. MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  143. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  144. module_param_array(patch, charp, NULL, 0444);
  145. MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  146. #endif
  147. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  148. module_param_array(beep_mode, bool, NULL, 0444);
  149. MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
  150. "(0=off, 1=on) (default=1).");
  151. #endif
  152. #ifdef CONFIG_PM
  153. static int param_set_xint(const char *val, const struct kernel_param *kp);
  154. static struct kernel_param_ops param_ops_xint = {
  155. .set = param_set_xint,
  156. .get = param_get_int,
  157. };
  158. #define param_check_xint param_check_int
  159. static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  160. module_param(power_save, xint, 0644);
  161. MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  162. "(in second, 0 = disable).");
  163. /* reset the HD-audio controller in power save mode.
  164. * this may give more power-saving, but will take longer time to
  165. * wake up.
  166. */
  167. static bool power_save_controller = 1;
  168. module_param(power_save_controller, bool, 0644);
  169. MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  170. #else
  171. #define power_save 0
  172. #endif /* CONFIG_PM */
  173. static int align_buffer_size = -1;
  174. module_param(align_buffer_size, bint, 0644);
  175. MODULE_PARM_DESC(align_buffer_size,
  176. "Force buffer and period sizes to be multiple of 128 bytes.");
  177. #ifdef CONFIG_X86
  178. static int hda_snoop = -1;
  179. module_param_named(snoop, hda_snoop, bint, 0444);
  180. MODULE_PARM_DESC(snoop, "Enable/disable snooping");
  181. #else
  182. #define hda_snoop true
  183. #endif
  184. MODULE_LICENSE("GPL");
  185. MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  186. "{Intel, ICH6M},"
  187. "{Intel, ICH7},"
  188. "{Intel, ESB2},"
  189. "{Intel, ICH8},"
  190. "{Intel, ICH9},"
  191. "{Intel, ICH10},"
  192. "{Intel, PCH},"
  193. "{Intel, CPT},"
  194. "{Intel, PPT},"
  195. "{Intel, LPT},"
  196. "{Intel, LPT_LP},"
  197. "{Intel, WPT_LP},"
  198. "{Intel, SPT},"
  199. "{Intel, SPT_LP},"
  200. "{Intel, HPT},"
  201. "{Intel, PBG},"
  202. "{Intel, SCH},"
  203. "{ATI, SB450},"
  204. "{ATI, SB600},"
  205. "{ATI, RS600},"
  206. "{ATI, RS690},"
  207. "{ATI, RS780},"
  208. "{ATI, R600},"
  209. "{ATI, RV630},"
  210. "{ATI, RV610},"
  211. "{ATI, RV670},"
  212. "{ATI, RV635},"
  213. "{ATI, RV620},"
  214. "{ATI, RV770},"
  215. "{VIA, VT8251},"
  216. "{VIA, VT8237A},"
  217. "{SiS, SIS966},"
  218. "{ULI, M5461}}");
  219. MODULE_DESCRIPTION("Intel HDA driver");
  220. #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
  221. #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
  222. #define SUPPORT_VGA_SWITCHEROO
  223. #endif
  224. #endif
  225. /*
  226. */
  227. /* driver types */
  228. enum {
  229. AZX_DRIVER_ICH,
  230. AZX_DRIVER_PCH,
  231. AZX_DRIVER_SCH,
  232. AZX_DRIVER_HDMI,
  233. AZX_DRIVER_ATI,
  234. AZX_DRIVER_ATIHDMI,
  235. AZX_DRIVER_ATIHDMI_NS,
  236. AZX_DRIVER_VIA,
  237. AZX_DRIVER_SIS,
  238. AZX_DRIVER_ULI,
  239. AZX_DRIVER_NVIDIA,
  240. AZX_DRIVER_TERA,
  241. AZX_DRIVER_CTX,
  242. AZX_DRIVER_CTHDA,
  243. AZX_DRIVER_CMEDIA,
  244. AZX_DRIVER_GENERIC,
  245. AZX_NUM_DRIVERS, /* keep this as last entry */
  246. };
  247. #define azx_get_snoop_type(chip) \
  248. (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
  249. #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
  250. /* quirks for old Intel chipsets */
  251. #define AZX_DCAPS_INTEL_ICH \
  252. (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
  253. /* quirks for Intel PCH */
  254. #define AZX_DCAPS_INTEL_PCH_NOPM \
  255. (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
  256. AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
  257. #define AZX_DCAPS_INTEL_PCH \
  258. (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
  259. #define AZX_DCAPS_INTEL_HASWELL \
  260. (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
  261. AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
  262. AZX_DCAPS_SNOOP_TYPE(SCH))
  263. /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
  264. #define AZX_DCAPS_INTEL_BROADWELL \
  265. (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
  266. AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
  267. AZX_DCAPS_SNOOP_TYPE(SCH))
  268. #define AZX_DCAPS_INTEL_BAYTRAIL \
  269. (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
  270. #define AZX_DCAPS_INTEL_BRASWELL \
  271. (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
  272. #define AZX_DCAPS_INTEL_SKYLAKE \
  273. (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
  274. AZX_DCAPS_I915_POWERWELL)
  275. /* quirks for ATI SB / AMD Hudson */
  276. #define AZX_DCAPS_PRESET_ATI_SB \
  277. (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
  278. AZX_DCAPS_SNOOP_TYPE(ATI))
  279. /* quirks for ATI/AMD HDMI */
  280. #define AZX_DCAPS_PRESET_ATI_HDMI \
  281. (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
  282. AZX_DCAPS_NO_MSI64)
  283. /* quirks for ATI HDMI with snoop off */
  284. #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
  285. (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
  286. /* quirks for Nvidia */
  287. #define AZX_DCAPS_PRESET_NVIDIA \
  288. (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
  289. AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
  290. AZX_DCAPS_SNOOP_TYPE(NVIDIA))
  291. #define AZX_DCAPS_PRESET_CTHDA \
  292. (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
  293. AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
  294. /*
  295. * VGA-switcher support
  296. */
  297. #ifdef SUPPORT_VGA_SWITCHEROO
  298. #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
  299. #else
  300. #define use_vga_switcheroo(chip) 0
  301. #endif
  302. static char *driver_short_names[] = {
  303. [AZX_DRIVER_ICH] = "HDA Intel",
  304. [AZX_DRIVER_PCH] = "HDA Intel PCH",
  305. [AZX_DRIVER_SCH] = "HDA Intel MID",
  306. [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
  307. [AZX_DRIVER_ATI] = "HDA ATI SB",
  308. [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
  309. [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
  310. [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
  311. [AZX_DRIVER_SIS] = "HDA SIS966",
  312. [AZX_DRIVER_ULI] = "HDA ULI M5461",
  313. [AZX_DRIVER_NVIDIA] = "HDA NVidia",
  314. [AZX_DRIVER_TERA] = "HDA Teradici",
  315. [AZX_DRIVER_CTX] = "HDA Creative",
  316. [AZX_DRIVER_CTHDA] = "HDA Creative",
  317. [AZX_DRIVER_CMEDIA] = "HDA C-Media",
  318. [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
  319. };
  320. #ifdef CONFIG_X86
  321. static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
  322. {
  323. int pages;
  324. if (azx_snoop(chip))
  325. return;
  326. if (!dmab || !dmab->area || !dmab->bytes)
  327. return;
  328. #ifdef CONFIG_SND_DMA_SGBUF
  329. if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
  330. struct snd_sg_buf *sgbuf = dmab->private_data;
  331. if (chip->driver_type == AZX_DRIVER_CMEDIA)
  332. return; /* deal with only CORB/RIRB buffers */
  333. if (on)
  334. set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
  335. else
  336. set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
  337. return;
  338. }
  339. #endif
  340. pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
  341. if (on)
  342. set_memory_wc((unsigned long)dmab->area, pages);
  343. else
  344. set_memory_wb((unsigned long)dmab->area, pages);
  345. }
  346. static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
  347. bool on)
  348. {
  349. __mark_pages_wc(chip, buf, on);
  350. }
  351. static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
  352. struct snd_pcm_substream *substream, bool on)
  353. {
  354. if (azx_dev->wc_marked != on) {
  355. __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
  356. azx_dev->wc_marked = on;
  357. }
  358. }
  359. #else
  360. /* NOP for other archs */
  361. static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
  362. bool on)
  363. {
  364. }
  365. static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
  366. struct snd_pcm_substream *substream, bool on)
  367. {
  368. }
  369. #endif
  370. static int azx_acquire_irq(struct azx *chip, int do_disconnect);
  371. /*
  372. * initialize the PCI registers
  373. */
  374. /* update bits in a PCI register byte */
  375. static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
  376. unsigned char mask, unsigned char val)
  377. {
  378. unsigned char data;
  379. pci_read_config_byte(pci, reg, &data);
  380. data &= ~mask;
  381. data |= (val & mask);
  382. pci_write_config_byte(pci, reg, data);
  383. }
  384. static void azx_init_pci(struct azx *chip)
  385. {
  386. int snoop_type = azx_get_snoop_type(chip);
  387. /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
  388. * TCSEL == Traffic Class Select Register, which sets PCI express QOS
  389. * Ensuring these bits are 0 clears playback static on some HD Audio
  390. * codecs.
  391. * The PCI register TCSEL is defined in the Intel manuals.
  392. */
  393. if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
  394. dev_dbg(chip->card->dev, "Clearing TCSEL\n");
  395. update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
  396. }
  397. /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
  398. * we need to enable snoop.
  399. */
  400. if (snoop_type == AZX_SNOOP_TYPE_ATI) {
  401. dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
  402. azx_snoop(chip));
  403. update_pci_byte(chip->pci,
  404. ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
  405. azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
  406. }
  407. /* For NVIDIA HDA, enable snoop */
  408. if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
  409. dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
  410. azx_snoop(chip));
  411. update_pci_byte(chip->pci,
  412. NVIDIA_HDA_TRANSREG_ADDR,
  413. 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
  414. update_pci_byte(chip->pci,
  415. NVIDIA_HDA_ISTRM_COH,
  416. 0x01, NVIDIA_HDA_ENABLE_COHBIT);
  417. update_pci_byte(chip->pci,
  418. NVIDIA_HDA_OSTRM_COH,
  419. 0x01, NVIDIA_HDA_ENABLE_COHBIT);
  420. }
  421. /* Enable SCH/PCH snoop if needed */
  422. if (snoop_type == AZX_SNOOP_TYPE_SCH) {
  423. unsigned short snoop;
  424. pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
  425. if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
  426. (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
  427. snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
  428. if (!azx_snoop(chip))
  429. snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
  430. pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
  431. pci_read_config_word(chip->pci,
  432. INTEL_SCH_HDA_DEVC, &snoop);
  433. }
  434. dev_dbg(chip->card->dev, "SCH snoop: %s\n",
  435. (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
  436. "Disabled" : "Enabled");
  437. }
  438. }
  439. static void hda_intel_init_chip(struct azx *chip, bool full_reset)
  440. {
  441. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  442. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
  443. hda_set_codec_wakeup(hda, true);
  444. azx_init_chip(chip, full_reset);
  445. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
  446. hda_set_codec_wakeup(hda, false);
  447. }
  448. /* calculate runtime delay from LPIB */
  449. static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
  450. unsigned int pos)
  451. {
  452. struct snd_pcm_substream *substream = azx_dev->core.substream;
  453. int stream = substream->stream;
  454. unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
  455. int delay;
  456. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  457. delay = pos - lpib_pos;
  458. else
  459. delay = lpib_pos - pos;
  460. if (delay < 0) {
  461. if (delay >= azx_dev->core.delay_negative_threshold)
  462. delay = 0;
  463. else
  464. delay += azx_dev->core.bufsize;
  465. }
  466. if (delay >= azx_dev->core.period_bytes) {
  467. dev_info(chip->card->dev,
  468. "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
  469. delay, azx_dev->core.period_bytes);
  470. delay = 0;
  471. chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
  472. chip->get_delay[stream] = NULL;
  473. }
  474. return bytes_to_frames(substream->runtime, delay);
  475. }
  476. static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
  477. /* called from IRQ */
  478. static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
  479. {
  480. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  481. int ok;
  482. ok = azx_position_ok(chip, azx_dev);
  483. if (ok == 1) {
  484. azx_dev->irq_pending = 0;
  485. return ok;
  486. } else if (ok == 0) {
  487. /* bogus IRQ, process it later */
  488. azx_dev->irq_pending = 1;
  489. schedule_work(&hda->irq_pending_work);
  490. }
  491. return 0;
  492. }
  493. /* Enable/disable i915 display power for the link */
  494. static int azx_intel_link_power(struct azx *chip, bool enable)
  495. {
  496. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  497. return hda_display_power(hda, enable);
  498. }
  499. /*
  500. * Check whether the current DMA position is acceptable for updating
  501. * periods. Returns non-zero if it's OK.
  502. *
  503. * Many HD-audio controllers appear pretty inaccurate about
  504. * the update-IRQ timing. The IRQ is issued before actually the
  505. * data is processed. So, we need to process it afterwords in a
  506. * workqueue.
  507. */
  508. static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
  509. {
  510. struct snd_pcm_substream *substream = azx_dev->core.substream;
  511. int stream = substream->stream;
  512. u32 wallclk;
  513. unsigned int pos;
  514. wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
  515. if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
  516. return -1; /* bogus (too early) interrupt */
  517. if (chip->get_position[stream])
  518. pos = chip->get_position[stream](chip, azx_dev);
  519. else { /* use the position buffer as default */
  520. pos = azx_get_pos_posbuf(chip, azx_dev);
  521. if (!pos || pos == (u32)-1) {
  522. dev_info(chip->card->dev,
  523. "Invalid position buffer, using LPIB read method instead.\n");
  524. chip->get_position[stream] = azx_get_pos_lpib;
  525. if (chip->get_position[0] == azx_get_pos_lpib &&
  526. chip->get_position[1] == azx_get_pos_lpib)
  527. azx_bus(chip)->use_posbuf = false;
  528. pos = azx_get_pos_lpib(chip, azx_dev);
  529. chip->get_delay[stream] = NULL;
  530. } else {
  531. chip->get_position[stream] = azx_get_pos_posbuf;
  532. if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
  533. chip->get_delay[stream] = azx_get_delay_from_lpib;
  534. }
  535. }
  536. if (pos >= azx_dev->core.bufsize)
  537. pos = 0;
  538. if (WARN_ONCE(!azx_dev->core.period_bytes,
  539. "hda-intel: zero azx_dev->period_bytes"))
  540. return -1; /* this shouldn't happen! */
  541. if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
  542. pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
  543. /* NG - it's below the first next period boundary */
  544. return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
  545. azx_dev->core.start_wallclk += wallclk;
  546. return 1; /* OK, it's fine */
  547. }
  548. /*
  549. * The work for pending PCM period updates.
  550. */
  551. static void azx_irq_pending_work(struct work_struct *work)
  552. {
  553. struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
  554. struct azx *chip = &hda->chip;
  555. struct hdac_bus *bus = azx_bus(chip);
  556. struct hdac_stream *s;
  557. int pending, ok;
  558. if (!hda->irq_pending_warned) {
  559. dev_info(chip->card->dev,
  560. "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
  561. chip->card->number);
  562. hda->irq_pending_warned = 1;
  563. }
  564. for (;;) {
  565. pending = 0;
  566. spin_lock_irq(&bus->reg_lock);
  567. list_for_each_entry(s, &bus->stream_list, list) {
  568. struct azx_dev *azx_dev = stream_to_azx_dev(s);
  569. if (!azx_dev->irq_pending ||
  570. !s->substream ||
  571. !s->running)
  572. continue;
  573. ok = azx_position_ok(chip, azx_dev);
  574. if (ok > 0) {
  575. azx_dev->irq_pending = 0;
  576. spin_unlock(&bus->reg_lock);
  577. snd_pcm_period_elapsed(s->substream);
  578. spin_lock(&bus->reg_lock);
  579. } else if (ok < 0) {
  580. pending = 0; /* too early */
  581. } else
  582. pending++;
  583. }
  584. spin_unlock_irq(&bus->reg_lock);
  585. if (!pending)
  586. return;
  587. msleep(1);
  588. }
  589. }
  590. /* clear irq_pending flags and assure no on-going workq */
  591. static void azx_clear_irq_pending(struct azx *chip)
  592. {
  593. struct hdac_bus *bus = azx_bus(chip);
  594. struct hdac_stream *s;
  595. spin_lock_irq(&bus->reg_lock);
  596. list_for_each_entry(s, &bus->stream_list, list) {
  597. struct azx_dev *azx_dev = stream_to_azx_dev(s);
  598. azx_dev->irq_pending = 0;
  599. }
  600. spin_unlock_irq(&bus->reg_lock);
  601. }
  602. static int azx_acquire_irq(struct azx *chip, int do_disconnect)
  603. {
  604. struct hdac_bus *bus = azx_bus(chip);
  605. if (request_irq(chip->pci->irq, azx_interrupt,
  606. chip->msi ? 0 : IRQF_SHARED,
  607. KBUILD_MODNAME, chip)) {
  608. dev_err(chip->card->dev,
  609. "unable to grab IRQ %d, disabling device\n",
  610. chip->pci->irq);
  611. if (do_disconnect)
  612. snd_card_disconnect(chip->card);
  613. return -1;
  614. }
  615. bus->irq = chip->pci->irq;
  616. pci_intx(chip->pci, !chip->msi);
  617. return 0;
  618. }
  619. /* get the current DMA position with correction on VIA chips */
  620. static unsigned int azx_via_get_position(struct azx *chip,
  621. struct azx_dev *azx_dev)
  622. {
  623. unsigned int link_pos, mini_pos, bound_pos;
  624. unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
  625. unsigned int fifo_size;
  626. link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
  627. if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  628. /* Playback, no problem using link position */
  629. return link_pos;
  630. }
  631. /* Capture */
  632. /* For new chipset,
  633. * use mod to get the DMA position just like old chipset
  634. */
  635. mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
  636. mod_dma_pos %= azx_dev->core.period_bytes;
  637. /* azx_dev->fifo_size can't get FIFO size of in stream.
  638. * Get from base address + offset.
  639. */
  640. fifo_size = readw(azx_bus(chip)->remap_addr +
  641. VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
  642. if (azx_dev->insufficient) {
  643. /* Link position never gather than FIFO size */
  644. if (link_pos <= fifo_size)
  645. return 0;
  646. azx_dev->insufficient = 0;
  647. }
  648. if (link_pos <= fifo_size)
  649. mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
  650. else
  651. mini_pos = link_pos - fifo_size;
  652. /* Find nearest previous boudary */
  653. mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
  654. mod_link_pos = link_pos % azx_dev->core.period_bytes;
  655. if (mod_link_pos >= fifo_size)
  656. bound_pos = link_pos - mod_link_pos;
  657. else if (mod_dma_pos >= mod_mini_pos)
  658. bound_pos = mini_pos - mod_mini_pos;
  659. else {
  660. bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
  661. if (bound_pos >= azx_dev->core.bufsize)
  662. bound_pos = 0;
  663. }
  664. /* Calculate real DMA position we want */
  665. return bound_pos + mod_dma_pos;
  666. }
  667. #ifdef CONFIG_PM
  668. static DEFINE_MUTEX(card_list_lock);
  669. static LIST_HEAD(card_list);
  670. static void azx_add_card_list(struct azx *chip)
  671. {
  672. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  673. mutex_lock(&card_list_lock);
  674. list_add(&hda->list, &card_list);
  675. mutex_unlock(&card_list_lock);
  676. }
  677. static void azx_del_card_list(struct azx *chip)
  678. {
  679. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  680. mutex_lock(&card_list_lock);
  681. list_del_init(&hda->list);
  682. mutex_unlock(&card_list_lock);
  683. }
  684. /* trigger power-save check at writing parameter */
  685. static int param_set_xint(const char *val, const struct kernel_param *kp)
  686. {
  687. struct hda_intel *hda;
  688. struct azx *chip;
  689. int prev = power_save;
  690. int ret = param_set_int(val, kp);
  691. if (ret || prev == power_save)
  692. return ret;
  693. mutex_lock(&card_list_lock);
  694. list_for_each_entry(hda, &card_list, list) {
  695. chip = &hda->chip;
  696. if (!hda->probe_continued || chip->disabled)
  697. continue;
  698. snd_hda_set_power_save(&chip->bus, power_save * 1000);
  699. }
  700. mutex_unlock(&card_list_lock);
  701. return 0;
  702. }
  703. #else
  704. #define azx_add_card_list(chip) /* NOP */
  705. #define azx_del_card_list(chip) /* NOP */
  706. #endif /* CONFIG_PM */
  707. #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
  708. /*
  709. * power management
  710. */
  711. static int azx_suspend(struct device *dev)
  712. {
  713. struct snd_card *card = dev_get_drvdata(dev);
  714. struct azx *chip;
  715. struct hda_intel *hda;
  716. struct hdac_bus *bus;
  717. if (!card)
  718. return 0;
  719. chip = card->private_data;
  720. hda = container_of(chip, struct hda_intel, chip);
  721. if (chip->disabled || hda->init_failed)
  722. return 0;
  723. bus = azx_bus(chip);
  724. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  725. azx_clear_irq_pending(chip);
  726. azx_stop_chip(chip);
  727. azx_enter_link_reset(chip);
  728. if (bus->irq >= 0) {
  729. free_irq(bus->irq, chip);
  730. bus->irq = -1;
  731. }
  732. if (chip->msi)
  733. pci_disable_msi(chip->pci);
  734. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
  735. && hda->need_i915_power)
  736. hda_display_power(hda, false);
  737. return 0;
  738. }
  739. static int azx_resume(struct device *dev)
  740. {
  741. struct pci_dev *pci = to_pci_dev(dev);
  742. struct snd_card *card = dev_get_drvdata(dev);
  743. struct azx *chip;
  744. struct hda_intel *hda;
  745. if (!card)
  746. return 0;
  747. chip = card->private_data;
  748. hda = container_of(chip, struct hda_intel, chip);
  749. if (chip->disabled || hda->init_failed)
  750. return 0;
  751. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
  752. && hda->need_i915_power) {
  753. hda_display_power(hda, true);
  754. haswell_set_bclk(hda);
  755. }
  756. if (chip->msi)
  757. if (pci_enable_msi(pci) < 0)
  758. chip->msi = 0;
  759. if (azx_acquire_irq(chip, 1) < 0)
  760. return -EIO;
  761. azx_init_pci(chip);
  762. hda_intel_init_chip(chip, true);
  763. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  764. return 0;
  765. }
  766. #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
  767. #ifdef CONFIG_PM
  768. static int azx_runtime_suspend(struct device *dev)
  769. {
  770. struct snd_card *card = dev_get_drvdata(dev);
  771. struct azx *chip;
  772. struct hda_intel *hda;
  773. if (!card)
  774. return 0;
  775. chip = card->private_data;
  776. hda = container_of(chip, struct hda_intel, chip);
  777. if (chip->disabled || hda->init_failed)
  778. return 0;
  779. if (!azx_has_pm_runtime(chip))
  780. return 0;
  781. /* enable controller wake up event */
  782. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
  783. STATESTS_INT_MASK);
  784. azx_stop_chip(chip);
  785. azx_enter_link_reset(chip);
  786. azx_clear_irq_pending(chip);
  787. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
  788. && hda->need_i915_power)
  789. hda_display_power(hda, false);
  790. return 0;
  791. }
  792. static int azx_runtime_resume(struct device *dev)
  793. {
  794. struct snd_card *card = dev_get_drvdata(dev);
  795. struct azx *chip;
  796. struct hda_intel *hda;
  797. struct hda_codec *codec;
  798. int status;
  799. if (!card)
  800. return 0;
  801. chip = card->private_data;
  802. hda = container_of(chip, struct hda_intel, chip);
  803. if (chip->disabled || hda->init_failed)
  804. return 0;
  805. if (!azx_has_pm_runtime(chip))
  806. return 0;
  807. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
  808. && hda->need_i915_power) {
  809. hda_display_power(hda, true);
  810. haswell_set_bclk(hda);
  811. /* toggle codec wakeup bit for STATESTS read */
  812. hda_set_codec_wakeup(hda, true);
  813. hda_set_codec_wakeup(hda, false);
  814. }
  815. /* Read STATESTS before controller reset */
  816. status = azx_readw(chip, STATESTS);
  817. azx_init_pci(chip);
  818. hda_intel_init_chip(chip, true);
  819. if (status) {
  820. list_for_each_codec(codec, &chip->bus)
  821. if (status & (1 << codec->addr))
  822. schedule_delayed_work(&codec->jackpoll_work,
  823. codec->jackpoll_interval);
  824. }
  825. /* disable controller Wake Up event*/
  826. azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
  827. ~STATESTS_INT_MASK);
  828. return 0;
  829. }
  830. static int azx_runtime_idle(struct device *dev)
  831. {
  832. struct snd_card *card = dev_get_drvdata(dev);
  833. struct azx *chip;
  834. struct hda_intel *hda;
  835. if (!card)
  836. return 0;
  837. chip = card->private_data;
  838. hda = container_of(chip, struct hda_intel, chip);
  839. if (chip->disabled || hda->init_failed)
  840. return 0;
  841. if (!power_save_controller || !azx_has_pm_runtime(chip) ||
  842. azx_bus(chip)->codec_powered)
  843. return -EBUSY;
  844. return 0;
  845. }
  846. static const struct dev_pm_ops azx_pm = {
  847. SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
  848. SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
  849. };
  850. #define AZX_PM_OPS &azx_pm
  851. #else
  852. #define AZX_PM_OPS NULL
  853. #endif /* CONFIG_PM */
  854. static int azx_probe_continue(struct azx *chip);
  855. #ifdef SUPPORT_VGA_SWITCHEROO
  856. static struct pci_dev *get_bound_vga(struct pci_dev *pci);
  857. static void azx_vs_set_state(struct pci_dev *pci,
  858. enum vga_switcheroo_state state)
  859. {
  860. struct snd_card *card = pci_get_drvdata(pci);
  861. struct azx *chip = card->private_data;
  862. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  863. bool disabled;
  864. wait_for_completion(&hda->probe_wait);
  865. if (hda->init_failed)
  866. return;
  867. disabled = (state == VGA_SWITCHEROO_OFF);
  868. if (chip->disabled == disabled)
  869. return;
  870. if (!hda->probe_continued) {
  871. chip->disabled = disabled;
  872. if (!disabled) {
  873. dev_info(chip->card->dev,
  874. "Start delayed initialization\n");
  875. if (azx_probe_continue(chip) < 0) {
  876. dev_err(chip->card->dev, "initialization error\n");
  877. hda->init_failed = true;
  878. }
  879. }
  880. } else {
  881. dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
  882. disabled ? "Disabling" : "Enabling");
  883. if (disabled) {
  884. pm_runtime_put_sync_suspend(card->dev);
  885. azx_suspend(card->dev);
  886. /* when we get suspended by vga switcheroo we end up in D3cold,
  887. * however we have no ACPI handle, so pci/acpi can't put us there,
  888. * put ourselves there */
  889. pci->current_state = PCI_D3cold;
  890. chip->disabled = true;
  891. if (snd_hda_lock_devices(&chip->bus))
  892. dev_warn(chip->card->dev,
  893. "Cannot lock devices!\n");
  894. } else {
  895. snd_hda_unlock_devices(&chip->bus);
  896. pm_runtime_get_noresume(card->dev);
  897. chip->disabled = false;
  898. azx_resume(card->dev);
  899. }
  900. }
  901. }
  902. static bool azx_vs_can_switch(struct pci_dev *pci)
  903. {
  904. struct snd_card *card = pci_get_drvdata(pci);
  905. struct azx *chip = card->private_data;
  906. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  907. wait_for_completion(&hda->probe_wait);
  908. if (hda->init_failed)
  909. return false;
  910. if (chip->disabled || !hda->probe_continued)
  911. return true;
  912. if (snd_hda_lock_devices(&chip->bus))
  913. return false;
  914. snd_hda_unlock_devices(&chip->bus);
  915. return true;
  916. }
  917. static void init_vga_switcheroo(struct azx *chip)
  918. {
  919. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  920. struct pci_dev *p = get_bound_vga(chip->pci);
  921. if (p) {
  922. dev_info(chip->card->dev,
  923. "Handle VGA-switcheroo audio client\n");
  924. hda->use_vga_switcheroo = 1;
  925. pci_dev_put(p);
  926. }
  927. }
  928. static const struct vga_switcheroo_client_ops azx_vs_ops = {
  929. .set_gpu_state = azx_vs_set_state,
  930. .can_switch = azx_vs_can_switch,
  931. };
  932. static int register_vga_switcheroo(struct azx *chip)
  933. {
  934. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  935. int err;
  936. if (!hda->use_vga_switcheroo)
  937. return 0;
  938. /* FIXME: currently only handling DIS controller
  939. * is there any machine with two switchable HDMI audio controllers?
  940. */
  941. err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
  942. VGA_SWITCHEROO_DIS,
  943. hda->probe_continued);
  944. if (err < 0)
  945. return err;
  946. hda->vga_switcheroo_registered = 1;
  947. /* register as an optimus hdmi audio power domain */
  948. vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
  949. &hda->hdmi_pm_domain);
  950. return 0;
  951. }
  952. #else
  953. #define init_vga_switcheroo(chip) /* NOP */
  954. #define register_vga_switcheroo(chip) 0
  955. #define check_hdmi_disabled(pci) false
  956. #endif /* SUPPORT_VGA_SWITCHER */
  957. /*
  958. * destructor
  959. */
  960. static int azx_free(struct azx *chip)
  961. {
  962. struct pci_dev *pci = chip->pci;
  963. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  964. struct hdac_bus *bus = azx_bus(chip);
  965. if (azx_has_pm_runtime(chip) && chip->running)
  966. pm_runtime_get_noresume(&pci->dev);
  967. azx_del_card_list(chip);
  968. hda->init_failed = 1; /* to be sure */
  969. complete_all(&hda->probe_wait);
  970. if (use_vga_switcheroo(hda)) {
  971. if (chip->disabled && hda->probe_continued)
  972. snd_hda_unlock_devices(&chip->bus);
  973. if (hda->vga_switcheroo_registered)
  974. vga_switcheroo_unregister_client(chip->pci);
  975. }
  976. if (bus->chip_init) {
  977. azx_clear_irq_pending(chip);
  978. azx_stop_all_streams(chip);
  979. azx_stop_chip(chip);
  980. }
  981. if (bus->irq >= 0)
  982. free_irq(bus->irq, (void*)chip);
  983. if (chip->msi)
  984. pci_disable_msi(chip->pci);
  985. iounmap(bus->remap_addr);
  986. azx_free_stream_pages(chip);
  987. azx_free_streams(chip);
  988. snd_hdac_bus_exit(bus);
  989. if (chip->region_requested)
  990. pci_release_regions(chip->pci);
  991. pci_disable_device(chip->pci);
  992. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  993. release_firmware(chip->fw);
  994. #endif
  995. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
  996. if (hda->need_i915_power)
  997. hda_display_power(hda, false);
  998. hda_i915_exit(hda);
  999. }
  1000. kfree(hda);
  1001. return 0;
  1002. }
  1003. static int azx_dev_disconnect(struct snd_device *device)
  1004. {
  1005. struct azx *chip = device->device_data;
  1006. chip->bus.shutdown = 1;
  1007. return 0;
  1008. }
  1009. static int azx_dev_free(struct snd_device *device)
  1010. {
  1011. return azx_free(device->device_data);
  1012. }
  1013. #ifdef SUPPORT_VGA_SWITCHEROO
  1014. /*
  1015. * Check of disabled HDMI controller by vga-switcheroo
  1016. */
  1017. static struct pci_dev *get_bound_vga(struct pci_dev *pci)
  1018. {
  1019. struct pci_dev *p;
  1020. /* check only discrete GPU */
  1021. switch (pci->vendor) {
  1022. case PCI_VENDOR_ID_ATI:
  1023. case PCI_VENDOR_ID_AMD:
  1024. case PCI_VENDOR_ID_NVIDIA:
  1025. if (pci->devfn == 1) {
  1026. p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
  1027. pci->bus->number, 0);
  1028. if (p) {
  1029. if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
  1030. return p;
  1031. pci_dev_put(p);
  1032. }
  1033. }
  1034. break;
  1035. }
  1036. return NULL;
  1037. }
  1038. static bool check_hdmi_disabled(struct pci_dev *pci)
  1039. {
  1040. bool vga_inactive = false;
  1041. struct pci_dev *p = get_bound_vga(pci);
  1042. if (p) {
  1043. if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
  1044. vga_inactive = true;
  1045. pci_dev_put(p);
  1046. }
  1047. return vga_inactive;
  1048. }
  1049. #endif /* SUPPORT_VGA_SWITCHEROO */
  1050. /*
  1051. * white/black-listing for position_fix
  1052. */
  1053. static struct snd_pci_quirk position_fix_list[] = {
  1054. SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
  1055. SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
  1056. SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
  1057. SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
  1058. SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
  1059. SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
  1060. SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
  1061. SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
  1062. SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
  1063. SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
  1064. SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
  1065. SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
  1066. SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
  1067. SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
  1068. {}
  1069. };
  1070. static int check_position_fix(struct azx *chip, int fix)
  1071. {
  1072. const struct snd_pci_quirk *q;
  1073. switch (fix) {
  1074. case POS_FIX_AUTO:
  1075. case POS_FIX_LPIB:
  1076. case POS_FIX_POSBUF:
  1077. case POS_FIX_VIACOMBO:
  1078. case POS_FIX_COMBO:
  1079. return fix;
  1080. }
  1081. q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
  1082. if (q) {
  1083. dev_info(chip->card->dev,
  1084. "position_fix set to %d for device %04x:%04x\n",
  1085. q->value, q->subvendor, q->subdevice);
  1086. return q->value;
  1087. }
  1088. /* Check VIA/ATI HD Audio Controller exist */
  1089. if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
  1090. dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
  1091. return POS_FIX_VIACOMBO;
  1092. }
  1093. if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
  1094. dev_dbg(chip->card->dev, "Using LPIB position fix\n");
  1095. return POS_FIX_LPIB;
  1096. }
  1097. return POS_FIX_AUTO;
  1098. }
  1099. static void assign_position_fix(struct azx *chip, int fix)
  1100. {
  1101. static azx_get_pos_callback_t callbacks[] = {
  1102. [POS_FIX_AUTO] = NULL,
  1103. [POS_FIX_LPIB] = azx_get_pos_lpib,
  1104. [POS_FIX_POSBUF] = azx_get_pos_posbuf,
  1105. [POS_FIX_VIACOMBO] = azx_via_get_position,
  1106. [POS_FIX_COMBO] = azx_get_pos_lpib,
  1107. };
  1108. chip->get_position[0] = chip->get_position[1] = callbacks[fix];
  1109. /* combo mode uses LPIB only for playback */
  1110. if (fix == POS_FIX_COMBO)
  1111. chip->get_position[1] = NULL;
  1112. if (fix == POS_FIX_POSBUF &&
  1113. (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
  1114. chip->get_delay[0] = chip->get_delay[1] =
  1115. azx_get_delay_from_lpib;
  1116. }
  1117. }
  1118. /*
  1119. * black-lists for probe_mask
  1120. */
  1121. static struct snd_pci_quirk probe_mask_list[] = {
  1122. /* Thinkpad often breaks the controller communication when accessing
  1123. * to the non-working (or non-existing) modem codec slot.
  1124. */
  1125. SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
  1126. SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
  1127. SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
  1128. /* broken BIOS */
  1129. SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
  1130. /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
  1131. SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
  1132. /* forced codec slots */
  1133. SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
  1134. SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
  1135. /* WinFast VP200 H (Teradici) user reported broken communication */
  1136. SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
  1137. {}
  1138. };
  1139. #define AZX_FORCE_CODEC_MASK 0x100
  1140. static void check_probe_mask(struct azx *chip, int dev)
  1141. {
  1142. const struct snd_pci_quirk *q;
  1143. chip->codec_probe_mask = probe_mask[dev];
  1144. if (chip->codec_probe_mask == -1) {
  1145. q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
  1146. if (q) {
  1147. dev_info(chip->card->dev,
  1148. "probe_mask set to 0x%x for device %04x:%04x\n",
  1149. q->value, q->subvendor, q->subdevice);
  1150. chip->codec_probe_mask = q->value;
  1151. }
  1152. }
  1153. /* check forced option */
  1154. if (chip->codec_probe_mask != -1 &&
  1155. (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
  1156. azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
  1157. dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
  1158. (int)azx_bus(chip)->codec_mask);
  1159. }
  1160. }
  1161. /*
  1162. * white/black-list for enable_msi
  1163. */
  1164. static struct snd_pci_quirk msi_black_list[] = {
  1165. SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
  1166. SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
  1167. SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
  1168. SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
  1169. SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
  1170. SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
  1171. SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
  1172. SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
  1173. SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
  1174. SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
  1175. {}
  1176. };
  1177. static void check_msi(struct azx *chip)
  1178. {
  1179. const struct snd_pci_quirk *q;
  1180. if (enable_msi >= 0) {
  1181. chip->msi = !!enable_msi;
  1182. return;
  1183. }
  1184. chip->msi = 1; /* enable MSI as default */
  1185. q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
  1186. if (q) {
  1187. dev_info(chip->card->dev,
  1188. "msi for device %04x:%04x set to %d\n",
  1189. q->subvendor, q->subdevice, q->value);
  1190. chip->msi = q->value;
  1191. return;
  1192. }
  1193. /* NVidia chipsets seem to cause troubles with MSI */
  1194. if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
  1195. dev_info(chip->card->dev, "Disabling MSI\n");
  1196. chip->msi = 0;
  1197. }
  1198. }
  1199. /* check the snoop mode availability */
  1200. static void azx_check_snoop_available(struct azx *chip)
  1201. {
  1202. int snoop = hda_snoop;
  1203. if (snoop >= 0) {
  1204. dev_info(chip->card->dev, "Force to %s mode by module option\n",
  1205. snoop ? "snoop" : "non-snoop");
  1206. chip->snoop = snoop;
  1207. return;
  1208. }
  1209. snoop = true;
  1210. if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
  1211. chip->driver_type == AZX_DRIVER_VIA) {
  1212. /* force to non-snoop mode for a new VIA controller
  1213. * when BIOS is set
  1214. */
  1215. u8 val;
  1216. pci_read_config_byte(chip->pci, 0x42, &val);
  1217. if (!(val & 0x80) && chip->pci->revision == 0x30)
  1218. snoop = false;
  1219. }
  1220. if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
  1221. snoop = false;
  1222. chip->snoop = snoop;
  1223. if (!snoop)
  1224. dev_info(chip->card->dev, "Force to non-snoop mode\n");
  1225. }
  1226. static void azx_probe_work(struct work_struct *work)
  1227. {
  1228. struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
  1229. azx_probe_continue(&hda->chip);
  1230. }
  1231. /*
  1232. * constructor
  1233. */
  1234. static const struct hdac_io_ops pci_hda_io_ops;
  1235. static const struct hda_controller_ops pci_hda_ops;
  1236. static int azx_create(struct snd_card *card, struct pci_dev *pci,
  1237. int dev, unsigned int driver_caps,
  1238. struct azx **rchip)
  1239. {
  1240. static struct snd_device_ops ops = {
  1241. .dev_disconnect = azx_dev_disconnect,
  1242. .dev_free = azx_dev_free,
  1243. };
  1244. struct hda_intel *hda;
  1245. struct azx *chip;
  1246. int err;
  1247. *rchip = NULL;
  1248. err = pci_enable_device(pci);
  1249. if (err < 0)
  1250. return err;
  1251. hda = kzalloc(sizeof(*hda), GFP_KERNEL);
  1252. if (!hda) {
  1253. pci_disable_device(pci);
  1254. return -ENOMEM;
  1255. }
  1256. chip = &hda->chip;
  1257. mutex_init(&chip->open_mutex);
  1258. chip->card = card;
  1259. chip->pci = pci;
  1260. chip->ops = &pci_hda_ops;
  1261. chip->driver_caps = driver_caps;
  1262. chip->driver_type = driver_caps & 0xff;
  1263. check_msi(chip);
  1264. chip->dev_index = dev;
  1265. chip->jackpoll_ms = jackpoll_ms;
  1266. INIT_LIST_HEAD(&chip->pcm_list);
  1267. INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
  1268. INIT_LIST_HEAD(&hda->list);
  1269. init_vga_switcheroo(chip);
  1270. init_completion(&hda->probe_wait);
  1271. assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
  1272. check_probe_mask(chip, dev);
  1273. chip->single_cmd = single_cmd;
  1274. azx_check_snoop_available(chip);
  1275. if (bdl_pos_adj[dev] < 0) {
  1276. switch (chip->driver_type) {
  1277. case AZX_DRIVER_ICH:
  1278. case AZX_DRIVER_PCH:
  1279. bdl_pos_adj[dev] = 1;
  1280. break;
  1281. default:
  1282. bdl_pos_adj[dev] = 32;
  1283. break;
  1284. }
  1285. }
  1286. chip->bdl_pos_adj = bdl_pos_adj;
  1287. err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
  1288. if (err < 0) {
  1289. kfree(hda);
  1290. pci_disable_device(pci);
  1291. return err;
  1292. }
  1293. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  1294. if (err < 0) {
  1295. dev_err(card->dev, "Error creating device [card]!\n");
  1296. azx_free(chip);
  1297. return err;
  1298. }
  1299. /* continue probing in work context as may trigger request module */
  1300. INIT_WORK(&hda->probe_work, azx_probe_work);
  1301. *rchip = chip;
  1302. return 0;
  1303. }
  1304. static int azx_first_init(struct azx *chip)
  1305. {
  1306. int dev = chip->dev_index;
  1307. struct pci_dev *pci = chip->pci;
  1308. struct snd_card *card = chip->card;
  1309. struct hdac_bus *bus = azx_bus(chip);
  1310. int err;
  1311. unsigned short gcap;
  1312. unsigned int dma_bits = 64;
  1313. #if BITS_PER_LONG != 64
  1314. /* Fix up base address on ULI M5461 */
  1315. if (chip->driver_type == AZX_DRIVER_ULI) {
  1316. u16 tmp3;
  1317. pci_read_config_word(pci, 0x40, &tmp3);
  1318. pci_write_config_word(pci, 0x40, tmp3 | 0x10);
  1319. pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
  1320. }
  1321. #endif
  1322. err = pci_request_regions(pci, "ICH HD audio");
  1323. if (err < 0)
  1324. return err;
  1325. chip->region_requested = 1;
  1326. bus->addr = pci_resource_start(pci, 0);
  1327. bus->remap_addr = pci_ioremap_bar(pci, 0);
  1328. if (bus->remap_addr == NULL) {
  1329. dev_err(card->dev, "ioremap error\n");
  1330. return -ENXIO;
  1331. }
  1332. if (chip->msi) {
  1333. if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
  1334. dev_dbg(card->dev, "Disabling 64bit MSI\n");
  1335. pci->no_64bit_msi = true;
  1336. }
  1337. if (pci_enable_msi(pci) < 0)
  1338. chip->msi = 0;
  1339. }
  1340. if (azx_acquire_irq(chip, 0) < 0)
  1341. return -EBUSY;
  1342. pci_set_master(pci);
  1343. synchronize_irq(bus->irq);
  1344. gcap = azx_readw(chip, GCAP);
  1345. dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
  1346. /* AMD devices support 40 or 48bit DMA, take the safe one */
  1347. if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
  1348. dma_bits = 40;
  1349. /* disable SB600 64bit support for safety */
  1350. if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
  1351. struct pci_dev *p_smbus;
  1352. dma_bits = 40;
  1353. p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
  1354. PCI_DEVICE_ID_ATI_SBX00_SMBUS,
  1355. NULL);
  1356. if (p_smbus) {
  1357. if (p_smbus->revision < 0x30)
  1358. gcap &= ~AZX_GCAP_64OK;
  1359. pci_dev_put(p_smbus);
  1360. }
  1361. }
  1362. /* disable 64bit DMA address on some devices */
  1363. if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
  1364. dev_dbg(card->dev, "Disabling 64bit DMA\n");
  1365. gcap &= ~AZX_GCAP_64OK;
  1366. }
  1367. /* disable buffer size rounding to 128-byte multiples if supported */
  1368. if (align_buffer_size >= 0)
  1369. chip->align_buffer_size = !!align_buffer_size;
  1370. else {
  1371. if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
  1372. chip->align_buffer_size = 0;
  1373. else
  1374. chip->align_buffer_size = 1;
  1375. }
  1376. /* allow 64bit DMA address if supported by H/W */
  1377. if (!(gcap & AZX_GCAP_64OK))
  1378. dma_bits = 32;
  1379. if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
  1380. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
  1381. } else {
  1382. dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
  1383. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
  1384. }
  1385. /* read number of streams from GCAP register instead of using
  1386. * hardcoded value
  1387. */
  1388. chip->capture_streams = (gcap >> 8) & 0x0f;
  1389. chip->playback_streams = (gcap >> 12) & 0x0f;
  1390. if (!chip->playback_streams && !chip->capture_streams) {
  1391. /* gcap didn't give any info, switching to old method */
  1392. switch (chip->driver_type) {
  1393. case AZX_DRIVER_ULI:
  1394. chip->playback_streams = ULI_NUM_PLAYBACK;
  1395. chip->capture_streams = ULI_NUM_CAPTURE;
  1396. break;
  1397. case AZX_DRIVER_ATIHDMI:
  1398. case AZX_DRIVER_ATIHDMI_NS:
  1399. chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
  1400. chip->capture_streams = ATIHDMI_NUM_CAPTURE;
  1401. break;
  1402. case AZX_DRIVER_GENERIC:
  1403. default:
  1404. chip->playback_streams = ICH6_NUM_PLAYBACK;
  1405. chip->capture_streams = ICH6_NUM_CAPTURE;
  1406. break;
  1407. }
  1408. }
  1409. chip->capture_index_offset = 0;
  1410. chip->playback_index_offset = chip->capture_streams;
  1411. chip->num_streams = chip->playback_streams + chip->capture_streams;
  1412. /* initialize streams */
  1413. err = azx_init_streams(chip);
  1414. if (err < 0)
  1415. return err;
  1416. err = azx_alloc_stream_pages(chip);
  1417. if (err < 0)
  1418. return err;
  1419. /* initialize chip */
  1420. azx_init_pci(chip);
  1421. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
  1422. struct hda_intel *hda;
  1423. hda = container_of(chip, struct hda_intel, chip);
  1424. haswell_set_bclk(hda);
  1425. }
  1426. hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
  1427. /* codec detection */
  1428. if (!azx_bus(chip)->codec_mask) {
  1429. dev_err(card->dev, "no codecs found!\n");
  1430. return -ENODEV;
  1431. }
  1432. strcpy(card->driver, "HDA-Intel");
  1433. strlcpy(card->shortname, driver_short_names[chip->driver_type],
  1434. sizeof(card->shortname));
  1435. snprintf(card->longname, sizeof(card->longname),
  1436. "%s at 0x%lx irq %i",
  1437. card->shortname, bus->addr, bus->irq);
  1438. return 0;
  1439. }
  1440. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1441. /* callback from request_firmware_nowait() */
  1442. static void azx_firmware_cb(const struct firmware *fw, void *context)
  1443. {
  1444. struct snd_card *card = context;
  1445. struct azx *chip = card->private_data;
  1446. struct pci_dev *pci = chip->pci;
  1447. if (!fw) {
  1448. dev_err(card->dev, "Cannot load firmware, aborting\n");
  1449. goto error;
  1450. }
  1451. chip->fw = fw;
  1452. if (!chip->disabled) {
  1453. /* continue probing */
  1454. if (azx_probe_continue(chip))
  1455. goto error;
  1456. }
  1457. return; /* OK */
  1458. error:
  1459. snd_card_free(card);
  1460. pci_set_drvdata(pci, NULL);
  1461. }
  1462. #endif
  1463. /*
  1464. * HDA controller ops.
  1465. */
  1466. /* PCI register access. */
  1467. static void pci_azx_writel(u32 value, u32 __iomem *addr)
  1468. {
  1469. writel(value, addr);
  1470. }
  1471. static u32 pci_azx_readl(u32 __iomem *addr)
  1472. {
  1473. return readl(addr);
  1474. }
  1475. static void pci_azx_writew(u16 value, u16 __iomem *addr)
  1476. {
  1477. writew(value, addr);
  1478. }
  1479. static u16 pci_azx_readw(u16 __iomem *addr)
  1480. {
  1481. return readw(addr);
  1482. }
  1483. static void pci_azx_writeb(u8 value, u8 __iomem *addr)
  1484. {
  1485. writeb(value, addr);
  1486. }
  1487. static u8 pci_azx_readb(u8 __iomem *addr)
  1488. {
  1489. return readb(addr);
  1490. }
  1491. static int disable_msi_reset_irq(struct azx *chip)
  1492. {
  1493. struct hdac_bus *bus = azx_bus(chip);
  1494. int err;
  1495. free_irq(bus->irq, chip);
  1496. bus->irq = -1;
  1497. pci_disable_msi(chip->pci);
  1498. chip->msi = 0;
  1499. err = azx_acquire_irq(chip, 1);
  1500. if (err < 0)
  1501. return err;
  1502. return 0;
  1503. }
  1504. /* DMA page allocation helpers. */
  1505. static int dma_alloc_pages(struct hdac_bus *bus,
  1506. int type,
  1507. size_t size,
  1508. struct snd_dma_buffer *buf)
  1509. {
  1510. struct azx *chip = bus_to_azx(bus);
  1511. int err;
  1512. err = snd_dma_alloc_pages(type,
  1513. bus->dev,
  1514. size, buf);
  1515. if (err < 0)
  1516. return err;
  1517. mark_pages_wc(chip, buf, true);
  1518. return 0;
  1519. }
  1520. static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
  1521. {
  1522. struct azx *chip = bus_to_azx(bus);
  1523. mark_pages_wc(chip, buf, false);
  1524. snd_dma_free_pages(buf);
  1525. }
  1526. static int substream_alloc_pages(struct azx *chip,
  1527. struct snd_pcm_substream *substream,
  1528. size_t size)
  1529. {
  1530. struct azx_dev *azx_dev = get_azx_dev(substream);
  1531. int ret;
  1532. mark_runtime_wc(chip, azx_dev, substream, false);
  1533. ret = snd_pcm_lib_malloc_pages(substream, size);
  1534. if (ret < 0)
  1535. return ret;
  1536. mark_runtime_wc(chip, azx_dev, substream, true);
  1537. return 0;
  1538. }
  1539. static int substream_free_pages(struct azx *chip,
  1540. struct snd_pcm_substream *substream)
  1541. {
  1542. struct azx_dev *azx_dev = get_azx_dev(substream);
  1543. mark_runtime_wc(chip, azx_dev, substream, false);
  1544. return snd_pcm_lib_free_pages(substream);
  1545. }
  1546. static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
  1547. struct vm_area_struct *area)
  1548. {
  1549. #ifdef CONFIG_X86
  1550. struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
  1551. struct azx *chip = apcm->chip;
  1552. if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
  1553. area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
  1554. #endif
  1555. }
  1556. static const struct hdac_io_ops pci_hda_io_ops = {
  1557. .reg_writel = pci_azx_writel,
  1558. .reg_readl = pci_azx_readl,
  1559. .reg_writew = pci_azx_writew,
  1560. .reg_readw = pci_azx_readw,
  1561. .reg_writeb = pci_azx_writeb,
  1562. .reg_readb = pci_azx_readb,
  1563. .dma_alloc_pages = dma_alloc_pages,
  1564. .dma_free_pages = dma_free_pages,
  1565. };
  1566. static const struct hda_controller_ops pci_hda_ops = {
  1567. .disable_msi_reset_irq = disable_msi_reset_irq,
  1568. .substream_alloc_pages = substream_alloc_pages,
  1569. .substream_free_pages = substream_free_pages,
  1570. .pcm_mmap_prepare = pcm_mmap_prepare,
  1571. .position_check = azx_position_check,
  1572. .link_power = azx_intel_link_power,
  1573. };
  1574. static int azx_probe(struct pci_dev *pci,
  1575. const struct pci_device_id *pci_id)
  1576. {
  1577. static int dev;
  1578. struct snd_card *card;
  1579. struct hda_intel *hda;
  1580. struct azx *chip;
  1581. bool schedule_probe;
  1582. int err;
  1583. if (dev >= SNDRV_CARDS)
  1584. return -ENODEV;
  1585. if (!enable[dev]) {
  1586. dev++;
  1587. return -ENOENT;
  1588. }
  1589. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  1590. 0, &card);
  1591. if (err < 0) {
  1592. dev_err(&pci->dev, "Error creating card!\n");
  1593. return err;
  1594. }
  1595. err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
  1596. if (err < 0)
  1597. goto out_free;
  1598. card->private_data = chip;
  1599. hda = container_of(chip, struct hda_intel, chip);
  1600. pci_set_drvdata(pci, card);
  1601. err = register_vga_switcheroo(chip);
  1602. if (err < 0) {
  1603. dev_err(card->dev, "Error registering VGA-switcheroo client\n");
  1604. goto out_free;
  1605. }
  1606. if (check_hdmi_disabled(pci)) {
  1607. dev_info(card->dev, "VGA controller is disabled\n");
  1608. dev_info(card->dev, "Delaying initialization\n");
  1609. chip->disabled = true;
  1610. }
  1611. schedule_probe = !chip->disabled;
  1612. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1613. if (patch[dev] && *patch[dev]) {
  1614. dev_info(card->dev, "Applying patch firmware '%s'\n",
  1615. patch[dev]);
  1616. err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
  1617. &pci->dev, GFP_KERNEL, card,
  1618. azx_firmware_cb);
  1619. if (err < 0)
  1620. goto out_free;
  1621. schedule_probe = false; /* continued in azx_firmware_cb() */
  1622. }
  1623. #endif /* CONFIG_SND_HDA_PATCH_LOADER */
  1624. #ifndef CONFIG_SND_HDA_I915
  1625. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
  1626. dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
  1627. #endif
  1628. if (schedule_probe)
  1629. schedule_work(&hda->probe_work);
  1630. dev++;
  1631. if (chip->disabled)
  1632. complete_all(&hda->probe_wait);
  1633. return 0;
  1634. out_free:
  1635. snd_card_free(card);
  1636. return err;
  1637. }
  1638. /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
  1639. static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
  1640. [AZX_DRIVER_NVIDIA] = 8,
  1641. [AZX_DRIVER_TERA] = 1,
  1642. };
  1643. static int azx_probe_continue(struct azx *chip)
  1644. {
  1645. struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
  1646. struct pci_dev *pci = chip->pci;
  1647. int dev = chip->dev_index;
  1648. int err;
  1649. hda->probe_continued = 1;
  1650. /* Request display power well for the HDA controller or codec. For
  1651. * Haswell/Broadwell, both the display HDA controller and codec need
  1652. * this power. For other platforms, like Baytrail/Braswell, only the
  1653. * display codec needs the power and it can be released after probe.
  1654. */
  1655. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
  1656. /* Baytral/Braswell controllers don't need this power */
  1657. if (pci->device != 0x0f04 && pci->device != 0x2284)
  1658. hda->need_i915_power = 1;
  1659. err = hda_i915_init(hda);
  1660. if (err < 0)
  1661. goto i915_power_fail;
  1662. err = hda_display_power(hda, true);
  1663. if (err < 0) {
  1664. dev_err(chip->card->dev,
  1665. "Cannot turn on display power on i915\n");
  1666. goto i915_power_fail;
  1667. }
  1668. }
  1669. err = azx_first_init(chip);
  1670. if (err < 0)
  1671. goto out_free;
  1672. #ifdef CONFIG_SND_HDA_INPUT_BEEP
  1673. chip->beep_mode = beep_mode[dev];
  1674. #endif
  1675. /* create codec instances */
  1676. err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
  1677. if (err < 0)
  1678. goto out_free;
  1679. #ifdef CONFIG_SND_HDA_PATCH_LOADER
  1680. if (chip->fw) {
  1681. err = snd_hda_load_patch(&chip->bus, chip->fw->size,
  1682. chip->fw->data);
  1683. if (err < 0)
  1684. goto out_free;
  1685. #ifndef CONFIG_PM
  1686. release_firmware(chip->fw); /* no longer needed */
  1687. chip->fw = NULL;
  1688. #endif
  1689. }
  1690. #endif
  1691. if ((probe_only[dev] & 1) == 0) {
  1692. err = azx_codec_configure(chip);
  1693. if (err < 0)
  1694. goto out_free;
  1695. }
  1696. err = snd_card_register(chip->card);
  1697. if (err < 0)
  1698. goto out_free;
  1699. chip->running = 1;
  1700. azx_add_card_list(chip);
  1701. snd_hda_set_power_save(&chip->bus, power_save * 1000);
  1702. if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
  1703. pm_runtime_put_noidle(&pci->dev);
  1704. out_free:
  1705. if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
  1706. && !hda->need_i915_power)
  1707. hda_display_power(hda, false);
  1708. i915_power_fail:
  1709. if (err < 0)
  1710. hda->init_failed = 1;
  1711. complete_all(&hda->probe_wait);
  1712. return err;
  1713. }
  1714. static void azx_remove(struct pci_dev *pci)
  1715. {
  1716. struct snd_card *card = pci_get_drvdata(pci);
  1717. if (card)
  1718. snd_card_free(card);
  1719. }
  1720. static void azx_shutdown(struct pci_dev *pci)
  1721. {
  1722. struct snd_card *card = pci_get_drvdata(pci);
  1723. struct azx *chip;
  1724. if (!card)
  1725. return;
  1726. chip = card->private_data;
  1727. if (chip && chip->running)
  1728. azx_stop_chip(chip);
  1729. }
  1730. /* PCI IDs */
  1731. static const struct pci_device_id azx_ids[] = {
  1732. /* CPT */
  1733. { PCI_DEVICE(0x8086, 0x1c20),
  1734. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1735. /* PBG */
  1736. { PCI_DEVICE(0x8086, 0x1d20),
  1737. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1738. /* Panther Point */
  1739. { PCI_DEVICE(0x8086, 0x1e20),
  1740. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1741. /* Lynx Point */
  1742. { PCI_DEVICE(0x8086, 0x8c20),
  1743. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1744. /* 9 Series */
  1745. { PCI_DEVICE(0x8086, 0x8ca0),
  1746. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1747. /* Wellsburg */
  1748. { PCI_DEVICE(0x8086, 0x8d20),
  1749. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1750. { PCI_DEVICE(0x8086, 0x8d21),
  1751. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1752. /* Lynx Point-LP */
  1753. { PCI_DEVICE(0x8086, 0x9c20),
  1754. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1755. /* Lynx Point-LP */
  1756. { PCI_DEVICE(0x8086, 0x9c21),
  1757. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1758. /* Wildcat Point-LP */
  1759. { PCI_DEVICE(0x8086, 0x9ca0),
  1760. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
  1761. /* Sunrise Point */
  1762. { PCI_DEVICE(0x8086, 0xa170),
  1763. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
  1764. /* Sunrise Point-LP */
  1765. { PCI_DEVICE(0x8086, 0x9d70),
  1766. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
  1767. /* Haswell */
  1768. { PCI_DEVICE(0x8086, 0x0a0c),
  1769. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  1770. { PCI_DEVICE(0x8086, 0x0c0c),
  1771. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  1772. { PCI_DEVICE(0x8086, 0x0d0c),
  1773. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
  1774. /* Broadwell */
  1775. { PCI_DEVICE(0x8086, 0x160c),
  1776. .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
  1777. /* 5 Series/3400 */
  1778. { PCI_DEVICE(0x8086, 0x3b56),
  1779. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1780. /* Poulsbo */
  1781. { PCI_DEVICE(0x8086, 0x811b),
  1782. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1783. /* Oaktrail */
  1784. { PCI_DEVICE(0x8086, 0x080a),
  1785. .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
  1786. /* BayTrail */
  1787. { PCI_DEVICE(0x8086, 0x0f04),
  1788. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
  1789. /* Braswell */
  1790. { PCI_DEVICE(0x8086, 0x2284),
  1791. .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
  1792. /* ICH6 */
  1793. { PCI_DEVICE(0x8086, 0x2668),
  1794. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1795. /* ICH7 */
  1796. { PCI_DEVICE(0x8086, 0x27d8),
  1797. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1798. /* ESB2 */
  1799. { PCI_DEVICE(0x8086, 0x269a),
  1800. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1801. /* ICH8 */
  1802. { PCI_DEVICE(0x8086, 0x284b),
  1803. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1804. /* ICH9 */
  1805. { PCI_DEVICE(0x8086, 0x293e),
  1806. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1807. /* ICH9 */
  1808. { PCI_DEVICE(0x8086, 0x293f),
  1809. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1810. /* ICH10 */
  1811. { PCI_DEVICE(0x8086, 0x3a3e),
  1812. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1813. /* ICH10 */
  1814. { PCI_DEVICE(0x8086, 0x3a6e),
  1815. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
  1816. /* Generic Intel */
  1817. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
  1818. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  1819. .class_mask = 0xffffff,
  1820. .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
  1821. /* ATI SB 450/600/700/800/900 */
  1822. { PCI_DEVICE(0x1002, 0x437b),
  1823. .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
  1824. { PCI_DEVICE(0x1002, 0x4383),
  1825. .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
  1826. /* AMD Hudson */
  1827. { PCI_DEVICE(0x1022, 0x780d),
  1828. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
  1829. /* ATI HDMI */
  1830. { PCI_DEVICE(0x1002, 0x793b),
  1831. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1832. { PCI_DEVICE(0x1002, 0x7919),
  1833. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1834. { PCI_DEVICE(0x1002, 0x960f),
  1835. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1836. { PCI_DEVICE(0x1002, 0x970f),
  1837. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1838. { PCI_DEVICE(0x1002, 0xaa00),
  1839. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1840. { PCI_DEVICE(0x1002, 0xaa08),
  1841. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1842. { PCI_DEVICE(0x1002, 0xaa10),
  1843. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1844. { PCI_DEVICE(0x1002, 0xaa18),
  1845. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1846. { PCI_DEVICE(0x1002, 0xaa20),
  1847. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1848. { PCI_DEVICE(0x1002, 0xaa28),
  1849. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1850. { PCI_DEVICE(0x1002, 0xaa30),
  1851. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1852. { PCI_DEVICE(0x1002, 0xaa38),
  1853. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1854. { PCI_DEVICE(0x1002, 0xaa40),
  1855. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1856. { PCI_DEVICE(0x1002, 0xaa48),
  1857. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1858. { PCI_DEVICE(0x1002, 0xaa50),
  1859. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1860. { PCI_DEVICE(0x1002, 0xaa58),
  1861. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1862. { PCI_DEVICE(0x1002, 0xaa60),
  1863. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1864. { PCI_DEVICE(0x1002, 0xaa68),
  1865. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1866. { PCI_DEVICE(0x1002, 0xaa80),
  1867. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1868. { PCI_DEVICE(0x1002, 0xaa88),
  1869. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1870. { PCI_DEVICE(0x1002, 0xaa90),
  1871. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1872. { PCI_DEVICE(0x1002, 0xaa98),
  1873. .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
  1874. { PCI_DEVICE(0x1002, 0x9902),
  1875. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  1876. { PCI_DEVICE(0x1002, 0xaaa0),
  1877. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  1878. { PCI_DEVICE(0x1002, 0xaaa8),
  1879. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  1880. { PCI_DEVICE(0x1002, 0xaab0),
  1881. .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
  1882. /* VIA VT8251/VT8237A */
  1883. { PCI_DEVICE(0x1106, 0x3288),
  1884. .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
  1885. /* VIA GFX VT7122/VX900 */
  1886. { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
  1887. /* VIA GFX VT6122/VX11 */
  1888. { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
  1889. /* SIS966 */
  1890. { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
  1891. /* ULI M5461 */
  1892. { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
  1893. /* NVIDIA MCP */
  1894. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  1895. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  1896. .class_mask = 0xffffff,
  1897. .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
  1898. /* Teradici */
  1899. { PCI_DEVICE(0x6549, 0x1200),
  1900. .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
  1901. { PCI_DEVICE(0x6549, 0x2200),
  1902. .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
  1903. /* Creative X-Fi (CA0110-IBG) */
  1904. /* CTHDA chips */
  1905. { PCI_DEVICE(0x1102, 0x0010),
  1906. .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
  1907. { PCI_DEVICE(0x1102, 0x0012),
  1908. .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
  1909. #if !IS_ENABLED(CONFIG_SND_CTXFI)
  1910. /* the following entry conflicts with snd-ctxfi driver,
  1911. * as ctxfi driver mutates from HD-audio to native mode with
  1912. * a special command sequence.
  1913. */
  1914. { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
  1915. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  1916. .class_mask = 0xffffff,
  1917. .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
  1918. AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
  1919. #else
  1920. /* this entry seems still valid -- i.e. without emu20kx chip */
  1921. { PCI_DEVICE(0x1102, 0x0009),
  1922. .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
  1923. AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
  1924. #endif
  1925. /* CM8888 */
  1926. { PCI_DEVICE(0x13f6, 0x5011),
  1927. .driver_data = AZX_DRIVER_CMEDIA |
  1928. AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
  1929. /* Vortex86MX */
  1930. { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
  1931. /* VMware HDAudio */
  1932. { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
  1933. /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
  1934. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
  1935. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  1936. .class_mask = 0xffffff,
  1937. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
  1938. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
  1939. .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
  1940. .class_mask = 0xffffff,
  1941. .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
  1942. { 0, }
  1943. };
  1944. MODULE_DEVICE_TABLE(pci, azx_ids);
  1945. /* pci_driver definition */
  1946. static struct pci_driver azx_driver = {
  1947. .name = KBUILD_MODNAME,
  1948. .id_table = azx_ids,
  1949. .probe = azx_probe,
  1950. .remove = azx_remove,
  1951. .shutdown = azx_shutdown,
  1952. .driver = {
  1953. .pm = AZX_PM_OPS,
  1954. },
  1955. };
  1956. module_pci_driver(azx_driver);