xhci-dbgcap.c 22 KB

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  1. /**
  2. * xhci-dbgcap.c - xHCI debug capability support
  3. *
  4. * Copyright (C) 2017 Intel Corporation
  5. *
  6. * Author: Lu Baolu <baolu.lu@linux.intel.com>
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/slab.h>
  10. #include <linux/nls.h>
  11. #include "xhci.h"
  12. #include "xhci-trace.h"
  13. #include "xhci-dbgcap.h"
  14. static inline void *
  15. dbc_dma_alloc_coherent(struct xhci_hcd *xhci, size_t size,
  16. dma_addr_t *dma_handle, gfp_t flags)
  17. {
  18. void *vaddr;
  19. vaddr = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
  20. size, dma_handle, flags);
  21. memset(vaddr, 0, size);
  22. return vaddr;
  23. }
  24. static inline void
  25. dbc_dma_free_coherent(struct xhci_hcd *xhci, size_t size,
  26. void *cpu_addr, dma_addr_t dma_handle)
  27. {
  28. if (cpu_addr)
  29. dma_free_coherent(xhci_to_hcd(xhci)->self.sysdev,
  30. size, cpu_addr, dma_handle);
  31. }
  32. static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
  33. {
  34. struct usb_string_descriptor *s_desc;
  35. u32 string_length;
  36. /* Serial string: */
  37. s_desc = (struct usb_string_descriptor *)strings->serial;
  38. utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
  39. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  40. DBC_MAX_STRING_LENGTH);
  41. s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
  42. s_desc->bDescriptorType = USB_DT_STRING;
  43. string_length = s_desc->bLength;
  44. string_length <<= 8;
  45. /* Product string: */
  46. s_desc = (struct usb_string_descriptor *)strings->product;
  47. utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
  48. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  49. DBC_MAX_STRING_LENGTH);
  50. s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
  51. s_desc->bDescriptorType = USB_DT_STRING;
  52. string_length += s_desc->bLength;
  53. string_length <<= 8;
  54. /* Manufacture string: */
  55. s_desc = (struct usb_string_descriptor *)strings->manufacturer;
  56. utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
  57. strlen(DBC_STRING_MANUFACTURER),
  58. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  59. DBC_MAX_STRING_LENGTH);
  60. s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
  61. s_desc->bDescriptorType = USB_DT_STRING;
  62. string_length += s_desc->bLength;
  63. string_length <<= 8;
  64. /* String0: */
  65. strings->string0[0] = 4;
  66. strings->string0[1] = USB_DT_STRING;
  67. strings->string0[2] = 0x09;
  68. strings->string0[3] = 0x04;
  69. string_length += 4;
  70. return string_length;
  71. }
  72. static void xhci_dbc_init_contexts(struct xhci_hcd *xhci, u32 string_length)
  73. {
  74. struct xhci_dbc *dbc;
  75. struct dbc_info_context *info;
  76. struct xhci_ep_ctx *ep_ctx;
  77. u32 dev_info;
  78. dma_addr_t deq, dma;
  79. unsigned int max_burst;
  80. dbc = xhci->dbc;
  81. if (!dbc)
  82. return;
  83. /* Populate info Context: */
  84. info = (struct dbc_info_context *)dbc->ctx->bytes;
  85. dma = dbc->string_dma;
  86. info->string0 = cpu_to_le64(dma);
  87. info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
  88. info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
  89. info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
  90. info->length = cpu_to_le32(string_length);
  91. /* Populate bulk out endpoint context: */
  92. ep_ctx = dbc_bulkout_ctx(dbc);
  93. max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
  94. deq = dbc_bulkout_enq(dbc);
  95. ep_ctx->ep_info = 0;
  96. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
  97. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
  98. /* Populate bulk in endpoint context: */
  99. ep_ctx = dbc_bulkin_ctx(dbc);
  100. deq = dbc_bulkin_enq(dbc);
  101. ep_ctx->ep_info = 0;
  102. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
  103. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
  104. /* Set DbC context and info registers: */
  105. xhci_write_64(xhci, dbc->ctx->dma, &dbc->regs->dccp);
  106. dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
  107. writel(dev_info, &dbc->regs->devinfo1);
  108. dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
  109. writel(dev_info, &dbc->regs->devinfo2);
  110. }
  111. static void xhci_dbc_giveback(struct dbc_request *req, int status)
  112. __releases(&dbc->lock)
  113. __acquires(&dbc->lock)
  114. {
  115. struct dbc_ep *dep = req->dep;
  116. struct xhci_dbc *dbc = dep->dbc;
  117. struct xhci_hcd *xhci = dbc->xhci;
  118. struct device *dev = xhci_to_hcd(dbc->xhci)->self.sysdev;
  119. list_del_init(&req->list_pending);
  120. req->trb_dma = 0;
  121. req->trb = NULL;
  122. if (req->status == -EINPROGRESS)
  123. req->status = status;
  124. trace_xhci_dbc_giveback_request(req);
  125. dma_unmap_single(dev,
  126. req->dma,
  127. req->length,
  128. dbc_ep_dma_direction(dep));
  129. /* Give back the transfer request: */
  130. spin_unlock(&dbc->lock);
  131. req->complete(xhci, req);
  132. spin_lock(&dbc->lock);
  133. }
  134. static void xhci_dbc_flush_single_request(struct dbc_request *req)
  135. {
  136. union xhci_trb *trb = req->trb;
  137. trb->generic.field[0] = 0;
  138. trb->generic.field[1] = 0;
  139. trb->generic.field[2] = 0;
  140. trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
  141. trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
  142. xhci_dbc_giveback(req, -ESHUTDOWN);
  143. }
  144. static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
  145. {
  146. struct dbc_request *req, *tmp;
  147. list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
  148. xhci_dbc_flush_single_request(req);
  149. }
  150. static void xhci_dbc_flush_reqests(struct xhci_dbc *dbc)
  151. {
  152. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
  153. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
  154. }
  155. struct dbc_request *
  156. dbc_alloc_request(struct dbc_ep *dep, gfp_t gfp_flags)
  157. {
  158. struct dbc_request *req;
  159. req = kzalloc(sizeof(*req), gfp_flags);
  160. if (!req)
  161. return NULL;
  162. req->dep = dep;
  163. INIT_LIST_HEAD(&req->list_pending);
  164. INIT_LIST_HEAD(&req->list_pool);
  165. req->direction = dep->direction;
  166. trace_xhci_dbc_alloc_request(req);
  167. return req;
  168. }
  169. void
  170. dbc_free_request(struct dbc_ep *dep, struct dbc_request *req)
  171. {
  172. trace_xhci_dbc_free_request(req);
  173. kfree(req);
  174. }
  175. static void
  176. xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
  177. u32 field2, u32 field3, u32 field4)
  178. {
  179. union xhci_trb *trb, *next;
  180. trb = ring->enqueue;
  181. trb->generic.field[0] = cpu_to_le32(field1);
  182. trb->generic.field[1] = cpu_to_le32(field2);
  183. trb->generic.field[2] = cpu_to_le32(field3);
  184. trb->generic.field[3] = cpu_to_le32(field4);
  185. trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
  186. ring->num_trbs_free--;
  187. next = ++(ring->enqueue);
  188. if (TRB_TYPE_LINK_LE32(next->link.control)) {
  189. next->link.control ^= cpu_to_le32(TRB_CYCLE);
  190. ring->enqueue = ring->enq_seg->trbs;
  191. ring->cycle_state ^= 1;
  192. }
  193. }
  194. static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
  195. struct dbc_request *req)
  196. {
  197. u64 addr;
  198. union xhci_trb *trb;
  199. unsigned int num_trbs;
  200. struct xhci_dbc *dbc = dep->dbc;
  201. struct xhci_ring *ring = dep->ring;
  202. u32 length, control, cycle;
  203. num_trbs = count_trbs(req->dma, req->length);
  204. WARN_ON(num_trbs != 1);
  205. if (ring->num_trbs_free < num_trbs)
  206. return -EBUSY;
  207. addr = req->dma;
  208. trb = ring->enqueue;
  209. cycle = ring->cycle_state;
  210. length = TRB_LEN(req->length);
  211. control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
  212. if (cycle)
  213. control &= cpu_to_le32(~TRB_CYCLE);
  214. else
  215. control |= cpu_to_le32(TRB_CYCLE);
  216. req->trb = ring->enqueue;
  217. req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
  218. xhci_dbc_queue_trb(ring,
  219. lower_32_bits(addr),
  220. upper_32_bits(addr),
  221. length, control);
  222. /*
  223. * Add a barrier between writes of trb fields and flipping
  224. * the cycle bit:
  225. */
  226. wmb();
  227. if (cycle)
  228. trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
  229. else
  230. trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
  231. writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
  232. return 0;
  233. }
  234. static int
  235. dbc_ep_do_queue(struct dbc_ep *dep, struct dbc_request *req)
  236. {
  237. int ret;
  238. struct device *dev;
  239. struct xhci_dbc *dbc = dep->dbc;
  240. struct xhci_hcd *xhci = dbc->xhci;
  241. dev = xhci_to_hcd(xhci)->self.sysdev;
  242. if (!req->length || !req->buf)
  243. return -EINVAL;
  244. req->actual = 0;
  245. req->status = -EINPROGRESS;
  246. req->dma = dma_map_single(dev,
  247. req->buf,
  248. req->length,
  249. dbc_ep_dma_direction(dep));
  250. if (dma_mapping_error(dev, req->dma)) {
  251. xhci_err(xhci, "failed to map buffer\n");
  252. return -EFAULT;
  253. }
  254. ret = xhci_dbc_queue_bulk_tx(dep, req);
  255. if (ret) {
  256. xhci_err(xhci, "failed to queue trbs\n");
  257. dma_unmap_single(dev,
  258. req->dma,
  259. req->length,
  260. dbc_ep_dma_direction(dep));
  261. return -EFAULT;
  262. }
  263. list_add_tail(&req->list_pending, &dep->list_pending);
  264. return 0;
  265. }
  266. int dbc_ep_queue(struct dbc_ep *dep, struct dbc_request *req,
  267. gfp_t gfp_flags)
  268. {
  269. unsigned long flags;
  270. struct xhci_dbc *dbc = dep->dbc;
  271. int ret = -ESHUTDOWN;
  272. spin_lock_irqsave(&dbc->lock, flags);
  273. if (dbc->state == DS_CONFIGURED)
  274. ret = dbc_ep_do_queue(dep, req);
  275. spin_unlock_irqrestore(&dbc->lock, flags);
  276. mod_delayed_work(system_wq, &dbc->event_work, 0);
  277. trace_xhci_dbc_queue_request(req);
  278. return ret;
  279. }
  280. static inline void xhci_dbc_do_eps_init(struct xhci_hcd *xhci, bool direction)
  281. {
  282. struct dbc_ep *dep;
  283. struct xhci_dbc *dbc = xhci->dbc;
  284. dep = &dbc->eps[direction];
  285. dep->dbc = dbc;
  286. dep->direction = direction;
  287. dep->ring = direction ? dbc->ring_in : dbc->ring_out;
  288. INIT_LIST_HEAD(&dep->list_pending);
  289. }
  290. static void xhci_dbc_eps_init(struct xhci_hcd *xhci)
  291. {
  292. xhci_dbc_do_eps_init(xhci, BULK_OUT);
  293. xhci_dbc_do_eps_init(xhci, BULK_IN);
  294. }
  295. static void xhci_dbc_eps_exit(struct xhci_hcd *xhci)
  296. {
  297. struct xhci_dbc *dbc = xhci->dbc;
  298. memset(dbc->eps, 0, sizeof(struct dbc_ep) * ARRAY_SIZE(dbc->eps));
  299. }
  300. static int xhci_dbc_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  301. {
  302. int ret;
  303. dma_addr_t deq;
  304. u32 string_length;
  305. struct xhci_dbc *dbc = xhci->dbc;
  306. /* Allocate various rings for events and transfers: */
  307. dbc->ring_evt = xhci_ring_alloc(xhci, 1, 1, TYPE_EVENT, 0, flags);
  308. if (!dbc->ring_evt)
  309. goto evt_fail;
  310. dbc->ring_in = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  311. if (!dbc->ring_in)
  312. goto in_fail;
  313. dbc->ring_out = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  314. if (!dbc->ring_out)
  315. goto out_fail;
  316. /* Allocate and populate ERST: */
  317. ret = xhci_alloc_erst(xhci, dbc->ring_evt, &dbc->erst, flags);
  318. if (ret)
  319. goto erst_fail;
  320. /* Allocate context data structure: */
  321. dbc->ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  322. if (!dbc->ctx)
  323. goto ctx_fail;
  324. /* Allocate the string table: */
  325. dbc->string_size = sizeof(struct dbc_str_descs);
  326. dbc->string = dbc_dma_alloc_coherent(xhci,
  327. dbc->string_size,
  328. &dbc->string_dma,
  329. flags);
  330. if (!dbc->string)
  331. goto string_fail;
  332. /* Setup ERST register: */
  333. writel(dbc->erst.erst_size, &dbc->regs->ersts);
  334. xhci_write_64(xhci, dbc->erst.erst_dma_addr, &dbc->regs->erstba);
  335. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  336. dbc->ring_evt->dequeue);
  337. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  338. /* Setup strings and contexts: */
  339. string_length = xhci_dbc_populate_strings(dbc->string);
  340. xhci_dbc_init_contexts(xhci, string_length);
  341. mmiowb();
  342. xhci_dbc_eps_init(xhci);
  343. dbc->state = DS_INITIALIZED;
  344. return 0;
  345. string_fail:
  346. xhci_free_container_ctx(xhci, dbc->ctx);
  347. dbc->ctx = NULL;
  348. ctx_fail:
  349. xhci_free_erst(xhci, &dbc->erst);
  350. erst_fail:
  351. xhci_ring_free(xhci, dbc->ring_out);
  352. dbc->ring_out = NULL;
  353. out_fail:
  354. xhci_ring_free(xhci, dbc->ring_in);
  355. dbc->ring_in = NULL;
  356. in_fail:
  357. xhci_ring_free(xhci, dbc->ring_evt);
  358. dbc->ring_evt = NULL;
  359. evt_fail:
  360. return -ENOMEM;
  361. }
  362. static void xhci_dbc_mem_cleanup(struct xhci_hcd *xhci)
  363. {
  364. struct xhci_dbc *dbc = xhci->dbc;
  365. if (!dbc)
  366. return;
  367. xhci_dbc_eps_exit(xhci);
  368. if (dbc->string) {
  369. dbc_dma_free_coherent(xhci,
  370. dbc->string_size,
  371. dbc->string, dbc->string_dma);
  372. dbc->string = NULL;
  373. }
  374. xhci_free_container_ctx(xhci, dbc->ctx);
  375. dbc->ctx = NULL;
  376. xhci_free_erst(xhci, &dbc->erst);
  377. xhci_ring_free(xhci, dbc->ring_out);
  378. xhci_ring_free(xhci, dbc->ring_in);
  379. xhci_ring_free(xhci, dbc->ring_evt);
  380. dbc->ring_in = NULL;
  381. dbc->ring_out = NULL;
  382. dbc->ring_evt = NULL;
  383. }
  384. static int xhci_do_dbc_start(struct xhci_hcd *xhci)
  385. {
  386. int ret;
  387. u32 ctrl;
  388. struct xhci_dbc *dbc = xhci->dbc;
  389. if (dbc->state != DS_DISABLED)
  390. return -EINVAL;
  391. writel(0, &dbc->regs->control);
  392. ret = xhci_handshake(&dbc->regs->control,
  393. DBC_CTRL_DBC_ENABLE,
  394. 0, 1000);
  395. if (ret)
  396. return ret;
  397. ret = xhci_dbc_mem_init(xhci, GFP_ATOMIC);
  398. if (ret)
  399. return ret;
  400. ctrl = readl(&dbc->regs->control);
  401. writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
  402. &dbc->regs->control);
  403. ret = xhci_handshake(&dbc->regs->control,
  404. DBC_CTRL_DBC_ENABLE,
  405. DBC_CTRL_DBC_ENABLE, 1000);
  406. if (ret)
  407. return ret;
  408. dbc->state = DS_ENABLED;
  409. return 0;
  410. }
  411. static void xhci_do_dbc_stop(struct xhci_hcd *xhci)
  412. {
  413. struct xhci_dbc *dbc = xhci->dbc;
  414. if (dbc->state == DS_DISABLED)
  415. return;
  416. writel(0, &dbc->regs->control);
  417. xhci_dbc_mem_cleanup(xhci);
  418. dbc->state = DS_DISABLED;
  419. }
  420. static int xhci_dbc_start(struct xhci_hcd *xhci)
  421. {
  422. int ret;
  423. unsigned long flags;
  424. struct xhci_dbc *dbc = xhci->dbc;
  425. WARN_ON(!dbc);
  426. pm_runtime_get_sync(xhci_to_hcd(xhci)->self.controller);
  427. spin_lock_irqsave(&dbc->lock, flags);
  428. ret = xhci_do_dbc_start(xhci);
  429. spin_unlock_irqrestore(&dbc->lock, flags);
  430. if (ret) {
  431. pm_runtime_put(xhci_to_hcd(xhci)->self.controller);
  432. return ret;
  433. }
  434. return mod_delayed_work(system_wq, &dbc->event_work, 1);
  435. }
  436. static void xhci_dbc_stop(struct xhci_hcd *xhci)
  437. {
  438. unsigned long flags;
  439. struct xhci_dbc *dbc = xhci->dbc;
  440. struct dbc_port *port = &dbc->port;
  441. WARN_ON(!dbc);
  442. cancel_delayed_work_sync(&dbc->event_work);
  443. if (port->registered)
  444. xhci_dbc_tty_unregister_device(xhci);
  445. spin_lock_irqsave(&dbc->lock, flags);
  446. xhci_do_dbc_stop(xhci);
  447. spin_unlock_irqrestore(&dbc->lock, flags);
  448. pm_runtime_put_sync(xhci_to_hcd(xhci)->self.controller);
  449. }
  450. static void
  451. dbc_handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
  452. {
  453. u32 portsc;
  454. struct xhci_dbc *dbc = xhci->dbc;
  455. portsc = readl(&dbc->regs->portsc);
  456. if (portsc & DBC_PORTSC_CONN_CHANGE)
  457. xhci_info(xhci, "DbC port connect change\n");
  458. if (portsc & DBC_PORTSC_RESET_CHANGE)
  459. xhci_info(xhci, "DbC port reset change\n");
  460. if (portsc & DBC_PORTSC_LINK_CHANGE)
  461. xhci_info(xhci, "DbC port link status change\n");
  462. if (portsc & DBC_PORTSC_CONFIG_CHANGE)
  463. xhci_info(xhci, "DbC config error change\n");
  464. /* Port reset change bit will be cleared in other place: */
  465. writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
  466. }
  467. static void dbc_handle_xfer_event(struct xhci_hcd *xhci, union xhci_trb *event)
  468. {
  469. struct dbc_ep *dep;
  470. struct xhci_ring *ring;
  471. int ep_id;
  472. int status;
  473. u32 comp_code;
  474. size_t remain_length;
  475. struct dbc_request *req = NULL, *r;
  476. comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
  477. remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
  478. ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
  479. dep = (ep_id == EPID_OUT) ?
  480. get_out_ep(xhci) : get_in_ep(xhci);
  481. ring = dep->ring;
  482. switch (comp_code) {
  483. case COMP_SUCCESS:
  484. remain_length = 0;
  485. /* FALLTHROUGH */
  486. case COMP_SHORT_PACKET:
  487. status = 0;
  488. break;
  489. case COMP_TRB_ERROR:
  490. case COMP_BABBLE_DETECTED_ERROR:
  491. case COMP_USB_TRANSACTION_ERROR:
  492. case COMP_STALL_ERROR:
  493. xhci_warn(xhci, "tx error %d detected\n", comp_code);
  494. status = -comp_code;
  495. break;
  496. default:
  497. xhci_err(xhci, "unknown tx error %d\n", comp_code);
  498. status = -comp_code;
  499. break;
  500. }
  501. /* Match the pending request: */
  502. list_for_each_entry(r, &dep->list_pending, list_pending) {
  503. if (r->trb_dma == event->trans_event.buffer) {
  504. req = r;
  505. break;
  506. }
  507. }
  508. if (!req) {
  509. xhci_warn(xhci, "no matched request\n");
  510. return;
  511. }
  512. trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
  513. ring->num_trbs_free++;
  514. req->actual = req->length - remain_length;
  515. xhci_dbc_giveback(req, status);
  516. }
  517. static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
  518. {
  519. dma_addr_t deq;
  520. struct dbc_ep *dep;
  521. union xhci_trb *evt;
  522. u32 ctrl, portsc;
  523. struct xhci_hcd *xhci = dbc->xhci;
  524. bool update_erdp = false;
  525. /* DbC state machine: */
  526. switch (dbc->state) {
  527. case DS_DISABLED:
  528. case DS_INITIALIZED:
  529. return EVT_ERR;
  530. case DS_ENABLED:
  531. portsc = readl(&dbc->regs->portsc);
  532. if (portsc & DBC_PORTSC_CONN_STATUS) {
  533. dbc->state = DS_CONNECTED;
  534. xhci_info(xhci, "DbC connected\n");
  535. }
  536. return EVT_DONE;
  537. case DS_CONNECTED:
  538. ctrl = readl(&dbc->regs->control);
  539. if (ctrl & DBC_CTRL_DBC_RUN) {
  540. dbc->state = DS_CONFIGURED;
  541. xhci_info(xhci, "DbC configured\n");
  542. portsc = readl(&dbc->regs->portsc);
  543. writel(portsc, &dbc->regs->portsc);
  544. return EVT_GSER;
  545. }
  546. return EVT_DONE;
  547. case DS_CONFIGURED:
  548. /* Handle cable unplug event: */
  549. portsc = readl(&dbc->regs->portsc);
  550. if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
  551. !(portsc & DBC_PORTSC_CONN_STATUS)) {
  552. xhci_info(xhci, "DbC cable unplugged\n");
  553. dbc->state = DS_ENABLED;
  554. xhci_dbc_flush_reqests(dbc);
  555. return EVT_DISC;
  556. }
  557. /* Handle debug port reset event: */
  558. if (portsc & DBC_PORTSC_RESET_CHANGE) {
  559. xhci_info(xhci, "DbC port reset\n");
  560. writel(portsc, &dbc->regs->portsc);
  561. dbc->state = DS_ENABLED;
  562. xhci_dbc_flush_reqests(dbc);
  563. return EVT_DISC;
  564. }
  565. /* Handle endpoint stall event: */
  566. ctrl = readl(&dbc->regs->control);
  567. if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
  568. (ctrl & DBC_CTRL_HALT_OUT_TR)) {
  569. xhci_info(xhci, "DbC Endpoint stall\n");
  570. dbc->state = DS_STALLED;
  571. if (ctrl & DBC_CTRL_HALT_IN_TR) {
  572. dep = get_in_ep(xhci);
  573. xhci_dbc_flush_endpoint_requests(dep);
  574. }
  575. if (ctrl & DBC_CTRL_HALT_OUT_TR) {
  576. dep = get_out_ep(xhci);
  577. xhci_dbc_flush_endpoint_requests(dep);
  578. }
  579. return EVT_DONE;
  580. }
  581. /* Clear DbC run change bit: */
  582. if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
  583. writel(ctrl, &dbc->regs->control);
  584. ctrl = readl(&dbc->regs->control);
  585. }
  586. break;
  587. case DS_STALLED:
  588. ctrl = readl(&dbc->regs->control);
  589. if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
  590. !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
  591. (ctrl & DBC_CTRL_DBC_RUN)) {
  592. dbc->state = DS_CONFIGURED;
  593. break;
  594. }
  595. return EVT_DONE;
  596. default:
  597. xhci_err(xhci, "Unknown DbC state %d\n", dbc->state);
  598. break;
  599. }
  600. /* Handle the events in the event ring: */
  601. evt = dbc->ring_evt->dequeue;
  602. while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
  603. dbc->ring_evt->cycle_state) {
  604. /*
  605. * Add a barrier between reading the cycle flag and any
  606. * reads of the event's flags/data below:
  607. */
  608. rmb();
  609. trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
  610. switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
  611. case TRB_TYPE(TRB_PORT_STATUS):
  612. dbc_handle_port_status(xhci, evt);
  613. break;
  614. case TRB_TYPE(TRB_TRANSFER):
  615. dbc_handle_xfer_event(xhci, evt);
  616. break;
  617. default:
  618. break;
  619. }
  620. inc_deq(xhci, dbc->ring_evt);
  621. evt = dbc->ring_evt->dequeue;
  622. update_erdp = true;
  623. }
  624. /* Update event ring dequeue pointer: */
  625. if (update_erdp) {
  626. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  627. dbc->ring_evt->dequeue);
  628. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  629. }
  630. return EVT_DONE;
  631. }
  632. static void xhci_dbc_handle_events(struct work_struct *work)
  633. {
  634. int ret;
  635. enum evtreturn evtr;
  636. struct xhci_dbc *dbc;
  637. unsigned long flags;
  638. struct xhci_hcd *xhci;
  639. dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
  640. xhci = dbc->xhci;
  641. spin_lock_irqsave(&dbc->lock, flags);
  642. evtr = xhci_dbc_do_handle_events(dbc);
  643. spin_unlock_irqrestore(&dbc->lock, flags);
  644. switch (evtr) {
  645. case EVT_GSER:
  646. ret = xhci_dbc_tty_register_device(xhci);
  647. if (ret) {
  648. xhci_err(xhci, "failed to alloc tty device\n");
  649. break;
  650. }
  651. xhci_info(xhci, "DbC now attached to /dev/ttyDBC0\n");
  652. break;
  653. case EVT_DISC:
  654. xhci_dbc_tty_unregister_device(xhci);
  655. break;
  656. case EVT_DONE:
  657. break;
  658. default:
  659. xhci_info(xhci, "stop handling dbc events\n");
  660. return;
  661. }
  662. mod_delayed_work(system_wq, &dbc->event_work, 1);
  663. }
  664. static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
  665. {
  666. unsigned long flags;
  667. spin_lock_irqsave(&xhci->lock, flags);
  668. kfree(xhci->dbc);
  669. xhci->dbc = NULL;
  670. spin_unlock_irqrestore(&xhci->lock, flags);
  671. }
  672. static int xhci_do_dbc_init(struct xhci_hcd *xhci)
  673. {
  674. u32 reg;
  675. struct xhci_dbc *dbc;
  676. unsigned long flags;
  677. void __iomem *base;
  678. int dbc_cap_offs;
  679. base = &xhci->cap_regs->hc_capbase;
  680. dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
  681. if (!dbc_cap_offs)
  682. return -ENODEV;
  683. dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
  684. if (!dbc)
  685. return -ENOMEM;
  686. dbc->regs = base + dbc_cap_offs;
  687. /* We will avoid using DbC in xhci driver if it's in use. */
  688. reg = readl(&dbc->regs->control);
  689. if (reg & DBC_CTRL_DBC_ENABLE) {
  690. kfree(dbc);
  691. return -EBUSY;
  692. }
  693. spin_lock_irqsave(&xhci->lock, flags);
  694. if (xhci->dbc) {
  695. spin_unlock_irqrestore(&xhci->lock, flags);
  696. kfree(dbc);
  697. return -EBUSY;
  698. }
  699. xhci->dbc = dbc;
  700. spin_unlock_irqrestore(&xhci->lock, flags);
  701. dbc->xhci = xhci;
  702. INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
  703. spin_lock_init(&dbc->lock);
  704. return 0;
  705. }
  706. static ssize_t dbc_show(struct device *dev,
  707. struct device_attribute *attr,
  708. char *buf)
  709. {
  710. const char *p;
  711. struct xhci_dbc *dbc;
  712. struct xhci_hcd *xhci;
  713. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  714. dbc = xhci->dbc;
  715. switch (dbc->state) {
  716. case DS_DISABLED:
  717. p = "disabled";
  718. break;
  719. case DS_INITIALIZED:
  720. p = "initialized";
  721. break;
  722. case DS_ENABLED:
  723. p = "enabled";
  724. break;
  725. case DS_CONNECTED:
  726. p = "connected";
  727. break;
  728. case DS_CONFIGURED:
  729. p = "configured";
  730. break;
  731. case DS_STALLED:
  732. p = "stalled";
  733. break;
  734. default:
  735. p = "unknown";
  736. }
  737. return sprintf(buf, "%s\n", p);
  738. }
  739. static ssize_t dbc_store(struct device *dev,
  740. struct device_attribute *attr,
  741. const char *buf, size_t count)
  742. {
  743. struct xhci_dbc *dbc;
  744. struct xhci_hcd *xhci;
  745. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  746. dbc = xhci->dbc;
  747. if (!strncmp(buf, "enable", 6))
  748. xhci_dbc_start(xhci);
  749. else if (!strncmp(buf, "disable", 7))
  750. xhci_dbc_stop(xhci);
  751. else
  752. return -EINVAL;
  753. return count;
  754. }
  755. static DEVICE_ATTR_RW(dbc);
  756. int xhci_dbc_init(struct xhci_hcd *xhci)
  757. {
  758. int ret;
  759. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  760. ret = xhci_do_dbc_init(xhci);
  761. if (ret)
  762. goto init_err3;
  763. ret = xhci_dbc_tty_register_driver(xhci);
  764. if (ret)
  765. goto init_err2;
  766. ret = device_create_file(dev, &dev_attr_dbc);
  767. if (ret)
  768. goto init_err1;
  769. return 0;
  770. init_err1:
  771. xhci_dbc_tty_unregister_driver();
  772. init_err2:
  773. xhci_do_dbc_exit(xhci);
  774. init_err3:
  775. return ret;
  776. }
  777. void xhci_dbc_exit(struct xhci_hcd *xhci)
  778. {
  779. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  780. if (!xhci->dbc)
  781. return;
  782. device_remove_file(dev, &dev_attr_dbc);
  783. xhci_dbc_tty_unregister_driver();
  784. xhci_dbc_stop(xhci);
  785. xhci_do_dbc_exit(xhci);
  786. }
  787. #ifdef CONFIG_PM
  788. int xhci_dbc_suspend(struct xhci_hcd *xhci)
  789. {
  790. struct xhci_dbc *dbc = xhci->dbc;
  791. if (!dbc)
  792. return 0;
  793. if (dbc->state == DS_CONFIGURED)
  794. dbc->resume_required = 1;
  795. xhci_dbc_stop(xhci);
  796. return 0;
  797. }
  798. int xhci_dbc_resume(struct xhci_hcd *xhci)
  799. {
  800. int ret = 0;
  801. struct xhci_dbc *dbc = xhci->dbc;
  802. if (!dbc)
  803. return 0;
  804. if (dbc->resume_required) {
  805. dbc->resume_required = 0;
  806. xhci_dbc_start(xhci);
  807. }
  808. return ret;
  809. }
  810. #endif /* CONFIG_PM */