atmel_usba_udc.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Atmel USBA high speed USB device controller
  4. *
  5. * Copyright (C) 2005-2007 Atmel Corporation
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/clk/at91_pmc.h>
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/slab.h>
  14. #include <linux/device.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/list.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/ctype.h>
  21. #include <linux/usb/ch9.h>
  22. #include <linux/usb/gadget.h>
  23. #include <linux/usb/atmel_usba_udc.h>
  24. #include <linux/delay.h>
  25. #include <linux/of.h>
  26. #include <linux/irq.h>
  27. #include <linux/gpio/consumer.h>
  28. #include "atmel_usba_udc.h"
  29. #define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \
  30. | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)
  31. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  32. #include <linux/debugfs.h>
  33. #include <linux/uaccess.h>
  34. static int queue_dbg_open(struct inode *inode, struct file *file)
  35. {
  36. struct usba_ep *ep = inode->i_private;
  37. struct usba_request *req, *req_copy;
  38. struct list_head *queue_data;
  39. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  40. if (!queue_data)
  41. return -ENOMEM;
  42. INIT_LIST_HEAD(queue_data);
  43. spin_lock_irq(&ep->udc->lock);
  44. list_for_each_entry(req, &ep->queue, queue) {
  45. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  46. if (!req_copy)
  47. goto fail;
  48. list_add_tail(&req_copy->queue, queue_data);
  49. }
  50. spin_unlock_irq(&ep->udc->lock);
  51. file->private_data = queue_data;
  52. return 0;
  53. fail:
  54. spin_unlock_irq(&ep->udc->lock);
  55. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  56. list_del(&req->queue);
  57. kfree(req);
  58. }
  59. kfree(queue_data);
  60. return -ENOMEM;
  61. }
  62. /*
  63. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  64. *
  65. * b: buffer address
  66. * l: buffer length
  67. * I/i: interrupt/no interrupt
  68. * Z/z: zero/no zero
  69. * S/s: short ok/short not ok
  70. * s: status
  71. * n: nr_packets
  72. * F/f: submitted/not submitted to FIFO
  73. * D/d: using/not using DMA
  74. * L/l: last transaction/not last transaction
  75. */
  76. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  77. size_t nbytes, loff_t *ppos)
  78. {
  79. struct list_head *queue = file->private_data;
  80. struct usba_request *req, *tmp_req;
  81. size_t len, remaining, actual = 0;
  82. char tmpbuf[38];
  83. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  84. return -EFAULT;
  85. inode_lock(file_inode(file));
  86. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  87. len = snprintf(tmpbuf, sizeof(tmpbuf),
  88. "%8p %08x %c%c%c %5d %c%c%c\n",
  89. req->req.buf, req->req.length,
  90. req->req.no_interrupt ? 'i' : 'I',
  91. req->req.zero ? 'Z' : 'z',
  92. req->req.short_not_ok ? 's' : 'S',
  93. req->req.status,
  94. req->submitted ? 'F' : 'f',
  95. req->using_dma ? 'D' : 'd',
  96. req->last_transaction ? 'L' : 'l');
  97. len = min(len, sizeof(tmpbuf));
  98. if (len > nbytes)
  99. break;
  100. list_del(&req->queue);
  101. kfree(req);
  102. remaining = __copy_to_user(buf, tmpbuf, len);
  103. actual += len - remaining;
  104. if (remaining)
  105. break;
  106. nbytes -= len;
  107. buf += len;
  108. }
  109. inode_unlock(file_inode(file));
  110. return actual;
  111. }
  112. static int queue_dbg_release(struct inode *inode, struct file *file)
  113. {
  114. struct list_head *queue_data = file->private_data;
  115. struct usba_request *req, *tmp_req;
  116. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  117. list_del(&req->queue);
  118. kfree(req);
  119. }
  120. kfree(queue_data);
  121. return 0;
  122. }
  123. static int regs_dbg_open(struct inode *inode, struct file *file)
  124. {
  125. struct usba_udc *udc;
  126. unsigned int i;
  127. u32 *data;
  128. int ret = -ENOMEM;
  129. inode_lock(inode);
  130. udc = inode->i_private;
  131. data = kmalloc(inode->i_size, GFP_KERNEL);
  132. if (!data)
  133. goto out;
  134. spin_lock_irq(&udc->lock);
  135. for (i = 0; i < inode->i_size / 4; i++)
  136. data[i] = readl_relaxed(udc->regs + i * 4);
  137. spin_unlock_irq(&udc->lock);
  138. file->private_data = data;
  139. ret = 0;
  140. out:
  141. inode_unlock(inode);
  142. return ret;
  143. }
  144. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  145. size_t nbytes, loff_t *ppos)
  146. {
  147. struct inode *inode = file_inode(file);
  148. int ret;
  149. inode_lock(inode);
  150. ret = simple_read_from_buffer(buf, nbytes, ppos,
  151. file->private_data,
  152. file_inode(file)->i_size);
  153. inode_unlock(inode);
  154. return ret;
  155. }
  156. static int regs_dbg_release(struct inode *inode, struct file *file)
  157. {
  158. kfree(file->private_data);
  159. return 0;
  160. }
  161. const struct file_operations queue_dbg_fops = {
  162. .owner = THIS_MODULE,
  163. .open = queue_dbg_open,
  164. .llseek = no_llseek,
  165. .read = queue_dbg_read,
  166. .release = queue_dbg_release,
  167. };
  168. const struct file_operations regs_dbg_fops = {
  169. .owner = THIS_MODULE,
  170. .open = regs_dbg_open,
  171. .llseek = generic_file_llseek,
  172. .read = regs_dbg_read,
  173. .release = regs_dbg_release,
  174. };
  175. static void usba_ep_init_debugfs(struct usba_udc *udc,
  176. struct usba_ep *ep)
  177. {
  178. struct dentry *ep_root;
  179. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  180. if (!ep_root)
  181. goto err_root;
  182. ep->debugfs_dir = ep_root;
  183. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  184. ep, &queue_dbg_fops);
  185. if (!ep->debugfs_queue)
  186. goto err_queue;
  187. if (ep->can_dma) {
  188. ep->debugfs_dma_status
  189. = debugfs_create_u32("dma_status", 0400, ep_root,
  190. &ep->last_dma_status);
  191. if (!ep->debugfs_dma_status)
  192. goto err_dma_status;
  193. }
  194. if (ep_is_control(ep)) {
  195. ep->debugfs_state
  196. = debugfs_create_u32("state", 0400, ep_root,
  197. &ep->state);
  198. if (!ep->debugfs_state)
  199. goto err_state;
  200. }
  201. return;
  202. err_state:
  203. if (ep->can_dma)
  204. debugfs_remove(ep->debugfs_dma_status);
  205. err_dma_status:
  206. debugfs_remove(ep->debugfs_queue);
  207. err_queue:
  208. debugfs_remove(ep_root);
  209. err_root:
  210. dev_err(&ep->udc->pdev->dev,
  211. "failed to create debugfs directory for %s\n", ep->ep.name);
  212. }
  213. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  214. {
  215. debugfs_remove(ep->debugfs_queue);
  216. debugfs_remove(ep->debugfs_dma_status);
  217. debugfs_remove(ep->debugfs_state);
  218. debugfs_remove(ep->debugfs_dir);
  219. ep->debugfs_dma_status = NULL;
  220. ep->debugfs_dir = NULL;
  221. }
  222. static void usba_init_debugfs(struct usba_udc *udc)
  223. {
  224. struct dentry *root, *regs;
  225. struct resource *regs_resource;
  226. root = debugfs_create_dir(udc->gadget.name, NULL);
  227. if (IS_ERR(root) || !root)
  228. goto err_root;
  229. udc->debugfs_root = root;
  230. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  231. CTRL_IOMEM_ID);
  232. if (regs_resource) {
  233. regs = debugfs_create_file_size("regs", 0400, root, udc,
  234. &regs_dbg_fops,
  235. resource_size(regs_resource));
  236. if (!regs)
  237. goto err_regs;
  238. udc->debugfs_regs = regs;
  239. }
  240. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  241. return;
  242. err_regs:
  243. debugfs_remove(root);
  244. err_root:
  245. udc->debugfs_root = NULL;
  246. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  247. }
  248. static void usba_cleanup_debugfs(struct usba_udc *udc)
  249. {
  250. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  251. debugfs_remove(udc->debugfs_regs);
  252. debugfs_remove(udc->debugfs_root);
  253. udc->debugfs_regs = NULL;
  254. udc->debugfs_root = NULL;
  255. }
  256. #else
  257. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  258. struct usba_ep *ep)
  259. {
  260. }
  261. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  262. {
  263. }
  264. static inline void usba_init_debugfs(struct usba_udc *udc)
  265. {
  266. }
  267. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  268. {
  269. }
  270. #endif
  271. static ushort fifo_mode;
  272. module_param(fifo_mode, ushort, 0x0);
  273. MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
  274. /* mode 0 - uses autoconfig */
  275. /* mode 1 - fits in 8KB, generic max fifo configuration */
  276. static struct usba_fifo_cfg mode_1_cfg[] = {
  277. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  278. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
  279. { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, },
  280. { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, },
  281. { .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, },
  282. { .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, },
  283. { .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, },
  284. };
  285. /* mode 2 - fits in 8KB, performance max fifo configuration */
  286. static struct usba_fifo_cfg mode_2_cfg[] = {
  287. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  288. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, },
  289. { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, },
  290. { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, },
  291. };
  292. /* mode 3 - fits in 8KB, mixed fifo configuration */
  293. static struct usba_fifo_cfg mode_3_cfg[] = {
  294. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  295. { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, },
  296. { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
  297. { .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, },
  298. { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
  299. { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
  300. { .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, },
  301. };
  302. /* mode 4 - fits in 8KB, custom fifo configuration */
  303. static struct usba_fifo_cfg mode_4_cfg[] = {
  304. { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, },
  305. { .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, },
  306. { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, },
  307. { .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, },
  308. { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, },
  309. { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, },
  310. { .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, },
  311. { .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, },
  312. { .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, },
  313. };
  314. /* Add additional configurations here */
  315. static int usba_config_fifo_table(struct usba_udc *udc)
  316. {
  317. int n;
  318. switch (fifo_mode) {
  319. default:
  320. fifo_mode = 0;
  321. case 0:
  322. udc->fifo_cfg = NULL;
  323. n = 0;
  324. break;
  325. case 1:
  326. udc->fifo_cfg = mode_1_cfg;
  327. n = ARRAY_SIZE(mode_1_cfg);
  328. break;
  329. case 2:
  330. udc->fifo_cfg = mode_2_cfg;
  331. n = ARRAY_SIZE(mode_2_cfg);
  332. break;
  333. case 3:
  334. udc->fifo_cfg = mode_3_cfg;
  335. n = ARRAY_SIZE(mode_3_cfg);
  336. break;
  337. case 4:
  338. udc->fifo_cfg = mode_4_cfg;
  339. n = ARRAY_SIZE(mode_4_cfg);
  340. break;
  341. }
  342. DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
  343. return n;
  344. }
  345. static inline u32 usba_int_enb_get(struct usba_udc *udc)
  346. {
  347. return udc->int_enb_cache;
  348. }
  349. static inline void usba_int_enb_set(struct usba_udc *udc, u32 val)
  350. {
  351. usba_writel(udc, INT_ENB, val);
  352. udc->int_enb_cache = val;
  353. }
  354. static int vbus_is_present(struct usba_udc *udc)
  355. {
  356. if (udc->vbus_pin)
  357. return gpiod_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  358. /* No Vbus detection: Assume always present */
  359. return 1;
  360. }
  361. static void toggle_bias(struct usba_udc *udc, int is_on)
  362. {
  363. if (udc->errata && udc->errata->toggle_bias)
  364. udc->errata->toggle_bias(udc, is_on);
  365. }
  366. static void generate_bias_pulse(struct usba_udc *udc)
  367. {
  368. if (!udc->bias_pulse_needed)
  369. return;
  370. if (udc->errata && udc->errata->pulse_bias)
  371. udc->errata->pulse_bias(udc);
  372. udc->bias_pulse_needed = false;
  373. }
  374. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  375. {
  376. unsigned int transaction_len;
  377. transaction_len = req->req.length - req->req.actual;
  378. req->last_transaction = 1;
  379. if (transaction_len > ep->ep.maxpacket) {
  380. transaction_len = ep->ep.maxpacket;
  381. req->last_transaction = 0;
  382. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  383. req->last_transaction = 0;
  384. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  385. ep->ep.name, req, transaction_len,
  386. req->last_transaction ? ", done" : "");
  387. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  388. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  389. req->req.actual += transaction_len;
  390. }
  391. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  392. {
  393. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  394. ep->ep.name, req, req->req.length);
  395. req->req.actual = 0;
  396. req->submitted = 1;
  397. if (req->using_dma) {
  398. if (req->req.length == 0) {
  399. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  400. return;
  401. }
  402. if (req->req.zero)
  403. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  404. else
  405. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  406. usba_dma_writel(ep, ADDRESS, req->req.dma);
  407. usba_dma_writel(ep, CONTROL, req->ctrl);
  408. } else {
  409. next_fifo_transaction(ep, req);
  410. if (req->last_transaction) {
  411. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  412. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  413. } else {
  414. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  415. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  416. }
  417. }
  418. }
  419. static void submit_next_request(struct usba_ep *ep)
  420. {
  421. struct usba_request *req;
  422. if (list_empty(&ep->queue)) {
  423. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  424. return;
  425. }
  426. req = list_entry(ep->queue.next, struct usba_request, queue);
  427. if (!req->submitted)
  428. submit_request(ep, req);
  429. }
  430. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  431. {
  432. ep->state = STATUS_STAGE_IN;
  433. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  434. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  435. }
  436. static void receive_data(struct usba_ep *ep)
  437. {
  438. struct usba_udc *udc = ep->udc;
  439. struct usba_request *req;
  440. unsigned long status;
  441. unsigned int bytecount, nr_busy;
  442. int is_complete = 0;
  443. status = usba_ep_readl(ep, STA);
  444. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  445. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  446. while (nr_busy > 0) {
  447. if (list_empty(&ep->queue)) {
  448. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  449. break;
  450. }
  451. req = list_entry(ep->queue.next,
  452. struct usba_request, queue);
  453. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  454. if (status & (1 << 31))
  455. is_complete = 1;
  456. if (req->req.actual + bytecount >= req->req.length) {
  457. is_complete = 1;
  458. bytecount = req->req.length - req->req.actual;
  459. }
  460. memcpy_fromio(req->req.buf + req->req.actual,
  461. ep->fifo, bytecount);
  462. req->req.actual += bytecount;
  463. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  464. if (is_complete) {
  465. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  466. req->req.status = 0;
  467. list_del_init(&req->queue);
  468. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  469. spin_unlock(&udc->lock);
  470. usb_gadget_giveback_request(&ep->ep, &req->req);
  471. spin_lock(&udc->lock);
  472. }
  473. status = usba_ep_readl(ep, STA);
  474. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  475. if (is_complete && ep_is_control(ep)) {
  476. send_status(udc, ep);
  477. break;
  478. }
  479. }
  480. }
  481. static void
  482. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  483. {
  484. struct usba_udc *udc = ep->udc;
  485. WARN_ON(!list_empty(&req->queue));
  486. if (req->req.status == -EINPROGRESS)
  487. req->req.status = status;
  488. if (req->using_dma)
  489. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  490. DBG(DBG_GADGET | DBG_REQ,
  491. "%s: req %p complete: status %d, actual %u\n",
  492. ep->ep.name, req, req->req.status, req->req.actual);
  493. spin_unlock(&udc->lock);
  494. usb_gadget_giveback_request(&ep->ep, &req->req);
  495. spin_lock(&udc->lock);
  496. }
  497. static void
  498. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  499. {
  500. struct usba_request *req, *tmp_req;
  501. list_for_each_entry_safe(req, tmp_req, list, queue) {
  502. list_del_init(&req->queue);
  503. request_complete(ep, req, status);
  504. }
  505. }
  506. static int
  507. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  508. {
  509. struct usba_ep *ep = to_usba_ep(_ep);
  510. struct usba_udc *udc = ep->udc;
  511. unsigned long flags, maxpacket;
  512. unsigned int nr_trans;
  513. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  514. maxpacket = usb_endpoint_maxp(desc);
  515. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  516. || ep->index == 0
  517. || desc->bDescriptorType != USB_DT_ENDPOINT
  518. || maxpacket == 0
  519. || maxpacket > ep->fifo_size) {
  520. DBG(DBG_ERR, "ep_enable: Invalid argument");
  521. return -EINVAL;
  522. }
  523. ep->is_isoc = 0;
  524. ep->is_in = 0;
  525. DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
  526. ep->ep.name, ep->ept_cfg, maxpacket);
  527. if (usb_endpoint_dir_in(desc)) {
  528. ep->is_in = 1;
  529. ep->ept_cfg |= USBA_EPT_DIR_IN;
  530. }
  531. switch (usb_endpoint_type(desc)) {
  532. case USB_ENDPOINT_XFER_CONTROL:
  533. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  534. break;
  535. case USB_ENDPOINT_XFER_ISOC:
  536. if (!ep->can_isoc) {
  537. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  538. ep->ep.name);
  539. return -EINVAL;
  540. }
  541. /*
  542. * Bits 11:12 specify number of _additional_
  543. * transactions per microframe.
  544. */
  545. nr_trans = usb_endpoint_maxp_mult(desc);
  546. if (nr_trans > 3)
  547. return -EINVAL;
  548. ep->is_isoc = 1;
  549. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  550. ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  551. break;
  552. case USB_ENDPOINT_XFER_BULK:
  553. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  554. break;
  555. case USB_ENDPOINT_XFER_INT:
  556. ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  557. break;
  558. }
  559. spin_lock_irqsave(&ep->udc->lock, flags);
  560. ep->ep.desc = desc;
  561. ep->ep.maxpacket = maxpacket;
  562. usba_ep_writel(ep, CFG, ep->ept_cfg);
  563. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  564. if (ep->can_dma) {
  565. u32 ctrl;
  566. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  567. USBA_BF(EPT_INT, 1 << ep->index) |
  568. USBA_BF(DMA_INT, 1 << ep->index));
  569. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  570. usba_ep_writel(ep, CTL_ENB, ctrl);
  571. } else {
  572. usba_int_enb_set(udc, usba_int_enb_get(udc) |
  573. USBA_BF(EPT_INT, 1 << ep->index));
  574. }
  575. spin_unlock_irqrestore(&udc->lock, flags);
  576. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  577. (unsigned long)usba_ep_readl(ep, CFG));
  578. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  579. (unsigned long)usba_int_enb_get(udc));
  580. return 0;
  581. }
  582. static int usba_ep_disable(struct usb_ep *_ep)
  583. {
  584. struct usba_ep *ep = to_usba_ep(_ep);
  585. struct usba_udc *udc = ep->udc;
  586. LIST_HEAD(req_list);
  587. unsigned long flags;
  588. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  589. spin_lock_irqsave(&udc->lock, flags);
  590. if (!ep->ep.desc) {
  591. spin_unlock_irqrestore(&udc->lock, flags);
  592. /* REVISIT because this driver disables endpoints in
  593. * reset_all_endpoints() before calling disconnect(),
  594. * most gadget drivers would trigger this non-error ...
  595. */
  596. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  597. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  598. ep->ep.name);
  599. return -EINVAL;
  600. }
  601. ep->ep.desc = NULL;
  602. list_splice_init(&ep->queue, &req_list);
  603. if (ep->can_dma) {
  604. usba_dma_writel(ep, CONTROL, 0);
  605. usba_dma_writel(ep, ADDRESS, 0);
  606. usba_dma_readl(ep, STATUS);
  607. }
  608. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  609. usba_int_enb_set(udc, usba_int_enb_get(udc) &
  610. ~USBA_BF(EPT_INT, 1 << ep->index));
  611. request_complete_list(ep, &req_list, -ESHUTDOWN);
  612. spin_unlock_irqrestore(&udc->lock, flags);
  613. return 0;
  614. }
  615. static struct usb_request *
  616. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  617. {
  618. struct usba_request *req;
  619. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  620. req = kzalloc(sizeof(*req), gfp_flags);
  621. if (!req)
  622. return NULL;
  623. INIT_LIST_HEAD(&req->queue);
  624. return &req->req;
  625. }
  626. static void
  627. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  628. {
  629. struct usba_request *req = to_usba_req(_req);
  630. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  631. kfree(req);
  632. }
  633. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  634. struct usba_request *req, gfp_t gfp_flags)
  635. {
  636. unsigned long flags;
  637. int ret;
  638. DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
  639. ep->ep.name, req->req.length, &req->req.dma,
  640. req->req.zero ? 'Z' : 'z',
  641. req->req.short_not_ok ? 'S' : 's',
  642. req->req.no_interrupt ? 'I' : 'i');
  643. if (req->req.length > 0x10000) {
  644. /* Lengths from 0 to 65536 (inclusive) are supported */
  645. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  646. return -EINVAL;
  647. }
  648. ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
  649. if (ret)
  650. return ret;
  651. req->using_dma = 1;
  652. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  653. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  654. | USBA_DMA_END_BUF_EN;
  655. if (!ep->is_in)
  656. req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  657. /*
  658. * Add this request to the queue and submit for DMA if
  659. * possible. Check if we're still alive first -- we may have
  660. * received a reset since last time we checked.
  661. */
  662. ret = -ESHUTDOWN;
  663. spin_lock_irqsave(&udc->lock, flags);
  664. if (ep->ep.desc) {
  665. if (list_empty(&ep->queue))
  666. submit_request(ep, req);
  667. list_add_tail(&req->queue, &ep->queue);
  668. ret = 0;
  669. }
  670. spin_unlock_irqrestore(&udc->lock, flags);
  671. return ret;
  672. }
  673. static int
  674. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  675. {
  676. struct usba_request *req = to_usba_req(_req);
  677. struct usba_ep *ep = to_usba_ep(_ep);
  678. struct usba_udc *udc = ep->udc;
  679. unsigned long flags;
  680. int ret;
  681. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  682. ep->ep.name, req, _req->length);
  683. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  684. !ep->ep.desc)
  685. return -ESHUTDOWN;
  686. req->submitted = 0;
  687. req->using_dma = 0;
  688. req->last_transaction = 0;
  689. _req->status = -EINPROGRESS;
  690. _req->actual = 0;
  691. if (ep->can_dma)
  692. return queue_dma(udc, ep, req, gfp_flags);
  693. /* May have received a reset since last time we checked */
  694. ret = -ESHUTDOWN;
  695. spin_lock_irqsave(&udc->lock, flags);
  696. if (ep->ep.desc) {
  697. list_add_tail(&req->queue, &ep->queue);
  698. if ((!ep_is_control(ep) && ep->is_in) ||
  699. (ep_is_control(ep)
  700. && (ep->state == DATA_STAGE_IN
  701. || ep->state == STATUS_STAGE_IN)))
  702. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  703. else
  704. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  705. ret = 0;
  706. }
  707. spin_unlock_irqrestore(&udc->lock, flags);
  708. return ret;
  709. }
  710. static void
  711. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  712. {
  713. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  714. }
  715. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  716. {
  717. unsigned int timeout;
  718. u32 status;
  719. /*
  720. * Stop the DMA controller. When writing both CH_EN
  721. * and LINK to 0, the other bits are not affected.
  722. */
  723. usba_dma_writel(ep, CONTROL, 0);
  724. /* Wait for the FIFO to empty */
  725. for (timeout = 40; timeout; --timeout) {
  726. status = usba_dma_readl(ep, STATUS);
  727. if (!(status & USBA_DMA_CH_EN))
  728. break;
  729. udelay(1);
  730. }
  731. if (pstatus)
  732. *pstatus = status;
  733. if (timeout == 0) {
  734. dev_err(&ep->udc->pdev->dev,
  735. "%s: timed out waiting for DMA FIFO to empty\n",
  736. ep->ep.name);
  737. return -ETIMEDOUT;
  738. }
  739. return 0;
  740. }
  741. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  742. {
  743. struct usba_ep *ep = to_usba_ep(_ep);
  744. struct usba_udc *udc = ep->udc;
  745. struct usba_request *req;
  746. unsigned long flags;
  747. u32 status;
  748. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  749. ep->ep.name, req);
  750. spin_lock_irqsave(&udc->lock, flags);
  751. list_for_each_entry(req, &ep->queue, queue) {
  752. if (&req->req == _req)
  753. break;
  754. }
  755. if (&req->req != _req) {
  756. spin_unlock_irqrestore(&udc->lock, flags);
  757. return -EINVAL;
  758. }
  759. if (req->using_dma) {
  760. /*
  761. * If this request is currently being transferred,
  762. * stop the DMA controller and reset the FIFO.
  763. */
  764. if (ep->queue.next == &req->queue) {
  765. status = usba_dma_readl(ep, STATUS);
  766. if (status & USBA_DMA_CH_EN)
  767. stop_dma(ep, &status);
  768. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  769. ep->last_dma_status = status;
  770. #endif
  771. usba_writel(udc, EPT_RST, 1 << ep->index);
  772. usba_update_req(ep, req, status);
  773. }
  774. }
  775. /*
  776. * Errors should stop the queue from advancing until the
  777. * completion function returns.
  778. */
  779. list_del_init(&req->queue);
  780. request_complete(ep, req, -ECONNRESET);
  781. /* Process the next request if any */
  782. submit_next_request(ep);
  783. spin_unlock_irqrestore(&udc->lock, flags);
  784. return 0;
  785. }
  786. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  787. {
  788. struct usba_ep *ep = to_usba_ep(_ep);
  789. struct usba_udc *udc = ep->udc;
  790. unsigned long flags;
  791. int ret = 0;
  792. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  793. value ? "set" : "clear");
  794. if (!ep->ep.desc) {
  795. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  796. ep->ep.name);
  797. return -ENODEV;
  798. }
  799. if (ep->is_isoc) {
  800. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  801. ep->ep.name);
  802. return -ENOTTY;
  803. }
  804. spin_lock_irqsave(&udc->lock, flags);
  805. /*
  806. * We can't halt IN endpoints while there are still data to be
  807. * transferred
  808. */
  809. if (!list_empty(&ep->queue)
  810. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  811. & USBA_BF(BUSY_BANKS, -1L))))) {
  812. ret = -EAGAIN;
  813. } else {
  814. if (value)
  815. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  816. else
  817. usba_ep_writel(ep, CLR_STA,
  818. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  819. usba_ep_readl(ep, STA);
  820. }
  821. spin_unlock_irqrestore(&udc->lock, flags);
  822. return ret;
  823. }
  824. static int usba_ep_fifo_status(struct usb_ep *_ep)
  825. {
  826. struct usba_ep *ep = to_usba_ep(_ep);
  827. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  828. }
  829. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  830. {
  831. struct usba_ep *ep = to_usba_ep(_ep);
  832. struct usba_udc *udc = ep->udc;
  833. usba_writel(udc, EPT_RST, 1 << ep->index);
  834. }
  835. static const struct usb_ep_ops usba_ep_ops = {
  836. .enable = usba_ep_enable,
  837. .disable = usba_ep_disable,
  838. .alloc_request = usba_ep_alloc_request,
  839. .free_request = usba_ep_free_request,
  840. .queue = usba_ep_queue,
  841. .dequeue = usba_ep_dequeue,
  842. .set_halt = usba_ep_set_halt,
  843. .fifo_status = usba_ep_fifo_status,
  844. .fifo_flush = usba_ep_fifo_flush,
  845. };
  846. static int usba_udc_get_frame(struct usb_gadget *gadget)
  847. {
  848. struct usba_udc *udc = to_usba_udc(gadget);
  849. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  850. }
  851. static int usba_udc_wakeup(struct usb_gadget *gadget)
  852. {
  853. struct usba_udc *udc = to_usba_udc(gadget);
  854. unsigned long flags;
  855. u32 ctrl;
  856. int ret = -EINVAL;
  857. spin_lock_irqsave(&udc->lock, flags);
  858. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  859. ctrl = usba_readl(udc, CTRL);
  860. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  861. ret = 0;
  862. }
  863. spin_unlock_irqrestore(&udc->lock, flags);
  864. return ret;
  865. }
  866. static int
  867. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  868. {
  869. struct usba_udc *udc = to_usba_udc(gadget);
  870. unsigned long flags;
  871. gadget->is_selfpowered = (is_selfpowered != 0);
  872. spin_lock_irqsave(&udc->lock, flags);
  873. if (is_selfpowered)
  874. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  875. else
  876. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  877. spin_unlock_irqrestore(&udc->lock, flags);
  878. return 0;
  879. }
  880. static int atmel_usba_start(struct usb_gadget *gadget,
  881. struct usb_gadget_driver *driver);
  882. static int atmel_usba_stop(struct usb_gadget *gadget);
  883. static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget,
  884. struct usb_endpoint_descriptor *desc,
  885. struct usb_ss_ep_comp_descriptor *ep_comp)
  886. {
  887. struct usb_ep *_ep;
  888. struct usba_ep *ep;
  889. /* Look at endpoints until an unclaimed one looks usable */
  890. list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
  891. if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
  892. goto found_ep;
  893. }
  894. /* Fail */
  895. return NULL;
  896. found_ep:
  897. if (fifo_mode == 0) {
  898. /* Optimize hw fifo size based on ep type and other info */
  899. ep = to_usba_ep(_ep);
  900. switch (usb_endpoint_type(desc)) {
  901. case USB_ENDPOINT_XFER_CONTROL:
  902. break;
  903. case USB_ENDPOINT_XFER_ISOC:
  904. ep->fifo_size = 1024;
  905. ep->nr_banks = 2;
  906. break;
  907. case USB_ENDPOINT_XFER_BULK:
  908. ep->fifo_size = 512;
  909. ep->nr_banks = 1;
  910. break;
  911. case USB_ENDPOINT_XFER_INT:
  912. if (desc->wMaxPacketSize == 0)
  913. ep->fifo_size =
  914. roundup_pow_of_two(_ep->maxpacket_limit);
  915. else
  916. ep->fifo_size =
  917. roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
  918. ep->nr_banks = 1;
  919. break;
  920. }
  921. /* It might be a little bit late to set this */
  922. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  923. /* Generate ept_cfg basd on FIFO size and number of banks */
  924. if (ep->fifo_size <= 8)
  925. ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  926. else
  927. /* LSB is bit 1, not 0 */
  928. ep->ept_cfg =
  929. USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
  930. ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
  931. ep->udc->configured_ep++;
  932. }
  933. return _ep;
  934. }
  935. static const struct usb_gadget_ops usba_udc_ops = {
  936. .get_frame = usba_udc_get_frame,
  937. .wakeup = usba_udc_wakeup,
  938. .set_selfpowered = usba_udc_set_selfpowered,
  939. .udc_start = atmel_usba_start,
  940. .udc_stop = atmel_usba_stop,
  941. .match_ep = atmel_usba_match_ep,
  942. };
  943. static struct usb_endpoint_descriptor usba_ep0_desc = {
  944. .bLength = USB_DT_ENDPOINT_SIZE,
  945. .bDescriptorType = USB_DT_ENDPOINT,
  946. .bEndpointAddress = 0,
  947. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  948. .wMaxPacketSize = cpu_to_le16(64),
  949. /* FIXME: I have no idea what to put here */
  950. .bInterval = 1,
  951. };
  952. static struct usb_gadget usba_gadget_template = {
  953. .ops = &usba_udc_ops,
  954. .max_speed = USB_SPEED_HIGH,
  955. .name = "atmel_usba_udc",
  956. };
  957. /*
  958. * Called with interrupts disabled and udc->lock held.
  959. */
  960. static void reset_all_endpoints(struct usba_udc *udc)
  961. {
  962. struct usba_ep *ep;
  963. struct usba_request *req, *tmp_req;
  964. usba_writel(udc, EPT_RST, ~0UL);
  965. ep = to_usba_ep(udc->gadget.ep0);
  966. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  967. list_del_init(&req->queue);
  968. request_complete(ep, req, -ECONNRESET);
  969. }
  970. }
  971. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  972. {
  973. struct usba_ep *ep;
  974. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  975. return to_usba_ep(udc->gadget.ep0);
  976. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  977. u8 bEndpointAddress;
  978. if (!ep->ep.desc)
  979. continue;
  980. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  981. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  982. continue;
  983. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  984. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  985. return ep;
  986. }
  987. return NULL;
  988. }
  989. /* Called with interrupts disabled and udc->lock held */
  990. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  991. {
  992. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  993. ep->state = WAIT_FOR_SETUP;
  994. }
  995. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  996. {
  997. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  998. return 1;
  999. return 0;
  1000. }
  1001. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  1002. {
  1003. u32 regval;
  1004. DBG(DBG_BUS, "setting address %u...\n", addr);
  1005. regval = usba_readl(udc, CTRL);
  1006. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  1007. usba_writel(udc, CTRL, regval);
  1008. }
  1009. static int do_test_mode(struct usba_udc *udc)
  1010. {
  1011. static const char test_packet_buffer[] = {
  1012. /* JKJKJKJK * 9 */
  1013. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1014. /* JJKKJJKK * 8 */
  1015. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  1016. /* JJKKJJKK * 8 */
  1017. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  1018. /* JJJJJJJKKKKKKK * 8 */
  1019. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  1020. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  1021. /* JJJJJJJK * 8 */
  1022. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  1023. /* {JKKKKKKK * 10}, JK */
  1024. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  1025. };
  1026. struct usba_ep *ep;
  1027. struct device *dev = &udc->pdev->dev;
  1028. int test_mode;
  1029. test_mode = udc->test_mode;
  1030. /* Start from a clean slate */
  1031. reset_all_endpoints(udc);
  1032. switch (test_mode) {
  1033. case 0x0100:
  1034. /* Test_J */
  1035. usba_writel(udc, TST, USBA_TST_J_MODE);
  1036. dev_info(dev, "Entering Test_J mode...\n");
  1037. break;
  1038. case 0x0200:
  1039. /* Test_K */
  1040. usba_writel(udc, TST, USBA_TST_K_MODE);
  1041. dev_info(dev, "Entering Test_K mode...\n");
  1042. break;
  1043. case 0x0300:
  1044. /*
  1045. * Test_SE0_NAK: Force high-speed mode and set up ep0
  1046. * for Bulk IN transfers
  1047. */
  1048. ep = &udc->usba_ep[0];
  1049. usba_writel(udc, TST,
  1050. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  1051. usba_ep_writel(ep, CFG,
  1052. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  1053. | USBA_EPT_DIR_IN
  1054. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1055. | USBA_BF(BK_NUMBER, 1));
  1056. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1057. set_protocol_stall(udc, ep);
  1058. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  1059. } else {
  1060. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1061. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  1062. }
  1063. break;
  1064. case 0x0400:
  1065. /* Test_Packet */
  1066. ep = &udc->usba_ep[0];
  1067. usba_ep_writel(ep, CFG,
  1068. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  1069. | USBA_EPT_DIR_IN
  1070. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1071. | USBA_BF(BK_NUMBER, 1));
  1072. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1073. set_protocol_stall(udc, ep);
  1074. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  1075. } else {
  1076. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1077. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  1078. memcpy_toio(ep->fifo, test_packet_buffer,
  1079. sizeof(test_packet_buffer));
  1080. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1081. dev_info(dev, "Entering Test_Packet mode...\n");
  1082. }
  1083. break;
  1084. default:
  1085. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  1086. return -EINVAL;
  1087. }
  1088. return 0;
  1089. }
  1090. /* Avoid overly long expressions */
  1091. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  1092. {
  1093. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1094. return true;
  1095. return false;
  1096. }
  1097. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1098. {
  1099. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  1100. return true;
  1101. return false;
  1102. }
  1103. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1104. {
  1105. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1106. return true;
  1107. return false;
  1108. }
  1109. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1110. struct usb_ctrlrequest *crq)
  1111. {
  1112. int retval = 0;
  1113. switch (crq->bRequest) {
  1114. case USB_REQ_GET_STATUS: {
  1115. u16 status;
  1116. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1117. status = cpu_to_le16(udc->devstatus);
  1118. } else if (crq->bRequestType
  1119. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1120. status = cpu_to_le16(0);
  1121. } else if (crq->bRequestType
  1122. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1123. struct usba_ep *target;
  1124. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1125. if (!target)
  1126. goto stall;
  1127. status = 0;
  1128. if (is_stalled(udc, target))
  1129. status |= cpu_to_le16(1);
  1130. } else
  1131. goto delegate;
  1132. /* Write directly to the FIFO. No queueing is done. */
  1133. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1134. goto stall;
  1135. ep->state = DATA_STAGE_IN;
  1136. writew_relaxed(status, ep->fifo);
  1137. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1138. break;
  1139. }
  1140. case USB_REQ_CLEAR_FEATURE: {
  1141. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1142. if (feature_is_dev_remote_wakeup(crq))
  1143. udc->devstatus
  1144. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1145. else
  1146. /* Can't CLEAR_FEATURE TEST_MODE */
  1147. goto stall;
  1148. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1149. struct usba_ep *target;
  1150. if (crq->wLength != cpu_to_le16(0)
  1151. || !feature_is_ep_halt(crq))
  1152. goto stall;
  1153. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1154. if (!target)
  1155. goto stall;
  1156. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1157. if (target->index != 0)
  1158. usba_ep_writel(target, CLR_STA,
  1159. USBA_TOGGLE_CLR);
  1160. } else {
  1161. goto delegate;
  1162. }
  1163. send_status(udc, ep);
  1164. break;
  1165. }
  1166. case USB_REQ_SET_FEATURE: {
  1167. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1168. if (feature_is_dev_test_mode(crq)) {
  1169. send_status(udc, ep);
  1170. ep->state = STATUS_STAGE_TEST;
  1171. udc->test_mode = le16_to_cpu(crq->wIndex);
  1172. return 0;
  1173. } else if (feature_is_dev_remote_wakeup(crq)) {
  1174. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1175. } else {
  1176. goto stall;
  1177. }
  1178. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1179. struct usba_ep *target;
  1180. if (crq->wLength != cpu_to_le16(0)
  1181. || !feature_is_ep_halt(crq))
  1182. goto stall;
  1183. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1184. if (!target)
  1185. goto stall;
  1186. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1187. } else
  1188. goto delegate;
  1189. send_status(udc, ep);
  1190. break;
  1191. }
  1192. case USB_REQ_SET_ADDRESS:
  1193. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1194. goto delegate;
  1195. set_address(udc, le16_to_cpu(crq->wValue));
  1196. send_status(udc, ep);
  1197. ep->state = STATUS_STAGE_ADDR;
  1198. break;
  1199. default:
  1200. delegate:
  1201. spin_unlock(&udc->lock);
  1202. retval = udc->driver->setup(&udc->gadget, crq);
  1203. spin_lock(&udc->lock);
  1204. }
  1205. return retval;
  1206. stall:
  1207. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1208. "halting endpoint...\n",
  1209. ep->ep.name, crq->bRequestType, crq->bRequest,
  1210. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1211. le16_to_cpu(crq->wLength));
  1212. set_protocol_stall(udc, ep);
  1213. return -1;
  1214. }
  1215. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1216. {
  1217. struct usba_request *req;
  1218. u32 epstatus;
  1219. u32 epctrl;
  1220. restart:
  1221. epstatus = usba_ep_readl(ep, STA);
  1222. epctrl = usba_ep_readl(ep, CTL);
  1223. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1224. ep->ep.name, ep->state, epstatus, epctrl);
  1225. req = NULL;
  1226. if (!list_empty(&ep->queue))
  1227. req = list_entry(ep->queue.next,
  1228. struct usba_request, queue);
  1229. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1230. if (req->submitted)
  1231. next_fifo_transaction(ep, req);
  1232. else
  1233. submit_request(ep, req);
  1234. if (req->last_transaction) {
  1235. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1236. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1237. }
  1238. goto restart;
  1239. }
  1240. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1241. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1242. switch (ep->state) {
  1243. case DATA_STAGE_IN:
  1244. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1245. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1246. ep->state = STATUS_STAGE_OUT;
  1247. break;
  1248. case STATUS_STAGE_ADDR:
  1249. /* Activate our new address */
  1250. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1251. | USBA_FADDR_EN));
  1252. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1253. ep->state = WAIT_FOR_SETUP;
  1254. break;
  1255. case STATUS_STAGE_IN:
  1256. if (req) {
  1257. list_del_init(&req->queue);
  1258. request_complete(ep, req, 0);
  1259. submit_next_request(ep);
  1260. }
  1261. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1262. ep->state = WAIT_FOR_SETUP;
  1263. break;
  1264. case STATUS_STAGE_TEST:
  1265. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1266. ep->state = WAIT_FOR_SETUP;
  1267. if (do_test_mode(udc))
  1268. set_protocol_stall(udc, ep);
  1269. break;
  1270. default:
  1271. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1272. "halting endpoint...\n",
  1273. ep->ep.name, ep->state);
  1274. set_protocol_stall(udc, ep);
  1275. break;
  1276. }
  1277. goto restart;
  1278. }
  1279. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1280. switch (ep->state) {
  1281. case STATUS_STAGE_OUT:
  1282. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1283. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1284. if (req) {
  1285. list_del_init(&req->queue);
  1286. request_complete(ep, req, 0);
  1287. }
  1288. ep->state = WAIT_FOR_SETUP;
  1289. break;
  1290. case DATA_STAGE_OUT:
  1291. receive_data(ep);
  1292. break;
  1293. default:
  1294. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1295. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1296. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1297. "halting endpoint...\n",
  1298. ep->ep.name, ep->state);
  1299. set_protocol_stall(udc, ep);
  1300. break;
  1301. }
  1302. goto restart;
  1303. }
  1304. if (epstatus & USBA_RX_SETUP) {
  1305. union {
  1306. struct usb_ctrlrequest crq;
  1307. unsigned long data[2];
  1308. } crq;
  1309. unsigned int pkt_len;
  1310. int ret;
  1311. if (ep->state != WAIT_FOR_SETUP) {
  1312. /*
  1313. * Didn't expect a SETUP packet at this
  1314. * point. Clean up any pending requests (which
  1315. * may be successful).
  1316. */
  1317. int status = -EPROTO;
  1318. /*
  1319. * RXRDY and TXCOMP are dropped when SETUP
  1320. * packets arrive. Just pretend we received
  1321. * the status packet.
  1322. */
  1323. if (ep->state == STATUS_STAGE_OUT
  1324. || ep->state == STATUS_STAGE_IN) {
  1325. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1326. status = 0;
  1327. }
  1328. if (req) {
  1329. list_del_init(&req->queue);
  1330. request_complete(ep, req, status);
  1331. }
  1332. }
  1333. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1334. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1335. if (pkt_len != sizeof(crq)) {
  1336. pr_warn("udc: Invalid packet length %u (expected %zu)\n",
  1337. pkt_len, sizeof(crq));
  1338. set_protocol_stall(udc, ep);
  1339. return;
  1340. }
  1341. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1342. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1343. /* Free up one bank in the FIFO so that we can
  1344. * generate or receive a reply right away. */
  1345. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1346. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1347. ep->state, crq.crq.bRequestType,
  1348. crq.crq.bRequest); */
  1349. if (crq.crq.bRequestType & USB_DIR_IN) {
  1350. /*
  1351. * The USB 2.0 spec states that "if wLength is
  1352. * zero, there is no data transfer phase."
  1353. * However, testusb #14 seems to actually
  1354. * expect a data phase even if wLength = 0...
  1355. */
  1356. ep->state = DATA_STAGE_IN;
  1357. } else {
  1358. if (crq.crq.wLength != cpu_to_le16(0))
  1359. ep->state = DATA_STAGE_OUT;
  1360. else
  1361. ep->state = STATUS_STAGE_IN;
  1362. }
  1363. ret = -1;
  1364. if (ep->index == 0)
  1365. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1366. else {
  1367. spin_unlock(&udc->lock);
  1368. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1369. spin_lock(&udc->lock);
  1370. }
  1371. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1372. crq.crq.bRequestType, crq.crq.bRequest,
  1373. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1374. if (ret < 0) {
  1375. /* Let the host know that we failed */
  1376. set_protocol_stall(udc, ep);
  1377. }
  1378. }
  1379. }
  1380. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1381. {
  1382. struct usba_request *req;
  1383. u32 epstatus;
  1384. u32 epctrl;
  1385. epstatus = usba_ep_readl(ep, STA);
  1386. epctrl = usba_ep_readl(ep, CTL);
  1387. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1388. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1389. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1390. if (list_empty(&ep->queue)) {
  1391. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1392. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1393. return;
  1394. }
  1395. req = list_entry(ep->queue.next, struct usba_request, queue);
  1396. if (req->using_dma) {
  1397. /* Send a zero-length packet */
  1398. usba_ep_writel(ep, SET_STA,
  1399. USBA_TX_PK_RDY);
  1400. usba_ep_writel(ep, CTL_DIS,
  1401. USBA_TX_PK_RDY);
  1402. list_del_init(&req->queue);
  1403. submit_next_request(ep);
  1404. request_complete(ep, req, 0);
  1405. } else {
  1406. if (req->submitted)
  1407. next_fifo_transaction(ep, req);
  1408. else
  1409. submit_request(ep, req);
  1410. if (req->last_transaction) {
  1411. list_del_init(&req->queue);
  1412. submit_next_request(ep);
  1413. request_complete(ep, req, 0);
  1414. }
  1415. }
  1416. epstatus = usba_ep_readl(ep, STA);
  1417. epctrl = usba_ep_readl(ep, CTL);
  1418. }
  1419. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1420. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1421. receive_data(ep);
  1422. }
  1423. }
  1424. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1425. {
  1426. struct usba_request *req;
  1427. u32 status, control, pending;
  1428. status = usba_dma_readl(ep, STATUS);
  1429. control = usba_dma_readl(ep, CONTROL);
  1430. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1431. ep->last_dma_status = status;
  1432. #endif
  1433. pending = status & control;
  1434. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1435. if (status & USBA_DMA_CH_EN) {
  1436. dev_err(&udc->pdev->dev,
  1437. "DMA_CH_EN is set after transfer is finished!\n");
  1438. dev_err(&udc->pdev->dev,
  1439. "status=%#08x, pending=%#08x, control=%#08x\n",
  1440. status, pending, control);
  1441. /*
  1442. * try to pretend nothing happened. We might have to
  1443. * do something here...
  1444. */
  1445. }
  1446. if (list_empty(&ep->queue))
  1447. /* Might happen if a reset comes along at the right moment */
  1448. return;
  1449. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1450. req = list_entry(ep->queue.next, struct usba_request, queue);
  1451. usba_update_req(ep, req, status);
  1452. list_del_init(&req->queue);
  1453. submit_next_request(ep);
  1454. request_complete(ep, req, 0);
  1455. }
  1456. }
  1457. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1458. {
  1459. struct usba_udc *udc = devid;
  1460. u32 status, int_enb;
  1461. u32 dma_status;
  1462. u32 ep_status;
  1463. spin_lock(&udc->lock);
  1464. int_enb = usba_int_enb_get(udc);
  1465. status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
  1466. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1467. if (status & USBA_DET_SUSPEND) {
  1468. toggle_bias(udc, 0);
  1469. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1470. usba_int_enb_set(udc, int_enb | USBA_WAKE_UP);
  1471. udc->bias_pulse_needed = true;
  1472. DBG(DBG_BUS, "Suspend detected\n");
  1473. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1474. && udc->driver && udc->driver->suspend) {
  1475. spin_unlock(&udc->lock);
  1476. udc->driver->suspend(&udc->gadget);
  1477. spin_lock(&udc->lock);
  1478. }
  1479. }
  1480. if (status & USBA_WAKE_UP) {
  1481. toggle_bias(udc, 1);
  1482. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1483. usba_int_enb_set(udc, int_enb & ~USBA_WAKE_UP);
  1484. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1485. }
  1486. if (status & USBA_END_OF_RESUME) {
  1487. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1488. generate_bias_pulse(udc);
  1489. DBG(DBG_BUS, "Resume detected\n");
  1490. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1491. && udc->driver && udc->driver->resume) {
  1492. spin_unlock(&udc->lock);
  1493. udc->driver->resume(&udc->gadget);
  1494. spin_lock(&udc->lock);
  1495. }
  1496. }
  1497. dma_status = USBA_BFEXT(DMA_INT, status);
  1498. if (dma_status) {
  1499. int i;
  1500. for (i = 1; i <= USBA_NR_DMAS; i++)
  1501. if (dma_status & (1 << i))
  1502. usba_dma_irq(udc, &udc->usba_ep[i]);
  1503. }
  1504. ep_status = USBA_BFEXT(EPT_INT, status);
  1505. if (ep_status) {
  1506. int i;
  1507. for (i = 0; i < udc->num_ep; i++)
  1508. if (ep_status & (1 << i)) {
  1509. if (ep_is_control(&udc->usba_ep[i]))
  1510. usba_control_irq(udc, &udc->usba_ep[i]);
  1511. else
  1512. usba_ep_irq(udc, &udc->usba_ep[i]);
  1513. }
  1514. }
  1515. if (status & USBA_END_OF_RESET) {
  1516. struct usba_ep *ep0, *ep;
  1517. int i, n;
  1518. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1519. generate_bias_pulse(udc);
  1520. reset_all_endpoints(udc);
  1521. if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
  1522. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1523. spin_unlock(&udc->lock);
  1524. usb_gadget_udc_reset(&udc->gadget, udc->driver);
  1525. spin_lock(&udc->lock);
  1526. }
  1527. if (status & USBA_HIGH_SPEED)
  1528. udc->gadget.speed = USB_SPEED_HIGH;
  1529. else
  1530. udc->gadget.speed = USB_SPEED_FULL;
  1531. DBG(DBG_BUS, "%s bus reset detected\n",
  1532. usb_speed_string(udc->gadget.speed));
  1533. ep0 = &udc->usba_ep[0];
  1534. ep0->ep.desc = &usba_ep0_desc;
  1535. ep0->state = WAIT_FOR_SETUP;
  1536. usba_ep_writel(ep0, CFG,
  1537. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1538. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1539. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1540. usba_ep_writel(ep0, CTL_ENB,
  1541. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1542. usba_int_enb_set(udc, int_enb | USBA_BF(EPT_INT, 1) |
  1543. USBA_DET_SUSPEND | USBA_END_OF_RESUME);
  1544. /*
  1545. * Unclear why we hit this irregularly, e.g. in usbtest,
  1546. * but it's clearly harmless...
  1547. */
  1548. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1549. dev_err(&udc->pdev->dev,
  1550. "ODD: EP0 configuration is invalid!\n");
  1551. /* Preallocate other endpoints */
  1552. n = fifo_mode ? udc->num_ep : udc->configured_ep;
  1553. for (i = 1; i < n; i++) {
  1554. ep = &udc->usba_ep[i];
  1555. usba_ep_writel(ep, CFG, ep->ept_cfg);
  1556. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
  1557. dev_err(&udc->pdev->dev,
  1558. "ODD: EP%d configuration is invalid!\n", i);
  1559. }
  1560. }
  1561. spin_unlock(&udc->lock);
  1562. return IRQ_HANDLED;
  1563. }
  1564. static int start_clock(struct usba_udc *udc)
  1565. {
  1566. int ret;
  1567. if (udc->clocked)
  1568. return 0;
  1569. ret = clk_prepare_enable(udc->pclk);
  1570. if (ret)
  1571. return ret;
  1572. ret = clk_prepare_enable(udc->hclk);
  1573. if (ret) {
  1574. clk_disable_unprepare(udc->pclk);
  1575. return ret;
  1576. }
  1577. udc->clocked = true;
  1578. return 0;
  1579. }
  1580. static void stop_clock(struct usba_udc *udc)
  1581. {
  1582. if (!udc->clocked)
  1583. return;
  1584. clk_disable_unprepare(udc->hclk);
  1585. clk_disable_unprepare(udc->pclk);
  1586. udc->clocked = false;
  1587. }
  1588. static int usba_start(struct usba_udc *udc)
  1589. {
  1590. unsigned long flags;
  1591. int ret;
  1592. ret = start_clock(udc);
  1593. if (ret)
  1594. return ret;
  1595. spin_lock_irqsave(&udc->lock, flags);
  1596. toggle_bias(udc, 1);
  1597. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1598. usba_int_enb_set(udc, USBA_END_OF_RESET);
  1599. spin_unlock_irqrestore(&udc->lock, flags);
  1600. return 0;
  1601. }
  1602. static void usba_stop(struct usba_udc *udc)
  1603. {
  1604. unsigned long flags;
  1605. spin_lock_irqsave(&udc->lock, flags);
  1606. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1607. reset_all_endpoints(udc);
  1608. /* This will also disable the DP pullup */
  1609. toggle_bias(udc, 0);
  1610. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1611. spin_unlock_irqrestore(&udc->lock, flags);
  1612. stop_clock(udc);
  1613. }
  1614. static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
  1615. {
  1616. struct usba_udc *udc = devid;
  1617. int vbus;
  1618. /* debounce */
  1619. udelay(10);
  1620. mutex_lock(&udc->vbus_mutex);
  1621. vbus = vbus_is_present(udc);
  1622. if (vbus != udc->vbus_prev) {
  1623. if (vbus) {
  1624. usba_start(udc);
  1625. } else {
  1626. usba_stop(udc);
  1627. if (udc->driver->disconnect)
  1628. udc->driver->disconnect(&udc->gadget);
  1629. }
  1630. udc->vbus_prev = vbus;
  1631. }
  1632. mutex_unlock(&udc->vbus_mutex);
  1633. return IRQ_HANDLED;
  1634. }
  1635. static int atmel_usba_start(struct usb_gadget *gadget,
  1636. struct usb_gadget_driver *driver)
  1637. {
  1638. int ret;
  1639. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1640. unsigned long flags;
  1641. spin_lock_irqsave(&udc->lock, flags);
  1642. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1643. udc->driver = driver;
  1644. spin_unlock_irqrestore(&udc->lock, flags);
  1645. mutex_lock(&udc->vbus_mutex);
  1646. if (udc->vbus_pin)
  1647. enable_irq(gpiod_to_irq(udc->vbus_pin));
  1648. /* If Vbus is present, enable the controller and wait for reset */
  1649. udc->vbus_prev = vbus_is_present(udc);
  1650. if (udc->vbus_prev) {
  1651. ret = usba_start(udc);
  1652. if (ret)
  1653. goto err;
  1654. }
  1655. mutex_unlock(&udc->vbus_mutex);
  1656. return 0;
  1657. err:
  1658. if (udc->vbus_pin)
  1659. disable_irq(gpiod_to_irq(udc->vbus_pin));
  1660. mutex_unlock(&udc->vbus_mutex);
  1661. spin_lock_irqsave(&udc->lock, flags);
  1662. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1663. udc->driver = NULL;
  1664. spin_unlock_irqrestore(&udc->lock, flags);
  1665. return ret;
  1666. }
  1667. static int atmel_usba_stop(struct usb_gadget *gadget)
  1668. {
  1669. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1670. if (udc->vbus_pin)
  1671. disable_irq(gpiod_to_irq(udc->vbus_pin));
  1672. if (fifo_mode == 0)
  1673. udc->configured_ep = 1;
  1674. usba_stop(udc);
  1675. udc->driver = NULL;
  1676. return 0;
  1677. }
  1678. static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
  1679. {
  1680. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1681. is_on ? AT91_PMC_BIASEN : 0);
  1682. }
  1683. static void at91sam9g45_pulse_bias(struct usba_udc *udc)
  1684. {
  1685. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
  1686. regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
  1687. AT91_PMC_BIASEN);
  1688. }
  1689. static const struct usba_udc_errata at91sam9rl_errata = {
  1690. .toggle_bias = at91sam9rl_toggle_bias,
  1691. };
  1692. static const struct usba_udc_errata at91sam9g45_errata = {
  1693. .pulse_bias = at91sam9g45_pulse_bias,
  1694. };
  1695. static const struct of_device_id atmel_udc_dt_ids[] = {
  1696. { .compatible = "atmel,at91sam9rl-udc", .data = &at91sam9rl_errata },
  1697. { .compatible = "atmel,at91sam9g45-udc", .data = &at91sam9g45_errata },
  1698. { .compatible = "atmel,sama5d3-udc" },
  1699. { /* sentinel */ }
  1700. };
  1701. MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
  1702. static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
  1703. struct usba_udc *udc)
  1704. {
  1705. u32 val;
  1706. const char *name;
  1707. struct device_node *np = pdev->dev.of_node;
  1708. const struct of_device_id *match;
  1709. struct device_node *pp;
  1710. int i, ret;
  1711. struct usba_ep *eps, *ep;
  1712. match = of_match_node(atmel_udc_dt_ids, np);
  1713. if (!match)
  1714. return ERR_PTR(-EINVAL);
  1715. udc->errata = match->data;
  1716. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
  1717. if (IS_ERR(udc->pmc))
  1718. udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
  1719. if (udc->errata && IS_ERR(udc->pmc))
  1720. return ERR_CAST(udc->pmc);
  1721. udc->num_ep = 0;
  1722. udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus",
  1723. GPIOD_IN);
  1724. udc->vbus_pin_inverted = gpiod_is_active_low(udc->vbus_pin);
  1725. if (fifo_mode == 0) {
  1726. pp = NULL;
  1727. while ((pp = of_get_next_child(np, pp)))
  1728. udc->num_ep++;
  1729. udc->configured_ep = 1;
  1730. } else {
  1731. udc->num_ep = usba_config_fifo_table(udc);
  1732. }
  1733. eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
  1734. GFP_KERNEL);
  1735. if (!eps)
  1736. return ERR_PTR(-ENOMEM);
  1737. udc->gadget.ep0 = &eps[0].ep;
  1738. INIT_LIST_HEAD(&eps[0].ep.ep_list);
  1739. pp = NULL;
  1740. i = 0;
  1741. while ((pp = of_get_next_child(np, pp)) && i < udc->num_ep) {
  1742. ep = &eps[i];
  1743. ret = of_property_read_u32(pp, "reg", &val);
  1744. if (ret) {
  1745. dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
  1746. goto err;
  1747. }
  1748. ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : val;
  1749. ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
  1750. if (ret) {
  1751. dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
  1752. goto err;
  1753. }
  1754. if (fifo_mode) {
  1755. if (val < udc->fifo_cfg[i].fifo_size) {
  1756. dev_warn(&pdev->dev,
  1757. "Using max fifo-size value from DT\n");
  1758. ep->fifo_size = val;
  1759. } else {
  1760. ep->fifo_size = udc->fifo_cfg[i].fifo_size;
  1761. }
  1762. } else {
  1763. ep->fifo_size = val;
  1764. }
  1765. ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
  1766. if (ret) {
  1767. dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
  1768. goto err;
  1769. }
  1770. if (fifo_mode) {
  1771. if (val < udc->fifo_cfg[i].nr_banks) {
  1772. dev_warn(&pdev->dev,
  1773. "Using max nb-banks value from DT\n");
  1774. ep->nr_banks = val;
  1775. } else {
  1776. ep->nr_banks = udc->fifo_cfg[i].nr_banks;
  1777. }
  1778. } else {
  1779. ep->nr_banks = val;
  1780. }
  1781. ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
  1782. ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
  1783. ret = of_property_read_string(pp, "name", &name);
  1784. if (ret) {
  1785. dev_err(&pdev->dev, "of_probe: name error(%d)\n", ret);
  1786. goto err;
  1787. }
  1788. sprintf(ep->name, "ep%d", ep->index);
  1789. ep->ep.name = ep->name;
  1790. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1791. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1792. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1793. ep->ep.ops = &usba_ep_ops;
  1794. usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
  1795. ep->udc = udc;
  1796. INIT_LIST_HEAD(&ep->queue);
  1797. if (ep->index == 0) {
  1798. ep->ep.caps.type_control = true;
  1799. } else {
  1800. ep->ep.caps.type_iso = ep->can_isoc;
  1801. ep->ep.caps.type_bulk = true;
  1802. ep->ep.caps.type_int = true;
  1803. }
  1804. ep->ep.caps.dir_in = true;
  1805. ep->ep.caps.dir_out = true;
  1806. if (fifo_mode != 0) {
  1807. /*
  1808. * Generate ept_cfg based on FIFO size and
  1809. * banks number
  1810. */
  1811. if (ep->fifo_size <= 8)
  1812. ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  1813. else
  1814. /* LSB is bit 1, not 0 */
  1815. ep->ept_cfg =
  1816. USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
  1817. ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
  1818. }
  1819. if (i)
  1820. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1821. i++;
  1822. }
  1823. if (i == 0) {
  1824. dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
  1825. ret = -EINVAL;
  1826. goto err;
  1827. }
  1828. return eps;
  1829. err:
  1830. return ERR_PTR(ret);
  1831. }
  1832. static int usba_udc_probe(struct platform_device *pdev)
  1833. {
  1834. struct resource *res;
  1835. struct clk *pclk, *hclk;
  1836. struct usba_udc *udc;
  1837. int irq, ret, i;
  1838. udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
  1839. if (!udc)
  1840. return -ENOMEM;
  1841. udc->gadget = usba_gadget_template;
  1842. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1843. res = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1844. udc->regs = devm_ioremap_resource(&pdev->dev, res);
  1845. if (IS_ERR(udc->regs))
  1846. return PTR_ERR(udc->regs);
  1847. dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n",
  1848. res, udc->regs);
  1849. res = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1850. udc->fifo = devm_ioremap_resource(&pdev->dev, res);
  1851. if (IS_ERR(udc->fifo))
  1852. return PTR_ERR(udc->fifo);
  1853. dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo);
  1854. irq = platform_get_irq(pdev, 0);
  1855. if (irq < 0)
  1856. return irq;
  1857. pclk = devm_clk_get(&pdev->dev, "pclk");
  1858. if (IS_ERR(pclk))
  1859. return PTR_ERR(pclk);
  1860. hclk = devm_clk_get(&pdev->dev, "hclk");
  1861. if (IS_ERR(hclk))
  1862. return PTR_ERR(hclk);
  1863. spin_lock_init(&udc->lock);
  1864. mutex_init(&udc->vbus_mutex);
  1865. udc->pdev = pdev;
  1866. udc->pclk = pclk;
  1867. udc->hclk = hclk;
  1868. platform_set_drvdata(pdev, udc);
  1869. /* Make sure we start from a clean slate */
  1870. ret = clk_prepare_enable(pclk);
  1871. if (ret) {
  1872. dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
  1873. return ret;
  1874. }
  1875. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1876. clk_disable_unprepare(pclk);
  1877. udc->usba_ep = atmel_udc_of_init(pdev, udc);
  1878. toggle_bias(udc, 0);
  1879. if (IS_ERR(udc->usba_ep))
  1880. return PTR_ERR(udc->usba_ep);
  1881. ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
  1882. "atmel_usba_udc", udc);
  1883. if (ret) {
  1884. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1885. irq, ret);
  1886. return ret;
  1887. }
  1888. udc->irq = irq;
  1889. if (udc->vbus_pin) {
  1890. irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN);
  1891. ret = devm_request_threaded_irq(&pdev->dev,
  1892. gpiod_to_irq(udc->vbus_pin), NULL,
  1893. usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
  1894. "atmel_usba_udc", udc);
  1895. if (ret) {
  1896. udc->vbus_pin = NULL;
  1897. dev_warn(&udc->pdev->dev,
  1898. "failed to request vbus irq; "
  1899. "assuming always on\n");
  1900. }
  1901. }
  1902. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1903. if (ret)
  1904. return ret;
  1905. device_init_wakeup(&pdev->dev, 1);
  1906. usba_init_debugfs(udc);
  1907. for (i = 1; i < udc->num_ep; i++)
  1908. usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
  1909. return 0;
  1910. }
  1911. static int usba_udc_remove(struct platform_device *pdev)
  1912. {
  1913. struct usba_udc *udc;
  1914. int i;
  1915. udc = platform_get_drvdata(pdev);
  1916. device_init_wakeup(&pdev->dev, 0);
  1917. usb_del_gadget_udc(&udc->gadget);
  1918. for (i = 1; i < udc->num_ep; i++)
  1919. usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
  1920. usba_cleanup_debugfs(udc);
  1921. return 0;
  1922. }
  1923. #ifdef CONFIG_PM_SLEEP
  1924. static int usba_udc_suspend(struct device *dev)
  1925. {
  1926. struct usba_udc *udc = dev_get_drvdata(dev);
  1927. /* Not started */
  1928. if (!udc->driver)
  1929. return 0;
  1930. mutex_lock(&udc->vbus_mutex);
  1931. if (!device_may_wakeup(dev)) {
  1932. usba_stop(udc);
  1933. goto out;
  1934. }
  1935. /*
  1936. * Device may wake up. We stay clocked if we failed
  1937. * to request vbus irq, assuming always on.
  1938. */
  1939. if (udc->vbus_pin) {
  1940. usba_stop(udc);
  1941. enable_irq_wake(gpiod_to_irq(udc->vbus_pin));
  1942. }
  1943. out:
  1944. mutex_unlock(&udc->vbus_mutex);
  1945. return 0;
  1946. }
  1947. static int usba_udc_resume(struct device *dev)
  1948. {
  1949. struct usba_udc *udc = dev_get_drvdata(dev);
  1950. /* Not started */
  1951. if (!udc->driver)
  1952. return 0;
  1953. if (device_may_wakeup(dev) && udc->vbus_pin)
  1954. disable_irq_wake(gpiod_to_irq(udc->vbus_pin));
  1955. /* If Vbus is present, enable the controller and wait for reset */
  1956. mutex_lock(&udc->vbus_mutex);
  1957. udc->vbus_prev = vbus_is_present(udc);
  1958. if (udc->vbus_prev)
  1959. usba_start(udc);
  1960. mutex_unlock(&udc->vbus_mutex);
  1961. return 0;
  1962. }
  1963. #endif
  1964. static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
  1965. static struct platform_driver udc_driver = {
  1966. .remove = usba_udc_remove,
  1967. .driver = {
  1968. .name = "atmel_usba_udc",
  1969. .pm = &usba_udc_pm_ops,
  1970. .of_match_table = atmel_udc_dt_ids,
  1971. },
  1972. };
  1973. module_platform_driver_probe(udc_driver, usba_udc_probe);
  1974. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1975. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1976. MODULE_LICENSE("GPL");
  1977. MODULE_ALIAS("platform:atmel_usba_udc");