drd.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * drd.c - DesignWare USB3 DRD Controller Dual-role support
  4. *
  5. * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Roger Quadros <rogerq@ti.com>
  8. */
  9. #include <linux/extcon.h>
  10. #include <linux/platform_device.h>
  11. #include "debug.h"
  12. #include "core.h"
  13. #include "gadget.h"
  14. static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask)
  15. {
  16. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
  17. reg &= ~(disable_mask);
  18. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  19. }
  20. static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask)
  21. {
  22. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
  23. reg |= (enable_mask);
  24. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  25. }
  26. static void dwc3_otg_clear_events(struct dwc3 *dwc)
  27. {
  28. u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT);
  29. dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
  30. }
  31. #define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \
  32. DWC3_OEVTEN_DEVRUNSTPSETEN | DWC3_OEVTEN_HIBENTRYEN | \
  33. DWC3_OEVTEN_CONIDSTSCHNGEN | DWC3_OEVTEN_HRRCONFNOTIFEN | \
  34. DWC3_OEVTEN_HRRINITNOTIFEN | DWC3_OEVTEN_ADEVIDLEEN | \
  35. DWC3_OEVTEN_ADEVBHOSTENDEN | DWC3_OEVTEN_ADEVHOSTEN | \
  36. DWC3_OEVTEN_ADEVHNPCHNGEN | DWC3_OEVTEN_ADEVSRPDETEN | \
  37. DWC3_OEVTEN_ADEVSESSENDDETEN | DWC3_OEVTEN_BDEVBHOSTENDEN | \
  38. DWC3_OEVTEN_BDEVHNPCHNGEN | DWC3_OEVTEN_BDEVSESSVLDDETEN | \
  39. DWC3_OEVTEN_BDEVVBUSCHNGEN)
  40. static irqreturn_t dwc3_otg_thread_irq(int irq, void *_dwc)
  41. {
  42. struct dwc3 *dwc = _dwc;
  43. spin_lock(&dwc->lock);
  44. if (dwc->otg_restart_host) {
  45. dwc3_otg_host_init(dwc);
  46. dwc->otg_restart_host = 0;
  47. }
  48. spin_unlock(&dwc->lock);
  49. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  50. return IRQ_HANDLED;
  51. }
  52. static irqreturn_t dwc3_otg_irq(int irq, void *_dwc)
  53. {
  54. u32 reg;
  55. struct dwc3 *dwc = _dwc;
  56. irqreturn_t ret = IRQ_NONE;
  57. reg = dwc3_readl(dwc->regs, DWC3_OEVT);
  58. if (reg) {
  59. /* ignore non OTG events, we can't disable them in OEVTEN */
  60. if (!(reg & DWC3_OTG_ALL_EVENTS)) {
  61. dwc3_writel(dwc->regs, DWC3_OEVT, reg);
  62. return IRQ_NONE;
  63. }
  64. if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST &&
  65. !(reg & DWC3_OEVT_DEVICEMODE))
  66. dwc->otg_restart_host = 1;
  67. dwc3_writel(dwc->regs, DWC3_OEVT, reg);
  68. ret = IRQ_WAKE_THREAD;
  69. }
  70. return ret;
  71. }
  72. static void dwc3_otgregs_init(struct dwc3 *dwc)
  73. {
  74. u32 reg;
  75. /*
  76. * Prevent host/device reset from resetting OTG core.
  77. * If we don't do this then xhci_reset (USBCMD.HCRST) will reset
  78. * the signal outputs sent to the PHY, the OTG FSM logic of the
  79. * core and also the resets to the VBUS filters inside the core.
  80. */
  81. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  82. reg |= DWC3_OCFG_SFTRSTMASK;
  83. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  84. /* Disable hibernation for simplicity */
  85. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  86. reg &= ~DWC3_GCTL_GBLHIBERNATIONEN;
  87. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  88. /*
  89. * Initialize OTG registers as per
  90. * Figure 11-4 OTG Driver Overall Programming Flow
  91. */
  92. /* OCFG.SRPCap = 0, OCFG.HNPCap = 0 */
  93. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  94. reg &= ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP);
  95. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  96. /* OEVT = FFFF */
  97. dwc3_otg_clear_events(dwc);
  98. /* OEVTEN = 0 */
  99. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  100. /* OEVTEN.ConIDStsChngEn = 1. Instead we enable all events */
  101. dwc3_otg_enable_events(dwc, DWC3_OTG_ALL_EVENTS);
  102. /*
  103. * OCTL.PeriMode = 1, OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0,
  104. * OCTL.HNPReq = 0
  105. */
  106. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  107. reg |= DWC3_OCTL_PERIMODE;
  108. reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN |
  109. DWC3_OCTL_HNPREQ);
  110. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  111. }
  112. static int dwc3_otg_get_irq(struct dwc3 *dwc)
  113. {
  114. struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
  115. int irq;
  116. irq = platform_get_irq_byname(dwc3_pdev, "otg");
  117. if (irq > 0)
  118. goto out;
  119. if (irq == -EPROBE_DEFER)
  120. goto out;
  121. irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
  122. if (irq > 0)
  123. goto out;
  124. if (irq == -EPROBE_DEFER)
  125. goto out;
  126. irq = platform_get_irq(dwc3_pdev, 0);
  127. if (irq > 0)
  128. goto out;
  129. if (irq != -EPROBE_DEFER)
  130. dev_err(dwc->dev, "missing OTG IRQ\n");
  131. if (!irq)
  132. irq = -EINVAL;
  133. out:
  134. return irq;
  135. }
  136. void dwc3_otg_init(struct dwc3 *dwc)
  137. {
  138. u32 reg;
  139. /*
  140. * As per Figure 11-4 OTG Driver Overall Programming Flow,
  141. * block "Initialize GCTL for OTG operation".
  142. */
  143. /* GCTL.PrtCapDir=2'b11 */
  144. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
  145. /* GUSB2PHYCFG0.SusPHY=0 */
  146. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  147. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  148. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  149. /* Initialize OTG registers */
  150. dwc3_otgregs_init(dwc);
  151. }
  152. void dwc3_otg_exit(struct dwc3 *dwc)
  153. {
  154. /* disable all OTG IRQs */
  155. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  156. /* clear all events */
  157. dwc3_otg_clear_events(dwc);
  158. }
  159. /* should be called before Host controller driver is started */
  160. void dwc3_otg_host_init(struct dwc3 *dwc)
  161. {
  162. u32 reg;
  163. /* As per Figure 11-10 A-Device Flow Diagram */
  164. /* OCFG.HNPCap = 0, OCFG.SRPCap = 0. Already 0 */
  165. /*
  166. * OCTL.PeriMode=0, OCTL.TermSelDLPulse = 0,
  167. * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
  168. */
  169. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  170. reg &= ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE |
  171. DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
  172. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  173. /*
  174. * OCFG.DisPrtPwrCutoff = 0/1
  175. */
  176. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  177. reg &= ~DWC3_OCFG_DISPWRCUTTOFF;
  178. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  179. /*
  180. * OCFG.SRPCap = 1, OCFG.HNPCap = GHWPARAMS6.HNP_CAP
  181. * We don't want SRP/HNP for simple dual-role so leave
  182. * these disabled.
  183. */
  184. /*
  185. * OEVTEN.OTGADevHostEvntEn = 1
  186. * OEVTEN.OTGADevSessEndDetEvntEn = 1
  187. * We don't want HNP/role-swap so leave these disabled.
  188. */
  189. /* GUSB2PHYCFG.ULPIAutoRes = 1/0, GUSB2PHYCFG.SusPHY = 1 */
  190. if (!dwc->dis_u2_susphy_quirk) {
  191. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  192. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  193. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  194. }
  195. /* Set Port Power to enable VBUS: OCTL.PrtPwrCtl = 1 */
  196. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  197. reg |= DWC3_OCTL_PRTPWRCTL;
  198. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  199. }
  200. /* should be called after Host controller driver is stopped */
  201. static void dwc3_otg_host_exit(struct dwc3 *dwc)
  202. {
  203. u32 reg;
  204. /*
  205. * Exit from A-device flow as per
  206. * Figure 11-4 OTG Driver Overall Programming Flow
  207. */
  208. /*
  209. * OEVTEN.OTGADevBHostEndEvntEn=0, OEVTEN.OTGADevHNPChngEvntEn=0
  210. * OEVTEN.OTGADevSessEndDetEvntEn=0,
  211. * OEVTEN.OTGADevHostEvntEn = 0
  212. * But we don't disable any OTG events
  213. */
  214. /* OCTL.HstSetHNPEn = 0, OCTL.PrtPwrCtl=0 */
  215. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  216. reg &= ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL);
  217. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  218. }
  219. /* should be called before the gadget controller driver is started */
  220. static void dwc3_otg_device_init(struct dwc3 *dwc)
  221. {
  222. u32 reg;
  223. /* As per Figure 11-20 B-Device Flow Diagram */
  224. /*
  225. * OCFG.HNPCap = GHWPARAMS6.HNP_CAP, OCFG.SRPCap = 1
  226. * but we keep them 0 for simple dual-role operation.
  227. */
  228. reg = dwc3_readl(dwc->regs, DWC3_OCFG);
  229. /* OCFG.OTGSftRstMsk = 0/1 */
  230. reg |= DWC3_OCFG_SFTRSTMASK;
  231. dwc3_writel(dwc->regs, DWC3_OCFG, reg);
  232. /*
  233. * OCTL.PeriMode = 1
  234. * OCTL.TermSelDLPulse = 0/1, OCTL.HNPReq = 0
  235. * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
  236. */
  237. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  238. reg |= DWC3_OCTL_PERIMODE;
  239. reg &= ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ |
  240. DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
  241. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  242. /* OEVTEN.OTGBDevSesVldDetEvntEn = 1 */
  243. dwc3_otg_enable_events(dwc, DWC3_OEVTEN_BDEVSESSVLDDETEN);
  244. /* GUSB2PHYCFG.ULPIAutoRes = 0, GUSB2PHYCFG0.SusPHY = 1 */
  245. if (!dwc->dis_u2_susphy_quirk) {
  246. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  247. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  248. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  249. }
  250. /* GCTL.GblHibernationEn = 0. Already 0. */
  251. }
  252. /* should be called after the gadget controller driver is stopped */
  253. static void dwc3_otg_device_exit(struct dwc3 *dwc)
  254. {
  255. u32 reg;
  256. /*
  257. * Exit from B-device flow as per
  258. * Figure 11-4 OTG Driver Overall Programming Flow
  259. */
  260. /*
  261. * OEVTEN.OTGBDevHNPChngEvntEn = 0
  262. * OEVTEN.OTGBDevVBusChngEvntEn = 0
  263. * OEVTEN.OTGBDevBHostEndEvntEn = 0
  264. */
  265. dwc3_otg_disable_events(dwc, DWC3_OEVTEN_BDEVHNPCHNGEN |
  266. DWC3_OEVTEN_BDEVVBUSCHNGEN |
  267. DWC3_OEVTEN_BDEVBHOSTENDEN);
  268. /* OCTL.DevSetHNPEn = 0, OCTL.HNPReq = 0, OCTL.PeriMode=1 */
  269. reg = dwc3_readl(dwc->regs, DWC3_OCTL);
  270. reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ);
  271. reg |= DWC3_OCTL_PERIMODE;
  272. dwc3_writel(dwc->regs, DWC3_OCTL, reg);
  273. }
  274. void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
  275. {
  276. int ret;
  277. u32 reg;
  278. int id;
  279. unsigned long flags;
  280. if (dwc->dr_mode != USB_DR_MODE_OTG)
  281. return;
  282. /* don't do anything if debug user changed role to not OTG */
  283. if (dwc->current_dr_role != DWC3_GCTL_PRTCAP_OTG)
  284. return;
  285. if (!ignore_idstatus) {
  286. reg = dwc3_readl(dwc->regs, DWC3_OSTS);
  287. id = !!(reg & DWC3_OSTS_CONIDSTS);
  288. dwc->desired_otg_role = id ? DWC3_OTG_ROLE_DEVICE :
  289. DWC3_OTG_ROLE_HOST;
  290. }
  291. if (dwc->desired_otg_role == dwc->current_otg_role)
  292. return;
  293. switch (dwc->current_otg_role) {
  294. case DWC3_OTG_ROLE_HOST:
  295. dwc3_host_exit(dwc);
  296. spin_lock_irqsave(&dwc->lock, flags);
  297. dwc3_otg_host_exit(dwc);
  298. spin_unlock_irqrestore(&dwc->lock, flags);
  299. break;
  300. case DWC3_OTG_ROLE_DEVICE:
  301. dwc3_gadget_exit(dwc);
  302. spin_lock_irqsave(&dwc->lock, flags);
  303. dwc3_event_buffers_cleanup(dwc);
  304. dwc3_otg_device_exit(dwc);
  305. spin_unlock_irqrestore(&dwc->lock, flags);
  306. break;
  307. default:
  308. break;
  309. }
  310. spin_lock_irqsave(&dwc->lock, flags);
  311. dwc->current_otg_role = dwc->desired_otg_role;
  312. spin_unlock_irqrestore(&dwc->lock, flags);
  313. switch (dwc->desired_otg_role) {
  314. case DWC3_OTG_ROLE_HOST:
  315. spin_lock_irqsave(&dwc->lock, flags);
  316. dwc3_otgregs_init(dwc);
  317. dwc3_otg_host_init(dwc);
  318. spin_unlock_irqrestore(&dwc->lock, flags);
  319. ret = dwc3_host_init(dwc);
  320. if (ret) {
  321. dev_err(dwc->dev, "failed to initialize host\n");
  322. } else {
  323. if (dwc->usb2_phy)
  324. otg_set_vbus(dwc->usb2_phy->otg, true);
  325. if (dwc->usb2_generic_phy)
  326. phy_set_mode(dwc->usb2_generic_phy,
  327. PHY_MODE_USB_HOST);
  328. }
  329. break;
  330. case DWC3_OTG_ROLE_DEVICE:
  331. spin_lock_irqsave(&dwc->lock, flags);
  332. dwc3_otgregs_init(dwc);
  333. dwc3_otg_device_init(dwc);
  334. dwc3_event_buffers_setup(dwc);
  335. spin_unlock_irqrestore(&dwc->lock, flags);
  336. if (dwc->usb2_phy)
  337. otg_set_vbus(dwc->usb2_phy->otg, false);
  338. if (dwc->usb2_generic_phy)
  339. phy_set_mode(dwc->usb2_generic_phy,
  340. PHY_MODE_USB_DEVICE);
  341. ret = dwc3_gadget_init(dwc);
  342. if (ret)
  343. dev_err(dwc->dev, "failed to initialize peripheral\n");
  344. break;
  345. default:
  346. break;
  347. }
  348. }
  349. static void dwc3_drd_update(struct dwc3 *dwc)
  350. {
  351. int id;
  352. if (dwc->edev) {
  353. id = extcon_get_state(dwc->edev, EXTCON_USB_HOST);
  354. if (id < 0)
  355. id = 0;
  356. dwc3_set_mode(dwc, id ?
  357. DWC3_GCTL_PRTCAP_HOST :
  358. DWC3_GCTL_PRTCAP_DEVICE);
  359. }
  360. }
  361. static int dwc3_drd_notifier(struct notifier_block *nb,
  362. unsigned long event, void *ptr)
  363. {
  364. struct dwc3 *dwc = container_of(nb, struct dwc3, edev_nb);
  365. dwc3_set_mode(dwc, event ?
  366. DWC3_GCTL_PRTCAP_HOST :
  367. DWC3_GCTL_PRTCAP_DEVICE);
  368. return NOTIFY_DONE;
  369. }
  370. int dwc3_drd_init(struct dwc3 *dwc)
  371. {
  372. int ret, irq;
  373. if (dwc->dev->of_node &&
  374. of_property_read_bool(dwc->dev->of_node, "extcon")) {
  375. dwc->edev = extcon_get_edev_by_phandle(dwc->dev, 0);
  376. if (IS_ERR(dwc->edev))
  377. return PTR_ERR(dwc->edev);
  378. dwc->edev_nb.notifier_call = dwc3_drd_notifier;
  379. ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST,
  380. &dwc->edev_nb);
  381. if (ret < 0) {
  382. dev_err(dwc->dev, "couldn't register cable notifier\n");
  383. return ret;
  384. }
  385. dwc3_drd_update(dwc);
  386. } else {
  387. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
  388. dwc->current_dr_role = DWC3_GCTL_PRTCAP_OTG;
  389. /* use OTG block to get ID event */
  390. irq = dwc3_otg_get_irq(dwc);
  391. if (irq < 0)
  392. return irq;
  393. dwc->otg_irq = irq;
  394. /* disable all OTG IRQs */
  395. dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS);
  396. /* clear all events */
  397. dwc3_otg_clear_events(dwc);
  398. ret = request_threaded_irq(dwc->otg_irq, dwc3_otg_irq,
  399. dwc3_otg_thread_irq,
  400. IRQF_SHARED, "dwc3-otg", dwc);
  401. if (ret) {
  402. dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
  403. dwc->otg_irq, ret);
  404. ret = -ENODEV;
  405. return ret;
  406. }
  407. dwc3_otg_init(dwc);
  408. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  409. }
  410. return 0;
  411. }
  412. void dwc3_drd_exit(struct dwc3 *dwc)
  413. {
  414. unsigned long flags;
  415. if (dwc->edev)
  416. extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST,
  417. &dwc->edev_nb);
  418. cancel_work_sync(&dwc->drd_work);
  419. /* debug user might have changed role, clean based on current role */
  420. switch (dwc->current_dr_role) {
  421. case DWC3_GCTL_PRTCAP_HOST:
  422. dwc3_host_exit(dwc);
  423. break;
  424. case DWC3_GCTL_PRTCAP_DEVICE:
  425. dwc3_gadget_exit(dwc);
  426. dwc3_event_buffers_cleanup(dwc);
  427. break;
  428. case DWC3_GCTL_PRTCAP_OTG:
  429. dwc3_otg_exit(dwc);
  430. spin_lock_irqsave(&dwc->lock, flags);
  431. dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
  432. spin_unlock_irqrestore(&dwc->lock, flags);
  433. dwc3_otg_update(dwc, 1);
  434. break;
  435. default:
  436. break;
  437. }
  438. if (!dwc->edev)
  439. free_irq(dwc->otg_irq, dwc);
  440. }