pinctrl-ocelot.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs pinctrl driver
  4. *
  5. * Author: <alexandre.belloni@free-electrons.com>
  6. * License: Dual MIT/GPL
  7. * Copyright (c) 2017 Microsemi Corporation
  8. */
  9. #include <linux/gpio/driver.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/pinctrl/pinctrl.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include "core.h"
  22. #include "pinconf.h"
  23. #include "pinmux.h"
  24. #define OCELOT_GPIO_OUT_SET 0x0
  25. #define OCELOT_GPIO_OUT_CLR 0x4
  26. #define OCELOT_GPIO_OUT 0x8
  27. #define OCELOT_GPIO_IN 0xc
  28. #define OCELOT_GPIO_OE 0x10
  29. #define OCELOT_GPIO_INTR 0x14
  30. #define OCELOT_GPIO_INTR_ENA 0x18
  31. #define OCELOT_GPIO_INTR_IDENT 0x1c
  32. #define OCELOT_GPIO_ALT0 0x20
  33. #define OCELOT_GPIO_ALT1 0x24
  34. #define OCELOT_GPIO_SD_MAP 0x28
  35. #define OCELOT_PINS 22
  36. #define OCELOT_FUNC_PER_PIN 4
  37. enum {
  38. FUNC_NONE,
  39. FUNC_GPIO,
  40. FUNC_IRQ0_IN,
  41. FUNC_IRQ0_OUT,
  42. FUNC_IRQ1_IN,
  43. FUNC_IRQ1_OUT,
  44. FUNC_MIIM1,
  45. FUNC_PCI_WAKE,
  46. FUNC_PTP0,
  47. FUNC_PTP1,
  48. FUNC_PTP2,
  49. FUNC_PTP3,
  50. FUNC_PWM,
  51. FUNC_RECO_CLK0,
  52. FUNC_RECO_CLK1,
  53. FUNC_SFP0,
  54. FUNC_SFP1,
  55. FUNC_SFP2,
  56. FUNC_SFP3,
  57. FUNC_SFP4,
  58. FUNC_SFP5,
  59. FUNC_SG0,
  60. FUNC_SI,
  61. FUNC_TACHO,
  62. FUNC_TWI,
  63. FUNC_TWI_SCL_M,
  64. FUNC_UART,
  65. FUNC_UART2,
  66. FUNC_MAX
  67. };
  68. static const char *const ocelot_function_names[] = {
  69. [FUNC_NONE] = "none",
  70. [FUNC_GPIO] = "gpio",
  71. [FUNC_IRQ0_IN] = "irq0_in",
  72. [FUNC_IRQ0_OUT] = "irq0_out",
  73. [FUNC_IRQ1_IN] = "irq1_in",
  74. [FUNC_IRQ1_OUT] = "irq1_out",
  75. [FUNC_MIIM1] = "miim1",
  76. [FUNC_PCI_WAKE] = "pci_wake",
  77. [FUNC_PTP0] = "ptp0",
  78. [FUNC_PTP1] = "ptp1",
  79. [FUNC_PTP2] = "ptp2",
  80. [FUNC_PTP3] = "ptp3",
  81. [FUNC_PWM] = "pwm",
  82. [FUNC_RECO_CLK0] = "reco_clk0",
  83. [FUNC_RECO_CLK1] = "reco_clk1",
  84. [FUNC_SFP0] = "sfp0",
  85. [FUNC_SFP1] = "sfp1",
  86. [FUNC_SFP2] = "sfp2",
  87. [FUNC_SFP3] = "sfp3",
  88. [FUNC_SFP4] = "sfp4",
  89. [FUNC_SFP5] = "sfp5",
  90. [FUNC_SG0] = "sg0",
  91. [FUNC_SI] = "si",
  92. [FUNC_TACHO] = "tacho",
  93. [FUNC_TWI] = "twi",
  94. [FUNC_TWI_SCL_M] = "twi_scl_m",
  95. [FUNC_UART] = "uart",
  96. [FUNC_UART2] = "uart2",
  97. };
  98. struct ocelot_pmx_func {
  99. const char **groups;
  100. unsigned int ngroups;
  101. };
  102. struct ocelot_pin_caps {
  103. unsigned int pin;
  104. unsigned char functions[OCELOT_FUNC_PER_PIN];
  105. };
  106. struct ocelot_pinctrl {
  107. struct device *dev;
  108. struct pinctrl_dev *pctl;
  109. struct gpio_chip gpio_chip;
  110. struct regmap *map;
  111. struct ocelot_pmx_func func[FUNC_MAX];
  112. };
  113. #define OCELOT_P(p, f0, f1, f2) \
  114. static struct ocelot_pin_caps ocelot_pin_##p = { \
  115. .pin = p, \
  116. .functions = { \
  117. FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
  118. }, \
  119. }
  120. OCELOT_P(0, SG0, NONE, NONE);
  121. OCELOT_P(1, SG0, NONE, NONE);
  122. OCELOT_P(2, SG0, NONE, NONE);
  123. OCELOT_P(3, SG0, NONE, NONE);
  124. OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI);
  125. OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
  126. OCELOT_P(6, UART, TWI_SCL_M, NONE);
  127. OCELOT_P(7, UART, TWI_SCL_M, NONE);
  128. OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
  129. OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
  130. OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
  131. OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
  132. OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
  133. OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
  134. OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
  135. OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
  136. OCELOT_P(16, TWI, NONE, SI);
  137. OCELOT_P(17, TWI, TWI_SCL_M, SI);
  138. OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
  139. OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
  140. OCELOT_P(20, RECO_CLK0, TACHO, NONE);
  141. OCELOT_P(21, RECO_CLK1, PWM, NONE);
  142. #define OCELOT_PIN(n) { \
  143. .number = n, \
  144. .name = "GPIO_"#n, \
  145. .drv_data = &ocelot_pin_##n \
  146. }
  147. static const struct pinctrl_pin_desc ocelot_pins[] = {
  148. OCELOT_PIN(0),
  149. OCELOT_PIN(1),
  150. OCELOT_PIN(2),
  151. OCELOT_PIN(3),
  152. OCELOT_PIN(4),
  153. OCELOT_PIN(5),
  154. OCELOT_PIN(6),
  155. OCELOT_PIN(7),
  156. OCELOT_PIN(8),
  157. OCELOT_PIN(9),
  158. OCELOT_PIN(10),
  159. OCELOT_PIN(11),
  160. OCELOT_PIN(12),
  161. OCELOT_PIN(13),
  162. OCELOT_PIN(14),
  163. OCELOT_PIN(15),
  164. OCELOT_PIN(16),
  165. OCELOT_PIN(17),
  166. OCELOT_PIN(18),
  167. OCELOT_PIN(19),
  168. OCELOT_PIN(20),
  169. OCELOT_PIN(21),
  170. };
  171. static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
  172. {
  173. return ARRAY_SIZE(ocelot_function_names);
  174. }
  175. static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
  176. unsigned int function)
  177. {
  178. return ocelot_function_names[function];
  179. }
  180. static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
  181. unsigned int function,
  182. const char *const **groups,
  183. unsigned *const num_groups)
  184. {
  185. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  186. *groups = info->func[function].groups;
  187. *num_groups = info->func[function].ngroups;
  188. return 0;
  189. }
  190. static int ocelot_pin_function_idx(unsigned int pin, unsigned int function)
  191. {
  192. struct ocelot_pin_caps *p = ocelot_pins[pin].drv_data;
  193. int i;
  194. for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
  195. if (function == p->functions[i])
  196. return i;
  197. }
  198. return -1;
  199. }
  200. static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
  201. unsigned int selector, unsigned int group)
  202. {
  203. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  204. struct ocelot_pin_caps *pin = ocelot_pins[group].drv_data;
  205. int f;
  206. f = ocelot_pin_function_idx(group, selector);
  207. if (f < 0)
  208. return -EINVAL;
  209. /*
  210. * f is encoded on two bits.
  211. * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of
  212. * ALT1
  213. * This is racy because both registers can't be updated at the same time
  214. * but it doesn't matter much for now.
  215. */
  216. regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(pin->pin),
  217. f << pin->pin);
  218. regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(pin->pin),
  219. f << (pin->pin - 1));
  220. return 0;
  221. }
  222. static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
  223. struct pinctrl_gpio_range *range,
  224. unsigned int pin, bool input)
  225. {
  226. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  227. regmap_update_bits(info->map, OCELOT_GPIO_OE, BIT(pin),
  228. input ? 0 : BIT(pin));
  229. return 0;
  230. }
  231. static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
  232. struct pinctrl_gpio_range *range,
  233. unsigned int offset)
  234. {
  235. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  236. regmap_update_bits(info->map, OCELOT_GPIO_ALT0, BIT(offset), 0);
  237. regmap_update_bits(info->map, OCELOT_GPIO_ALT1, BIT(offset), 0);
  238. return 0;
  239. }
  240. static const struct pinmux_ops ocelot_pmx_ops = {
  241. .get_functions_count = ocelot_get_functions_count,
  242. .get_function_name = ocelot_get_function_name,
  243. .get_function_groups = ocelot_get_function_groups,
  244. .set_mux = ocelot_pinmux_set_mux,
  245. .gpio_set_direction = ocelot_gpio_set_direction,
  246. .gpio_request_enable = ocelot_gpio_request_enable,
  247. };
  248. static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  249. {
  250. return ARRAY_SIZE(ocelot_pins);
  251. }
  252. static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
  253. unsigned int group)
  254. {
  255. return ocelot_pins[group].name;
  256. }
  257. static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  258. unsigned int group,
  259. const unsigned int **pins,
  260. unsigned int *num_pins)
  261. {
  262. *pins = &ocelot_pins[group].number;
  263. *num_pins = 1;
  264. return 0;
  265. }
  266. static const struct pinctrl_ops ocelot_pctl_ops = {
  267. .get_groups_count = ocelot_pctl_get_groups_count,
  268. .get_group_name = ocelot_pctl_get_group_name,
  269. .get_group_pins = ocelot_pctl_get_group_pins,
  270. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  271. .dt_free_map = pinconf_generic_dt_free_map,
  272. };
  273. static struct pinctrl_desc ocelot_desc = {
  274. .name = "ocelot-pinctrl",
  275. .pins = ocelot_pins,
  276. .npins = ARRAY_SIZE(ocelot_pins),
  277. .pctlops = &ocelot_pctl_ops,
  278. .pmxops = &ocelot_pmx_ops,
  279. .owner = THIS_MODULE,
  280. };
  281. static int ocelot_create_group_func_map(struct device *dev,
  282. struct ocelot_pinctrl *info)
  283. {
  284. u16 pins[ARRAY_SIZE(ocelot_pins)];
  285. int f, npins, i;
  286. for (f = 0; f < FUNC_MAX; f++) {
  287. for (npins = 0, i = 0; i < ARRAY_SIZE(ocelot_pins); i++) {
  288. if (ocelot_pin_function_idx(i, f) >= 0)
  289. pins[npins++] = i;
  290. }
  291. info->func[f].ngroups = npins;
  292. info->func[f].groups = devm_kzalloc(dev, npins *
  293. sizeof(char *),
  294. GFP_KERNEL);
  295. if (!info->func[f].groups)
  296. return -ENOMEM;
  297. for (i = 0; i < npins; i++)
  298. info->func[f].groups[i] = ocelot_pins[pins[i]].name;
  299. }
  300. return 0;
  301. }
  302. static int ocelot_pinctrl_register(struct platform_device *pdev,
  303. struct ocelot_pinctrl *info)
  304. {
  305. int ret;
  306. ret = ocelot_create_group_func_map(&pdev->dev, info);
  307. if (ret) {
  308. dev_err(&pdev->dev, "Unable to create group func map.\n");
  309. return ret;
  310. }
  311. info->pctl = devm_pinctrl_register(&pdev->dev, &ocelot_desc, info);
  312. if (IS_ERR(info->pctl)) {
  313. dev_err(&pdev->dev, "Failed to register pinctrl\n");
  314. return PTR_ERR(info->pctl);
  315. }
  316. return 0;
  317. }
  318. static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
  319. {
  320. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  321. unsigned int val;
  322. regmap_read(info->map, OCELOT_GPIO_IN, &val);
  323. return !!(val & BIT(offset));
  324. }
  325. static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
  326. int value)
  327. {
  328. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  329. if (value)
  330. regmap_write(info->map, OCELOT_GPIO_OUT_SET, BIT(offset));
  331. else
  332. regmap_write(info->map, OCELOT_GPIO_OUT_CLR, BIT(offset));
  333. }
  334. static int ocelot_gpio_get_direction(struct gpio_chip *chip,
  335. unsigned int offset)
  336. {
  337. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  338. unsigned int val;
  339. regmap_read(info->map, OCELOT_GPIO_OE, &val);
  340. return !(val & BIT(offset));
  341. }
  342. static int ocelot_gpio_direction_input(struct gpio_chip *chip,
  343. unsigned int offset)
  344. {
  345. return pinctrl_gpio_direction_input(chip->base + offset);
  346. }
  347. static int ocelot_gpio_direction_output(struct gpio_chip *chip,
  348. unsigned int offset, int value)
  349. {
  350. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  351. unsigned int pin = BIT(offset);
  352. if (value)
  353. regmap_write(info->map, OCELOT_GPIO_OUT_SET, pin);
  354. else
  355. regmap_write(info->map, OCELOT_GPIO_OUT_CLR, pin);
  356. return pinctrl_gpio_direction_output(chip->base + offset);
  357. }
  358. static const struct gpio_chip ocelot_gpiolib_chip = {
  359. .request = gpiochip_generic_request,
  360. .free = gpiochip_generic_free,
  361. .set = ocelot_gpio_set,
  362. .get = ocelot_gpio_get,
  363. .get_direction = ocelot_gpio_get_direction,
  364. .direction_input = ocelot_gpio_direction_input,
  365. .direction_output = ocelot_gpio_direction_output,
  366. .owner = THIS_MODULE,
  367. };
  368. static int ocelot_gpiochip_register(struct platform_device *pdev,
  369. struct ocelot_pinctrl *info)
  370. {
  371. struct gpio_chip *gc;
  372. int ret;
  373. info->gpio_chip = ocelot_gpiolib_chip;
  374. gc = &info->gpio_chip;
  375. gc->ngpio = OCELOT_PINS;
  376. gc->parent = &pdev->dev;
  377. gc->base = 0;
  378. gc->of_node = info->dev->of_node;
  379. gc->label = "ocelot-gpio";
  380. ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
  381. if (ret)
  382. return ret;
  383. /* TODO: this can be used as an irqchip but no board is using that */
  384. return 0;
  385. }
  386. static const struct regmap_config ocelot_pinctrl_regmap_config = {
  387. .reg_bits = 32,
  388. .val_bits = 32,
  389. .reg_stride = 4,
  390. .max_register = 0x64,
  391. };
  392. static const struct of_device_id ocelot_pinctrl_of_match[] = {
  393. { .compatible = "mscc,ocelot-pinctrl" },
  394. {},
  395. };
  396. static int ocelot_pinctrl_probe(struct platform_device *pdev)
  397. {
  398. struct device *dev = &pdev->dev;
  399. struct ocelot_pinctrl *info;
  400. void __iomem *base;
  401. int ret;
  402. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  403. if (!info)
  404. return -ENOMEM;
  405. base = devm_ioremap_resource(dev,
  406. platform_get_resource(pdev, IORESOURCE_MEM, 0));
  407. if (IS_ERR(base)) {
  408. dev_err(dev, "Failed to ioremap registers\n");
  409. return PTR_ERR(base);
  410. }
  411. info->map = devm_regmap_init_mmio(dev, base,
  412. &ocelot_pinctrl_regmap_config);
  413. if (IS_ERR(info->map)) {
  414. dev_err(dev, "Failed to create regmap\n");
  415. return PTR_ERR(info->map);
  416. }
  417. dev_set_drvdata(dev, info->map);
  418. info->dev = dev;
  419. ret = ocelot_pinctrl_register(pdev, info);
  420. if (ret)
  421. return ret;
  422. ret = ocelot_gpiochip_register(pdev, info);
  423. if (ret)
  424. return ret;
  425. return 0;
  426. }
  427. static struct platform_driver ocelot_pinctrl_driver = {
  428. .driver = {
  429. .name = "pinctrl-ocelot",
  430. .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
  431. .suppress_bind_attrs = true,
  432. },
  433. .probe = ocelot_pinctrl_probe,
  434. };
  435. builtin_platform_driver(ocelot_pinctrl_driver);