Kconfig 3.0 KB

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  1. #
  2. # Intel pin control drivers
  3. #
  4. if (X86 || COMPILE_TEST)
  5. config PINCTRL_BAYTRAIL
  6. bool "Intel Baytrail GPIO pin control"
  7. depends on ACPI
  8. select GPIOLIB
  9. select GPIOLIB_IRQCHIP
  10. select PINMUX
  11. select PINCONF
  12. select GENERIC_PINCONF
  13. help
  14. driver for memory mapped GPIO functionality on Intel Baytrail
  15. platforms. Supports 3 banks with 102, 28 and 44 gpios.
  16. Most pins are usually muxed to some other functionality by firmware,
  17. so only a small amount is available for gpio use.
  18. Requires ACPI device enumeration code to set up a platform device.
  19. config PINCTRL_CHERRYVIEW
  20. tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
  21. depends on ACPI
  22. select PINMUX
  23. select PINCONF
  24. select GENERIC_PINCONF
  25. select GPIOLIB
  26. select GPIOLIB_IRQCHIP
  27. help
  28. Cherryview/Braswell pinctrl driver provides an interface that
  29. allows configuring of SoC pins and using them as GPIOs.
  30. config PINCTRL_MERRIFIELD
  31. tristate "Intel Merrifield pinctrl driver"
  32. depends on X86_INTEL_MID
  33. select PINMUX
  34. select PINCONF
  35. select GENERIC_PINCONF
  36. help
  37. Merrifield Family-Level Interface Shim (FLIS) driver provides an
  38. interface that allows configuring of SoC pins and using them as
  39. GPIOs.
  40. config PINCTRL_INTEL
  41. tristate
  42. select PINMUX
  43. select PINCONF
  44. select GENERIC_PINCONF
  45. select GPIOLIB
  46. select GPIOLIB_IRQCHIP
  47. config PINCTRL_BROXTON
  48. tristate "Intel Broxton pinctrl and GPIO driver"
  49. depends on ACPI
  50. select PINCTRL_INTEL
  51. help
  52. Broxton pinctrl driver provides an interface that allows
  53. configuring of SoC pins and using them as GPIOs.
  54. config PINCTRL_CANNONLAKE
  55. tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
  56. depends on ACPI
  57. select PINCTRL_INTEL
  58. help
  59. This pinctrl driver provides an interface that allows configuring
  60. of Intel Cannon Lake PCH pins and using them as GPIOs.
  61. config PINCTRL_CEDARFORK
  62. tristate "Intel Cedar Fork pinctrl and GPIO driver"
  63. depends on ACPI
  64. select PINCTRL_INTEL
  65. help
  66. This pinctrl driver provides an interface that allows configuring
  67. of Intel Cedar Fork PCH pins and using them as GPIOs.
  68. config PINCTRL_DENVERTON
  69. tristate "Intel Denverton pinctrl and GPIO driver"
  70. depends on ACPI
  71. select PINCTRL_INTEL
  72. help
  73. This pinctrl driver provides an interface that allows configuring
  74. of Intel Denverton SoC pins and using them as GPIOs.
  75. config PINCTRL_GEMINILAKE
  76. tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
  77. depends on ACPI
  78. select PINCTRL_INTEL
  79. help
  80. This pinctrl driver provides an interface that allows configuring
  81. of Intel Gemini Lake SoC pins and using them as GPIOs.
  82. config PINCTRL_LEWISBURG
  83. tristate "Intel Lewisburg pinctrl and GPIO driver"
  84. depends on ACPI
  85. select PINCTRL_INTEL
  86. help
  87. This pinctrl driver provides an interface that allows configuring
  88. of Intel Lewisburg pins and using them as GPIOs.
  89. config PINCTRL_SUNRISEPOINT
  90. tristate "Intel Sunrisepoint pinctrl and GPIO driver"
  91. depends on ACPI
  92. select PINCTRL_INTEL
  93. help
  94. Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
  95. provides an interface that allows configuring of PCH pins and
  96. using them as GPIOs.
  97. endif