phy-mtk-tphy.c 33 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #include <dt-bindings/phy/phy.h>
  16. #include <linux/clk.h>
  17. #include <linux/delay.h>
  18. #include <linux/io.h>
  19. #include <linux/iopoll.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_device.h>
  23. #include <linux/phy/phy.h>
  24. #include <linux/platform_device.h>
  25. /* version V1 sub-banks offset base address */
  26. /* banks shared by multiple phys */
  27. #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
  28. #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
  29. #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
  30. /* u2 phy bank */
  31. #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
  32. /* u3/pcie/sata phy banks */
  33. #define SSUSB_SIFSLV_V1_U3PHYD 0x000
  34. #define SSUSB_SIFSLV_V1_U3PHYA 0x200
  35. /* version V2 sub-banks offset base address */
  36. /* u2 phy banks */
  37. #define SSUSB_SIFSLV_V2_MISC 0x000
  38. #define SSUSB_SIFSLV_V2_U2FREQ 0x100
  39. #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
  40. /* u3/pcie/sata phy banks */
  41. #define SSUSB_SIFSLV_V2_SPLLC 0x000
  42. #define SSUSB_SIFSLV_V2_CHIP 0x100
  43. #define SSUSB_SIFSLV_V2_U3PHYD 0x200
  44. #define SSUSB_SIFSLV_V2_U3PHYA 0x400
  45. #define U3P_USBPHYACR0 0x000
  46. #define PA0_RG_U2PLL_FORCE_ON BIT(15)
  47. #define PA0_RG_USB20_INTR_EN BIT(5)
  48. #define U3P_USBPHYACR2 0x008
  49. #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
  50. #define U3P_USBPHYACR5 0x014
  51. #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  52. #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
  53. #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
  54. #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  55. #define U3P_USBPHYACR6 0x018
  56. #define PA6_RG_U2_BC11_SW_EN BIT(23)
  57. #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
  58. #define PA6_RG_U2_SQTH GENMASK(3, 0)
  59. #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
  60. #define U3P_U2PHYACR4 0x020
  61. #define P2C_RG_USB20_GPIO_CTL BIT(9)
  62. #define P2C_USB20_GPIO_MODE BIT(8)
  63. #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  64. #define U3D_U2PHYDCR0 0x060
  65. #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
  66. #define U3P_U2PHYDTM0 0x068
  67. #define P2C_FORCE_UART_EN BIT(26)
  68. #define P2C_FORCE_DATAIN BIT(23)
  69. #define P2C_FORCE_DM_PULLDOWN BIT(21)
  70. #define P2C_FORCE_DP_PULLDOWN BIT(20)
  71. #define P2C_FORCE_XCVRSEL BIT(19)
  72. #define P2C_FORCE_SUSPENDM BIT(18)
  73. #define P2C_FORCE_TERMSEL BIT(17)
  74. #define P2C_RG_DATAIN GENMASK(13, 10)
  75. #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
  76. #define P2C_RG_DMPULLDOWN BIT(7)
  77. #define P2C_RG_DPPULLDOWN BIT(6)
  78. #define P2C_RG_XCVRSEL GENMASK(5, 4)
  79. #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
  80. #define P2C_RG_SUSPENDM BIT(3)
  81. #define P2C_RG_TERMSEL BIT(2)
  82. #define P2C_DTM0_PART_MASK \
  83. (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  84. P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  85. P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  86. P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  87. #define U3P_U2PHYDTM1 0x06C
  88. #define P2C_RG_UART_EN BIT(16)
  89. #define P2C_FORCE_IDDIG BIT(9)
  90. #define P2C_RG_VBUSVALID BIT(5)
  91. #define P2C_RG_SESSEND BIT(4)
  92. #define P2C_RG_AVALID BIT(2)
  93. #define P2C_RG_IDDIG BIT(1)
  94. #define U3P_U3_CHIP_GPIO_CTLD 0x0c
  95. #define P3C_REG_IP_SW_RST BIT(31)
  96. #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
  97. #define P3C_FORCE_IP_SW_RST BIT(29)
  98. #define U3P_U3_CHIP_GPIO_CTLE 0x10
  99. #define P3C_RG_SWRST_U3_PHYD BIT(25)
  100. #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
  101. #define U3P_U3_PHYA_REG0 0x000
  102. #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
  103. #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
  104. #define U3P_U3_PHYA_REG1 0x004
  105. #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
  106. #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
  107. #define U3P_U3_PHYA_REG6 0x018
  108. #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
  109. #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
  110. #define U3P_U3_PHYA_REG9 0x024
  111. #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
  112. #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
  113. #define U3P_U3_PHYA_DA_REG0 0x100
  114. #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
  115. #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
  116. #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
  117. #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
  118. #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
  119. #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
  120. #define U3P_U3_PHYA_DA_REG4 0x108
  121. #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
  122. #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
  123. #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
  124. #define U3P_U3_PHYA_DA_REG5 0x10c
  125. #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
  126. #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
  127. #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
  128. #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
  129. #define U3P_U3_PHYA_DA_REG6 0x110
  130. #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
  131. #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
  132. #define U3P_U3_PHYA_DA_REG7 0x114
  133. #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
  134. #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
  135. #define U3P_U3_PHYA_DA_REG20 0x13c
  136. #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
  137. #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
  138. #define U3P_U3_PHYA_DA_REG25 0x148
  139. #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
  140. #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
  141. #define U3P_U3_PHYD_LFPS1 0x00c
  142. #define P3D_RG_FWAKE_TH GENMASK(21, 16)
  143. #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
  144. #define U3P_U3_PHYD_CDR1 0x05c
  145. #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
  146. #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
  147. #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
  148. #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
  149. #define U3P_U3_PHYD_RXDET1 0x128
  150. #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
  151. #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
  152. #define U3P_U3_PHYD_RXDET2 0x12c
  153. #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
  154. #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  155. #define U3P_SPLLC_XTALCTL3 0x018
  156. #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
  157. #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
  158. #define U3P_U2FREQ_FMCR0 0x00
  159. #define P2F_RG_MONCLK_SEL GENMASK(27, 26)
  160. #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
  161. #define P2F_RG_FREQDET_EN BIT(24)
  162. #define P2F_RG_CYCLECNT GENMASK(23, 0)
  163. #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
  164. #define U3P_U2FREQ_VALUE 0x0c
  165. #define U3P_U2FREQ_FMMONR1 0x10
  166. #define P2F_USB_FM_VALID BIT(0)
  167. #define P2F_RG_FRCK_EN BIT(8)
  168. #define U3P_REF_CLK 26 /* MHZ */
  169. #define U3P_SLEW_RATE_COEF 28
  170. #define U3P_SR_COEF_DIVISOR 1000
  171. #define U3P_FM_DET_CYCLE_CNT 1024
  172. /* SATA register setting */
  173. #define PHYD_CTRL_SIGNAL_MODE4 0x1c
  174. /* CDR Charge Pump P-path current adjustment */
  175. #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
  176. #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
  177. #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
  178. #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
  179. #define PHYD_DESIGN_OPTION2 0x24
  180. /* Symbol lock count selection */
  181. #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
  182. #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
  183. #define PHYD_DESIGN_OPTION9 0x40
  184. /* COMWAK GAP width window */
  185. #define RG_TG_MAX_MSK GENMASK(20, 16)
  186. #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
  187. /* COMINIT GAP width window */
  188. #define RG_T2_MAX_MSK GENMASK(13, 8)
  189. #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
  190. /* COMWAK GAP width window */
  191. #define RG_TG_MIN_MSK GENMASK(7, 5)
  192. #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
  193. /* COMINIT GAP width window */
  194. #define RG_T2_MIN_MSK GENMASK(4, 0)
  195. #define RG_T2_MIN_VAL(x) (0x1f & (x))
  196. #define ANA_RG_CTRL_SIGNAL1 0x4c
  197. /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
  198. #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
  199. #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
  200. #define ANA_RG_CTRL_SIGNAL4 0x58
  201. #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
  202. #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
  203. /* Loop filter R1 resistance adjustment for Gen1 speed */
  204. #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
  205. #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
  206. #define ANA_RG_CTRL_SIGNAL6 0x60
  207. /* I-path capacitance adjustment for Gen1 */
  208. #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
  209. #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
  210. #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
  211. #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
  212. #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
  213. /* RX Gen1 LEQ tuning step */
  214. #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
  215. #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
  216. #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
  217. #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
  218. #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
  219. #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
  220. #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
  221. #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
  222. enum mtk_phy_version {
  223. MTK_PHY_V1 = 1,
  224. MTK_PHY_V2,
  225. };
  226. struct mtk_phy_pdata {
  227. /* avoid RX sensitivity level degradation only for mt8173 */
  228. bool avoid_rx_sen_degradation;
  229. enum mtk_phy_version version;
  230. };
  231. struct u2phy_banks {
  232. void __iomem *misc;
  233. void __iomem *fmreg;
  234. void __iomem *com;
  235. };
  236. struct u3phy_banks {
  237. void __iomem *spllc;
  238. void __iomem *chip;
  239. void __iomem *phyd; /* include u3phyd_bank2 */
  240. void __iomem *phya; /* include u3phya_da */
  241. };
  242. struct mtk_phy_instance {
  243. struct phy *phy;
  244. void __iomem *port_base;
  245. union {
  246. struct u2phy_banks u2_banks;
  247. struct u3phy_banks u3_banks;
  248. };
  249. struct clk *ref_clk; /* reference clock of anolog phy */
  250. u32 index;
  251. u8 type;
  252. };
  253. struct mtk_tphy {
  254. struct device *dev;
  255. void __iomem *sif_base; /* only shared sif */
  256. /* deprecated, use @ref_clk instead in phy instance */
  257. struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */
  258. const struct mtk_phy_pdata *pdata;
  259. struct mtk_phy_instance **phys;
  260. int nphys;
  261. int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
  262. int src_coef; /* coefficient for slew rate calibrate */
  263. };
  264. static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
  265. struct mtk_phy_instance *instance)
  266. {
  267. struct u2phy_banks *u2_banks = &instance->u2_banks;
  268. void __iomem *fmreg = u2_banks->fmreg;
  269. void __iomem *com = u2_banks->com;
  270. int calibration_val;
  271. int fm_out;
  272. u32 tmp;
  273. /* enable USB ring oscillator */
  274. tmp = readl(com + U3P_USBPHYACR5);
  275. tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
  276. writel(tmp, com + U3P_USBPHYACR5);
  277. udelay(1);
  278. /*enable free run clock */
  279. tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
  280. tmp |= P2F_RG_FRCK_EN;
  281. writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
  282. /* set cycle count as 1024, and select u2 channel */
  283. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  284. tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
  285. tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
  286. if (tphy->pdata->version == MTK_PHY_V1)
  287. tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
  288. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  289. /* enable frequency meter */
  290. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  291. tmp |= P2F_RG_FREQDET_EN;
  292. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  293. /* ignore return value */
  294. readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
  295. (tmp & P2F_USB_FM_VALID), 10, 200);
  296. fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
  297. /* disable frequency meter */
  298. tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
  299. tmp &= ~P2F_RG_FREQDET_EN;
  300. writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
  301. /*disable free run clock */
  302. tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
  303. tmp &= ~P2F_RG_FRCK_EN;
  304. writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
  305. if (fm_out) {
  306. /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
  307. tmp = tphy->src_ref_clk * tphy->src_coef;
  308. tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
  309. calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
  310. } else {
  311. /* if FM detection fail, set default value */
  312. calibration_val = 4;
  313. }
  314. dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
  315. instance->index, fm_out, calibration_val,
  316. tphy->src_ref_clk, tphy->src_coef);
  317. /* set HS slew rate */
  318. tmp = readl(com + U3P_USBPHYACR5);
  319. tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
  320. tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
  321. writel(tmp, com + U3P_USBPHYACR5);
  322. /* disable USB ring oscillator */
  323. tmp = readl(com + U3P_USBPHYACR5);
  324. tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
  325. writel(tmp, com + U3P_USBPHYACR5);
  326. }
  327. static void u3_phy_instance_init(struct mtk_tphy *tphy,
  328. struct mtk_phy_instance *instance)
  329. {
  330. struct u3phy_banks *u3_banks = &instance->u3_banks;
  331. u32 tmp;
  332. /* gating PCIe Analog XTAL clock */
  333. tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
  334. tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
  335. writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
  336. /* gating XSQ */
  337. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  338. tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
  339. tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
  340. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  341. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
  342. tmp &= ~P3A_RG_RX_DAC_MUX;
  343. tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
  344. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
  345. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
  346. tmp &= ~P3A_RG_TX_EIDLE_CM;
  347. tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
  348. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
  349. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
  350. tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
  351. tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
  352. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
  353. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
  354. tmp &= ~P3D_RG_FWAKE_TH;
  355. tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
  356. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
  357. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  358. tmp &= ~P3D_RG_RXDET_STB2_SET;
  359. tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
  360. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  361. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  362. tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
  363. tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
  364. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  365. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  366. }
  367. static void u2_phy_instance_init(struct mtk_tphy *tphy,
  368. struct mtk_phy_instance *instance)
  369. {
  370. struct u2phy_banks *u2_banks = &instance->u2_banks;
  371. void __iomem *com = u2_banks->com;
  372. u32 index = instance->index;
  373. u32 tmp;
  374. /* switch to USB function, and enable usb pll */
  375. tmp = readl(com + U3P_U2PHYDTM0);
  376. tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
  377. tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
  378. writel(tmp, com + U3P_U2PHYDTM0);
  379. tmp = readl(com + U3P_U2PHYDTM1);
  380. tmp &= ~P2C_RG_UART_EN;
  381. writel(tmp, com + U3P_U2PHYDTM1);
  382. tmp = readl(com + U3P_USBPHYACR0);
  383. tmp |= PA0_RG_USB20_INTR_EN;
  384. writel(tmp, com + U3P_USBPHYACR0);
  385. /* disable switch 100uA current to SSUSB */
  386. tmp = readl(com + U3P_USBPHYACR5);
  387. tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
  388. writel(tmp, com + U3P_USBPHYACR5);
  389. if (!index) {
  390. tmp = readl(com + U3P_U2PHYACR4);
  391. tmp &= ~P2C_U2_GPIO_CTR_MSK;
  392. writel(tmp, com + U3P_U2PHYACR4);
  393. }
  394. if (tphy->pdata->avoid_rx_sen_degradation) {
  395. if (!index) {
  396. tmp = readl(com + U3P_USBPHYACR2);
  397. tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
  398. writel(tmp, com + U3P_USBPHYACR2);
  399. tmp = readl(com + U3D_U2PHYDCR0);
  400. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  401. writel(tmp, com + U3D_U2PHYDCR0);
  402. } else {
  403. tmp = readl(com + U3D_U2PHYDCR0);
  404. tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
  405. writel(tmp, com + U3D_U2PHYDCR0);
  406. tmp = readl(com + U3P_U2PHYDTM0);
  407. tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
  408. writel(tmp, com + U3P_U2PHYDTM0);
  409. }
  410. }
  411. tmp = readl(com + U3P_USBPHYACR6);
  412. tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
  413. tmp &= ~PA6_RG_U2_SQTH;
  414. tmp |= PA6_RG_U2_SQTH_VAL(2);
  415. writel(tmp, com + U3P_USBPHYACR6);
  416. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  417. }
  418. static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
  419. struct mtk_phy_instance *instance)
  420. {
  421. struct u2phy_banks *u2_banks = &instance->u2_banks;
  422. void __iomem *com = u2_banks->com;
  423. u32 index = instance->index;
  424. u32 tmp;
  425. tmp = readl(com + U3P_U2PHYDTM0);
  426. tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
  427. writel(tmp, com + U3P_U2PHYDTM0);
  428. /* OTG Enable */
  429. tmp = readl(com + U3P_USBPHYACR6);
  430. tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
  431. writel(tmp, com + U3P_USBPHYACR6);
  432. tmp = readl(com + U3P_U2PHYDTM1);
  433. tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
  434. tmp &= ~P2C_RG_SESSEND;
  435. writel(tmp, com + U3P_U2PHYDTM1);
  436. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  437. tmp = readl(com + U3D_U2PHYDCR0);
  438. tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
  439. writel(tmp, com + U3D_U2PHYDCR0);
  440. tmp = readl(com + U3P_U2PHYDTM0);
  441. tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
  442. writel(tmp, com + U3P_U2PHYDTM0);
  443. }
  444. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  445. }
  446. static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
  447. struct mtk_phy_instance *instance)
  448. {
  449. struct u2phy_banks *u2_banks = &instance->u2_banks;
  450. void __iomem *com = u2_banks->com;
  451. u32 index = instance->index;
  452. u32 tmp;
  453. tmp = readl(com + U3P_U2PHYDTM0);
  454. tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
  455. writel(tmp, com + U3P_U2PHYDTM0);
  456. /* OTG Disable */
  457. tmp = readl(com + U3P_USBPHYACR6);
  458. tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
  459. writel(tmp, com + U3P_USBPHYACR6);
  460. tmp = readl(com + U3P_U2PHYDTM1);
  461. tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
  462. tmp |= P2C_RG_SESSEND;
  463. writel(tmp, com + U3P_U2PHYDTM1);
  464. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  465. tmp = readl(com + U3P_U2PHYDTM0);
  466. tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
  467. writel(tmp, com + U3P_U2PHYDTM0);
  468. tmp = readl(com + U3D_U2PHYDCR0);
  469. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  470. writel(tmp, com + U3D_U2PHYDCR0);
  471. }
  472. dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
  473. }
  474. static void u2_phy_instance_exit(struct mtk_tphy *tphy,
  475. struct mtk_phy_instance *instance)
  476. {
  477. struct u2phy_banks *u2_banks = &instance->u2_banks;
  478. void __iomem *com = u2_banks->com;
  479. u32 index = instance->index;
  480. u32 tmp;
  481. if (tphy->pdata->avoid_rx_sen_degradation && index) {
  482. tmp = readl(com + U3D_U2PHYDCR0);
  483. tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
  484. writel(tmp, com + U3D_U2PHYDCR0);
  485. tmp = readl(com + U3P_U2PHYDTM0);
  486. tmp &= ~P2C_FORCE_SUSPENDM;
  487. writel(tmp, com + U3P_U2PHYDTM0);
  488. }
  489. }
  490. static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
  491. struct mtk_phy_instance *instance,
  492. enum phy_mode mode)
  493. {
  494. struct u2phy_banks *u2_banks = &instance->u2_banks;
  495. u32 tmp;
  496. tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
  497. switch (mode) {
  498. case PHY_MODE_USB_DEVICE:
  499. tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
  500. break;
  501. case PHY_MODE_USB_HOST:
  502. tmp |= P2C_FORCE_IDDIG;
  503. tmp &= ~P2C_RG_IDDIG;
  504. break;
  505. case PHY_MODE_USB_OTG:
  506. tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
  507. break;
  508. default:
  509. return;
  510. }
  511. writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
  512. }
  513. static void pcie_phy_instance_init(struct mtk_tphy *tphy,
  514. struct mtk_phy_instance *instance)
  515. {
  516. struct u3phy_banks *u3_banks = &instance->u3_banks;
  517. u32 tmp;
  518. if (tphy->pdata->version != MTK_PHY_V1)
  519. return;
  520. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  521. tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
  522. tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
  523. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
  524. /* ref clk drive */
  525. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
  526. tmp &= ~P3A_RG_CLKDRV_AMP;
  527. tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
  528. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
  529. tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
  530. tmp &= ~P3A_RG_CLKDRV_OFF;
  531. tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
  532. writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
  533. /* SSC delta -5000ppm */
  534. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
  535. tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
  536. tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
  537. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
  538. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
  539. tmp &= ~P3A_RG_PLL_DELTA_PE2H;
  540. tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
  541. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
  542. /* change pll BW 0.6M */
  543. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
  544. tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
  545. tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
  546. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
  547. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
  548. tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
  549. tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
  550. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
  551. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
  552. tmp &= ~P3A_RG_PLL_IR_PE2H;
  553. tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
  554. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
  555. tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
  556. tmp &= ~P3A_RG_PLL_BP_PE2H;
  557. tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
  558. writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
  559. /* Tx Detect Rx Timing: 10us -> 5us */
  560. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  561. tmp &= ~P3D_RG_RXDET_STB2_SET;
  562. tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
  563. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
  564. tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  565. tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
  566. tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
  567. writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
  568. /* wait for PCIe subsys register to active */
  569. usleep_range(2500, 3000);
  570. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  571. }
  572. static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
  573. struct mtk_phy_instance *instance)
  574. {
  575. struct u3phy_banks *bank = &instance->u3_banks;
  576. u32 tmp;
  577. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  578. tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  579. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  580. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  581. tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  582. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  583. }
  584. static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
  585. struct mtk_phy_instance *instance)
  586. {
  587. struct u3phy_banks *bank = &instance->u3_banks;
  588. u32 tmp;
  589. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  590. tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
  591. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
  592. tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  593. tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
  594. writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
  595. }
  596. static void sata_phy_instance_init(struct mtk_tphy *tphy,
  597. struct mtk_phy_instance *instance)
  598. {
  599. struct u3phy_banks *u3_banks = &instance->u3_banks;
  600. void __iomem *phyd = u3_banks->phyd;
  601. u32 tmp;
  602. /* charge current adjustment */
  603. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
  604. tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
  605. tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
  606. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
  607. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
  608. tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
  609. tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
  610. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
  611. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
  612. tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
  613. tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
  614. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
  615. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
  616. tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
  617. tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
  618. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
  619. tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
  620. tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
  621. tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
  622. writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
  623. tmp = readl(phyd + PHYD_DESIGN_OPTION2);
  624. tmp &= ~RG_LOCK_CNT_SEL_MSK;
  625. tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
  626. writel(tmp, phyd + PHYD_DESIGN_OPTION2);
  627. tmp = readl(phyd + PHYD_DESIGN_OPTION9);
  628. tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
  629. RG_T2_MAX_MSK | RG_TG_MAX_MSK);
  630. tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
  631. RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
  632. writel(tmp, phyd + PHYD_DESIGN_OPTION9);
  633. tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
  634. tmp &= ~RG_IDRV_0DB_GEN1_MSK;
  635. tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
  636. writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
  637. tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
  638. tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
  639. tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
  640. writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
  641. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  642. }
  643. static void phy_v1_banks_init(struct mtk_tphy *tphy,
  644. struct mtk_phy_instance *instance)
  645. {
  646. struct u2phy_banks *u2_banks = &instance->u2_banks;
  647. struct u3phy_banks *u3_banks = &instance->u3_banks;
  648. switch (instance->type) {
  649. case PHY_TYPE_USB2:
  650. u2_banks->misc = NULL;
  651. u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
  652. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
  653. break;
  654. case PHY_TYPE_USB3:
  655. case PHY_TYPE_PCIE:
  656. u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
  657. u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
  658. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  659. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
  660. break;
  661. case PHY_TYPE_SATA:
  662. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  663. break;
  664. default:
  665. dev_err(tphy->dev, "incompatible PHY type\n");
  666. return;
  667. }
  668. }
  669. static void phy_v2_banks_init(struct mtk_tphy *tphy,
  670. struct mtk_phy_instance *instance)
  671. {
  672. struct u2phy_banks *u2_banks = &instance->u2_banks;
  673. struct u3phy_banks *u3_banks = &instance->u3_banks;
  674. switch (instance->type) {
  675. case PHY_TYPE_USB2:
  676. u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
  677. u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
  678. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
  679. break;
  680. case PHY_TYPE_USB3:
  681. case PHY_TYPE_PCIE:
  682. u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
  683. u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
  684. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
  685. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
  686. break;
  687. default:
  688. dev_err(tphy->dev, "incompatible PHY type\n");
  689. return;
  690. }
  691. }
  692. static int mtk_phy_init(struct phy *phy)
  693. {
  694. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  695. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  696. int ret;
  697. ret = clk_prepare_enable(tphy->u3phya_ref);
  698. if (ret) {
  699. dev_err(tphy->dev, "failed to enable u3phya_ref\n");
  700. return ret;
  701. }
  702. ret = clk_prepare_enable(instance->ref_clk);
  703. if (ret) {
  704. dev_err(tphy->dev, "failed to enable ref_clk\n");
  705. return ret;
  706. }
  707. switch (instance->type) {
  708. case PHY_TYPE_USB2:
  709. u2_phy_instance_init(tphy, instance);
  710. break;
  711. case PHY_TYPE_USB3:
  712. u3_phy_instance_init(tphy, instance);
  713. break;
  714. case PHY_TYPE_PCIE:
  715. pcie_phy_instance_init(tphy, instance);
  716. break;
  717. case PHY_TYPE_SATA:
  718. sata_phy_instance_init(tphy, instance);
  719. break;
  720. default:
  721. dev_err(tphy->dev, "incompatible PHY type\n");
  722. return -EINVAL;
  723. }
  724. return 0;
  725. }
  726. static int mtk_phy_power_on(struct phy *phy)
  727. {
  728. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  729. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  730. if (instance->type == PHY_TYPE_USB2) {
  731. u2_phy_instance_power_on(tphy, instance);
  732. hs_slew_rate_calibrate(tphy, instance);
  733. } else if (instance->type == PHY_TYPE_PCIE) {
  734. pcie_phy_instance_power_on(tphy, instance);
  735. }
  736. return 0;
  737. }
  738. static int mtk_phy_power_off(struct phy *phy)
  739. {
  740. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  741. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  742. if (instance->type == PHY_TYPE_USB2)
  743. u2_phy_instance_power_off(tphy, instance);
  744. else if (instance->type == PHY_TYPE_PCIE)
  745. pcie_phy_instance_power_off(tphy, instance);
  746. return 0;
  747. }
  748. static int mtk_phy_exit(struct phy *phy)
  749. {
  750. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  751. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  752. if (instance->type == PHY_TYPE_USB2)
  753. u2_phy_instance_exit(tphy, instance);
  754. clk_disable_unprepare(instance->ref_clk);
  755. clk_disable_unprepare(tphy->u3phya_ref);
  756. return 0;
  757. }
  758. static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
  759. {
  760. struct mtk_phy_instance *instance = phy_get_drvdata(phy);
  761. struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
  762. if (instance->type == PHY_TYPE_USB2)
  763. u2_phy_instance_set_mode(tphy, instance, mode);
  764. return 0;
  765. }
  766. static struct phy *mtk_phy_xlate(struct device *dev,
  767. struct of_phandle_args *args)
  768. {
  769. struct mtk_tphy *tphy = dev_get_drvdata(dev);
  770. struct mtk_phy_instance *instance = NULL;
  771. struct device_node *phy_np = args->np;
  772. int index;
  773. if (args->args_count != 1) {
  774. dev_err(dev, "invalid number of cells in 'phy' property\n");
  775. return ERR_PTR(-EINVAL);
  776. }
  777. for (index = 0; index < tphy->nphys; index++)
  778. if (phy_np == tphy->phys[index]->phy->dev.of_node) {
  779. instance = tphy->phys[index];
  780. break;
  781. }
  782. if (!instance) {
  783. dev_err(dev, "failed to find appropriate phy\n");
  784. return ERR_PTR(-EINVAL);
  785. }
  786. instance->type = args->args[0];
  787. if (!(instance->type == PHY_TYPE_USB2 ||
  788. instance->type == PHY_TYPE_USB3 ||
  789. instance->type == PHY_TYPE_PCIE ||
  790. instance->type == PHY_TYPE_SATA)) {
  791. dev_err(dev, "unsupported device type: %d\n", instance->type);
  792. return ERR_PTR(-EINVAL);
  793. }
  794. if (tphy->pdata->version == MTK_PHY_V1) {
  795. phy_v1_banks_init(tphy, instance);
  796. } else if (tphy->pdata->version == MTK_PHY_V2) {
  797. phy_v2_banks_init(tphy, instance);
  798. } else {
  799. dev_err(dev, "phy version is not supported\n");
  800. return ERR_PTR(-EINVAL);
  801. }
  802. return instance->phy;
  803. }
  804. static const struct phy_ops mtk_tphy_ops = {
  805. .init = mtk_phy_init,
  806. .exit = mtk_phy_exit,
  807. .power_on = mtk_phy_power_on,
  808. .power_off = mtk_phy_power_off,
  809. .set_mode = mtk_phy_set_mode,
  810. .owner = THIS_MODULE,
  811. };
  812. static const struct mtk_phy_pdata tphy_v1_pdata = {
  813. .avoid_rx_sen_degradation = false,
  814. .version = MTK_PHY_V1,
  815. };
  816. static const struct mtk_phy_pdata tphy_v2_pdata = {
  817. .avoid_rx_sen_degradation = false,
  818. .version = MTK_PHY_V2,
  819. };
  820. static const struct mtk_phy_pdata mt8173_pdata = {
  821. .avoid_rx_sen_degradation = true,
  822. .version = MTK_PHY_V1,
  823. };
  824. static const struct of_device_id mtk_tphy_id_table[] = {
  825. { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
  826. { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
  827. { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
  828. { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
  829. { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
  830. { },
  831. };
  832. MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
  833. static int mtk_tphy_probe(struct platform_device *pdev)
  834. {
  835. struct device *dev = &pdev->dev;
  836. struct device_node *np = dev->of_node;
  837. struct device_node *child_np;
  838. struct phy_provider *provider;
  839. struct resource *sif_res;
  840. struct mtk_tphy *tphy;
  841. struct resource res;
  842. int port, retval;
  843. tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
  844. if (!tphy)
  845. return -ENOMEM;
  846. tphy->pdata = of_device_get_match_data(dev);
  847. if (!tphy->pdata)
  848. return -EINVAL;
  849. tphy->nphys = of_get_child_count(np);
  850. tphy->phys = devm_kcalloc(dev, tphy->nphys,
  851. sizeof(*tphy->phys), GFP_KERNEL);
  852. if (!tphy->phys)
  853. return -ENOMEM;
  854. tphy->dev = dev;
  855. platform_set_drvdata(pdev, tphy);
  856. sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  857. /* SATA phy of V1 needn't it if not shared with PCIe or USB */
  858. if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
  859. /* get banks shared by multiple phys */
  860. tphy->sif_base = devm_ioremap_resource(dev, sif_res);
  861. if (IS_ERR(tphy->sif_base)) {
  862. dev_err(dev, "failed to remap sif regs\n");
  863. return PTR_ERR(tphy->sif_base);
  864. }
  865. }
  866. /* it's deprecated, make it optional for backward compatibility */
  867. tphy->u3phya_ref = devm_clk_get(dev, "u3phya_ref");
  868. if (IS_ERR(tphy->u3phya_ref)) {
  869. if (PTR_ERR(tphy->u3phya_ref) == -EPROBE_DEFER)
  870. return -EPROBE_DEFER;
  871. tphy->u3phya_ref = NULL;
  872. }
  873. tphy->src_ref_clk = U3P_REF_CLK;
  874. tphy->src_coef = U3P_SLEW_RATE_COEF;
  875. /* update parameters of slew rate calibrate if exist */
  876. device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
  877. &tphy->src_ref_clk);
  878. device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
  879. port = 0;
  880. for_each_child_of_node(np, child_np) {
  881. struct mtk_phy_instance *instance;
  882. struct phy *phy;
  883. instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
  884. if (!instance) {
  885. retval = -ENOMEM;
  886. goto put_child;
  887. }
  888. tphy->phys[port] = instance;
  889. phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
  890. if (IS_ERR(phy)) {
  891. dev_err(dev, "failed to create phy\n");
  892. retval = PTR_ERR(phy);
  893. goto put_child;
  894. }
  895. retval = of_address_to_resource(child_np, 0, &res);
  896. if (retval) {
  897. dev_err(dev, "failed to get address resource(id-%d)\n",
  898. port);
  899. goto put_child;
  900. }
  901. instance->port_base = devm_ioremap_resource(&phy->dev, &res);
  902. if (IS_ERR(instance->port_base)) {
  903. dev_err(dev, "failed to remap phy regs\n");
  904. retval = PTR_ERR(instance->port_base);
  905. goto put_child;
  906. }
  907. instance->phy = phy;
  908. instance->index = port;
  909. phy_set_drvdata(phy, instance);
  910. port++;
  911. /* if deprecated clock is provided, ignore instance's one */
  912. if (tphy->u3phya_ref)
  913. continue;
  914. instance->ref_clk = devm_clk_get(&phy->dev, "ref");
  915. if (IS_ERR(instance->ref_clk)) {
  916. dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
  917. retval = PTR_ERR(instance->ref_clk);
  918. goto put_child;
  919. }
  920. }
  921. provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
  922. return PTR_ERR_OR_ZERO(provider);
  923. put_child:
  924. of_node_put(child_np);
  925. return retval;
  926. }
  927. static struct platform_driver mtk_tphy_driver = {
  928. .probe = mtk_tphy_probe,
  929. .driver = {
  930. .name = "mtk-tphy",
  931. .of_match_table = mtk_tphy_id_table,
  932. },
  933. };
  934. module_platform_driver(mtk_tphy_driver);
  935. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  936. MODULE_DESCRIPTION("MediaTek T-PHY driver");
  937. MODULE_LICENSE("GPL v2");