pci-ftpci100.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support for Faraday Technology FTPC100 PCI Controller
  4. *
  5. * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
  6. *
  7. * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
  8. * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
  9. * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
  10. * Based on SL2312 PCI controller code
  11. * Storlink (C) 2003
  12. */
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_pci.h>
  21. #include <linux/pci.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #include <linux/irqdomain.h>
  25. #include <linux/irqchip/chained_irq.h>
  26. #include <linux/bitops.h>
  27. #include <linux/irq.h>
  28. #include <linux/clk.h>
  29. /*
  30. * Special configuration registers directly in the first few words
  31. * in I/O space.
  32. */
  33. #define PCI_IOSIZE 0x00
  34. #define PCI_PROT 0x04 /* AHB protection */
  35. #define PCI_CTRL 0x08 /* PCI control signal */
  36. #define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
  37. #define PCI_CONFIG 0x28 /* PCI configuration command register */
  38. #define PCI_DATA 0x2C
  39. #define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
  40. #define FARADAY_PCI_PMC 0x40 /* Power management control */
  41. #define FARADAY_PCI_PMCSR 0x44 /* Power management status */
  42. #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
  43. #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
  44. #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
  45. #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
  46. #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
  47. #define PCI_STATUS_66MHZ_CAPABLE BIT(21)
  48. /* Bits 31..28 gives INTD..INTA status */
  49. #define PCI_CTRL2_INTSTS_SHIFT 28
  50. #define PCI_CTRL2_INTMASK_CMDERR BIT(27)
  51. #define PCI_CTRL2_INTMASK_PARERR BIT(26)
  52. /* Bits 25..22 masks INTD..INTA */
  53. #define PCI_CTRL2_INTMASK_SHIFT 22
  54. #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
  55. #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
  56. #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
  57. #define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
  58. #define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
  59. #define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
  60. /* Bit 15 reserved */
  61. #define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
  62. #define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
  63. #define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
  64. #define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
  65. #define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
  66. #define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
  67. #define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
  68. /* Bits 7..4 reserved */
  69. /* Bits 3..0 TRDYW */
  70. /*
  71. * Memory configs:
  72. * Bit 31..20 defines the PCI side memory base
  73. * Bit 19..16 (4 bits) defines the size per below
  74. */
  75. #define FARADAY_PCI_MEMBASE_MASK 0xfff00000
  76. #define FARADAY_PCI_MEMSIZE_1MB 0x0
  77. #define FARADAY_PCI_MEMSIZE_2MB 0x1
  78. #define FARADAY_PCI_MEMSIZE_4MB 0x2
  79. #define FARADAY_PCI_MEMSIZE_8MB 0x3
  80. #define FARADAY_PCI_MEMSIZE_16MB 0x4
  81. #define FARADAY_PCI_MEMSIZE_32MB 0x5
  82. #define FARADAY_PCI_MEMSIZE_64MB 0x6
  83. #define FARADAY_PCI_MEMSIZE_128MB 0x7
  84. #define FARADAY_PCI_MEMSIZE_256MB 0x8
  85. #define FARADAY_PCI_MEMSIZE_512MB 0x9
  86. #define FARADAY_PCI_MEMSIZE_1GB 0xa
  87. #define FARADAY_PCI_MEMSIZE_2GB 0xb
  88. #define FARADAY_PCI_MEMSIZE_SHIFT 16
  89. /*
  90. * The DMA base is set to 0x0 for all memory segments, it reflects the
  91. * fact that the memory of the host system starts at 0x0.
  92. */
  93. #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
  94. #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
  95. #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
  96. /* Defines for PCI configuration command register */
  97. #define PCI_CONF_ENABLE BIT(31)
  98. #define PCI_CONF_WHERE(r) ((r) & 0xFC)
  99. #define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
  100. #define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
  101. #define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
  102. /**
  103. * struct faraday_pci_variant - encodes IP block differences
  104. * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
  105. * embedded in the host bridge.
  106. */
  107. struct faraday_pci_variant {
  108. bool cascaded_irq;
  109. };
  110. struct faraday_pci {
  111. struct device *dev;
  112. void __iomem *base;
  113. struct irq_domain *irqdomain;
  114. struct pci_bus *bus;
  115. struct clk *bus_clk;
  116. };
  117. static int faraday_res_to_memcfg(resource_size_t mem_base,
  118. resource_size_t mem_size, u32 *val)
  119. {
  120. u32 outval;
  121. switch (mem_size) {
  122. case SZ_1M:
  123. outval = FARADAY_PCI_MEMSIZE_1MB;
  124. break;
  125. case SZ_2M:
  126. outval = FARADAY_PCI_MEMSIZE_2MB;
  127. break;
  128. case SZ_4M:
  129. outval = FARADAY_PCI_MEMSIZE_4MB;
  130. break;
  131. case SZ_8M:
  132. outval = FARADAY_PCI_MEMSIZE_8MB;
  133. break;
  134. case SZ_16M:
  135. outval = FARADAY_PCI_MEMSIZE_16MB;
  136. break;
  137. case SZ_32M:
  138. outval = FARADAY_PCI_MEMSIZE_32MB;
  139. break;
  140. case SZ_64M:
  141. outval = FARADAY_PCI_MEMSIZE_64MB;
  142. break;
  143. case SZ_128M:
  144. outval = FARADAY_PCI_MEMSIZE_128MB;
  145. break;
  146. case SZ_256M:
  147. outval = FARADAY_PCI_MEMSIZE_256MB;
  148. break;
  149. case SZ_512M:
  150. outval = FARADAY_PCI_MEMSIZE_512MB;
  151. break;
  152. case SZ_1G:
  153. outval = FARADAY_PCI_MEMSIZE_1GB;
  154. break;
  155. case SZ_2G:
  156. outval = FARADAY_PCI_MEMSIZE_2GB;
  157. break;
  158. default:
  159. return -EINVAL;
  160. }
  161. outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
  162. /* This is probably not good */
  163. if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
  164. pr_warn("truncated PCI memory base\n");
  165. /* Translate to bridge side address space */
  166. outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
  167. pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
  168. &mem_base, &mem_size, outval);
  169. *val = outval;
  170. return 0;
  171. }
  172. static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
  173. unsigned int fn, int config, int size,
  174. u32 *value)
  175. {
  176. writel(PCI_CONF_BUS(bus_number) |
  177. PCI_CONF_DEVICE(PCI_SLOT(fn)) |
  178. PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
  179. PCI_CONF_WHERE(config) |
  180. PCI_CONF_ENABLE,
  181. p->base + PCI_CONFIG);
  182. *value = readl(p->base + PCI_DATA);
  183. if (size == 1)
  184. *value = (*value >> (8 * (config & 3))) & 0xFF;
  185. else if (size == 2)
  186. *value = (*value >> (8 * (config & 3))) & 0xFFFF;
  187. return PCIBIOS_SUCCESSFUL;
  188. }
  189. static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
  190. int config, int size, u32 *value)
  191. {
  192. struct faraday_pci *p = bus->sysdata;
  193. dev_dbg(&bus->dev,
  194. "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
  195. PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
  196. return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
  197. }
  198. static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
  199. unsigned int fn, int config, int size,
  200. u32 value)
  201. {
  202. int ret = PCIBIOS_SUCCESSFUL;
  203. writel(PCI_CONF_BUS(bus_number) |
  204. PCI_CONF_DEVICE(PCI_SLOT(fn)) |
  205. PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
  206. PCI_CONF_WHERE(config) |
  207. PCI_CONF_ENABLE,
  208. p->base + PCI_CONFIG);
  209. switch (size) {
  210. case 4:
  211. writel(value, p->base + PCI_DATA);
  212. break;
  213. case 2:
  214. writew(value, p->base + PCI_DATA + (config & 3));
  215. break;
  216. case 1:
  217. writeb(value, p->base + PCI_DATA + (config & 3));
  218. break;
  219. default:
  220. ret = PCIBIOS_BAD_REGISTER_NUMBER;
  221. }
  222. return ret;
  223. }
  224. static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
  225. int config, int size, u32 value)
  226. {
  227. struct faraday_pci *p = bus->sysdata;
  228. dev_dbg(&bus->dev,
  229. "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
  230. PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
  231. return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
  232. value);
  233. }
  234. static struct pci_ops faraday_pci_ops = {
  235. .read = faraday_pci_read_config,
  236. .write = faraday_pci_write_config,
  237. };
  238. static void faraday_pci_ack_irq(struct irq_data *d)
  239. {
  240. struct faraday_pci *p = irq_data_get_irq_chip_data(d);
  241. unsigned int reg;
  242. faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
  243. reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
  244. reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
  245. faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
  246. }
  247. static void faraday_pci_mask_irq(struct irq_data *d)
  248. {
  249. struct faraday_pci *p = irq_data_get_irq_chip_data(d);
  250. unsigned int reg;
  251. faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
  252. reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
  253. | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
  254. faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
  255. }
  256. static void faraday_pci_unmask_irq(struct irq_data *d)
  257. {
  258. struct faraday_pci *p = irq_data_get_irq_chip_data(d);
  259. unsigned int reg;
  260. faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
  261. reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
  262. reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
  263. faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
  264. }
  265. static void faraday_pci_irq_handler(struct irq_desc *desc)
  266. {
  267. struct faraday_pci *p = irq_desc_get_handler_data(desc);
  268. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  269. unsigned int irq_stat, reg, i;
  270. faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, &reg);
  271. irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
  272. chained_irq_enter(irqchip, desc);
  273. for (i = 0; i < 4; i++) {
  274. if ((irq_stat & BIT(i)) == 0)
  275. continue;
  276. generic_handle_irq(irq_find_mapping(p->irqdomain, i));
  277. }
  278. chained_irq_exit(irqchip, desc);
  279. }
  280. static struct irq_chip faraday_pci_irq_chip = {
  281. .name = "PCI",
  282. .irq_ack = faraday_pci_ack_irq,
  283. .irq_mask = faraday_pci_mask_irq,
  284. .irq_unmask = faraday_pci_unmask_irq,
  285. };
  286. static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
  287. irq_hw_number_t hwirq)
  288. {
  289. irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
  290. irq_set_chip_data(irq, domain->host_data);
  291. return 0;
  292. }
  293. static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
  294. .map = faraday_pci_irq_map,
  295. };
  296. static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
  297. {
  298. struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
  299. int irq;
  300. int i;
  301. if (!intc) {
  302. dev_err(p->dev, "missing child interrupt-controller node\n");
  303. return -EINVAL;
  304. }
  305. /* All PCI IRQs cascade off this one */
  306. irq = of_irq_get(intc, 0);
  307. if (irq <= 0) {
  308. dev_err(p->dev, "failed to get parent IRQ\n");
  309. return irq ?: -EINVAL;
  310. }
  311. p->irqdomain = irq_domain_add_linear(intc, PCI_NUM_INTX,
  312. &faraday_pci_irqdomain_ops, p);
  313. if (!p->irqdomain) {
  314. dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
  315. return -EINVAL;
  316. }
  317. irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
  318. for (i = 0; i < 4; i++)
  319. irq_create_mapping(p->irqdomain, i);
  320. return 0;
  321. }
  322. static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
  323. struct device_node *np)
  324. {
  325. struct of_pci_range range;
  326. struct of_pci_range_parser parser;
  327. struct device *dev = p->dev;
  328. u32 confreg[3] = {
  329. FARADAY_PCI_MEM1_BASE_SIZE,
  330. FARADAY_PCI_MEM2_BASE_SIZE,
  331. FARADAY_PCI_MEM3_BASE_SIZE,
  332. };
  333. int i = 0;
  334. u32 val;
  335. if (of_pci_dma_range_parser_init(&parser, np)) {
  336. dev_err(dev, "missing dma-ranges property\n");
  337. return -EINVAL;
  338. }
  339. /*
  340. * Get the dma-ranges from the device tree
  341. */
  342. for_each_of_pci_range(&parser, &range) {
  343. u64 end = range.pci_addr + range.size - 1;
  344. int ret;
  345. ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
  346. if (ret) {
  347. dev_err(dev,
  348. "DMA range %d: illegal MEM resource size\n", i);
  349. return -EINVAL;
  350. }
  351. dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
  352. i + 1, range.pci_addr, end, val);
  353. if (i <= 2) {
  354. faraday_raw_pci_write_config(p, 0, 0, confreg[i],
  355. 4, val);
  356. } else {
  357. dev_err(dev, "ignore extraneous dma-range %d\n", i);
  358. break;
  359. }
  360. i++;
  361. }
  362. return 0;
  363. }
  364. static int faraday_pci_probe(struct platform_device *pdev)
  365. {
  366. struct device *dev = &pdev->dev;
  367. const struct faraday_pci_variant *variant =
  368. of_device_get_match_data(dev);
  369. struct resource *regs;
  370. resource_size_t io_base;
  371. struct resource_entry *win;
  372. struct faraday_pci *p;
  373. struct resource *mem;
  374. struct resource *io;
  375. struct pci_host_bridge *host;
  376. struct clk *clk;
  377. unsigned char max_bus_speed = PCI_SPEED_33MHz;
  378. unsigned char cur_bus_speed = PCI_SPEED_33MHz;
  379. int ret;
  380. u32 val;
  381. LIST_HEAD(res);
  382. host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
  383. if (!host)
  384. return -ENOMEM;
  385. host->dev.parent = dev;
  386. host->ops = &faraday_pci_ops;
  387. host->busnr = 0;
  388. host->msi = NULL;
  389. host->map_irq = of_irq_parse_and_map_pci;
  390. host->swizzle_irq = pci_common_swizzle;
  391. p = pci_host_bridge_priv(host);
  392. host->sysdata = p;
  393. p->dev = dev;
  394. /* Retrieve and enable optional clocks */
  395. clk = devm_clk_get(dev, "PCLK");
  396. if (IS_ERR(clk))
  397. return PTR_ERR(clk);
  398. ret = clk_prepare_enable(clk);
  399. if (ret) {
  400. dev_err(dev, "could not prepare PCLK\n");
  401. return ret;
  402. }
  403. p->bus_clk = devm_clk_get(dev, "PCICLK");
  404. if (IS_ERR(p->bus_clk))
  405. return PTR_ERR(p->bus_clk);
  406. ret = clk_prepare_enable(p->bus_clk);
  407. if (ret) {
  408. dev_err(dev, "could not prepare PCICLK\n");
  409. return ret;
  410. }
  411. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  412. p->base = devm_ioremap_resource(dev, regs);
  413. if (IS_ERR(p->base))
  414. return PTR_ERR(p->base);
  415. ret = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
  416. &res, &io_base);
  417. if (ret)
  418. return ret;
  419. ret = devm_request_pci_bus_resources(dev, &res);
  420. if (ret)
  421. return ret;
  422. /* Get the I/O and memory ranges from DT */
  423. resource_list_for_each_entry(win, &res) {
  424. switch (resource_type(win->res)) {
  425. case IORESOURCE_IO:
  426. io = win->res;
  427. io->name = "Gemini PCI I/O";
  428. if (!faraday_res_to_memcfg(io->start - win->offset,
  429. resource_size(io), &val)) {
  430. /* setup I/O space size */
  431. writel(val, p->base + PCI_IOSIZE);
  432. } else {
  433. dev_err(dev, "illegal IO mem size\n");
  434. return -EINVAL;
  435. }
  436. ret = pci_remap_iospace(io, io_base);
  437. if (ret) {
  438. dev_warn(dev, "error %d: failed to map resource %pR\n",
  439. ret, io);
  440. continue;
  441. }
  442. break;
  443. case IORESOURCE_MEM:
  444. mem = win->res;
  445. mem->name = "Gemini PCI MEM";
  446. break;
  447. case IORESOURCE_BUS:
  448. break;
  449. default:
  450. break;
  451. }
  452. }
  453. /* Setup hostbridge */
  454. val = readl(p->base + PCI_CTRL);
  455. val |= PCI_COMMAND_IO;
  456. val |= PCI_COMMAND_MEMORY;
  457. val |= PCI_COMMAND_MASTER;
  458. writel(val, p->base + PCI_CTRL);
  459. /* Mask and clear all interrupts */
  460. faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
  461. if (variant->cascaded_irq) {
  462. ret = faraday_pci_setup_cascaded_irq(p);
  463. if (ret) {
  464. dev_err(dev, "failed to setup cascaded IRQ\n");
  465. return ret;
  466. }
  467. }
  468. /* Check bus clock if we can gear up to 66 MHz */
  469. if (!IS_ERR(p->bus_clk)) {
  470. unsigned long rate;
  471. u32 val;
  472. faraday_raw_pci_read_config(p, 0, 0,
  473. FARADAY_PCI_STATUS_CMD, 4, &val);
  474. rate = clk_get_rate(p->bus_clk);
  475. if ((rate == 33000000) && (val & PCI_STATUS_66MHZ_CAPABLE)) {
  476. dev_info(dev, "33MHz bus is 66MHz capable\n");
  477. max_bus_speed = PCI_SPEED_66MHz;
  478. ret = clk_set_rate(p->bus_clk, 66000000);
  479. if (ret)
  480. dev_err(dev, "failed to set bus clock\n");
  481. } else {
  482. dev_info(dev, "33MHz only bus\n");
  483. max_bus_speed = PCI_SPEED_33MHz;
  484. }
  485. /* Bumping the clock may fail so read back the rate */
  486. rate = clk_get_rate(p->bus_clk);
  487. if (rate == 33000000)
  488. cur_bus_speed = PCI_SPEED_33MHz;
  489. if (rate == 66000000)
  490. cur_bus_speed = PCI_SPEED_66MHz;
  491. }
  492. ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
  493. if (ret)
  494. return ret;
  495. list_splice_init(&res, &host->windows);
  496. ret = pci_scan_root_bus_bridge(host);
  497. if (ret) {
  498. dev_err(dev, "failed to scan host: %d\n", ret);
  499. return ret;
  500. }
  501. p->bus = host->bus;
  502. p->bus->max_bus_speed = max_bus_speed;
  503. p->bus->cur_bus_speed = cur_bus_speed;
  504. pci_bus_assign_resources(p->bus);
  505. pci_bus_add_devices(p->bus);
  506. pci_free_resource_list(&res);
  507. return 0;
  508. }
  509. /*
  510. * We encode bridge variants here, we have at least two so it doesn't
  511. * hurt to have infrastructure to encompass future variants as well.
  512. */
  513. static const struct faraday_pci_variant faraday_regular = {
  514. .cascaded_irq = true,
  515. };
  516. static const struct faraday_pci_variant faraday_dual = {
  517. .cascaded_irq = false,
  518. };
  519. static const struct of_device_id faraday_pci_of_match[] = {
  520. {
  521. .compatible = "faraday,ftpci100",
  522. .data = &faraday_regular,
  523. },
  524. {
  525. .compatible = "faraday,ftpci100-dual",
  526. .data = &faraday_dual,
  527. },
  528. {},
  529. };
  530. static struct platform_driver faraday_pci_driver = {
  531. .driver = {
  532. .name = "ftpci100",
  533. .of_match_table = of_match_ptr(faraday_pci_of_match),
  534. .suppress_bind_attrs = true,
  535. },
  536. .probe = faraday_pci_probe,
  537. };
  538. builtin_platform_driver(faraday_pci_driver);